mmu_oea.c revision 152180
1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#include <sys/cdefs.h> 94__FBSDID("$FreeBSD: head/sys/powerpc/aim/mmu_oea.c 152180 2005-11-08 06:49:45Z grehan $"); 95 96/* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117#include "opt_kstack_pages.h" 118 119#include <sys/param.h> 120#include <sys/kernel.h> 121#include <sys/ktr.h> 122#include <sys/lock.h> 123#include <sys/msgbuf.h> 124#include <sys/mutex.h> 125#include <sys/proc.h> 126#include <sys/sysctl.h> 127#include <sys/systm.h> 128#include <sys/vmmeter.h> 129 130#include <dev/ofw/openfirm.h> 131 132#include <vm/vm.h> 133#include <vm/vm_param.h> 134#include <vm/vm_kern.h> 135#include <vm/vm_page.h> 136#include <vm/vm_map.h> 137#include <vm/vm_object.h> 138#include <vm/vm_extern.h> 139#include <vm/vm_pageout.h> 140#include <vm/vm_pager.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/powerpc.h> 145#include <machine/bat.h> 146#include <machine/frame.h> 147#include <machine/md_var.h> 148#include <machine/psl.h> 149#include <machine/pte.h> 150#include <machine/sr.h> 151#include <machine/mmuvar.h> 152 153#include "mmu_if.h" 154 155#define MOEA_DEBUG 156 157#define TODO panic("%s: not implemented", __func__); 158 159#define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va)) 160#define TLBSYNC() __asm __volatile("tlbsync"); 161#define SYNC() __asm __volatile("sync"); 162#define EIEIO() __asm __volatile("eieio"); 163 164#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 165#define VSID_TO_SR(vsid) ((vsid) & 0xf) 166#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 167 168#define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */ 169#define PVO_PTEGIDX_VALID 0x008 /* slot is valid */ 170#define PVO_WIRED 0x010 /* PVO entry is wired */ 171#define PVO_MANAGED 0x020 /* PVO entry is managed */ 172#define PVO_EXECUTABLE 0x040 /* PVO entry is executable */ 173#define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during 174 bootstrap */ 175#define PVO_FAKE 0x100 /* fictitious phys page */ 176#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 177#define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 178#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE) 179#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 180#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 181#define PVO_PTEGIDX_CLR(pvo) \ 182 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 183#define PVO_PTEGIDX_SET(pvo, i) \ 184 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 185 186#define MOEA_PVO_CHECK(pvo) 187 188struct ofw_map { 189 vm_offset_t om_va; 190 vm_size_t om_len; 191 vm_offset_t om_pa; 192 u_int om_mode; 193}; 194 195/* 196 * Map of physical memory regions. 197 */ 198static struct mem_region *regions; 199static struct mem_region *pregions; 200u_int phys_avail_count; 201int regions_sz, pregions_sz; 202static struct ofw_map *translations; 203 204extern struct pmap ofw_pmap; 205 206 207 208/* 209 * Lock for the pteg and pvo tables. 210 */ 211struct mtx moea_table_mutex; 212 213/* 214 * PTEG data. 215 */ 216static struct pteg *moea_pteg_table; 217u_int moea_pteg_count; 218u_int moea_pteg_mask; 219 220/* 221 * PVO data. 222 */ 223struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 224struct pvo_head moea_pvo_kunmanaged = 225 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 226struct pvo_head moea_pvo_unmanaged = 227 LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */ 228 229uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 230uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 231 232#define BPVO_POOL_SIZE 32768 233static struct pvo_entry *moea_bpvo_pool; 234static int moea_bpvo_pool_index = 0; 235 236#define VSID_NBPW (sizeof(u_int32_t) * 8) 237static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 238 239static boolean_t moea_initialized = FALSE; 240 241/* 242 * Statistics. 243 */ 244u_int moea_pte_valid = 0; 245u_int moea_pte_overflow = 0; 246u_int moea_pte_replacements = 0; 247u_int moea_pvo_entries = 0; 248u_int moea_pvo_enter_calls = 0; 249u_int moea_pvo_remove_calls = 0; 250u_int moea_pte_spills = 0; 251SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 252 0, ""); 253SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 254 &moea_pte_overflow, 0, ""); 255SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 256 &moea_pte_replacements, 0, ""); 257SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 258 0, ""); 259SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 260 &moea_pvo_enter_calls, 0, ""); 261SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 262 &moea_pvo_remove_calls, 0, ""); 263SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 264 &moea_pte_spills, 0, ""); 265 266struct pvo_entry *moea_pvo_zeropage; 267 268vm_offset_t moea_rkva_start = VM_MIN_KERNEL_ADDRESS; 269u_int moea_rkva_count = 4; 270 271/* 272 * Allocate physical memory for use in moea_bootstrap. 273 */ 274static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 275 276/* 277 * PTE calls. 278 */ 279static int moea_pte_insert(u_int, struct pte *); 280 281/* 282 * PVO calls. 283 */ 284static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 285 vm_offset_t, vm_offset_t, u_int, int); 286static void moea_pvo_remove(struct pvo_entry *, int); 287static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 288static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 289 290/* 291 * Utility routines. 292 */ 293static struct pvo_entry *moea_rkva_alloc(mmu_t); 294static void moea_pa_map(struct pvo_entry *, vm_offset_t, 295 struct pte *, int *); 296static void moea_pa_unmap(struct pvo_entry *, struct pte *, int *); 297static void moea_syncicache(vm_offset_t, vm_size_t); 298static boolean_t moea_query_bit(vm_page_t, int); 299static u_int moea_clear_bit(vm_page_t, int, int *); 300static void moea_kremove(mmu_t, vm_offset_t); 301static void tlbia(void); 302int moea_pte_spill(vm_offset_t); 303 304/* 305 * Kernel MMU interface 306 */ 307void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 308void moea_clear_modify(mmu_t, vm_page_t); 309void moea_clear_reference(mmu_t, vm_page_t); 310void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 311void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 312vm_page_t moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 313 vm_page_t); 314vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 315vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 316void moea_init(mmu_t); 317boolean_t moea_is_modified(mmu_t, vm_page_t); 318boolean_t moea_ts_referenced(mmu_t, vm_page_t); 319vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 320boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 321void moea_page_protect(mmu_t, vm_page_t, vm_prot_t); 322void moea_pinit(mmu_t, pmap_t); 323void moea_pinit0(mmu_t, pmap_t); 324void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 325void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 326void moea_qremove(mmu_t, vm_offset_t, int); 327void moea_release(mmu_t, pmap_t); 328void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 329void moea_remove_all(mmu_t, vm_page_t); 330void moea_zero_page(mmu_t, vm_page_t); 331void moea_zero_page_area(mmu_t, vm_page_t, int, int); 332void moea_zero_page_idle(mmu_t, vm_page_t); 333void moea_activate(mmu_t, struct thread *); 334void moea_deactivate(mmu_t, struct thread *); 335void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 336void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 337void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 338vm_offset_t moea_kextract(mmu_t, vm_offset_t); 339void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 340boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 341 342static mmu_method_t moea_methods[] = { 343 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 344 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 345 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 346 MMUMETHOD(mmu_copy_page, moea_copy_page), 347 MMUMETHOD(mmu_enter, moea_enter), 348 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 349 MMUMETHOD(mmu_extract, moea_extract), 350 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 351 MMUMETHOD(mmu_init, moea_init), 352 MMUMETHOD(mmu_is_modified, moea_is_modified), 353 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 354 MMUMETHOD(mmu_map, moea_map), 355 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 356 MMUMETHOD(mmu_page_protect, moea_page_protect), 357 MMUMETHOD(mmu_pinit, moea_pinit), 358 MMUMETHOD(mmu_pinit0, moea_pinit0), 359 MMUMETHOD(mmu_protect, moea_protect), 360 MMUMETHOD(mmu_qenter, moea_qenter), 361 MMUMETHOD(mmu_qremove, moea_qremove), 362 MMUMETHOD(mmu_release, moea_release), 363 MMUMETHOD(mmu_remove, moea_remove), 364 MMUMETHOD(mmu_remove_all, moea_remove_all), 365 MMUMETHOD(mmu_zero_page, moea_zero_page), 366 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 367 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 368 MMUMETHOD(mmu_activate, moea_activate), 369 MMUMETHOD(mmu_deactivate, moea_deactivate), 370 371 /* Internal interfaces */ 372 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 373 MMUMETHOD(mmu_mapdev, moea_mapdev), 374 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 375 MMUMETHOD(mmu_kextract, moea_kextract), 376 MMUMETHOD(mmu_kenter, moea_kenter), 377 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 378 379 { 0, 0 } 380}; 381 382static mmu_def_t oea_mmu = { 383 MMU_TYPE_OEA, 384 moea_methods, 385 0 386}; 387MMU_DEF(oea_mmu); 388 389 390static __inline int 391va_to_sr(u_int *sr, vm_offset_t va) 392{ 393 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 394} 395 396static __inline u_int 397va_to_pteg(u_int sr, vm_offset_t addr) 398{ 399 u_int hash; 400 401 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 402 ADDR_PIDX_SHFT); 403 return (hash & moea_pteg_mask); 404} 405 406static __inline struct pvo_head * 407pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 408{ 409 struct vm_page *pg; 410 411 pg = PHYS_TO_VM_PAGE(pa); 412 413 if (pg_p != NULL) 414 *pg_p = pg; 415 416 if (pg == NULL) 417 return (&moea_pvo_unmanaged); 418 419 return (&pg->md.mdpg_pvoh); 420} 421 422static __inline struct pvo_head * 423vm_page_to_pvoh(vm_page_t m) 424{ 425 426 return (&m->md.mdpg_pvoh); 427} 428 429static __inline void 430moea_attr_clear(vm_page_t m, int ptebit) 431{ 432 433 m->md.mdpg_attrs &= ~ptebit; 434} 435 436static __inline int 437moea_attr_fetch(vm_page_t m) 438{ 439 440 return (m->md.mdpg_attrs); 441} 442 443static __inline void 444moea_attr_save(vm_page_t m, int ptebit) 445{ 446 447 m->md.mdpg_attrs |= ptebit; 448} 449 450static __inline int 451moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 452{ 453 if (pt->pte_hi == pvo_pt->pte_hi) 454 return (1); 455 456 return (0); 457} 458 459static __inline int 460moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 461{ 462 return (pt->pte_hi & ~PTE_VALID) == 463 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 464 ((va >> ADDR_API_SHFT) & PTE_API) | which); 465} 466 467static __inline void 468moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 469{ 470 /* 471 * Construct a PTE. Default to IMB initially. Valid bit only gets 472 * set when the real pte is set in memory. 473 * 474 * Note: Don't set the valid bit for correct operation of tlb update. 475 */ 476 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 477 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 478 pt->pte_lo = pte_lo; 479} 480 481static __inline void 482moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 483{ 484 485 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 486} 487 488static __inline void 489moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 490{ 491 492 /* 493 * As shown in Section 7.6.3.2.3 494 */ 495 pt->pte_lo &= ~ptebit; 496 TLBIE(va); 497 EIEIO(); 498 TLBSYNC(); 499 SYNC(); 500} 501 502static __inline void 503moea_pte_set(struct pte *pt, struct pte *pvo_pt) 504{ 505 506 pvo_pt->pte_hi |= PTE_VALID; 507 508 /* 509 * Update the PTE as defined in section 7.6.3.1. 510 * Note that the REF/CHG bits are from pvo_pt and thus should havce 511 * been saved so this routine can restore them (if desired). 512 */ 513 pt->pte_lo = pvo_pt->pte_lo; 514 EIEIO(); 515 pt->pte_hi = pvo_pt->pte_hi; 516 SYNC(); 517 moea_pte_valid++; 518} 519 520static __inline void 521moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 522{ 523 524 pvo_pt->pte_hi &= ~PTE_VALID; 525 526 /* 527 * Force the reg & chg bits back into the PTEs. 528 */ 529 SYNC(); 530 531 /* 532 * Invalidate the pte. 533 */ 534 pt->pte_hi &= ~PTE_VALID; 535 536 SYNC(); 537 TLBIE(va); 538 EIEIO(); 539 TLBSYNC(); 540 SYNC(); 541 542 /* 543 * Save the reg & chg bits. 544 */ 545 moea_pte_synch(pt, pvo_pt); 546 moea_pte_valid--; 547} 548 549static __inline void 550moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 551{ 552 553 /* 554 * Invalidate the PTE 555 */ 556 moea_pte_unset(pt, pvo_pt, va); 557 moea_pte_set(pt, pvo_pt); 558} 559 560/* 561 * Quick sort callout for comparing memory regions. 562 */ 563static int mr_cmp(const void *a, const void *b); 564static int om_cmp(const void *a, const void *b); 565 566static int 567mr_cmp(const void *a, const void *b) 568{ 569 const struct mem_region *regiona; 570 const struct mem_region *regionb; 571 572 regiona = a; 573 regionb = b; 574 if (regiona->mr_start < regionb->mr_start) 575 return (-1); 576 else if (regiona->mr_start > regionb->mr_start) 577 return (1); 578 else 579 return (0); 580} 581 582static int 583om_cmp(const void *a, const void *b) 584{ 585 const struct ofw_map *mapa; 586 const struct ofw_map *mapb; 587 588 mapa = a; 589 mapb = b; 590 if (mapa->om_pa < mapb->om_pa) 591 return (-1); 592 else if (mapa->om_pa > mapb->om_pa) 593 return (1); 594 else 595 return (0); 596} 597 598void 599moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 600{ 601 ihandle_t mmui; 602 phandle_t chosen, mmu; 603 int sz; 604 int i, j; 605 int ofw_mappings; 606 vm_size_t size, physsz, hwphyssz; 607 vm_offset_t pa, va, off; 608 u_int batl, batu; 609 610 /* 611 * Set up BAT0 to map the lowest 256 MB area 612 */ 613 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 614 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 615 616 /* 617 * Map PCI memory space. 618 */ 619 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 620 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 621 622 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 623 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 624 625 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 626 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 627 628 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 629 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 630 631 /* 632 * Map obio devices. 633 */ 634 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 635 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 636 637 /* 638 * Use an IBAT and a DBAT to map the bottom segment of memory 639 * where we are. 640 */ 641 batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 642 batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 643 __asm (".balign 32; \n" 644 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 645 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 646 :: "r"(batu), "r"(batl)); 647 648#if 0 649 /* map frame buffer */ 650 batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 651 batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 652 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync" 653 :: "r"(batu), "r"(batl)); 654#endif 655 656#if 1 657 /* map pci space */ 658 batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 659 batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 660 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync" 661 :: "r"(batu), "r"(batl)); 662#endif 663 664 /* 665 * Set the start and end of kva. 666 */ 667 virtual_avail = VM_MIN_KERNEL_ADDRESS; 668 virtual_end = VM_MAX_KERNEL_ADDRESS; 669 670 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 671 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 672 673 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 674 for (i = 0; i < pregions_sz; i++) { 675 vm_offset_t pa; 676 vm_offset_t end; 677 678 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 679 pregions[i].mr_start, 680 pregions[i].mr_start + pregions[i].mr_size, 681 pregions[i].mr_size); 682 /* 683 * Install entries into the BAT table to allow all 684 * of physmem to be convered by on-demand BAT entries. 685 * The loop will sometimes set the same battable element 686 * twice, but that's fine since they won't be used for 687 * a while yet. 688 */ 689 pa = pregions[i].mr_start & 0xf0000000; 690 end = pregions[i].mr_start + pregions[i].mr_size; 691 do { 692 u_int n = pa >> ADDR_SR_SHFT; 693 694 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 695 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 696 pa += SEGMENT_LENGTH; 697 } while (pa < end); 698 } 699 700 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 701 panic("moea_bootstrap: phys_avail too small"); 702 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 703 phys_avail_count = 0; 704 physsz = 0; 705 hwphyssz = 0; 706 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 707 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 708 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 709 regions[i].mr_start + regions[i].mr_size, 710 regions[i].mr_size); 711 if (hwphyssz != 0 && 712 (physsz + regions[i].mr_size) >= hwphyssz) { 713 if (physsz < hwphyssz) { 714 phys_avail[j] = regions[i].mr_start; 715 phys_avail[j + 1] = regions[i].mr_start + 716 hwphyssz - physsz; 717 physsz = hwphyssz; 718 phys_avail_count++; 719 } 720 break; 721 } 722 phys_avail[j] = regions[i].mr_start; 723 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 724 phys_avail_count++; 725 physsz += regions[i].mr_size; 726 } 727 physmem = btoc(physsz); 728 729 /* 730 * Allocate PTEG table. 731 */ 732#ifdef PTEGCOUNT 733 moea_pteg_count = PTEGCOUNT; 734#else 735 moea_pteg_count = 0x1000; 736 737 while (moea_pteg_count < physmem) 738 moea_pteg_count <<= 1; 739 740 moea_pteg_count >>= 1; 741#endif /* PTEGCOUNT */ 742 743 size = moea_pteg_count * sizeof(struct pteg); 744 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 745 size); 746 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 747 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 748 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 749 moea_pteg_mask = moea_pteg_count - 1; 750 751 /* 752 * Allocate pv/overflow lists. 753 */ 754 size = sizeof(struct pvo_head) * moea_pteg_count; 755 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 756 PAGE_SIZE); 757 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 758 for (i = 0; i < moea_pteg_count; i++) 759 LIST_INIT(&moea_pvo_table[i]); 760 761 /* 762 * Initialize the lock that synchronizes access to the pteg and pvo 763 * tables. 764 */ 765 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF); 766 767 /* 768 * Allocate the message buffer. 769 */ 770 msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, 0); 771 772 /* 773 * Initialise the unmanaged pvo pool. 774 */ 775 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 776 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 777 moea_bpvo_pool_index = 0; 778 779 /* 780 * Make sure kernel vsid is allocated as well as VSID 0. 781 */ 782 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 783 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 784 moea_vsid_bitmap[0] |= 1; 785 786 /* 787 * Set up the Open Firmware pmap and add it's mappings. 788 */ 789 moea_pinit(mmup, &ofw_pmap); 790 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 791 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 792 if ((chosen = OF_finddevice("/chosen")) == -1) 793 panic("moea_bootstrap: can't find /chosen"); 794 OF_getprop(chosen, "mmu", &mmui, 4); 795 if ((mmu = OF_instance_to_package(mmui)) == -1) 796 panic("moea_bootstrap: can't get mmu package"); 797 if ((sz = OF_getproplen(mmu, "translations")) == -1) 798 panic("moea_bootstrap: can't get ofw translation count"); 799 translations = NULL; 800 for (i = 0; phys_avail[i] != 0; i += 2) { 801 if (phys_avail[i + 1] >= sz) { 802 translations = (struct ofw_map *)phys_avail[i]; 803 break; 804 } 805 } 806 if (translations == NULL) 807 panic("moea_bootstrap: no space to copy translations"); 808 bzero(translations, sz); 809 if (OF_getprop(mmu, "translations", translations, sz) == -1) 810 panic("moea_bootstrap: can't get ofw translations"); 811 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 812 sz /= sizeof(*translations); 813 qsort(translations, sz, sizeof (*translations), om_cmp); 814 for (i = 0, ofw_mappings = 0; i < sz; i++) { 815 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 816 translations[i].om_pa, translations[i].om_va, 817 translations[i].om_len); 818 819 /* 820 * If the mapping is 1:1, let the RAM and device on-demand 821 * BAT tables take care of the translation. 822 */ 823 if (translations[i].om_va == translations[i].om_pa) 824 continue; 825 826 /* Enter the pages */ 827 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 828 struct vm_page m; 829 830 m.phys_addr = translations[i].om_pa + off; 831 moea_enter(mmup, &ofw_pmap, 832 translations[i].om_va + off, &m, 833 VM_PROT_ALL, 1); 834 ofw_mappings++; 835 } 836 } 837#ifdef SMP 838 TLBSYNC(); 839#endif 840 841 /* 842 * Initialize the kernel pmap (which is statically allocated). 843 */ 844 PMAP_LOCK_INIT(kernel_pmap); 845 for (i = 0; i < 16; i++) { 846 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 847 } 848 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 849 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT; 850 kernel_pmap->pm_active = ~0; 851 852 /* 853 * Allocate a kernel stack with a guard page for thread0 and map it 854 * into the kernel page map. 855 */ 856 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0); 857 kstack0_phys = pa; 858 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE); 859 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", kstack0_phys, 860 kstack0); 861 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE; 862 for (i = 0; i < KSTACK_PAGES; i++) { 863 pa = kstack0_phys + i * PAGE_SIZE; 864 va = kstack0 + i * PAGE_SIZE; 865 moea_kenter(mmup, va, pa); 866 TLBIE(va); 867 } 868 869 /* 870 * Calculate the last available physical address. 871 */ 872 for (i = 0; phys_avail[i + 2] != 0; i += 2) 873 ; 874 Maxmem = powerpc_btop(phys_avail[i + 1]); 875 876 /* 877 * Allocate virtual address space for the message buffer. 878 */ 879 msgbufp = (struct msgbuf *)virtual_avail; 880 virtual_avail += round_page(MSGBUF_SIZE); 881 882 /* 883 * Initialize hardware. 884 */ 885 for (i = 0; i < 16; i++) { 886 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 887 } 888 __asm __volatile ("mtsr %0,%1" 889 :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 890 __asm __volatile ("mtsr %0,%1" 891 :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT)); 892 __asm __volatile ("sync; mtsdr1 %0; isync" 893 :: "r"((u_int)moea_pteg_table | (moea_pteg_mask >> 10))); 894 tlbia(); 895 896 pmap_bootstrapped++; 897} 898 899/* 900 * Activate a user pmap. The pmap must be activated before it's address 901 * space can be accessed in any way. 902 */ 903void 904moea_activate(mmu_t mmu, struct thread *td) 905{ 906 pmap_t pm, pmr; 907 908 /* 909 * Load all the data we need up front to encourage the compiler to 910 * not issue any loads while we have interrupts disabled below. 911 */ 912 pm = &td->td_proc->p_vmspace->vm_pmap; 913 914 if ((pmr = (pmap_t)moea_kextract(mmu, (vm_offset_t)pm)) == NULL) 915 pmr = pm; 916 917 pm->pm_active |= PCPU_GET(cpumask); 918 PCPU_SET(curpmap, pmr); 919} 920 921void 922moea_deactivate(mmu_t mmu, struct thread *td) 923{ 924 pmap_t pm; 925 926 pm = &td->td_proc->p_vmspace->vm_pmap; 927 pm->pm_active &= ~(PCPU_GET(cpumask)); 928 PCPU_SET(curpmap, NULL); 929} 930 931void 932moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 933{ 934 struct pvo_entry *pvo; 935 936 PMAP_LOCK(pm); 937 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 938 939 if (pvo != NULL) { 940 if (wired) { 941 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 942 pm->pm_stats.wired_count++; 943 pvo->pvo_vaddr |= PVO_WIRED; 944 } else { 945 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 946 pm->pm_stats.wired_count--; 947 pvo->pvo_vaddr &= ~PVO_WIRED; 948 } 949 } 950 PMAP_UNLOCK(pm); 951} 952 953void 954moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 955{ 956 vm_offset_t dst; 957 vm_offset_t src; 958 959 dst = VM_PAGE_TO_PHYS(mdst); 960 src = VM_PAGE_TO_PHYS(msrc); 961 962 kcopy((void *)src, (void *)dst, PAGE_SIZE); 963} 964 965/* 966 * Zero a page of physical memory by temporarily mapping it into the tlb. 967 */ 968void 969moea_zero_page(mmu_t mmu, vm_page_t m) 970{ 971 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 972 caddr_t va; 973 974 if (pa < SEGMENT_LENGTH) { 975 va = (caddr_t) pa; 976 } else if (moea_initialized) { 977 if (moea_pvo_zeropage == NULL) 978 moea_pvo_zeropage = moea_rkva_alloc(mmu); 979 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL); 980 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage); 981 } else { 982 panic("moea_zero_page: can't zero pa %#x", pa); 983 } 984 985 bzero(va, PAGE_SIZE); 986 987 if (pa >= SEGMENT_LENGTH) 988 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL); 989} 990 991void 992moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 993{ 994 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 995 caddr_t va; 996 997 if (pa < SEGMENT_LENGTH) { 998 va = (caddr_t) pa; 999 } else if (moea_initialized) { 1000 if (moea_pvo_zeropage == NULL) 1001 moea_pvo_zeropage = moea_rkva_alloc(mmu); 1002 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL); 1003 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage); 1004 } else { 1005 panic("moea_zero_page: can't zero pa %#x", pa); 1006 } 1007 1008 bzero(va + off, size); 1009 1010 if (pa >= SEGMENT_LENGTH) 1011 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL); 1012} 1013 1014void 1015moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1016{ 1017 1018 /* XXX this is called outside of Giant, is moea_zero_page safe? */ 1019 /* XXX maybe have a dedicated mapping for this to avoid the problem? */ 1020 mtx_lock(&Giant); 1021 moea_zero_page(mmu, m); 1022 mtx_unlock(&Giant); 1023} 1024 1025/* 1026 * Map the given physical page at the specified virtual address in the 1027 * target pmap with the protection requested. If specified the page 1028 * will be wired down. 1029 */ 1030void 1031moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1032 boolean_t wired) 1033{ 1034 struct pvo_head *pvo_head; 1035 uma_zone_t zone; 1036 vm_page_t pg; 1037 u_int pte_lo, pvo_flags, was_exec, i; 1038 int error; 1039 1040 if (!moea_initialized) { 1041 pvo_head = &moea_pvo_kunmanaged; 1042 zone = moea_upvo_zone; 1043 pvo_flags = 0; 1044 pg = NULL; 1045 was_exec = PTE_EXEC; 1046 } else { 1047 pvo_head = vm_page_to_pvoh(m); 1048 pg = m; 1049 zone = moea_mpvo_zone; 1050 pvo_flags = PVO_MANAGED; 1051 was_exec = 0; 1052 } 1053 if (pmap_bootstrapped) 1054 vm_page_lock_queues(); 1055 PMAP_LOCK(pmap); 1056 1057 /* XXX change the pvo head for fake pages */ 1058 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) 1059 pvo_head = &moea_pvo_kunmanaged; 1060 1061 /* 1062 * If this is a managed page, and it's the first reference to the page, 1063 * clear the execness of the page. Otherwise fetch the execness. 1064 */ 1065 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 1066 if (LIST_EMPTY(pvo_head)) { 1067 moea_attr_clear(pg, PTE_EXEC); 1068 } else { 1069 was_exec = moea_attr_fetch(pg) & PTE_EXEC; 1070 } 1071 } 1072 1073 /* 1074 * Assume the page is cache inhibited and access is guarded unless 1075 * it's in our available memory array. 1076 */ 1077 pte_lo = PTE_I | PTE_G; 1078 for (i = 0; i < pregions_sz; i++) { 1079 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 1080 (VM_PAGE_TO_PHYS(m) < 1081 (pregions[i].mr_start + pregions[i].mr_size))) { 1082 pte_lo &= ~(PTE_I | PTE_G); 1083 break; 1084 } 1085 } 1086 1087 if (prot & VM_PROT_WRITE) 1088 pte_lo |= PTE_BW; 1089 else 1090 pte_lo |= PTE_BR; 1091 1092 if (prot & VM_PROT_EXECUTE) 1093 pvo_flags |= PVO_EXECUTABLE; 1094 1095 if (wired) 1096 pvo_flags |= PVO_WIRED; 1097 1098 if ((m->flags & PG_FICTITIOUS) != 0) 1099 pvo_flags |= PVO_FAKE; 1100 1101 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1102 pte_lo, pvo_flags); 1103 1104 /* 1105 * Flush the real page from the instruction cache if this page is 1106 * mapped executable and cacheable and was not previously mapped (or 1107 * was not mapped executable). 1108 */ 1109 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1110 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1111 /* 1112 * Flush the real memory from the cache. 1113 */ 1114 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1115 if (pg != NULL) 1116 moea_attr_save(pg, PTE_EXEC); 1117 } 1118 if (pmap_bootstrapped) 1119 vm_page_unlock_queues(); 1120 1121 /* XXX syncicache always until problems are sorted */ 1122 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1123 PMAP_UNLOCK(pmap); 1124} 1125 1126vm_page_t 1127moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1128 vm_prot_t prot, vm_page_t mpte) 1129{ 1130 1131 vm_page_busy(m); 1132 vm_page_unlock_queues(); 1133 VM_OBJECT_UNLOCK(m->object); 1134 mtx_lock(&Giant); 1135 moea_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1136 FALSE); 1137 mtx_unlock(&Giant); 1138 VM_OBJECT_LOCK(m->object); 1139 vm_page_lock_queues(); 1140 vm_page_wakeup(m); 1141 return (NULL); 1142} 1143 1144vm_paddr_t 1145moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1146{ 1147 struct pvo_entry *pvo; 1148 vm_paddr_t pa; 1149 1150 PMAP_LOCK(pm); 1151 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1152 if (pvo == NULL) 1153 pa = 0; 1154 else 1155 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1156 PMAP_UNLOCK(pm); 1157 return (pa); 1158} 1159 1160/* 1161 * Atomically extract and hold the physical page with the given 1162 * pmap and virtual address pair if that mapping permits the given 1163 * protection. 1164 */ 1165vm_page_t 1166moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1167{ 1168 struct pvo_entry *pvo; 1169 vm_page_t m; 1170 1171 m = NULL; 1172 mtx_lock(&Giant); 1173 vm_page_lock_queues(); 1174 PMAP_LOCK(pmap); 1175 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1176 if (pvo != NULL && (pvo->pvo_pte.pte_hi & PTE_VALID) && 1177 ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_RW || 1178 (prot & VM_PROT_WRITE) == 0)) { 1179 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1180 vm_page_hold(m); 1181 } 1182 vm_page_unlock_queues(); 1183 PMAP_UNLOCK(pmap); 1184 mtx_unlock(&Giant); 1185 return (m); 1186} 1187 1188void 1189moea_init(mmu_t mmu) 1190{ 1191 1192 CTR0(KTR_PMAP, "moea_init"); 1193 1194 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1195 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1196 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1197 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1198 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1199 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1200 moea_initialized = TRUE; 1201} 1202 1203boolean_t 1204moea_is_modified(mmu_t mmu, vm_page_t m) 1205{ 1206 1207 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0) 1208 return (FALSE); 1209 1210 return (moea_query_bit(m, PTE_CHG)); 1211} 1212 1213void 1214moea_clear_reference(mmu_t mmu, vm_page_t m) 1215{ 1216 1217 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1218 return; 1219 moea_clear_bit(m, PTE_REF, NULL); 1220} 1221 1222void 1223moea_clear_modify(mmu_t mmu, vm_page_t m) 1224{ 1225 1226 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1227 return; 1228 moea_clear_bit(m, PTE_CHG, NULL); 1229} 1230 1231/* 1232 * moea_ts_referenced: 1233 * 1234 * Return a count of reference bits for a page, clearing those bits. 1235 * It is not necessary for every reference bit to be cleared, but it 1236 * is necessary that 0 only be returned when there are truly no 1237 * reference bits set. 1238 * 1239 * XXX: The exact number of bits to check and clear is a matter that 1240 * should be tested and standardized at some point in the future for 1241 * optimal aging of shared pages. 1242 */ 1243boolean_t 1244moea_ts_referenced(mmu_t mmu, vm_page_t m) 1245{ 1246 int count; 1247 1248 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1249 return (0); 1250 1251 count = moea_clear_bit(m, PTE_REF, NULL); 1252 1253 return (count); 1254} 1255 1256/* 1257 * Map a wired page into kernel virtual address space. 1258 */ 1259void 1260moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1261{ 1262 u_int pte_lo; 1263 int error; 1264 int i; 1265 1266#if 0 1267 if (va < VM_MIN_KERNEL_ADDRESS) 1268 panic("moea_kenter: attempt to enter non-kernel address %#x", 1269 va); 1270#endif 1271 1272 pte_lo = PTE_I | PTE_G; 1273 for (i = 0; i < pregions_sz; i++) { 1274 if ((pa >= pregions[i].mr_start) && 1275 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1276 pte_lo &= ~(PTE_I | PTE_G); 1277 break; 1278 } 1279 } 1280 1281 PMAP_LOCK(kernel_pmap); 1282 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1283 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1284 1285 if (error != 0 && error != ENOENT) 1286 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1287 pa, error); 1288 1289 /* 1290 * Flush the real memory from the instruction cache. 1291 */ 1292 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1293 moea_syncicache(pa, PAGE_SIZE); 1294 } 1295 PMAP_UNLOCK(kernel_pmap); 1296} 1297 1298/* 1299 * Extract the physical page address associated with the given kernel virtual 1300 * address. 1301 */ 1302vm_offset_t 1303moea_kextract(mmu_t mmu, vm_offset_t va) 1304{ 1305 struct pvo_entry *pvo; 1306 vm_paddr_t pa; 1307 1308#ifdef UMA_MD_SMALL_ALLOC 1309 /* 1310 * Allow direct mappings 1311 */ 1312 if (va < VM_MIN_KERNEL_ADDRESS) { 1313 return (va); 1314 } 1315#endif 1316 1317 PMAP_LOCK(kernel_pmap); 1318 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1319 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1320 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1321 PMAP_UNLOCK(kernel_pmap); 1322 return (pa); 1323} 1324 1325/* 1326 * Remove a wired page from kernel virtual address space. 1327 */ 1328void 1329moea_kremove(mmu_t mmu, vm_offset_t va) 1330{ 1331 1332 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1333} 1334 1335/* 1336 * Map a range of physical addresses into kernel virtual address space. 1337 * 1338 * The value passed in *virt is a suggested virtual address for the mapping. 1339 * Architectures which can support a direct-mapped physical to virtual region 1340 * can return the appropriate address within that region, leaving '*virt' 1341 * unchanged. We cannot and therefore do not; *virt is updated with the 1342 * first usable address after the mapped region. 1343 */ 1344vm_offset_t 1345moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1346 vm_offset_t pa_end, int prot) 1347{ 1348 vm_offset_t sva, va; 1349 1350 sva = *virt; 1351 va = sva; 1352 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1353 moea_kenter(mmu, va, pa_start); 1354 *virt = va; 1355 return (sva); 1356} 1357 1358/* 1359 * Lower the permission for all mappings to a given page. 1360 */ 1361void 1362moea_page_protect(mmu_t mmu, vm_page_t m, vm_prot_t prot) 1363{ 1364 struct pvo_head *pvo_head; 1365 struct pvo_entry *pvo, *next_pvo; 1366 struct pte *pt; 1367 pmap_t pmap; 1368 1369 /* 1370 * Since the routine only downgrades protection, if the 1371 * maximal protection is desired, there isn't any change 1372 * to be made. 1373 */ 1374 if ((prot & (VM_PROT_READ|VM_PROT_WRITE)) == 1375 (VM_PROT_READ|VM_PROT_WRITE)) 1376 return; 1377 1378 pvo_head = vm_page_to_pvoh(m); 1379 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1380 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1381 MOEA_PVO_CHECK(pvo); /* sanity check */ 1382 pmap = pvo->pvo_pmap; 1383 PMAP_LOCK(pmap); 1384 1385 /* 1386 * Downgrading to no mapping at all, we just remove the entry. 1387 */ 1388 if ((prot & VM_PROT_READ) == 0) { 1389 moea_pvo_remove(pvo, -1); 1390 PMAP_UNLOCK(pmap); 1391 continue; 1392 } 1393 1394 /* 1395 * If EXEC permission is being revoked, just clear the flag 1396 * in the PVO. 1397 */ 1398 if ((prot & VM_PROT_EXECUTE) == 0) 1399 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1400 1401 /* 1402 * If this entry is already RO, don't diddle with the page 1403 * table. 1404 */ 1405 if ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_BR) { 1406 PMAP_UNLOCK(pmap); 1407 MOEA_PVO_CHECK(pvo); 1408 continue; 1409 } 1410 1411 /* 1412 * Grab the PTE before we diddle the bits so pvo_to_pte can 1413 * verify the pte contents are as expected. 1414 */ 1415 pt = moea_pvo_to_pte(pvo, -1); 1416 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1417 pvo->pvo_pte.pte_lo |= PTE_BR; 1418 if (pt != NULL) 1419 moea_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1420 PMAP_UNLOCK(pmap); 1421 MOEA_PVO_CHECK(pvo); /* sanity check */ 1422 } 1423 1424 /* 1425 * Downgrading from writeable: clear the VM page flag 1426 */ 1427 if ((prot & VM_PROT_WRITE) != VM_PROT_WRITE) 1428 vm_page_flag_clear(m, PG_WRITEABLE); 1429} 1430 1431/* 1432 * Returns true if the pmap's pv is one of the first 1433 * 16 pvs linked to from this page. This count may 1434 * be changed upwards or downwards in the future; it 1435 * is only necessary that true be returned for a small 1436 * subset of pmaps for proper page aging. 1437 */ 1438boolean_t 1439moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1440{ 1441 int loops; 1442 struct pvo_entry *pvo; 1443 1444 if (!moea_initialized || (m->flags & PG_FICTITIOUS)) 1445 return FALSE; 1446 1447 loops = 0; 1448 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1449 if (pvo->pvo_pmap == pmap) 1450 return (TRUE); 1451 if (++loops >= 16) 1452 break; 1453 } 1454 1455 return (FALSE); 1456} 1457 1458static u_int moea_vsidcontext; 1459 1460void 1461moea_pinit(mmu_t mmu, pmap_t pmap) 1462{ 1463 int i, mask; 1464 u_int entropy; 1465 1466 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1467 PMAP_LOCK_INIT(pmap); 1468 1469 entropy = 0; 1470 __asm __volatile("mftb %0" : "=r"(entropy)); 1471 1472 /* 1473 * Allocate some segment registers for this pmap. 1474 */ 1475 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1476 u_int hash, n; 1477 1478 /* 1479 * Create a new value by mutiplying by a prime and adding in 1480 * entropy from the timebase register. This is to make the 1481 * VSID more random so that the PT hash function collides 1482 * less often. (Note that the prime casues gcc to do shifts 1483 * instead of a multiply.) 1484 */ 1485 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1486 hash = moea_vsidcontext & (NPMAPS - 1); 1487 if (hash == 0) /* 0 is special, avoid it */ 1488 continue; 1489 n = hash >> 5; 1490 mask = 1 << (hash & (VSID_NBPW - 1)); 1491 hash = (moea_vsidcontext & 0xfffff); 1492 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1493 /* anything free in this bucket? */ 1494 if (moea_vsid_bitmap[n] == 0xffffffff) { 1495 entropy = (moea_vsidcontext >> 20); 1496 continue; 1497 } 1498 i = ffs(~moea_vsid_bitmap[i]) - 1; 1499 mask = 1 << i; 1500 hash &= 0xfffff & ~(VSID_NBPW - 1); 1501 hash |= i; 1502 } 1503 moea_vsid_bitmap[n] |= mask; 1504 for (i = 0; i < 16; i++) 1505 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1506 return; 1507 } 1508 1509 panic("moea_pinit: out of segments"); 1510} 1511 1512/* 1513 * Initialize the pmap associated with process 0. 1514 */ 1515void 1516moea_pinit0(mmu_t mmu, pmap_t pm) 1517{ 1518 1519 moea_pinit(mmu, pm); 1520 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1521} 1522 1523/* 1524 * Set the physical protection on the specified range of this map as requested. 1525 */ 1526void 1527moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1528 vm_prot_t prot) 1529{ 1530 struct pvo_entry *pvo; 1531 struct pte *pt; 1532 int pteidx; 1533 1534 CTR4(KTR_PMAP, "moea_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1535 eva, prot); 1536 1537 1538 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1539 ("moea_protect: non current pmap")); 1540 1541 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1542 mtx_lock(&Giant); 1543 moea_remove(mmu, pm, sva, eva); 1544 mtx_unlock(&Giant); 1545 return; 1546 } 1547 1548 mtx_lock(&Giant); 1549 vm_page_lock_queues(); 1550 PMAP_LOCK(pm); 1551 for (; sva < eva; sva += PAGE_SIZE) { 1552 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1553 if (pvo == NULL) 1554 continue; 1555 1556 if ((prot & VM_PROT_EXECUTE) == 0) 1557 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1558 1559 /* 1560 * Grab the PTE pointer before we diddle with the cached PTE 1561 * copy. 1562 */ 1563 pt = moea_pvo_to_pte(pvo, pteidx); 1564 /* 1565 * Change the protection of the page. 1566 */ 1567 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1568 pvo->pvo_pte.pte_lo |= PTE_BR; 1569 1570 /* 1571 * If the PVO is in the page table, update that pte as well. 1572 */ 1573 if (pt != NULL) 1574 moea_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1575 } 1576 vm_page_unlock_queues(); 1577 PMAP_UNLOCK(pm); 1578 mtx_unlock(&Giant); 1579} 1580 1581/* 1582 * Map a list of wired pages into kernel virtual address space. This is 1583 * intended for temporary mappings which do not need page modification or 1584 * references recorded. Existing mappings in the region are overwritten. 1585 */ 1586void 1587moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1588{ 1589 vm_offset_t va; 1590 1591 va = sva; 1592 while (count-- > 0) { 1593 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1594 va += PAGE_SIZE; 1595 m++; 1596 } 1597} 1598 1599/* 1600 * Remove page mappings from kernel virtual address space. Intended for 1601 * temporary mappings entered by moea_qenter. 1602 */ 1603void 1604moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1605{ 1606 vm_offset_t va; 1607 1608 va = sva; 1609 while (count-- > 0) { 1610 moea_kremove(mmu, va); 1611 va += PAGE_SIZE; 1612 } 1613} 1614 1615void 1616moea_release(mmu_t mmu, pmap_t pmap) 1617{ 1618 int idx, mask; 1619 1620 /* 1621 * Free segment register's VSID 1622 */ 1623 if (pmap->pm_sr[0] == 0) 1624 panic("moea_release"); 1625 1626 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1627 mask = 1 << (idx % VSID_NBPW); 1628 idx /= VSID_NBPW; 1629 moea_vsid_bitmap[idx] &= ~mask; 1630 PMAP_LOCK_DESTROY(pmap); 1631} 1632 1633/* 1634 * Remove the given range of addresses from the specified map. 1635 */ 1636void 1637moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1638{ 1639 struct pvo_entry *pvo; 1640 int pteidx; 1641 1642 vm_page_lock_queues(); 1643 PMAP_LOCK(pm); 1644 for (; sva < eva; sva += PAGE_SIZE) { 1645 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1646 if (pvo != NULL) { 1647 moea_pvo_remove(pvo, pteidx); 1648 } 1649 } 1650 PMAP_UNLOCK(pm); 1651 vm_page_unlock_queues(); 1652} 1653 1654/* 1655 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1656 * will reflect changes in pte's back to the vm_page. 1657 */ 1658void 1659moea_remove_all(mmu_t mmu, vm_page_t m) 1660{ 1661 struct pvo_head *pvo_head; 1662 struct pvo_entry *pvo, *next_pvo; 1663 pmap_t pmap; 1664 1665 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1666 1667 pvo_head = vm_page_to_pvoh(m); 1668 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1669 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1670 1671 MOEA_PVO_CHECK(pvo); /* sanity check */ 1672 pmap = pvo->pvo_pmap; 1673 PMAP_LOCK(pmap); 1674 moea_pvo_remove(pvo, -1); 1675 PMAP_UNLOCK(pmap); 1676 } 1677 vm_page_flag_clear(m, PG_WRITEABLE); 1678} 1679 1680/* 1681 * Allocate a physical page of memory directly from the phys_avail map. 1682 * Can only be called from moea_bootstrap before avail start and end are 1683 * calculated. 1684 */ 1685static vm_offset_t 1686moea_bootstrap_alloc(vm_size_t size, u_int align) 1687{ 1688 vm_offset_t s, e; 1689 int i, j; 1690 1691 size = round_page(size); 1692 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1693 if (align != 0) 1694 s = (phys_avail[i] + align - 1) & ~(align - 1); 1695 else 1696 s = phys_avail[i]; 1697 e = s + size; 1698 1699 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1700 continue; 1701 1702 if (s == phys_avail[i]) { 1703 phys_avail[i] += size; 1704 } else if (e == phys_avail[i + 1]) { 1705 phys_avail[i + 1] -= size; 1706 } else { 1707 for (j = phys_avail_count * 2; j > i; j -= 2) { 1708 phys_avail[j] = phys_avail[j - 2]; 1709 phys_avail[j + 1] = phys_avail[j - 1]; 1710 } 1711 1712 phys_avail[i + 3] = phys_avail[i + 1]; 1713 phys_avail[i + 1] = s; 1714 phys_avail[i + 2] = e; 1715 phys_avail_count++; 1716 } 1717 1718 return (s); 1719 } 1720 panic("moea_bootstrap_alloc: could not allocate memory"); 1721} 1722 1723/* 1724 * Return an unmapped pvo for a kernel virtual address. 1725 * Used by pmap functions that operate on physical pages. 1726 */ 1727static struct pvo_entry * 1728moea_rkva_alloc(mmu_t mmu) 1729{ 1730 struct pvo_entry *pvo; 1731 struct pte *pt; 1732 vm_offset_t kva; 1733 int pteidx; 1734 1735 if (moea_rkva_count == 0) 1736 panic("moea_rkva_alloc: no more reserved KVAs"); 1737 1738 kva = moea_rkva_start + (PAGE_SIZE * --moea_rkva_count); 1739 moea_kenter(mmu, kva, 0); 1740 1741 pvo = moea_pvo_find_va(kernel_pmap, kva, &pteidx); 1742 1743 if (pvo == NULL) 1744 panic("moea_kva_alloc: moea_pvo_find_va failed"); 1745 1746 pt = moea_pvo_to_pte(pvo, pteidx); 1747 1748 if (pt == NULL) 1749 panic("moea_kva_alloc: moea_pvo_to_pte failed"); 1750 1751 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1752 PVO_PTEGIDX_CLR(pvo); 1753 1754 moea_pte_overflow++; 1755 1756 return (pvo); 1757} 1758 1759static void 1760moea_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt, 1761 int *depth_p) 1762{ 1763 struct pte *pt; 1764 1765 /* 1766 * If this pvo already has a valid pte, we need to save it so it can 1767 * be restored later. We then just reload the new PTE over the old 1768 * slot. 1769 */ 1770 if (saved_pt != NULL) { 1771 pt = moea_pvo_to_pte(pvo, -1); 1772 1773 if (pt != NULL) { 1774 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1775 PVO_PTEGIDX_CLR(pvo); 1776 moea_pte_overflow++; 1777 } 1778 1779 *saved_pt = pvo->pvo_pte; 1780 1781 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1782 } 1783 1784 pvo->pvo_pte.pte_lo |= pa; 1785 1786 if (!moea_pte_spill(pvo->pvo_vaddr)) 1787 panic("moea_pa_map: could not spill pvo %p", pvo); 1788 1789 if (depth_p != NULL) 1790 (*depth_p)++; 1791} 1792 1793static void 1794moea_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p) 1795{ 1796 struct pte *pt; 1797 1798 pt = moea_pvo_to_pte(pvo, -1); 1799 1800 if (pt != NULL) { 1801 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1802 PVO_PTEGIDX_CLR(pvo); 1803 moea_pte_overflow++; 1804 } 1805 1806 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1807 1808 /* 1809 * If there is a saved PTE and it's valid, restore it and return. 1810 */ 1811 if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) { 1812 if (depth_p != NULL && --(*depth_p) == 0) 1813 panic("moea_pa_unmap: restoring but depth == 0"); 1814 1815 pvo->pvo_pte = *saved_pt; 1816 1817 if (!moea_pte_spill(pvo->pvo_vaddr)) 1818 panic("moea_pa_unmap: could not spill pvo %p", pvo); 1819 } 1820} 1821 1822static void 1823moea_syncicache(vm_offset_t pa, vm_size_t len) 1824{ 1825 __syncicache((void *)pa, len); 1826} 1827 1828static void 1829tlbia(void) 1830{ 1831 caddr_t i; 1832 1833 SYNC(); 1834 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) { 1835 TLBIE(i); 1836 EIEIO(); 1837 } 1838 TLBSYNC(); 1839 SYNC(); 1840} 1841 1842static int 1843moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1844 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1845{ 1846 struct pvo_entry *pvo; 1847 u_int sr; 1848 int first; 1849 u_int ptegidx; 1850 int i; 1851 int bootstrap; 1852 1853 moea_pvo_enter_calls++; 1854 first = 0; 1855 bootstrap = 0; 1856 1857 /* 1858 * Compute the PTE Group index. 1859 */ 1860 va &= ~ADDR_POFF; 1861 sr = va_to_sr(pm->pm_sr, va); 1862 ptegidx = va_to_pteg(sr, va); 1863 1864 /* 1865 * Remove any existing mapping for this page. Reuse the pvo entry if 1866 * there is a mapping. 1867 */ 1868 mtx_lock(&moea_table_mutex); 1869 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1870 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1871 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa && 1872 (pvo->pvo_pte.pte_lo & PTE_PP) == 1873 (pte_lo & PTE_PP)) { 1874 mtx_unlock(&moea_table_mutex); 1875 return (0); 1876 } 1877 moea_pvo_remove(pvo, -1); 1878 break; 1879 } 1880 } 1881 1882 /* 1883 * If we aren't overwriting a mapping, try to allocate. 1884 */ 1885 if (moea_initialized) { 1886 pvo = uma_zalloc(zone, M_NOWAIT); 1887 } else { 1888 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1889 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1890 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1891 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1892 } 1893 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1894 moea_bpvo_pool_index++; 1895 bootstrap = 1; 1896 } 1897 1898 if (pvo == NULL) { 1899 mtx_unlock(&moea_table_mutex); 1900 return (ENOMEM); 1901 } 1902 1903 moea_pvo_entries++; 1904 pvo->pvo_vaddr = va; 1905 pvo->pvo_pmap = pm; 1906 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1907 pvo->pvo_vaddr &= ~ADDR_POFF; 1908 if (flags & VM_PROT_EXECUTE) 1909 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1910 if (flags & PVO_WIRED) 1911 pvo->pvo_vaddr |= PVO_WIRED; 1912 if (pvo_head != &moea_pvo_kunmanaged) 1913 pvo->pvo_vaddr |= PVO_MANAGED; 1914 if (bootstrap) 1915 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1916 if (flags & PVO_FAKE) 1917 pvo->pvo_vaddr |= PVO_FAKE; 1918 1919 moea_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo); 1920 1921 /* 1922 * Remember if the list was empty and therefore will be the first 1923 * item. 1924 */ 1925 if (LIST_FIRST(pvo_head) == NULL) 1926 first = 1; 1927 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1928 1929 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1930 pm->pm_stats.wired_count++; 1931 pm->pm_stats.resident_count++; 1932 1933 /* 1934 * We hope this succeeds but it isn't required. 1935 */ 1936 i = moea_pte_insert(ptegidx, &pvo->pvo_pte); 1937 if (i >= 0) { 1938 PVO_PTEGIDX_SET(pvo, i); 1939 } else { 1940 panic("moea_pvo_enter: overflow"); 1941 moea_pte_overflow++; 1942 } 1943 mtx_unlock(&moea_table_mutex); 1944 1945 return (first ? ENOENT : 0); 1946} 1947 1948static void 1949moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 1950{ 1951 struct pte *pt; 1952 1953 /* 1954 * If there is an active pte entry, we need to deactivate it (and 1955 * save the ref & cfg bits). 1956 */ 1957 pt = moea_pvo_to_pte(pvo, pteidx); 1958 if (pt != NULL) { 1959 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1960 PVO_PTEGIDX_CLR(pvo); 1961 } else { 1962 moea_pte_overflow--; 1963 } 1964 1965 /* 1966 * Update our statistics. 1967 */ 1968 pvo->pvo_pmap->pm_stats.resident_count--; 1969 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1970 pvo->pvo_pmap->pm_stats.wired_count--; 1971 1972 /* 1973 * Save the REF/CHG bits into their cache if the page is managed. 1974 */ 1975 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 1976 struct vm_page *pg; 1977 1978 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1979 if (pg != NULL) { 1980 moea_attr_save(pg, pvo->pvo_pte.pte_lo & 1981 (PTE_REF | PTE_CHG)); 1982 } 1983 } 1984 1985 /* 1986 * Remove this PVO from the PV list. 1987 */ 1988 LIST_REMOVE(pvo, pvo_vlink); 1989 1990 /* 1991 * Remove this from the overflow list and return it to the pool 1992 * if we aren't going to reuse it. 1993 */ 1994 LIST_REMOVE(pvo, pvo_olink); 1995 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 1996 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 1997 moea_upvo_zone, pvo); 1998 moea_pvo_entries--; 1999 moea_pvo_remove_calls++; 2000} 2001 2002static __inline int 2003moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2004{ 2005 int pteidx; 2006 2007 /* 2008 * We can find the actual pte entry without searching by grabbing 2009 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2010 * noticing the HID bit. 2011 */ 2012 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2013 if (pvo->pvo_pte.pte_hi & PTE_HID) 2014 pteidx ^= moea_pteg_mask * 8; 2015 2016 return (pteidx); 2017} 2018 2019static struct pvo_entry * 2020moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2021{ 2022 struct pvo_entry *pvo; 2023 int ptegidx; 2024 u_int sr; 2025 2026 va &= ~ADDR_POFF; 2027 sr = va_to_sr(pm->pm_sr, va); 2028 ptegidx = va_to_pteg(sr, va); 2029 2030 mtx_lock(&moea_table_mutex); 2031 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2032 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2033 if (pteidx_p) 2034 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2035 break; 2036 } 2037 } 2038 mtx_unlock(&moea_table_mutex); 2039 2040 return (pvo); 2041} 2042 2043static struct pte * 2044moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2045{ 2046 struct pte *pt; 2047 2048 /* 2049 * If we haven't been supplied the ptegidx, calculate it. 2050 */ 2051 if (pteidx == -1) { 2052 int ptegidx; 2053 u_int sr; 2054 2055 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2056 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2057 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2058 } 2059 2060 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2061 2062 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2063 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2064 "valid pte index", pvo); 2065 } 2066 2067 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2068 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2069 "pvo but no valid pte", pvo); 2070 } 2071 2072 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2073 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) { 2074 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2075 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2076 } 2077 2078 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2079 != 0) { 2080 panic("moea_pvo_to_pte: pvo %p pte does not match " 2081 "pte %p in moea_pteg_table", pvo, pt); 2082 } 2083 2084 return (pt); 2085 } 2086 2087 if (pvo->pvo_pte.pte_hi & PTE_VALID) { 2088 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2089 "moea_pteg_table but valid in pvo", pvo, pt); 2090 } 2091 2092 return (NULL); 2093} 2094 2095/* 2096 * XXX: THIS STUFF SHOULD BE IN pte.c? 2097 */ 2098int 2099moea_pte_spill(vm_offset_t addr) 2100{ 2101 struct pvo_entry *source_pvo, *victim_pvo; 2102 struct pvo_entry *pvo; 2103 int ptegidx, i, j; 2104 u_int sr; 2105 struct pteg *pteg; 2106 struct pte *pt; 2107 2108 moea_pte_spills++; 2109 2110 sr = mfsrin(addr); 2111 ptegidx = va_to_pteg(sr, addr); 2112 2113 /* 2114 * Have to substitute some entry. Use the primary hash for this. 2115 * Use low bits of timebase as random generator. 2116 */ 2117 pteg = &moea_pteg_table[ptegidx]; 2118 mtx_lock(&moea_table_mutex); 2119 __asm __volatile("mftb %0" : "=r"(i)); 2120 i &= 7; 2121 pt = &pteg->pt[i]; 2122 2123 source_pvo = NULL; 2124 victim_pvo = NULL; 2125 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2126 /* 2127 * We need to find a pvo entry for this address. 2128 */ 2129 MOEA_PVO_CHECK(pvo); 2130 if (source_pvo == NULL && 2131 moea_pte_match(&pvo->pvo_pte, sr, addr, 2132 pvo->pvo_pte.pte_hi & PTE_HID)) { 2133 /* 2134 * Now found an entry to be spilled into the pteg. 2135 * The PTE is now valid, so we know it's active. 2136 */ 2137 j = moea_pte_insert(ptegidx, &pvo->pvo_pte); 2138 2139 if (j >= 0) { 2140 PVO_PTEGIDX_SET(pvo, j); 2141 moea_pte_overflow--; 2142 MOEA_PVO_CHECK(pvo); 2143 mtx_unlock(&moea_table_mutex); 2144 return (1); 2145 } 2146 2147 source_pvo = pvo; 2148 2149 if (victim_pvo != NULL) 2150 break; 2151 } 2152 2153 /* 2154 * We also need the pvo entry of the victim we are replacing 2155 * so save the R & C bits of the PTE. 2156 */ 2157 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2158 moea_pte_compare(pt, &pvo->pvo_pte)) { 2159 victim_pvo = pvo; 2160 if (source_pvo != NULL) 2161 break; 2162 } 2163 } 2164 2165 if (source_pvo == NULL) { 2166 mtx_unlock(&moea_table_mutex); 2167 return (0); 2168 } 2169 2170 if (victim_pvo == NULL) { 2171 if ((pt->pte_hi & PTE_HID) == 0) 2172 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2173 "entry", pt); 2174 2175 /* 2176 * If this is a secondary PTE, we need to search it's primary 2177 * pvo bucket for the matching PVO. 2178 */ 2179 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2180 pvo_olink) { 2181 MOEA_PVO_CHECK(pvo); 2182 /* 2183 * We also need the pvo entry of the victim we are 2184 * replacing so save the R & C bits of the PTE. 2185 */ 2186 if (moea_pte_compare(pt, &pvo->pvo_pte)) { 2187 victim_pvo = pvo; 2188 break; 2189 } 2190 } 2191 2192 if (victim_pvo == NULL) 2193 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2194 "entry", pt); 2195 } 2196 2197 /* 2198 * We are invalidating the TLB entry for the EA we are replacing even 2199 * though it's valid. If we don't, we lose any ref/chg bit changes 2200 * contained in the TLB entry. 2201 */ 2202 source_pvo->pvo_pte.pte_hi &= ~PTE_HID; 2203 2204 moea_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr); 2205 moea_pte_set(pt, &source_pvo->pvo_pte); 2206 2207 PVO_PTEGIDX_CLR(victim_pvo); 2208 PVO_PTEGIDX_SET(source_pvo, i); 2209 moea_pte_replacements++; 2210 2211 MOEA_PVO_CHECK(victim_pvo); 2212 MOEA_PVO_CHECK(source_pvo); 2213 2214 mtx_unlock(&moea_table_mutex); 2215 return (1); 2216} 2217 2218static int 2219moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2220{ 2221 struct pte *pt; 2222 int i; 2223 2224 /* 2225 * First try primary hash. 2226 */ 2227 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2228 if ((pt->pte_hi & PTE_VALID) == 0) { 2229 pvo_pt->pte_hi &= ~PTE_HID; 2230 moea_pte_set(pt, pvo_pt); 2231 return (i); 2232 } 2233 } 2234 2235 /* 2236 * Now try secondary hash. 2237 */ 2238 ptegidx ^= moea_pteg_mask; 2239 ptegidx++; 2240 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2241 if ((pt->pte_hi & PTE_VALID) == 0) { 2242 pvo_pt->pte_hi |= PTE_HID; 2243 moea_pte_set(pt, pvo_pt); 2244 return (i); 2245 } 2246 } 2247 2248 panic("moea_pte_insert: overflow"); 2249 return (-1); 2250} 2251 2252static boolean_t 2253moea_query_bit(vm_page_t m, int ptebit) 2254{ 2255 struct pvo_entry *pvo; 2256 struct pte *pt; 2257 2258#if 0 2259 if (moea_attr_fetch(m) & ptebit) 2260 return (TRUE); 2261#endif 2262 2263 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2264 MOEA_PVO_CHECK(pvo); /* sanity check */ 2265 2266 /* 2267 * See if we saved the bit off. If so, cache it and return 2268 * success. 2269 */ 2270 if (pvo->pvo_pte.pte_lo & ptebit) { 2271 moea_attr_save(m, ptebit); 2272 MOEA_PVO_CHECK(pvo); /* sanity check */ 2273 return (TRUE); 2274 } 2275 } 2276 2277 /* 2278 * No luck, now go through the hard part of looking at the PTEs 2279 * themselves. Sync so that any pending REF/CHG bits are flushed to 2280 * the PTEs. 2281 */ 2282 SYNC(); 2283 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2284 MOEA_PVO_CHECK(pvo); /* sanity check */ 2285 2286 /* 2287 * See if this pvo has a valid PTE. if so, fetch the 2288 * REF/CHG bits from the valid PTE. If the appropriate 2289 * ptebit is set, cache it and return success. 2290 */ 2291 pt = moea_pvo_to_pte(pvo, -1); 2292 if (pt != NULL) { 2293 moea_pte_synch(pt, &pvo->pvo_pte); 2294 if (pvo->pvo_pte.pte_lo & ptebit) { 2295 moea_attr_save(m, ptebit); 2296 MOEA_PVO_CHECK(pvo); /* sanity check */ 2297 return (TRUE); 2298 } 2299 } 2300 } 2301 2302 return (FALSE); 2303} 2304 2305static u_int 2306moea_clear_bit(vm_page_t m, int ptebit, int *origbit) 2307{ 2308 u_int count; 2309 struct pvo_entry *pvo; 2310 struct pte *pt; 2311 int rv; 2312 2313 /* 2314 * Clear the cached value. 2315 */ 2316 rv = moea_attr_fetch(m); 2317 moea_attr_clear(m, ptebit); 2318 2319 /* 2320 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2321 * we can reset the right ones). note that since the pvo entries and 2322 * list heads are accessed via BAT0 and are never placed in the page 2323 * table, we don't have to worry about further accesses setting the 2324 * REF/CHG bits. 2325 */ 2326 SYNC(); 2327 2328 /* 2329 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2330 * valid pte clear the ptebit from the valid pte. 2331 */ 2332 count = 0; 2333 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2334 MOEA_PVO_CHECK(pvo); /* sanity check */ 2335 pt = moea_pvo_to_pte(pvo, -1); 2336 if (pt != NULL) { 2337 moea_pte_synch(pt, &pvo->pvo_pte); 2338 if (pvo->pvo_pte.pte_lo & ptebit) { 2339 count++; 2340 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2341 } 2342 } 2343 rv |= pvo->pvo_pte.pte_lo; 2344 pvo->pvo_pte.pte_lo &= ~ptebit; 2345 MOEA_PVO_CHECK(pvo); /* sanity check */ 2346 } 2347 2348 if (origbit != NULL) { 2349 *origbit = rv; 2350 } 2351 2352 return (count); 2353} 2354 2355/* 2356 * Return true if the physical range is encompassed by the battable[idx] 2357 */ 2358static int 2359moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2360{ 2361 u_int prot; 2362 u_int32_t start; 2363 u_int32_t end; 2364 u_int32_t bat_ble; 2365 2366 /* 2367 * Return immediately if not a valid mapping 2368 */ 2369 if (!battable[idx].batu & BAT_Vs) 2370 return (EINVAL); 2371 2372 /* 2373 * The BAT entry must be cache-inhibited, guarded, and r/w 2374 * so it can function as an i/o page 2375 */ 2376 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2377 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2378 return (EPERM); 2379 2380 /* 2381 * The address should be within the BAT range. Assume that the 2382 * start address in the BAT has the correct alignment (thus 2383 * not requiring masking) 2384 */ 2385 start = battable[idx].batl & BAT_PBS; 2386 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2387 end = start | (bat_ble << 15) | 0x7fff; 2388 2389 if ((pa < start) || ((pa + size) > end)) 2390 return (ERANGE); 2391 2392 return (0); 2393} 2394 2395boolean_t 2396moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2397{ 2398 int i; 2399 2400 /* 2401 * This currently does not work for entries that 2402 * overlap 256M BAT segments. 2403 */ 2404 2405 for(i = 0; i < 16; i++) 2406 if (moea_bat_mapped(i, pa, size) == 0) 2407 return (0); 2408 2409 return (EFAULT); 2410} 2411 2412/* 2413 * Map a set of physical memory pages into the kernel virtual 2414 * address space. Return a pointer to where it is mapped. This 2415 * routine is intended to be used for mapping device memory, 2416 * NOT real memory. 2417 */ 2418void * 2419moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2420{ 2421 vm_offset_t va, tmpva, ppa, offset; 2422 int i; 2423 2424 ppa = trunc_page(pa); 2425 offset = pa & PAGE_MASK; 2426 size = roundup(offset + size, PAGE_SIZE); 2427 2428 GIANT_REQUIRED; 2429 2430 /* 2431 * If the physical address lies within a valid BAT table entry, 2432 * return the 1:1 mapping. This currently doesn't work 2433 * for regions that overlap 256M BAT segments. 2434 */ 2435 for (i = 0; i < 16; i++) { 2436 if (moea_bat_mapped(i, pa, size) == 0) 2437 return ((void *) pa); 2438 } 2439 2440 va = kmem_alloc_nofault(kernel_map, size); 2441 if (!va) 2442 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2443 2444 for (tmpva = va; size > 0;) { 2445 moea_kenter(mmu, tmpva, ppa); 2446 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */ 2447 size -= PAGE_SIZE; 2448 tmpva += PAGE_SIZE; 2449 ppa += PAGE_SIZE; 2450 } 2451 2452 return ((void *)(va + offset)); 2453} 2454 2455void 2456moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2457{ 2458 vm_offset_t base, offset; 2459 2460 /* 2461 * If this is outside kernel virtual space, then it's a 2462 * battable entry and doesn't require unmapping 2463 */ 2464 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2465 base = trunc_page(va); 2466 offset = va & PAGE_MASK; 2467 size = roundup(offset + size, PAGE_SIZE); 2468 kmem_free(kernel_map, base, size); 2469 } 2470} 2471