mmu_oea.c revision 103604
1/* 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/* 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68/* 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93#ifndef lint 94static const char rcsid[] = 95 "$FreeBSD: head/sys/powerpc/aim/mmu_oea.c 103604 2002-09-19 04:36:20Z grehan $"; 96#endif /* not lint */ 97 98/* 99 * Manages physical address maps. 100 * 101 * In addition to hardware address maps, this module is called upon to 102 * provide software-use-only maps which may or may not be stored in the 103 * same form as hardware maps. These pseudo-maps are used to store 104 * intermediate results from copy operations to and from address spaces. 105 * 106 * Since the information managed by this module is also stored by the 107 * logical address mapping module, this module may throw away valid virtual 108 * to physical mappings at almost any time. However, invalidations of 109 * mappings must be done as requested. 110 * 111 * In order to cope with hardware architectures which make virtual to 112 * physical map invalidates expensive, this module may delay invalidate 113 * reduced protection operations until such time as they are actually 114 * necessary. This module is given full information as to which processors 115 * are currently using which maps, and to when physical maps must be made 116 * correct. 117 */ 118 119#include <sys/param.h> 120#include <sys/kernel.h> 121#include <sys/ktr.h> 122#include <sys/lock.h> 123#include <sys/msgbuf.h> 124#include <sys/mutex.h> 125#include <sys/proc.h> 126#include <sys/sysctl.h> 127#include <sys/systm.h> 128#include <sys/vmmeter.h> 129 130#include <dev/ofw/openfirm.h> 131 132#include <vm/vm.h> 133#include <vm/vm_param.h> 134#include <vm/vm_kern.h> 135#include <vm/vm_page.h> 136#include <vm/vm_map.h> 137#include <vm/vm_object.h> 138#include <vm/vm_extern.h> 139#include <vm/vm_pageout.h> 140#include <vm/vm_pager.h> 141#include <vm/uma.h> 142 143#include <machine/powerpc.h> 144#include <machine/bat.h> 145#include <machine/frame.h> 146#include <machine/md_var.h> 147#include <machine/psl.h> 148#include <machine/pte.h> 149#include <machine/sr.h> 150 151#define PMAP_DEBUG 152 153#define TODO panic("%s: not implemented", __func__); 154 155#define PMAP_LOCK(pm) 156#define PMAP_UNLOCK(pm) 157 158#define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va)) 159#define TLBSYNC() __asm __volatile("tlbsync"); 160#define SYNC() __asm __volatile("sync"); 161#define EIEIO() __asm __volatile("eieio"); 162 163#define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 164#define VSID_TO_SR(vsid) ((vsid) & 0xf) 165#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 166 167#define PVO_PTEGIDX_MASK 0x0007 /* which PTEG slot */ 168#define PVO_PTEGIDX_VALID 0x0008 /* slot is valid */ 169#define PVO_WIRED 0x0010 /* PVO entry is wired */ 170#define PVO_MANAGED 0x0020 /* PVO entry is managed */ 171#define PVO_EXECUTABLE 0x0040 /* PVO entry is executable */ 172#define PVO_BOOTSTRAP 0x0080 /* PVO entry allocated during 173 bootstrap */ 174#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) 175#define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE) 176#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) 177#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) 178#define PVO_PTEGIDX_CLR(pvo) \ 179 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) 180#define PVO_PTEGIDX_SET(pvo, i) \ 181 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) 182 183#define PMAP_PVO_CHECK(pvo) 184 185struct ofw_map { 186 vm_offset_t om_va; 187 vm_size_t om_len; 188 vm_offset_t om_pa; 189 u_int om_mode; 190}; 191 192int pmap_bootstrapped = 0; 193 194/* 195 * Virtual and physical address of message buffer. 196 */ 197struct msgbuf *msgbufp; 198vm_offset_t msgbuf_phys; 199 200/* 201 * Physical addresses of first and last available physical page. 202 */ 203vm_offset_t avail_start; 204vm_offset_t avail_end; 205 206/* 207 * Map of physical memory regions. 208 */ 209vm_offset_t phys_avail[128]; 210u_int phys_avail_count; 211static struct mem_region *regions; 212static struct mem_region *pregions; 213int regions_sz, pregions_sz; 214static struct ofw_map *translations; 215 216/* 217 * First and last available kernel virtual addresses. 218 */ 219vm_offset_t virtual_avail; 220vm_offset_t virtual_end; 221vm_offset_t kernel_vm_end; 222 223/* 224 * Kernel pmap. 225 */ 226struct pmap kernel_pmap_store; 227extern struct pmap ofw_pmap; 228 229/* 230 * PTEG data. 231 */ 232static struct pteg *pmap_pteg_table; 233u_int pmap_pteg_count; 234u_int pmap_pteg_mask; 235 236/* 237 * PVO data. 238 */ 239struct pvo_head *pmap_pvo_table; /* pvo entries by pteg index */ 240struct pvo_head pmap_pvo_kunmanaged = 241 LIST_HEAD_INITIALIZER(pmap_pvo_kunmanaged); /* list of unmanaged pages */ 242struct pvo_head pmap_pvo_unmanaged = 243 LIST_HEAD_INITIALIZER(pmap_pvo_unmanaged); /* list of unmanaged pages */ 244 245uma_zone_t pmap_upvo_zone; /* zone for pvo entries for unmanaged pages */ 246uma_zone_t pmap_mpvo_zone; /* zone for pvo entries for managed pages */ 247struct vm_object pmap_upvo_zone_obj; 248struct vm_object pmap_mpvo_zone_obj; 249static vm_object_t pmap_pvo_obj; 250static u_int pmap_pvo_count; 251 252#define BPVO_POOL_SIZE 32768 253static struct pvo_entry *pmap_bpvo_pool; 254static int pmap_bpvo_pool_index = 0; 255 256#define VSID_NBPW (sizeof(u_int32_t) * 8) 257static u_int pmap_vsid_bitmap[NPMAPS / VSID_NBPW]; 258 259static boolean_t pmap_initialized = FALSE; 260 261/* 262 * Statistics. 263 */ 264u_int pmap_pte_valid = 0; 265u_int pmap_pte_overflow = 0; 266u_int pmap_pte_replacements = 0; 267u_int pmap_pvo_entries = 0; 268u_int pmap_pvo_enter_calls = 0; 269u_int pmap_pvo_remove_calls = 0; 270u_int pmap_pte_spills = 0; 271SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_valid, CTLFLAG_RD, &pmap_pte_valid, 272 0, ""); 273SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_overflow, CTLFLAG_RD, 274 &pmap_pte_overflow, 0, ""); 275SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_replacements, CTLFLAG_RD, 276 &pmap_pte_replacements, 0, ""); 277SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_entries, CTLFLAG_RD, &pmap_pvo_entries, 278 0, ""); 279SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_enter_calls, CTLFLAG_RD, 280 &pmap_pvo_enter_calls, 0, ""); 281SYSCTL_INT(_machdep, OID_AUTO, pmap_pvo_remove_calls, CTLFLAG_RD, 282 &pmap_pvo_remove_calls, 0, ""); 283SYSCTL_INT(_machdep, OID_AUTO, pmap_pte_spills, CTLFLAG_RD, 284 &pmap_pte_spills, 0, ""); 285 286struct pvo_entry *pmap_pvo_zeropage; 287 288vm_offset_t pmap_rkva_start = VM_MIN_KERNEL_ADDRESS; 289u_int pmap_rkva_count = 4; 290 291/* 292 * Allocate physical memory for use in pmap_bootstrap. 293 */ 294static vm_offset_t pmap_bootstrap_alloc(vm_size_t, u_int); 295 296/* 297 * PTE calls. 298 */ 299static int pmap_pte_insert(u_int, struct pte *); 300 301/* 302 * PVO calls. 303 */ 304static int pmap_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 305 vm_offset_t, vm_offset_t, u_int, int); 306static void pmap_pvo_remove(struct pvo_entry *, int); 307static struct pvo_entry *pmap_pvo_find_va(pmap_t, vm_offset_t, int *); 308static struct pte *pmap_pvo_to_pte(const struct pvo_entry *, int); 309 310/* 311 * Utility routines. 312 */ 313static void * pmap_pvo_allocf(uma_zone_t, int, u_int8_t *, int); 314static struct pvo_entry *pmap_rkva_alloc(void); 315static void pmap_pa_map(struct pvo_entry *, vm_offset_t, 316 struct pte *, int *); 317static void pmap_pa_unmap(struct pvo_entry *, struct pte *, int *); 318static void pmap_syncicache(vm_offset_t, vm_size_t); 319static boolean_t pmap_query_bit(vm_page_t, int); 320static boolean_t pmap_clear_bit(vm_page_t, int); 321static void tlbia(void); 322 323static __inline int 324va_to_sr(u_int *sr, vm_offset_t va) 325{ 326 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 327} 328 329static __inline u_int 330va_to_pteg(u_int sr, vm_offset_t addr) 331{ 332 u_int hash; 333 334 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 335 ADDR_PIDX_SHFT); 336 return (hash & pmap_pteg_mask); 337} 338 339static __inline struct pvo_head * 340pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p) 341{ 342 struct vm_page *pg; 343 344 pg = PHYS_TO_VM_PAGE(pa); 345 346 if (pg_p != NULL) 347 *pg_p = pg; 348 349 if (pg == NULL) 350 return (&pmap_pvo_unmanaged); 351 352 return (&pg->md.mdpg_pvoh); 353} 354 355static __inline struct pvo_head * 356vm_page_to_pvoh(vm_page_t m) 357{ 358 359 return (&m->md.mdpg_pvoh); 360} 361 362static __inline void 363pmap_attr_clear(vm_page_t m, int ptebit) 364{ 365 366 m->md.mdpg_attrs &= ~ptebit; 367} 368 369static __inline int 370pmap_attr_fetch(vm_page_t m) 371{ 372 373 return (m->md.mdpg_attrs); 374} 375 376static __inline void 377pmap_attr_save(vm_page_t m, int ptebit) 378{ 379 380 m->md.mdpg_attrs |= ptebit; 381} 382 383static __inline int 384pmap_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 385{ 386 if (pt->pte_hi == pvo_pt->pte_hi) 387 return (1); 388 389 return (0); 390} 391 392static __inline int 393pmap_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 394{ 395 return (pt->pte_hi & ~PTE_VALID) == 396 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 397 ((va >> ADDR_API_SHFT) & PTE_API) | which); 398} 399 400static __inline void 401pmap_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 402{ 403 /* 404 * Construct a PTE. Default to IMB initially. Valid bit only gets 405 * set when the real pte is set in memory. 406 * 407 * Note: Don't set the valid bit for correct operation of tlb update. 408 */ 409 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 410 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 411 pt->pte_lo = pte_lo; 412} 413 414static __inline void 415pmap_pte_synch(struct pte *pt, struct pte *pvo_pt) 416{ 417 418 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 419} 420 421static __inline void 422pmap_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 423{ 424 425 /* 426 * As shown in Section 7.6.3.2.3 427 */ 428 pt->pte_lo &= ~ptebit; 429 TLBIE(va); 430 EIEIO(); 431 TLBSYNC(); 432 SYNC(); 433} 434 435static __inline void 436pmap_pte_set(struct pte *pt, struct pte *pvo_pt) 437{ 438 439 pvo_pt->pte_hi |= PTE_VALID; 440 441 /* 442 * Update the PTE as defined in section 7.6.3.1. 443 * Note that the REF/CHG bits are from pvo_pt and thus should havce 444 * been saved so this routine can restore them (if desired). 445 */ 446 pt->pte_lo = pvo_pt->pte_lo; 447 EIEIO(); 448 pt->pte_hi = pvo_pt->pte_hi; 449 SYNC(); 450 pmap_pte_valid++; 451} 452 453static __inline void 454pmap_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 455{ 456 457 pvo_pt->pte_hi &= ~PTE_VALID; 458 459 /* 460 * Force the reg & chg bits back into the PTEs. 461 */ 462 SYNC(); 463 464 /* 465 * Invalidate the pte. 466 */ 467 pt->pte_hi &= ~PTE_VALID; 468 469 SYNC(); 470 TLBIE(va); 471 EIEIO(); 472 TLBSYNC(); 473 SYNC(); 474 475 /* 476 * Save the reg & chg bits. 477 */ 478 pmap_pte_synch(pt, pvo_pt); 479 pmap_pte_valid--; 480} 481 482static __inline void 483pmap_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 484{ 485 486 /* 487 * Invalidate the PTE 488 */ 489 pmap_pte_unset(pt, pvo_pt, va); 490 pmap_pte_set(pt, pvo_pt); 491} 492 493/* 494 * Quick sort callout for comparing memory regions. 495 */ 496static int mr_cmp(const void *a, const void *b); 497static int om_cmp(const void *a, const void *b); 498 499static int 500mr_cmp(const void *a, const void *b) 501{ 502 const struct mem_region *regiona; 503 const struct mem_region *regionb; 504 505 regiona = a; 506 regionb = b; 507 if (regiona->mr_start < regionb->mr_start) 508 return (-1); 509 else if (regiona->mr_start > regionb->mr_start) 510 return (1); 511 else 512 return (0); 513} 514 515static int 516om_cmp(const void *a, const void *b) 517{ 518 const struct ofw_map *mapa; 519 const struct ofw_map *mapb; 520 521 mapa = a; 522 mapb = b; 523 if (mapa->om_pa < mapb->om_pa) 524 return (-1); 525 else if (mapa->om_pa > mapb->om_pa) 526 return (1); 527 else 528 return (0); 529} 530 531void 532pmap_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 533{ 534 ihandle_t mmui; 535 phandle_t chosen, mmu; 536 int sz; 537 int i, j; 538 int ofw_mappings; 539 vm_size_t size, physsz; 540 vm_offset_t pa, va, off; 541 u_int batl, batu; 542 543 /* 544 * Set up BAT0 to map the lowest 256 MB area 545 */ 546 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 547 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 548 549 /* 550 * Map PCI memory space. 551 */ 552 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 553 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 554 555 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 556 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 557 558 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 559 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 560 561 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 562 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 563 564 /* 565 * Map obio devices. 566 */ 567 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 568 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 569 570 /* 571 * Use an IBAT and a DBAT to map the bottom segment of memory 572 * where we are. 573 */ 574 batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 575 batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 576 __asm ("mtibatu 0,%0; mtibatl 0,%1; mtdbatu 0,%0; mtdbatl 0,%1" 577 :: "r"(batu), "r"(batl)); 578 579#if 0 580 /* map frame buffer */ 581 batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 582 batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 583 __asm ("mtdbatu 1,%0; mtdbatl 1,%1" 584 :: "r"(batu), "r"(batl)); 585#endif 586 587#if 1 588 /* map pci space */ 589 batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 590 batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 591 __asm ("mtdbatu 1,%0; mtdbatl 1,%1" 592 :: "r"(batu), "r"(batl)); 593#endif 594 595 /* 596 * Set the start and end of kva. 597 */ 598 virtual_avail = VM_MIN_KERNEL_ADDRESS; 599 virtual_end = VM_MAX_KERNEL_ADDRESS; 600 601 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 602 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory"); 603 604 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 605 for (i = 0; i < pregions_sz; i++) { 606 vm_offset_t pa; 607 vm_offset_t end; 608 609 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 610 pregions[i].mr_start, 611 pregions[i].mr_start + pregions[i].mr_size, 612 pregions[i].mr_size); 613 /* 614 * Install entries into the BAT table to allow all 615 * of physmem to be convered by on-demand BAT entries. 616 * The loop will sometimes set the same battable element 617 * twice, but that's fine since they won't be used for 618 * a while yet. 619 */ 620 pa = pregions[i].mr_start & 0xf0000000; 621 end = pregions[i].mr_start + pregions[i].mr_size; 622 do { 623 u_int n = pa >> ADDR_SR_SHFT; 624 625 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 626 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 627 pa += SEGMENT_LENGTH; 628 } while (pa < end); 629 } 630 631 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 632 panic("pmap_bootstrap: phys_avail too small"); 633 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 634 phys_avail_count = 0; 635 physsz = 0; 636 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 637 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 638 regions[i].mr_start + regions[i].mr_size, 639 regions[i].mr_size); 640 phys_avail[j] = regions[i].mr_start; 641 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 642 phys_avail_count++; 643 physsz += regions[i].mr_size; 644 } 645 physmem = btoc(physsz); 646 647 /* 648 * Allocate PTEG table. 649 */ 650#ifdef PTEGCOUNT 651 pmap_pteg_count = PTEGCOUNT; 652#else 653 pmap_pteg_count = 0x1000; 654 655 while (pmap_pteg_count < physmem) 656 pmap_pteg_count <<= 1; 657 658 pmap_pteg_count >>= 1; 659#endif /* PTEGCOUNT */ 660 661 size = pmap_pteg_count * sizeof(struct pteg); 662 CTR2(KTR_PMAP, "pmap_bootstrap: %d PTEGs, %d bytes", pmap_pteg_count, 663 size); 664 pmap_pteg_table = (struct pteg *)pmap_bootstrap_alloc(size, size); 665 CTR1(KTR_PMAP, "pmap_bootstrap: PTEG table at %p", pmap_pteg_table); 666 bzero((void *)pmap_pteg_table, pmap_pteg_count * sizeof(struct pteg)); 667 pmap_pteg_mask = pmap_pteg_count - 1; 668 669 /* 670 * Allocate pv/overflow lists. 671 */ 672 size = sizeof(struct pvo_head) * pmap_pteg_count; 673 pmap_pvo_table = (struct pvo_head *)pmap_bootstrap_alloc(size, 674 PAGE_SIZE); 675 CTR1(KTR_PMAP, "pmap_bootstrap: PVO table at %p", pmap_pvo_table); 676 for (i = 0; i < pmap_pteg_count; i++) 677 LIST_INIT(&pmap_pvo_table[i]); 678 679 /* 680 * Allocate the message buffer. 681 */ 682 msgbuf_phys = pmap_bootstrap_alloc(MSGBUF_SIZE, 0); 683 684 /* 685 * Initialise the unmanaged pvo pool. 686 */ 687 pmap_bpvo_pool = (struct pvo_entry *)pmap_bootstrap_alloc( 688 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 689 pmap_bpvo_pool_index = 0; 690 691 /* 692 * Make sure kernel vsid is allocated as well as VSID 0. 693 */ 694 pmap_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 695 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 696 pmap_vsid_bitmap[0] |= 1; 697 698 /* 699 * Set up the OpenFirmware pmap and add it's mappings. 700 */ 701 pmap_pinit(&ofw_pmap); 702 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 703 if ((chosen = OF_finddevice("/chosen")) == -1) 704 panic("pmap_bootstrap: can't find /chosen"); 705 OF_getprop(chosen, "mmu", &mmui, 4); 706 if ((mmu = OF_instance_to_package(mmui)) == -1) 707 panic("pmap_bootstrap: can't get mmu package"); 708 if ((sz = OF_getproplen(mmu, "translations")) == -1) 709 panic("pmap_bootstrap: can't get ofw translation count"); 710 translations = NULL; 711 for (i = 0; phys_avail[i + 2] != 0; i += 2) { 712 if (phys_avail[i + 1] >= sz) 713 translations = (struct ofw_map *)phys_avail[i]; 714 } 715 if (translations == NULL) 716 panic("pmap_bootstrap: no space to copy translations"); 717 bzero(translations, sz); 718 if (OF_getprop(mmu, "translations", translations, sz) == -1) 719 panic("pmap_bootstrap: can't get ofw translations"); 720 CTR0(KTR_PMAP, "pmap_bootstrap: translations"); 721 sz /= sizeof(*translations); 722 qsort(translations, sz, sizeof (*translations), om_cmp); 723 for (i = 0, ofw_mappings = 0; i < sz; i++) { 724 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 725 translations[i].om_pa, translations[i].om_va, 726 translations[i].om_len); 727 728 /* 729 * If the mapping is 1:1, let the RAM and device on-demand 730 * BAT tables take care of the translation. 731 */ 732 if (translations[i].om_va == translations[i].om_pa) 733 continue; 734 735 /* Enter the pages */ 736 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 737 struct vm_page m; 738 739 m.phys_addr = translations[i].om_pa + off; 740 pmap_enter(&ofw_pmap, translations[i].om_va + off, &m, 741 VM_PROT_ALL, 1); 742 ofw_mappings++; 743 } 744 } 745#ifdef SMP 746 TLBSYNC(); 747#endif 748 749 /* 750 * Initialize the kernel pmap (which is statically allocated). 751 */ 752 for (i = 0; i < 16; i++) { 753 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT; 754 } 755 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT; 756 kernel_pmap->pm_active = ~0; 757 758 /* 759 * Allocate a kernel stack with a guard page for thread0 and map it 760 * into the kernel page map. 761 */ 762 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0); 763 kstack0_phys = pa; 764 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE); 765 CTR2(KTR_PMAP, "pmap_bootstrap: kstack0 at %#x (%#x)", kstack0_phys, 766 kstack0); 767 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE; 768 for (i = 0; i < KSTACK_PAGES; i++) { 769 pa = kstack0_phys + i * PAGE_SIZE; 770 va = kstack0 + i * PAGE_SIZE; 771 pmap_kenter(va, pa); 772 TLBIE(va); 773 } 774 775 /* 776 * Calculate the first and last available physical addresses. 777 */ 778 avail_start = phys_avail[0]; 779 for (i = 0; phys_avail[i + 2] != 0; i += 2) 780 ; 781 avail_end = phys_avail[i + 1]; 782 Maxmem = powerpc_btop(avail_end); 783 784 /* 785 * Allocate virtual address space for the message buffer. 786 */ 787 msgbufp = (struct msgbuf *)virtual_avail; 788 virtual_avail += round_page(MSGBUF_SIZE); 789 790 /* 791 * Initialize hardware. 792 */ 793 for (i = 0; i < 16; i++) { 794 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT); 795 } 796 __asm __volatile ("mtsr %0,%1" 797 :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT)); 798 __asm __volatile ("sync; mtsdr1 %0; isync" 799 :: "r"((u_int)pmap_pteg_table | (pmap_pteg_mask >> 10))); 800 tlbia(); 801 802 pmap_bootstrapped++; 803} 804 805/* 806 * Activate a user pmap. The pmap must be activated before it's address 807 * space can be accessed in any way. 808 */ 809void 810pmap_activate(struct thread *td) 811{ 812 pmap_t pm, pmr; 813 814 /* 815 * Load all the data we need up front to encourage the compiler to 816 * not issue any loads while we have interrupts disabled below. 817 */ 818 pm = &td->td_proc->p_vmspace->vm_pmap; 819 820 if ((pmr = (pmap_t)pmap_kextract((vm_offset_t)pm)) == NULL) 821 pmr = pm; 822 823 pm->pm_active |= PCPU_GET(cpumask); 824 PCPU_SET(curpmap, pmr); 825} 826 827void 828pmap_deactivate(struct thread *td) 829{ 830 pmap_t pm; 831 832 pm = &td->td_proc->p_vmspace->vm_pmap; 833 pm->pm_active &= ~(PCPU_GET(cpumask)); 834 PCPU_SET(curpmap, NULL); 835} 836 837vm_offset_t 838pmap_addr_hint(vm_object_t object, vm_offset_t va, vm_size_t size) 839{ 840 841 return (va); 842} 843 844void 845pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired) 846{ 847 struct pvo_entry *pvo; 848 849 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 850 851 if (pvo != NULL) { 852 if (wired) { 853 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 854 pm->pm_stats.wired_count++; 855 pvo->pvo_vaddr |= PVO_WIRED; 856 } else { 857 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 858 pm->pm_stats.wired_count--; 859 pvo->pvo_vaddr &= ~PVO_WIRED; 860 } 861 } 862} 863 864void 865pmap_clear_modify(vm_page_t m) 866{ 867 868 if (m->flags * PG_FICTITIOUS) 869 return; 870 pmap_clear_bit(m, PTE_CHG); 871} 872 873void 874pmap_collect(void) 875{ 876 TODO; 877} 878 879void 880pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 881 vm_size_t len, vm_offset_t src_addr) 882{ 883 884 /* 885 * This is not needed as it's mainly an optimisation. 886 * It may want to be implemented later though. 887 */ 888} 889 890void 891pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 892{ 893 vm_offset_t dst; 894 vm_offset_t src; 895 896 dst = VM_PAGE_TO_PHYS(mdst); 897 src = VM_PAGE_TO_PHYS(msrc); 898 899 kcopy((void *)src, (void *)dst, PAGE_SIZE); 900} 901 902/* 903 * Zero a page of physical memory by temporarily mapping it into the tlb. 904 */ 905void 906pmap_zero_page(vm_page_t m) 907{ 908 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 909 caddr_t va; 910 int i; 911 912 if (pa < SEGMENT_LENGTH) { 913 va = (caddr_t) pa; 914 } else if (pmap_initialized) { 915 if (pmap_pvo_zeropage == NULL) 916 pmap_pvo_zeropage = pmap_rkva_alloc(); 917 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 918 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 919 } else { 920 panic("pmap_zero_page: can't zero pa %#x", pa); 921 } 922 923 bzero(va, PAGE_SIZE); 924 925#if 0 926 for (i = PAGE_SIZE / CACHELINESIZE; i > 0; i--) { 927 __asm __volatile("dcbz 0,%0" :: "r"(va)); 928 va += CACHELINESIZE; 929 } 930#endif 931 932 if (pa >= SEGMENT_LENGTH) 933 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 934} 935 936void 937pmap_zero_page_area(vm_page_t m, int off, int size) 938{ 939 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 940 caddr_t va; 941 int i; 942 943 if (pa < SEGMENT_LENGTH) { 944 va = (caddr_t) pa; 945 } else if (pmap_initialized) { 946 if (pmap_pvo_zeropage == NULL) 947 pmap_pvo_zeropage = pmap_rkva_alloc(); 948 pmap_pa_map(pmap_pvo_zeropage, pa, NULL, NULL); 949 va = (caddr_t)PVO_VADDR(pmap_pvo_zeropage); 950 } else { 951 panic("pmap_zero_page: can't zero pa %#x", pa); 952 } 953 954 bzero(va + off, size); 955 956#if 0 957 for (i = size / CACHELINESIZE; i > 0; i--) { 958 __asm __volatile("dcbz 0,%0" :: "r"(va)); 959 va += CACHELINESIZE; 960 } 961#endif 962 963 if (pa >= SEGMENT_LENGTH) 964 pmap_pa_unmap(pmap_pvo_zeropage, NULL, NULL); 965} 966 967void 968pmap_zero_page_idle(vm_page_t m) 969{ 970 971 /* XXX this is called outside of Giant, is pmap_zero_page safe? */ 972 /* XXX maybe have a dedicated mapping for this to avoid the problem? */ 973 mtx_lock(&Giant); 974 pmap_zero_page(m); 975 mtx_unlock(&Giant); 976} 977 978/* 979 * Map the given physical page at the specified virtual address in the 980 * target pmap with the protection requested. If specified the page 981 * will be wired down. 982 */ 983void 984pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 985 boolean_t wired) 986{ 987 struct pvo_head *pvo_head; 988 uma_zone_t zone; 989 vm_page_t pg; 990 u_int pte_lo, pvo_flags, was_exec, i; 991 int error; 992 993 if (!pmap_initialized) { 994 pvo_head = &pmap_pvo_kunmanaged; 995 zone = pmap_upvo_zone; 996 pvo_flags = 0; 997 pg = NULL; 998 was_exec = PTE_EXEC; 999 } else { 1000 pvo_head = pa_to_pvoh(VM_PAGE_TO_PHYS(m), &pg); 1001 zone = pmap_mpvo_zone; 1002 pvo_flags = PVO_MANAGED; 1003 was_exec = 0; 1004 } 1005 1006 /* 1007 * If this is a managed page, and it's the first reference to the page, 1008 * clear the execness of the page. Otherwise fetch the execness. 1009 */ 1010 if (pg != NULL) { 1011 if (LIST_EMPTY(pvo_head)) { 1012 pmap_attr_clear(pg, PTE_EXEC); 1013 } else { 1014 was_exec = pmap_attr_fetch(pg) & PTE_EXEC; 1015 } 1016 } 1017 1018 1019 /* 1020 * Assume the page is cache inhibited and access is guarded unless 1021 * it's in our available memory array. 1022 */ 1023 pte_lo = PTE_I | PTE_G; 1024 for (i = 0; i < pregions_sz; i++) { 1025 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) && 1026 (VM_PAGE_TO_PHYS(m) < 1027 (pregions[i].mr_start + pregions[i].mr_size))) { 1028 pte_lo &= ~(PTE_I | PTE_G); 1029 break; 1030 } 1031 } 1032 1033 if (prot & VM_PROT_WRITE) 1034 pte_lo |= PTE_BW; 1035 else 1036 pte_lo |= PTE_BR; 1037 1038 pvo_flags |= (prot & VM_PROT_EXECUTE); 1039 1040 if (wired) 1041 pvo_flags |= PVO_WIRED; 1042 1043 error = pmap_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1044 pte_lo, pvo_flags); 1045 1046 /* 1047 * Flush the real page from the instruction cache if this page is 1048 * mapped executable and cacheable and was not previously mapped (or 1049 * was not mapped executable). 1050 */ 1051 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1052 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1053 /* 1054 * Flush the real memory from the cache. 1055 */ 1056 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1057 if (pg != NULL) 1058 pmap_attr_save(pg, PTE_EXEC); 1059 } 1060 1061 /* XXX syncicache always until problems are sorted */ 1062 pmap_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1063} 1064 1065vm_offset_t 1066pmap_extract(pmap_t pm, vm_offset_t va) 1067{ 1068 struct pvo_entry *pvo; 1069 1070 pvo = pmap_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1071 1072 if (pvo != NULL) { 1073 return ((pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF)); 1074 } 1075 1076 return (0); 1077} 1078 1079/* 1080 * Grow the number of kernel page table entries. Unneeded. 1081 */ 1082void 1083pmap_growkernel(vm_offset_t addr) 1084{ 1085} 1086 1087void 1088pmap_init(vm_offset_t phys_start, vm_offset_t phys_end) 1089{ 1090 1091 CTR0(KTR_PMAP, "pmap_init"); 1092 1093 pmap_pvo_obj = vm_object_allocate(OBJT_PHYS, 16); 1094 pmap_pvo_count = 0; 1095 pmap_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1096 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM); 1097 uma_zone_set_allocf(pmap_upvo_zone, pmap_pvo_allocf); 1098 pmap_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1099 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM); 1100 uma_zone_set_allocf(pmap_mpvo_zone, pmap_pvo_allocf); 1101 pmap_initialized = TRUE; 1102} 1103 1104void 1105pmap_init2(void) 1106{ 1107 1108 CTR0(KTR_PMAP, "pmap_init2"); 1109} 1110 1111boolean_t 1112pmap_is_modified(vm_page_t m) 1113{ 1114 1115 if (m->flags & PG_FICTITIOUS) 1116 return (FALSE); 1117 1118 return (pmap_query_bit(m, PTE_CHG)); 1119} 1120 1121void 1122pmap_clear_reference(vm_page_t m) 1123{ 1124 TODO; 1125} 1126 1127/* 1128 * pmap_ts_referenced: 1129 * 1130 * Return a count of reference bits for a page, clearing those bits. 1131 * It is not necessary for every reference bit to be cleared, but it 1132 * is necessary that 0 only be returned when there are truly no 1133 * reference bits set. 1134 * 1135 * XXX: The exact number of bits to check and clear is a matter that 1136 * should be tested and standardized at some point in the future for 1137 * optimal aging of shared pages. 1138 */ 1139 1140int 1141pmap_ts_referenced(vm_page_t m) 1142{ 1143 TODO; 1144 return (0); 1145} 1146 1147/* 1148 * Map a wired page into kernel virtual address space. 1149 */ 1150void 1151pmap_kenter(vm_offset_t va, vm_offset_t pa) 1152{ 1153 u_int pte_lo; 1154 int error; 1155 int i; 1156 1157#if 0 1158 if (va < VM_MIN_KERNEL_ADDRESS) 1159 panic("pmap_kenter: attempt to enter non-kernel address %#x", 1160 va); 1161#endif 1162 1163 pte_lo = PTE_I | PTE_G; 1164 for (i = 0; i < pregions_sz; i++) { 1165 if ((pa >= pregions[i].mr_start) && 1166 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 1167 pte_lo &= ~(PTE_I | PTE_G); 1168 break; 1169 } 1170 } 1171 1172 error = pmap_pvo_enter(kernel_pmap, pmap_upvo_zone, 1173 &pmap_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1174 1175 if (error != 0 && error != ENOENT) 1176 panic("pmap_kenter: failed to enter va %#x pa %#x: %d", va, 1177 pa, error); 1178 1179 /* 1180 * Flush the real memory from the instruction cache. 1181 */ 1182 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1183 pmap_syncicache(pa, PAGE_SIZE); 1184 } 1185} 1186 1187/* 1188 * Extract the physical page address associated with the given kernel virtual 1189 * address. 1190 */ 1191vm_offset_t 1192pmap_kextract(vm_offset_t va) 1193{ 1194 struct pvo_entry *pvo; 1195 1196 pvo = pmap_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1197 if (pvo == NULL) { 1198 return (0); 1199 } 1200 1201 return ((pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF)); 1202} 1203 1204/* 1205 * Remove a wired page from kernel virtual address space. 1206 */ 1207void 1208pmap_kremove(vm_offset_t va) 1209{ 1210 1211 pmap_remove(kernel_pmap, va, va + PAGE_SIZE); 1212} 1213 1214/* 1215 * Map a range of physical addresses into kernel virtual address space. 1216 * 1217 * The value passed in *virt is a suggested virtual address for the mapping. 1218 * Architectures which can support a direct-mapped physical to virtual region 1219 * can return the appropriate address within that region, leaving '*virt' 1220 * unchanged. We cannot and therefore do not; *virt is updated with the 1221 * first usable address after the mapped region. 1222 */ 1223vm_offset_t 1224pmap_map(vm_offset_t *virt, vm_offset_t pa_start, vm_offset_t pa_end, int prot) 1225{ 1226 vm_offset_t sva, va; 1227 1228 sva = *virt; 1229 va = sva; 1230 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1231 pmap_kenter(va, pa_start); 1232 *virt = va; 1233 return (sva); 1234} 1235 1236int 1237pmap_mincore(pmap_t pmap, vm_offset_t addr) 1238{ 1239 TODO; 1240 return (0); 1241} 1242 1243void 1244pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object, 1245 vm_pindex_t pindex, vm_size_t size, int limit) 1246{ 1247 1248 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1249 ("pmap_remove_pages: non current pmap")); 1250 /* XXX */ 1251} 1252 1253/* 1254 * Lower the permission for all mappings to a given page. 1255 */ 1256void 1257pmap_page_protect(vm_page_t m, vm_prot_t prot) 1258{ 1259 struct pvo_head *pvo_head; 1260 struct pvo_entry *pvo, *next_pvo; 1261 struct pte *pt; 1262 1263 /* 1264 * Since the routine only downgrades protection, if the 1265 * maximal protection is desired, there isn't any change 1266 * to be made. 1267 */ 1268 if ((prot & (VM_PROT_READ|VM_PROT_WRITE)) == 1269 (VM_PROT_READ|VM_PROT_WRITE)) 1270 return; 1271 1272 pvo_head = vm_page_to_pvoh(m); 1273 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1274 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1275 PMAP_PVO_CHECK(pvo); /* sanity check */ 1276 1277 /* 1278 * Downgrading to no mapping at all, we just remove the entry. 1279 */ 1280 if ((prot & VM_PROT_READ) == 0) { 1281 pmap_pvo_remove(pvo, -1); 1282 continue; 1283 } 1284 1285 /* 1286 * If EXEC permission is being revoked, just clear the flag 1287 * in the PVO. 1288 */ 1289 if ((prot & VM_PROT_EXECUTE) == 0) 1290 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1291 1292 /* 1293 * If this entry is already RO, don't diddle with the page 1294 * table. 1295 */ 1296 if ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_BR) { 1297 PMAP_PVO_CHECK(pvo); 1298 continue; 1299 } 1300 1301 /* 1302 * Grab the PTE before we diddle the bits so pvo_to_pte can 1303 * verify the pte contents are as expected. 1304 */ 1305 pt = pmap_pvo_to_pte(pvo, -1); 1306 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1307 pvo->pvo_pte.pte_lo |= PTE_BR; 1308 if (pt != NULL) 1309 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1310 PMAP_PVO_CHECK(pvo); /* sanity check */ 1311 } 1312} 1313 1314/* 1315 * Returns true if the pmap's pv is one of the first 1316 * 16 pvs linked to from this page. This count may 1317 * be changed upwards or downwards in the future; it 1318 * is only necessary that true be returned for a small 1319 * subset of pmaps for proper page aging. 1320 */ 1321boolean_t 1322pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 1323{ 1324 TODO; 1325 return (0); 1326} 1327 1328static u_int pmap_vsidcontext; 1329 1330void 1331pmap_pinit(pmap_t pmap) 1332{ 1333 int i, mask; 1334 u_int entropy; 1335 1336 entropy = 0; 1337 __asm __volatile("mftb %0" : "=r"(entropy)); 1338 1339 /* 1340 * Allocate some segment registers for this pmap. 1341 */ 1342 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1343 u_int hash, n; 1344 1345 /* 1346 * Create a new value by mutiplying by a prime and adding in 1347 * entropy from the timebase register. This is to make the 1348 * VSID more random so that the PT hash function collides 1349 * less often. (Note that the prime casues gcc to do shifts 1350 * instead of a multiply.) 1351 */ 1352 pmap_vsidcontext = (pmap_vsidcontext * 0x1105) + entropy; 1353 hash = pmap_vsidcontext & (NPMAPS - 1); 1354 if (hash == 0) /* 0 is special, avoid it */ 1355 continue; 1356 n = hash >> 5; 1357 mask = 1 << (hash & (VSID_NBPW - 1)); 1358 hash = (pmap_vsidcontext & 0xfffff); 1359 if (pmap_vsid_bitmap[n] & mask) { /* collision? */ 1360 /* anything free in this bucket? */ 1361 if (pmap_vsid_bitmap[n] == 0xffffffff) { 1362 entropy = (pmap_vsidcontext >> 20); 1363 continue; 1364 } 1365 i = ffs(~pmap_vsid_bitmap[i]) - 1; 1366 mask = 1 << i; 1367 hash &= 0xfffff & ~(VSID_NBPW - 1); 1368 hash |= i; 1369 } 1370 pmap_vsid_bitmap[n] |= mask; 1371 for (i = 0; i < 16; i++) 1372 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1373 return; 1374 } 1375 1376 panic("pmap_pinit: out of segments"); 1377} 1378 1379/* 1380 * Initialize the pmap associated with process 0. 1381 */ 1382void 1383pmap_pinit0(pmap_t pm) 1384{ 1385 1386 pmap_pinit(pm); 1387 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1388} 1389 1390void 1391pmap_pinit2(pmap_t pmap) 1392{ 1393 /* XXX: Remove this stub when no longer called */ 1394} 1395 1396void 1397pmap_prefault(pmap_t pm, vm_offset_t va, vm_map_entry_t entry) 1398{ 1399 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1400 ("pmap_prefault: non current pmap")); 1401 /* XXX */ 1402} 1403 1404/* 1405 * Set the physical protection on the specified range of this map as requested. 1406 */ 1407void 1408pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1409{ 1410 struct pvo_entry *pvo; 1411 struct pte *pt; 1412 int pteidx; 1413 1414 CTR4(KTR_PMAP, "pmap_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva, 1415 eva, prot); 1416 1417 1418 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1419 ("pmap_protect: non current pmap")); 1420 1421 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1422 pmap_remove(pm, sva, eva); 1423 return; 1424 } 1425 1426 for (; sva < eva; sva += PAGE_SIZE) { 1427 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1428 if (pvo == NULL) 1429 continue; 1430 1431 if ((prot & VM_PROT_EXECUTE) == 0) 1432 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1433 1434 /* 1435 * Grab the PTE pointer before we diddle with the cached PTE 1436 * copy. 1437 */ 1438 pt = pmap_pvo_to_pte(pvo, pteidx); 1439 /* 1440 * Change the protection of the page. 1441 */ 1442 pvo->pvo_pte.pte_lo &= ~PTE_PP; 1443 pvo->pvo_pte.pte_lo |= PTE_BR; 1444 1445 /* 1446 * If the PVO is in the page table, update that pte as well. 1447 */ 1448 if (pt != NULL) 1449 pmap_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1450 } 1451} 1452 1453vm_offset_t 1454pmap_phys_address(int ppn) 1455{ 1456 TODO; 1457 return (0); 1458} 1459 1460/* 1461 * Map a list of wired pages into kernel virtual address space. This is 1462 * intended for temporary mappings which do not need page modification or 1463 * references recorded. Existing mappings in the region are overwritten. 1464 */ 1465void 1466pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 1467{ 1468 int i; 1469 1470 for (i = 0; i < count; i++, va += PAGE_SIZE) 1471 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 1472} 1473 1474/* 1475 * Remove page mappings from kernel virtual address space. Intended for 1476 * temporary mappings entered by pmap_qenter. 1477 */ 1478void 1479pmap_qremove(vm_offset_t va, int count) 1480{ 1481 int i; 1482 1483 for (i = 0; i < count; i++, va += PAGE_SIZE) 1484 pmap_kremove(va); 1485} 1486 1487void 1488pmap_release(pmap_t pmap) 1489{ 1490 int idx, mask; 1491 1492 /* 1493 * Free segment register's VSID 1494 */ 1495 if (pmap->pm_sr[0] == 0) 1496 panic("pmap_release"); 1497 1498 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1499 mask = 1 << (idx % VSID_NBPW); 1500 idx /= VSID_NBPW; 1501 pmap_vsid_bitmap[idx] &= ~mask; 1502} 1503 1504/* 1505 * Remove the given range of addresses from the specified map. 1506 */ 1507void 1508pmap_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1509{ 1510 struct pvo_entry *pvo; 1511 int pteidx; 1512 1513 for (; sva < eva; sva += PAGE_SIZE) { 1514 pvo = pmap_pvo_find_va(pm, sva, &pteidx); 1515 if (pvo != NULL) { 1516 pmap_pvo_remove(pvo, pteidx); 1517 } 1518 } 1519} 1520 1521/* 1522 * Remove all pages from specified address space, this aids process exit 1523 * speeds. This is much faster than pmap_remove in the case of running down 1524 * an entire address space. Only works for the current pmap. 1525 */ 1526void 1527pmap_remove_pages(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1528{ 1529 1530 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1531 ("pmap_remove_pages: non current pmap")); 1532 pmap_remove(pm, sva, eva); 1533} 1534 1535/* 1536 * Create the kernel stack and pcb for a new thread. 1537 * This routine directly affects the fork perf for a process and 1538 * create performance for a thread. 1539 */ 1540void 1541pmap_new_thread(struct thread *td) 1542{ 1543 vm_object_t ksobj; 1544 vm_offset_t ks; 1545 vm_page_t m; 1546 u_int i; 1547 1548 /* 1549 * Allocate object for the kstack. 1550 */ 1551 ksobj = vm_object_allocate(OBJT_DEFAULT, KSTACK_PAGES); 1552 td->td_kstack_obj = ksobj; 1553 1554 /* 1555 * Get a kernel virtual address for the kstack for this thread. 1556 */ 1557 ks = kmem_alloc_nofault(kernel_map, 1558 (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE); 1559 if (ks == 0) 1560 panic("pmap_new_thread: kstack allocation failed"); 1561 TLBIE(ks); 1562 ks += KSTACK_GUARD_PAGES * PAGE_SIZE; 1563 td->td_kstack = ks; 1564 1565 for (i = 0; i < KSTACK_PAGES; i++) { 1566 /* 1567 * Get a kernel stack page. 1568 */ 1569 m = vm_page_grab(ksobj, i, 1570 VM_ALLOC_NORMAL | VM_ALLOC_RETRY | VM_ALLOC_WIRED); 1571 1572 /* 1573 * Enter the page into the kernel address space. 1574 */ 1575 pmap_kenter(ks + i * PAGE_SIZE, VM_PAGE_TO_PHYS(m)); 1576 1577 vm_page_wakeup(m); 1578 vm_page_flag_clear(m, PG_ZERO); 1579 m->valid = VM_PAGE_BITS_ALL; 1580 } 1581} 1582 1583void 1584pmap_dispose_thread(struct thread *td) 1585{ 1586 TODO; 1587} 1588 1589void 1590pmap_swapin_thread(struct thread *td) 1591{ 1592 TODO; 1593} 1594 1595void 1596pmap_swapout_thread(struct thread *td) 1597{ 1598 TODO; 1599} 1600 1601/* 1602 * Allocate a physical page of memory directly from the phys_avail map. 1603 * Can only be called from pmap_bootstrap before avail start and end are 1604 * calculated. 1605 */ 1606static vm_offset_t 1607pmap_bootstrap_alloc(vm_size_t size, u_int align) 1608{ 1609 vm_offset_t s, e; 1610 int i, j; 1611 1612 size = round_page(size); 1613 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1614 if (align != 0) 1615 s = (phys_avail[i] + align - 1) & ~(align - 1); 1616 else 1617 s = phys_avail[i]; 1618 e = s + size; 1619 1620 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1621 continue; 1622 1623 if (s == phys_avail[i]) { 1624 phys_avail[i] += size; 1625 } else if (e == phys_avail[i + 1]) { 1626 phys_avail[i + 1] -= size; 1627 } else { 1628 for (j = phys_avail_count * 2; j > i; j -= 2) { 1629 phys_avail[j] = phys_avail[j - 2]; 1630 phys_avail[j + 1] = phys_avail[j - 1]; 1631 } 1632 1633 phys_avail[i + 3] = phys_avail[i + 1]; 1634 phys_avail[i + 1] = s; 1635 phys_avail[i + 2] = e; 1636 phys_avail_count++; 1637 } 1638 1639 return (s); 1640 } 1641 panic("pmap_bootstrap_alloc: could not allocate memory"); 1642} 1643 1644/* 1645 * Return an unmapped pvo for a kernel virtual address. 1646 * Used by pmap functions that operate on physical pages. 1647 */ 1648static struct pvo_entry * 1649pmap_rkva_alloc(void) 1650{ 1651 struct pvo_entry *pvo; 1652 struct pte *pt; 1653 vm_offset_t kva; 1654 int pteidx; 1655 1656 if (pmap_rkva_count == 0) 1657 panic("pmap_rkva_alloc: no more reserved KVAs"); 1658 1659 kva = pmap_rkva_start + (PAGE_SIZE * --pmap_rkva_count); 1660 pmap_kenter(kva, 0); 1661 1662 pvo = pmap_pvo_find_va(kernel_pmap, kva, &pteidx); 1663 1664 if (pvo == NULL) 1665 panic("pmap_kva_alloc: pmap_pvo_find_va failed"); 1666 1667 pt = pmap_pvo_to_pte(pvo, pteidx); 1668 1669 if (pt == NULL) 1670 panic("pmap_kva_alloc: pmap_pvo_to_pte failed"); 1671 1672 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1673 PVO_PTEGIDX_CLR(pvo); 1674 1675 pmap_pte_overflow++; 1676 1677 return (pvo); 1678} 1679 1680static void 1681pmap_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt, 1682 int *depth_p) 1683{ 1684 struct pte *pt; 1685 1686 /* 1687 * If this pvo already has a valid pte, we need to save it so it can 1688 * be restored later. We then just reload the new PTE over the old 1689 * slot. 1690 */ 1691 if (saved_pt != NULL) { 1692 pt = pmap_pvo_to_pte(pvo, -1); 1693 1694 if (pt != NULL) { 1695 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1696 PVO_PTEGIDX_CLR(pvo); 1697 pmap_pte_overflow++; 1698 } 1699 1700 *saved_pt = pvo->pvo_pte; 1701 1702 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1703 } 1704 1705 pvo->pvo_pte.pte_lo |= pa; 1706 1707 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1708 panic("pmap_pa_map: could not spill pvo %p", pvo); 1709 1710 if (depth_p != NULL) 1711 (*depth_p)++; 1712} 1713 1714static void 1715pmap_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p) 1716{ 1717 struct pte *pt; 1718 1719 pt = pmap_pvo_to_pte(pvo, -1); 1720 1721 if (pt != NULL) { 1722 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1723 PVO_PTEGIDX_CLR(pvo); 1724 pmap_pte_overflow++; 1725 } 1726 1727 pvo->pvo_pte.pte_lo &= ~PTE_RPGN; 1728 1729 /* 1730 * If there is a saved PTE and it's valid, restore it and return. 1731 */ 1732 if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) { 1733 if (depth_p != NULL && --(*depth_p) == 0) 1734 panic("pmap_pa_unmap: restoring but depth == 0"); 1735 1736 pvo->pvo_pte = *saved_pt; 1737 1738 if (!pmap_pte_spill(pvo->pvo_vaddr)) 1739 panic("pmap_pa_unmap: could not spill pvo %p", pvo); 1740 } 1741} 1742 1743static void 1744pmap_syncicache(vm_offset_t pa, vm_size_t len) 1745{ 1746 __syncicache((void *)pa, len); 1747} 1748 1749static void 1750tlbia(void) 1751{ 1752 caddr_t i; 1753 1754 SYNC(); 1755 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) { 1756 TLBIE(i); 1757 EIEIO(); 1758 } 1759 TLBSYNC(); 1760 SYNC(); 1761} 1762 1763static int 1764pmap_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1765 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1766{ 1767 struct pvo_entry *pvo; 1768 u_int sr; 1769 int first; 1770 u_int ptegidx; 1771 int i; 1772 int bootstrap; 1773 1774 pmap_pvo_enter_calls++; 1775 first = 0; 1776 1777 bootstrap = 0; 1778 1779 /* 1780 * Compute the PTE Group index. 1781 */ 1782 va &= ~ADDR_POFF; 1783 sr = va_to_sr(pm->pm_sr, va); 1784 ptegidx = va_to_pteg(sr, va); 1785 1786 /* 1787 * Remove any existing mapping for this page. Reuse the pvo entry if 1788 * there is a mapping. 1789 */ 1790 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1791 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1792 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa && 1793 (pvo->pvo_pte.pte_lo & PTE_PP) == 1794 (pte_lo & PTE_PP)) { 1795 return (0); 1796 } 1797 pmap_pvo_remove(pvo, -1); 1798 break; 1799 } 1800 } 1801 1802 /* 1803 * If we aren't overwriting a mapping, try to allocate. 1804 */ 1805 if (pmap_initialized) { 1806 pvo = uma_zalloc(zone, M_NOWAIT); 1807 } else { 1808 if (pmap_bpvo_pool_index >= BPVO_POOL_SIZE) { 1809 panic("pmap_enter: bpvo pool exhausted, %d, %d, %d", 1810 pmap_bpvo_pool_index, BPVO_POOL_SIZE, 1811 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1812 } 1813 pvo = &pmap_bpvo_pool[pmap_bpvo_pool_index]; 1814 pmap_bpvo_pool_index++; 1815 bootstrap = 1; 1816 } 1817 1818 if (pvo == NULL) { 1819 return (ENOMEM); 1820 } 1821 1822 pmap_pvo_entries++; 1823 pvo->pvo_vaddr = va; 1824 pvo->pvo_pmap = pm; 1825 LIST_INSERT_HEAD(&pmap_pvo_table[ptegidx], pvo, pvo_olink); 1826 pvo->pvo_vaddr &= ~ADDR_POFF; 1827 if (flags & VM_PROT_EXECUTE) 1828 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1829 if (flags & PVO_WIRED) 1830 pvo->pvo_vaddr |= PVO_WIRED; 1831 if (pvo_head != &pmap_pvo_kunmanaged) 1832 pvo->pvo_vaddr |= PVO_MANAGED; 1833 if (bootstrap) 1834 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1835 pmap_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo); 1836 1837 /* 1838 * Remember if the list was empty and therefore will be the first 1839 * item. 1840 */ 1841 if (LIST_FIRST(pvo_head) == NULL) 1842 first = 1; 1843 1844 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1845 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1846 pvo->pvo_pmap->pm_stats.wired_count++; 1847 pvo->pvo_pmap->pm_stats.resident_count++; 1848 1849 /* 1850 * We hope this succeeds but it isn't required. 1851 */ 1852 i = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 1853 if (i >= 0) { 1854 PVO_PTEGIDX_SET(pvo, i); 1855 } else { 1856 panic("pmap_pvo_enter: overflow"); 1857 pmap_pte_overflow++; 1858 } 1859 1860 return (first ? ENOENT : 0); 1861} 1862 1863static void 1864pmap_pvo_remove(struct pvo_entry *pvo, int pteidx) 1865{ 1866 struct pte *pt; 1867 1868 /* 1869 * If there is an active pte entry, we need to deactivate it (and 1870 * save the ref & cfg bits). 1871 */ 1872 pt = pmap_pvo_to_pte(pvo, pteidx); 1873 if (pt != NULL) { 1874 pmap_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr); 1875 PVO_PTEGIDX_CLR(pvo); 1876 } else { 1877 pmap_pte_overflow--; 1878 } 1879 1880 /* 1881 * Update our statistics. 1882 */ 1883 pvo->pvo_pmap->pm_stats.resident_count--; 1884 if (pvo->pvo_pte.pte_lo & PVO_WIRED) 1885 pvo->pvo_pmap->pm_stats.wired_count--; 1886 1887 /* 1888 * Save the REF/CHG bits into their cache if the page is managed. 1889 */ 1890 if (pvo->pvo_vaddr & PVO_MANAGED) { 1891 struct vm_page *pg; 1892 1893 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN); 1894 if (pg != NULL) { 1895 pmap_attr_save(pg, pvo->pvo_pte.pte_lo & 1896 (PTE_REF | PTE_CHG)); 1897 } 1898 } 1899 1900 /* 1901 * Remove this PVO from the PV list. 1902 */ 1903 LIST_REMOVE(pvo, pvo_vlink); 1904 1905 /* 1906 * Remove this from the overflow list and return it to the pool 1907 * if we aren't going to reuse it. 1908 */ 1909 LIST_REMOVE(pvo, pvo_olink); 1910 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 1911 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? pmap_mpvo_zone : 1912 pmap_upvo_zone, pvo); 1913 pmap_pvo_entries--; 1914 pmap_pvo_remove_calls++; 1915} 1916 1917static __inline int 1918pmap_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 1919{ 1920 int pteidx; 1921 1922 /* 1923 * We can find the actual pte entry without searching by grabbing 1924 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 1925 * noticing the HID bit. 1926 */ 1927 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 1928 if (pvo->pvo_pte.pte_hi & PTE_HID) 1929 pteidx ^= pmap_pteg_mask * 8; 1930 1931 return (pteidx); 1932} 1933 1934static struct pvo_entry * 1935pmap_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 1936{ 1937 struct pvo_entry *pvo; 1938 int ptegidx; 1939 u_int sr; 1940 1941 va &= ~ADDR_POFF; 1942 sr = va_to_sr(pm->pm_sr, va); 1943 ptegidx = va_to_pteg(sr, va); 1944 1945 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 1946 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1947 if (pteidx_p) 1948 *pteidx_p = pmap_pvo_pte_index(pvo, ptegidx); 1949 return (pvo); 1950 } 1951 } 1952 1953 return (NULL); 1954} 1955 1956static struct pte * 1957pmap_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 1958{ 1959 struct pte *pt; 1960 1961 /* 1962 * If we haven't been supplied the ptegidx, calculate it. 1963 */ 1964 if (pteidx == -1) { 1965 int ptegidx; 1966 u_int sr; 1967 1968 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 1969 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 1970 pteidx = pmap_pvo_pte_index(pvo, ptegidx); 1971 } 1972 1973 pt = &pmap_pteg_table[pteidx >> 3].pt[pteidx & 7]; 1974 1975 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 1976 panic("pmap_pvo_to_pte: pvo %p has valid pte in pvo but no " 1977 "valid pte index", pvo); 1978 } 1979 1980 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 1981 panic("pmap_pvo_to_pte: pvo %p has valid pte index in pvo " 1982 "pvo but no valid pte", pvo); 1983 } 1984 1985 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 1986 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) { 1987 panic("pmap_pvo_to_pte: pvo %p has valid pte in " 1988 "pmap_pteg_table %p but invalid in pvo", pvo, pt); 1989 } 1990 1991 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 1992 != 0) { 1993 panic("pmap_pvo_to_pte: pvo %p pte does not match " 1994 "pte %p in pmap_pteg_table", pvo, pt); 1995 } 1996 1997 return (pt); 1998 } 1999 2000 if (pvo->pvo_pte.pte_hi & PTE_VALID) { 2001 panic("pmap_pvo_to_pte: pvo %p has invalid pte %p in " 2002 "pmap_pteg_table but valid in pvo", pvo, pt); 2003 } 2004 2005 return (NULL); 2006} 2007 2008static void * 2009pmap_pvo_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 2010{ 2011 vm_page_t m; 2012 2013 if (bytes != PAGE_SIZE) 2014 panic("pmap_pvo_allocf: benno was shortsighted. hit him."); 2015 2016 *flags = UMA_SLAB_PRIV; 2017 m = vm_page_alloc(pmap_pvo_obj, pmap_pvo_count, VM_ALLOC_SYSTEM); 2018 if (m == NULL) 2019 return (NULL); 2020 pmap_pvo_count++; 2021 return ((void *)VM_PAGE_TO_PHYS(m)); 2022} 2023 2024/* 2025 * XXX: THIS STUFF SHOULD BE IN pte.c? 2026 */ 2027int 2028pmap_pte_spill(vm_offset_t addr) 2029{ 2030 struct pvo_entry *source_pvo, *victim_pvo; 2031 struct pvo_entry *pvo; 2032 int ptegidx, i, j; 2033 u_int sr; 2034 struct pteg *pteg; 2035 struct pte *pt; 2036 2037 pmap_pte_spills++; 2038 2039 sr = mfsrin(addr); 2040 ptegidx = va_to_pteg(sr, addr); 2041 2042 /* 2043 * Have to substitute some entry. Use the primary hash for this. 2044 * Use low bits of timebase as random generator. 2045 */ 2046 pteg = &pmap_pteg_table[ptegidx]; 2047 __asm __volatile("mftb %0" : "=r"(i)); 2048 i &= 7; 2049 pt = &pteg->pt[i]; 2050 2051 source_pvo = NULL; 2052 victim_pvo = NULL; 2053 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx], pvo_olink) { 2054 /* 2055 * We need to find a pvo entry for this address. 2056 */ 2057 PMAP_PVO_CHECK(pvo); 2058 if (source_pvo == NULL && 2059 pmap_pte_match(&pvo->pvo_pte, sr, addr, 2060 pvo->pvo_pte.pte_hi & PTE_HID)) { 2061 /* 2062 * Now found an entry to be spilled into the pteg. 2063 * The PTE is now valid, so we know it's active. 2064 */ 2065 j = pmap_pte_insert(ptegidx, &pvo->pvo_pte); 2066 2067 if (j >= 0) { 2068 PVO_PTEGIDX_SET(pvo, j); 2069 pmap_pte_overflow--; 2070 PMAP_PVO_CHECK(pvo); 2071 return (1); 2072 } 2073 2074 source_pvo = pvo; 2075 2076 if (victim_pvo != NULL) 2077 break; 2078 } 2079 2080 /* 2081 * We also need the pvo entry of the victim we are replacing 2082 * so save the R & C bits of the PTE. 2083 */ 2084 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2085 pmap_pte_compare(pt, &pvo->pvo_pte)) { 2086 victim_pvo = pvo; 2087 if (source_pvo != NULL) 2088 break; 2089 } 2090 } 2091 2092 if (source_pvo == NULL) 2093 return (0); 2094 2095 if (victim_pvo == NULL) { 2096 if ((pt->pte_hi & PTE_HID) == 0) 2097 panic("pmap_pte_spill: victim p-pte (%p) has no pvo" 2098 "entry", pt); 2099 2100 /* 2101 * If this is a secondary PTE, we need to search it's primary 2102 * pvo bucket for the matching PVO. 2103 */ 2104 LIST_FOREACH(pvo, &pmap_pvo_table[ptegidx ^ pmap_pteg_mask], 2105 pvo_olink) { 2106 PMAP_PVO_CHECK(pvo); 2107 /* 2108 * We also need the pvo entry of the victim we are 2109 * replacing so save the R & C bits of the PTE. 2110 */ 2111 if (pmap_pte_compare(pt, &pvo->pvo_pte)) { 2112 victim_pvo = pvo; 2113 break; 2114 } 2115 } 2116 2117 if (victim_pvo == NULL) 2118 panic("pmap_pte_spill: victim s-pte (%p) has no pvo" 2119 "entry", pt); 2120 } 2121 2122 /* 2123 * We are invalidating the TLB entry for the EA we are replacing even 2124 * though it's valid. If we don't, we lose any ref/chg bit changes 2125 * contained in the TLB entry. 2126 */ 2127 source_pvo->pvo_pte.pte_hi &= ~PTE_HID; 2128 2129 pmap_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr); 2130 pmap_pte_set(pt, &source_pvo->pvo_pte); 2131 2132 PVO_PTEGIDX_CLR(victim_pvo); 2133 PVO_PTEGIDX_SET(source_pvo, i); 2134 pmap_pte_replacements++; 2135 2136 PMAP_PVO_CHECK(victim_pvo); 2137 PMAP_PVO_CHECK(source_pvo); 2138 2139 return (1); 2140} 2141 2142static int 2143pmap_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2144{ 2145 struct pte *pt; 2146 int i; 2147 2148 /* 2149 * First try primary hash. 2150 */ 2151 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2152 if ((pt->pte_hi & PTE_VALID) == 0) { 2153 pvo_pt->pte_hi &= ~PTE_HID; 2154 pmap_pte_set(pt, pvo_pt); 2155 return (i); 2156 } 2157 } 2158 2159 /* 2160 * Now try secondary hash. 2161 */ 2162 ptegidx ^= pmap_pteg_mask; 2163 ptegidx++; 2164 for (pt = pmap_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2165 if ((pt->pte_hi & PTE_VALID) == 0) { 2166 pvo_pt->pte_hi |= PTE_HID; 2167 pmap_pte_set(pt, pvo_pt); 2168 return (i); 2169 } 2170 } 2171 2172 panic("pmap_pte_insert: overflow"); 2173 return (-1); 2174} 2175 2176static boolean_t 2177pmap_query_bit(vm_page_t m, int ptebit) 2178{ 2179 struct pvo_entry *pvo; 2180 struct pte *pt; 2181 2182 if (pmap_attr_fetch(m) & ptebit) 2183 return (TRUE); 2184 2185 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2186 PMAP_PVO_CHECK(pvo); /* sanity check */ 2187 2188 /* 2189 * See if we saved the bit off. If so, cache it and return 2190 * success. 2191 */ 2192 if (pvo->pvo_pte.pte_lo & ptebit) { 2193 pmap_attr_save(m, ptebit); 2194 PMAP_PVO_CHECK(pvo); /* sanity check */ 2195 return (TRUE); 2196 } 2197 } 2198 2199 /* 2200 * No luck, now go through the hard part of looking at the PTEs 2201 * themselves. Sync so that any pending REF/CHG bits are flushed to 2202 * the PTEs. 2203 */ 2204 SYNC(); 2205 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2206 PMAP_PVO_CHECK(pvo); /* sanity check */ 2207 2208 /* 2209 * See if this pvo has a valid PTE. if so, fetch the 2210 * REF/CHG bits from the valid PTE. If the appropriate 2211 * ptebit is set, cache it and return success. 2212 */ 2213 pt = pmap_pvo_to_pte(pvo, -1); 2214 if (pt != NULL) { 2215 pmap_pte_synch(pt, &pvo->pvo_pte); 2216 if (pvo->pvo_pte.pte_lo & ptebit) { 2217 pmap_attr_save(m, ptebit); 2218 PMAP_PVO_CHECK(pvo); /* sanity check */ 2219 return (TRUE); 2220 } 2221 } 2222 } 2223 2224 return (TRUE); 2225} 2226 2227static boolean_t 2228pmap_clear_bit(vm_page_t m, int ptebit) 2229{ 2230 struct pvo_entry *pvo; 2231 struct pte *pt; 2232 int rv; 2233 2234 /* 2235 * Clear the cached value. 2236 */ 2237 rv = pmap_attr_fetch(m); 2238 pmap_attr_clear(m, ptebit); 2239 2240 /* 2241 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2242 * we can reset the right ones). note that since the pvo entries and 2243 * list heads are accessed via BAT0 and are never placed in the page 2244 * table, we don't have to worry about further accesses setting the 2245 * REF/CHG bits. 2246 */ 2247 SYNC(); 2248 2249 /* 2250 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2251 * valid pte clear the ptebit from the valid pte. 2252 */ 2253 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2254 PMAP_PVO_CHECK(pvo); /* sanity check */ 2255 pt = pmap_pvo_to_pte(pvo, -1); 2256 if (pt != NULL) { 2257 pmap_pte_synch(pt, &pvo->pvo_pte); 2258 if (pvo->pvo_pte.pte_lo & ptebit) 2259 pmap_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2260 } 2261 rv |= pvo->pvo_pte.pte_lo; 2262 pvo->pvo_pte.pte_lo &= ~ptebit; 2263 PMAP_PVO_CHECK(pvo); /* sanity check */ 2264 } 2265 2266 return ((rv & ptebit) != 0); 2267} 2268 2269/* 2270 * Return true if the physical range is encompassed by the battable[idx] 2271 */ 2272static int 2273pmap_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2274{ 2275 u_int prot; 2276 u_int32_t start; 2277 u_int32_t end; 2278 u_int32_t bat_ble; 2279 2280 /* 2281 * Return immediately if not a valid mapping 2282 */ 2283 if (!battable[idx].batu & BAT_Vs) 2284 return (EINVAL); 2285 2286 /* 2287 * The BAT entry must be cache-inhibited, guarded, and r/w 2288 * so it can function as an i/o page 2289 */ 2290 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2291 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2292 return (EPERM); 2293 2294 /* 2295 * The address should be within the BAT range. Assume that the 2296 * start address in the BAT has the correct alignment (thus 2297 * not requiring masking) 2298 */ 2299 start = battable[idx].batl & BAT_PBS; 2300 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2301 end = start | (bat_ble << 15) | 0x7fff; 2302 2303 if ((pa < start) || ((pa + size) > end)) 2304 return (ERANGE); 2305 2306 return (0); 2307} 2308 2309 2310/* 2311 * Map a set of physical memory pages into the kernel virtual 2312 * address space. Return a pointer to where it is mapped. This 2313 * routine is intended to be used for mapping device memory, 2314 * NOT real memory. 2315 */ 2316void * 2317pmap_mapdev(vm_offset_t pa, vm_size_t size) 2318{ 2319 vm_offset_t va, tmpva, ppa, offset; 2320 int i; 2321 2322 ppa = trunc_page(pa); 2323 offset = pa & PAGE_MASK; 2324 size = roundup(offset + size, PAGE_SIZE); 2325 2326 GIANT_REQUIRED; 2327 2328 /* 2329 * If the physical address lies within a valid BAT table entry, 2330 * return the 1:1 mapping. This currently doesn't work 2331 * for regions that overlap 256M BAT segments. 2332 */ 2333 for (i = 0; i < 16; i++) { 2334 if (pmap_bat_mapped(i, pa, size) == 0) 2335 return ((void *) pa); 2336 } 2337 2338 va = kmem_alloc_pageable(kernel_map, size); 2339 if (!va) 2340 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2341 2342 for (tmpva = va; size > 0;) { 2343 pmap_kenter(tmpva, ppa); 2344 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */ 2345 size -= PAGE_SIZE; 2346 tmpva += PAGE_SIZE; 2347 ppa += PAGE_SIZE; 2348 } 2349 2350 return ((void *)(va + offset)); 2351} 2352 2353void 2354pmap_unmapdev(vm_offset_t va, vm_size_t size) 2355{ 2356 vm_offset_t base, offset; 2357 2358 /* 2359 * If this is outside kernel virtual space, then it's a 2360 * battable entry and doesn't require unmapping 2361 */ 2362 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2363 base = trunc_page(va); 2364 offset = va & PAGE_MASK; 2365 size = roundup(offset + size, PAGE_SIZE); 2366 kmem_free(kernel_map, base, size); 2367 } 2368} 2369