1219820Sjeff/* 2219820Sjeff * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3219820Sjeff * 4219820Sjeff * This software is available to you under a choice of one of two 5219820Sjeff * licenses. You may choose to be licensed under the terms of the GNU 6219820Sjeff * General Public License (GPL) Version 2, available from the file 7219820Sjeff * COPYING in the main directory of this source tree, or the 8219820Sjeff * OpenIB.org BSD license below: 9219820Sjeff * 10219820Sjeff * Redistribution and use in source and binary forms, with or 11219820Sjeff * without modification, are permitted provided that the following 12219820Sjeff * conditions are met: 13219820Sjeff * 14219820Sjeff * - Redistributions of source code must retain the above 15219820Sjeff * copyright notice, this list of conditions and the following 16219820Sjeff * disclaimer. 17219820Sjeff * 18219820Sjeff * - Redistributions in binary form must reproduce the above 19219820Sjeff * copyright notice, this list of conditions and the following 20219820Sjeff * disclaimer in the documentation and/or other materials 21219820Sjeff * provided with the distribution. 22219820Sjeff * 23219820Sjeff * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24219820Sjeff * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25219820Sjeff * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26219820Sjeff * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27219820Sjeff * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28219820Sjeff * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29219820Sjeff * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30219820Sjeff * SOFTWARE. 31219820Sjeff */ 32219820Sjeff 33219820Sjeff#ifndef MLX4_DEVICE_H 34219820Sjeff#define MLX4_DEVICE_H 35219820Sjeff 36219820Sjeff#include <linux/pci.h> 37219820Sjeff#include <linux/completion.h> 38219820Sjeff#include <linux/radix-tree.h> 39255932Salfred//#include <linux/cpu_rmap.h> /* XXX SK Probably not needed in freeBSD XXX */ 40219820Sjeff 41219820Sjeff#include <asm/atomic.h> 42219820Sjeff 43255932Salfred#include <linux/clocksource.h> /* XXX SK ported to freeBSD */ 44219820Sjeff 45255932Salfred#define MAX_MSIX_P_PORT 17 46255932Salfred#define MAX_MSIX 64 47255932Salfred#define MSIX_LEGACY_SZ 4 48255932Salfred#define MIN_MSIX_P_PORT 5 49255932Salfred 50255932Salfred#define MLX4_ROCE_MAX_GIDS 128 51255932Salfred#define MLX4_ROCE_PF_GIDS 16 52255932Salfred 53255932Salfred#define MLX4_NUM_UP 8 54255932Salfred#define MLX4_NUM_TC 8 55255932Salfred#define MLX4_MAX_100M_UNITS_VAL 255 /* 56255932Salfred * work around: can't set values 57255932Salfred * greater then this value when 58255932Salfred * using 100 Mbps units. 59255932Salfred */ 60255932Salfred#define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ 61255932Salfred#define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ 62255932Salfred#define MLX4_RATELIMIT_DEFAULT 0x00ff 63255932Salfred 64255932Salfred 65255932Salfred 66255932Salfred#define MLX4_LEAST_ATTACHED_VECTOR 0xffffffff 67255932Salfred 68219820Sjeffenum { 69219820Sjeff MLX4_FLAG_MSI_X = 1 << 0, 70219820Sjeff MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 71255932Salfred MLX4_FLAG_MASTER = 1 << 2, 72255932Salfred MLX4_FLAG_SLAVE = 1 << 3, 73255932Salfred MLX4_FLAG_SRIOV = 1 << 4, 74219820Sjeff}; 75219820Sjeff 76219820Sjeffenum { 77255932Salfred MLX4_PORT_CAP_IS_SM = 1 << 1, 78255932Salfred MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, 79219820Sjeff}; 80219820Sjeff 81219820Sjeffenum { 82255932Salfred MLX4_MAX_PORTS = 2, 83255932Salfred MLX4_MAX_PORT_PKEYS = 128 84255932Salfred}; 85255932Salfred 86255932Salfred/* base qkey for use in sriov tunnel-qp/proxy-qp communication. 87255932Salfred * These qkeys must not be allowed for general use. This is a 64k range, 88255932Salfred * and to test for violation, we use the mask (protect against future chg). 89255932Salfred */ 90255932Salfred#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) 91255932Salfred#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) 92255932Salfred 93255932Salfredenum { 94219820Sjeff MLX4_BOARD_ID_LEN = 64 95219820Sjeff}; 96219820Sjeff 97219820Sjeffenum { 98255932Salfred MLX4_MAX_NUM_PF = 16, 99255932Salfred MLX4_MAX_NUM_VF = 64, 100255932Salfred MLX4_MFUNC_MAX = 80, 101255932Salfred MLX4_MAX_EQ_NUM = 1024, 102255932Salfred MLX4_MFUNC_EQ_NUM = 4, 103255932Salfred MLX4_MFUNC_MAX_EQES = 8, 104255932Salfred MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) 105219820Sjeff}; 106219820Sjeff 107255932Salfred/* Driver supports 3 diffrent device methods to manage traffic steering: 108255932Salfred * -device managed - High level API for ib and eth flow steering. FW is 109255932Salfred * managing flow steering tables. 110255932Salfred * - B0 steering mode - Common low level API for ib and (if supported) eth. 111255932Salfred * - A0 steering mode - Limited low level API for eth. In case of IB, 112255932Salfred * B0 mode is in use. 113255932Salfred */ 114219820Sjeffenum { 115255932Salfred MLX4_STEERING_MODE_A0, 116255932Salfred MLX4_STEERING_MODE_B0, 117255932Salfred MLX4_STEERING_MODE_DEVICE_MANAGED 118255932Salfred}; 119255932Salfred 120255932Salfredstatic inline const char *mlx4_steering_mode_str(int steering_mode) 121255932Salfred{ 122255932Salfred switch (steering_mode) { 123255932Salfred case MLX4_STEERING_MODE_A0: 124255932Salfred return "A0 steering"; 125255932Salfred 126255932Salfred case MLX4_STEERING_MODE_B0: 127255932Salfred return "B0 steering"; 128255932Salfred 129255932Salfred case MLX4_STEERING_MODE_DEVICE_MANAGED: 130255932Salfred return "Device managed flow steering"; 131255932Salfred 132255932Salfred default: 133255932Salfred return "Unrecognize steering mode"; 134255932Salfred } 135255932Salfred} 136255932Salfred 137255932Salfredenum { 138255932Salfred MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 139255932Salfred MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 140255932Salfred MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 141255932Salfred MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, 142255932Salfred MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, 143255932Salfred MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, 144255932Salfred MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 145255932Salfred MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 146255932Salfred MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, 147255932Salfred MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, 148255932Salfred MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, 149255932Salfred MLX4_DEV_CAP_FLAG_APM = 1LL << 17, 150255932Salfred MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, 151255932Salfred MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, 152255932Salfred MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, 153255932Salfred MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, 154255932Salfred MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, 155255932Salfred MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, 156255932Salfred MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, 157255932Salfred MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, 158255932Salfred MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, 159255932Salfred MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, 160255932Salfred MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, 161255932Salfred MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, 162255932Salfred MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, 163255932Salfred MLX4_DEV_CAP_FLAG_COUNTERS_EXT = 1LL << 49, 164255932Salfred MLX4_DEV_CAP_FLAG_SET_PORT_ETH_SCHED = 1LL << 53, 165255932Salfred MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, 166255932Salfred MLX4_DEV_CAP_FLAG_FAST_DROP = 1LL << 57, 167255932Salfred MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, 168255932Salfred MLX4_DEV_CAP_FLAG_ESWITCH_SUPPORT = 1LL << 60, 169255932Salfred MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, 170255932Salfred MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 171255932Salfred}; 172255932Salfred 173255932Salfredenum { 174255932Salfred MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, 175255932Salfred MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, 176255932Salfred MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, 177255932Salfred MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3 178255932Salfred}; 179255932Salfred 180255932Salfredenum { 181255932Salfred MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, 182255932Salfred MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1 183255932Salfred}; 184255932Salfred 185255932Salfredenum { 186255932Salfred MLX4_USER_DEV_CAP_64B_CQE = 1L << 0 187255932Salfred}; 188255932Salfred 189255932Salfredenum { 190255932Salfred MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0 191255932Salfred}; 192255932Salfred 193255932Salfred/* bit enums for an 8-bit flags field indicating special use 194255932Salfred * QPs which require special handling in qp_reserve_range. 195255932Salfred * Currently, this only includes QPs used by the ETH interface, 196255932Salfred * where we expect to use blueflame. These QPs must not have 197255932Salfred * bits 6 and 7 set in their qp number. 198255932Salfred * 199255932Salfred * This enum may use only bits 0..7. 200255932Salfred */ 201255932Salfredenum { 202255932Salfred MLX4_RESERVE_BF_QP = 1 << 7, 203255932Salfred}; 204255932Salfred 205255932Salfred 206255932Salfred#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 207255932Salfred 208255932Salfredenum { 209219820Sjeff MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 210219820Sjeff MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 211219820Sjeff MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 212219820Sjeff MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 213219820Sjeff MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 214219820Sjeff}; 215219820Sjeff 216219820Sjeffenum mlx4_event { 217219820Sjeff MLX4_EVENT_TYPE_COMP = 0x00, 218219820Sjeff MLX4_EVENT_TYPE_PATH_MIG = 0x01, 219219820Sjeff MLX4_EVENT_TYPE_COMM_EST = 0x02, 220219820Sjeff MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 221219820Sjeff MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 222219820Sjeff MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 223219820Sjeff MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 224219820Sjeff MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 225219820Sjeff MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 226219820Sjeff MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 227219820Sjeff MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 228219820Sjeff MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 229219820Sjeff MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 230219820Sjeff MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 231219820Sjeff MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 232219820Sjeff MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 233219820Sjeff MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 234255932Salfred MLX4_EVENT_TYPE_CMD = 0x0a, 235255932Salfred MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, 236255932Salfred MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, 237255932Salfred MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, 238255932Salfred MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 239255932Salfred MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 240255932Salfred MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 241255932Salfred MLX4_EVENT_TYPE_NONE = 0xff, 242219820Sjeff}; 243219820Sjeff 244219820Sjeffenum { 245219820Sjeff MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 246219820Sjeff MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 247219820Sjeff}; 248219820Sjeff 249219820Sjeffenum { 250255932Salfred MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 251255932Salfred}; 252255932Salfred 253255932Salfredenum slave_port_state { 254255932Salfred SLAVE_PORT_DOWN = 0, 255255932Salfred SLAVE_PENDING_UP, 256255932Salfred SLAVE_PORT_UP, 257255932Salfred}; 258255932Salfred 259255932Salfredenum slave_port_gen_event { 260255932Salfred SLAVE_PORT_GEN_EVENT_DOWN = 0, 261255932Salfred SLAVE_PORT_GEN_EVENT_UP, 262255932Salfred SLAVE_PORT_GEN_EVENT_NONE, 263255932Salfred}; 264255932Salfred 265255932Salfredenum slave_port_state_event { 266255932Salfred MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 267255932Salfred MLX4_PORT_STATE_DEV_EVENT_PORT_UP, 268255932Salfred MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, 269255932Salfred MLX4_PORT_STATE_IB_EVENT_GID_INVALID, 270255932Salfred}; 271255932Salfred 272255932Salfredenum { 273219820Sjeff MLX4_PERM_LOCAL_READ = 1 << 10, 274219820Sjeff MLX4_PERM_LOCAL_WRITE = 1 << 11, 275219820Sjeff MLX4_PERM_REMOTE_READ = 1 << 12, 276219820Sjeff MLX4_PERM_REMOTE_WRITE = 1 << 13, 277219820Sjeff MLX4_PERM_ATOMIC = 1 << 14 278219820Sjeff}; 279219820Sjeff 280219820Sjeffenum { 281219820Sjeff MLX4_OPCODE_NOP = 0x00, 282219820Sjeff MLX4_OPCODE_SEND_INVAL = 0x01, 283219820Sjeff MLX4_OPCODE_RDMA_WRITE = 0x08, 284219820Sjeff MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 285219820Sjeff MLX4_OPCODE_SEND = 0x0a, 286219820Sjeff MLX4_OPCODE_SEND_IMM = 0x0b, 287219820Sjeff MLX4_OPCODE_LSO = 0x0e, 288219820Sjeff MLX4_OPCODE_RDMA_READ = 0x10, 289219820Sjeff MLX4_OPCODE_ATOMIC_CS = 0x11, 290219820Sjeff MLX4_OPCODE_ATOMIC_FA = 0x12, 291219820Sjeff MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 292219820Sjeff MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 293219820Sjeff MLX4_OPCODE_BIND_MW = 0x18, 294219820Sjeff MLX4_OPCODE_FMR = 0x19, 295219820Sjeff MLX4_OPCODE_LOCAL_INVAL = 0x1b, 296219820Sjeff MLX4_OPCODE_CONFIG_CMD = 0x1f, 297219820Sjeff 298219820Sjeff MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 299219820Sjeff MLX4_RECV_OPCODE_SEND = 0x01, 300219820Sjeff MLX4_RECV_OPCODE_SEND_IMM = 0x02, 301219820Sjeff MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 302219820Sjeff 303219820Sjeff MLX4_CQE_OPCODE_ERROR = 0x1e, 304219820Sjeff MLX4_CQE_OPCODE_RESIZE = 0x16, 305219820Sjeff}; 306219820Sjeff 307219820Sjeffenum { 308219820Sjeff MLX4_STAT_RATE_OFFSET = 5 309219820Sjeff}; 310219820Sjeff 311255932Salfredenum mlx4_protocol { 312255932Salfred MLX4_PROT_IB_IPV6 = 0, 313255932Salfred MLX4_PROT_ETH, 314255932Salfred MLX4_PROT_IB_IPV4, 315255932Salfred MLX4_PROT_FCOE 316255932Salfred}; 317255932Salfred 318219820Sjeffenum { 319219820Sjeff MLX4_MTT_FLAG_PRESENT = 1 320219820Sjeff}; 321219820Sjeff 322255932Salfredenum { 323255932Salfred MLX4_MAX_MTT_SHIFT = 31 324255932Salfred}; 325255932Salfred 326219820Sjeffenum mlx4_qp_region { 327219820Sjeff MLX4_QP_REGION_FW = 0, 328219820Sjeff MLX4_QP_REGION_ETH_ADDR, 329219820Sjeff MLX4_QP_REGION_FC_ADDR, 330255932Salfred MLX4_QP_REGION_FC_EXCH, 331219820Sjeff MLX4_NUM_QP_REGION 332219820Sjeff}; 333219820Sjeff 334219820Sjeffenum mlx4_port_type { 335219820Sjeff MLX4_PORT_TYPE_NONE = 0, 336219820Sjeff MLX4_PORT_TYPE_IB = 1, 337219820Sjeff MLX4_PORT_TYPE_ETH = 2, 338219820Sjeff MLX4_PORT_TYPE_AUTO = 3 339219820Sjeff}; 340219820Sjeff 341219820Sjeffenum mlx4_special_vlan_idx { 342219820Sjeff MLX4_NO_VLAN_IDX = 0, 343219820Sjeff MLX4_VLAN_MISS_IDX, 344219820Sjeff MLX4_VLAN_REGULAR 345219820Sjeff}; 346219820Sjeff 347255932Salfredenum mlx4_steer_type { 348255932Salfred MLX4_MC_STEER = 0, 349255932Salfred MLX4_UC_STEER, 350255932Salfred MLX4_NUM_STEERS 351255932Salfred}; 352255932Salfred 353219820Sjeffenum { 354255932Salfred MLX4_NUM_FEXCH = 64 * 1024, 355219820Sjeff}; 356219820Sjeff 357219820Sjeffenum { 358255932Salfred MLX4_MAX_FAST_REG_PAGES = 511, 359219820Sjeff}; 360219820Sjeff 361255932Salfredenum { 362255932Salfred MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, 363255932Salfred MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, 364255932Salfred MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, 365255932Salfred}; 366255932Salfred 367255932Salfred/* Port mgmt change event handling */ 368255932Salfredenum { 369255932Salfred MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, 370255932Salfred MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, 371255932Salfred MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, 372255932Salfred MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, 373255932Salfred MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 374255932Salfred}; 375255932Salfred 376255932Salfred#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 377255932Salfred MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 378255932Salfred 379219820Sjeffstatic inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 380219820Sjeff{ 381219820Sjeff return (major << 32) | (minor << 16) | subminor; 382219820Sjeff} 383219820Sjeff 384255932Salfredstruct mlx4_phys_caps { 385255932Salfred u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; 386255932Salfred u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; 387255932Salfred u32 num_phys_eqs; 388255932Salfred u32 base_sqpn; 389255932Salfred u32 base_proxy_sqpn; 390255932Salfred u32 base_tunnel_sqpn; 391255932Salfred}; 392255932Salfred 393219820Sjeffstruct mlx4_caps { 394219820Sjeff u64 fw_ver; 395255932Salfred u32 function; 396219820Sjeff int num_ports; 397219820Sjeff int vl_cap[MLX4_MAX_PORTS + 1]; 398219820Sjeff int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 399219820Sjeff __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 400219820Sjeff u64 def_mac[MLX4_MAX_PORTS + 1]; 401219820Sjeff int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 402219820Sjeff int gid_table_len[MLX4_MAX_PORTS + 1]; 403219820Sjeff int pkey_table_len[MLX4_MAX_PORTS + 1]; 404219820Sjeff int trans_type[MLX4_MAX_PORTS + 1]; 405219820Sjeff int vendor_oui[MLX4_MAX_PORTS + 1]; 406219820Sjeff int wavelength[MLX4_MAX_PORTS + 1]; 407219820Sjeff u64 trans_code[MLX4_MAX_PORTS + 1]; 408219820Sjeff int local_ca_ack_delay; 409219820Sjeff int num_uars; 410255932Salfred u32 uar_page_size; 411219820Sjeff int bf_reg_size; 412219820Sjeff int bf_regs_per_page; 413219820Sjeff int max_sq_sg; 414219820Sjeff int max_rq_sg; 415219820Sjeff int num_qps; 416219820Sjeff int max_wqes; 417219820Sjeff int max_sq_desc_sz; 418219820Sjeff int max_rq_desc_sz; 419219820Sjeff int max_qp_init_rdma; 420219820Sjeff int max_qp_dest_rdma; 421255932Salfred u32 *qp0_proxy; 422255932Salfred u32 *qp1_proxy; 423255932Salfred u32 *qp0_tunnel; 424255932Salfred u32 *qp1_tunnel; 425219820Sjeff int num_srqs; 426219820Sjeff int max_srq_wqes; 427219820Sjeff int max_srq_sge; 428219820Sjeff int reserved_srqs; 429219820Sjeff int num_cqs; 430219820Sjeff int max_cqes; 431219820Sjeff int reserved_cqs; 432219820Sjeff int num_eqs; 433219820Sjeff int reserved_eqs; 434219820Sjeff int num_comp_vectors; 435255932Salfred int comp_pool; 436219820Sjeff int num_mpts; 437255932Salfred int max_fmr_maps; 438255932Salfred int num_mtts; 439219820Sjeff int fmr_reserved_mtts; 440219820Sjeff int reserved_mtts; 441219820Sjeff int reserved_mrws; 442219820Sjeff int reserved_uars; 443219820Sjeff int num_mgms; 444219820Sjeff int num_amgms; 445219820Sjeff int reserved_mcgs; 446219820Sjeff int num_qp_per_mgm; 447255932Salfred int steering_mode; 448219820Sjeff int num_pds; 449219820Sjeff int reserved_pds; 450255932Salfred int max_xrcds; 451255932Salfred int reserved_xrcds; 452219820Sjeff int mtt_entry_sz; 453219820Sjeff u32 max_msg_sz; 454219820Sjeff u32 page_size_cap; 455219820Sjeff u64 flags; 456255932Salfred u64 flags2; 457219820Sjeff u32 bmme_flags; 458219820Sjeff u32 reserved_lkey; 459219820Sjeff u16 stat_rate_support; 460255932Salfred u8 cq_timestamp; 461219820Sjeff u8 port_width_cap[MLX4_MAX_PORTS + 1]; 462219820Sjeff int max_gso_sz; 463255932Salfred int max_rss_tbl_sz; 464219820Sjeff int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 465219820Sjeff int reserved_qps; 466219820Sjeff int reserved_qps_base[MLX4_NUM_QP_REGION]; 467219820Sjeff int log_num_macs; 468219820Sjeff int log_num_vlans; 469219820Sjeff enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 470219820Sjeff u8 supported_type[MLX4_MAX_PORTS + 1]; 471255932Salfred u8 suggested_type[MLX4_MAX_PORTS + 1]; 472255932Salfred u8 default_sense[MLX4_MAX_PORTS + 1]; 473255932Salfred u32 port_mask[MLX4_MAX_PORTS + 1]; 474219820Sjeff enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 475255932Salfred u32 max_counters; 476255932Salfred u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; 477255932Salfred u16 sqp_demux; 478255932Salfred u32 sync_qp; 479255932Salfred u32 eqe_size; 480255932Salfred u32 cqe_size; 481255932Salfred u8 eqe_factor; 482255932Salfred u32 userspace_caps; /* userspace must be aware to */ 483255932Salfred u32 function_caps; /* functions must be aware to */ 484255932Salfred u8 fast_drop; 485255932Salfred u16 hca_core_clock; 486219820Sjeff u32 max_basic_counters; 487255932Salfred u32 max_extended_counters; 488219820Sjeff}; 489219820Sjeff 490219820Sjeffstruct mlx4_buf_list { 491219820Sjeff void *buf; 492219820Sjeff dma_addr_t map; 493219820Sjeff}; 494219820Sjeff 495219820Sjeffstruct mlx4_buf { 496219820Sjeff struct mlx4_buf_list direct; 497219820Sjeff struct mlx4_buf_list *page_list; 498219820Sjeff int nbufs; 499219820Sjeff int npages; 500219820Sjeff int page_shift; 501219820Sjeff}; 502219820Sjeff 503219820Sjeffstruct mlx4_mtt { 504255932Salfred u32 offset; 505219820Sjeff int order; 506219820Sjeff int page_shift; 507219820Sjeff}; 508219820Sjeff 509219820Sjeffenum { 510219820Sjeff MLX4_DB_PER_PAGE = PAGE_SIZE / 4 511219820Sjeff}; 512219820Sjeff 513219820Sjeffstruct mlx4_db_pgdir { 514219820Sjeff struct list_head list; 515219820Sjeff DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 516219820Sjeff DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 517219820Sjeff unsigned long *bits[2]; 518219820Sjeff __be32 *db_page; 519219820Sjeff dma_addr_t db_dma; 520219820Sjeff}; 521219820Sjeff 522219820Sjeffstruct mlx4_ib_user_db_page; 523219820Sjeff 524219820Sjeffstruct mlx4_db { 525219820Sjeff __be32 *db; 526219820Sjeff union { 527219820Sjeff struct mlx4_db_pgdir *pgdir; 528219820Sjeff struct mlx4_ib_user_db_page *user_page; 529219820Sjeff } u; 530219820Sjeff dma_addr_t dma; 531219820Sjeff int index; 532219820Sjeff int order; 533219820Sjeff}; 534219820Sjeff 535219820Sjeffstruct mlx4_hwq_resources { 536219820Sjeff struct mlx4_db db; 537219820Sjeff struct mlx4_mtt mtt; 538219820Sjeff struct mlx4_buf buf; 539219820Sjeff}; 540219820Sjeff 541219820Sjeffstruct mlx4_mr { 542219820Sjeff struct mlx4_mtt mtt; 543219820Sjeff u64 iova; 544219820Sjeff u64 size; 545219820Sjeff u32 key; 546219820Sjeff u32 pd; 547219820Sjeff u32 access; 548219820Sjeff int enabled; 549219820Sjeff}; 550219820Sjeff 551219820Sjeffstruct mlx4_fmr { 552219820Sjeff struct mlx4_mr mr; 553219820Sjeff struct mlx4_mpt_entry *mpt; 554219820Sjeff __be64 *mtts; 555219820Sjeff dma_addr_t dma_handle; 556219820Sjeff int max_pages; 557219820Sjeff int max_maps; 558219820Sjeff int maps; 559219820Sjeff u8 page_shift; 560219820Sjeff}; 561219820Sjeff 562219820Sjeffstruct mlx4_uar { 563219820Sjeff unsigned long pfn; 564219820Sjeff int index; 565219820Sjeff struct list_head bf_list; 566219820Sjeff unsigned free_bf_bmap; 567219820Sjeff void __iomem *map; 568219820Sjeff void __iomem *bf_map; 569219820Sjeff}; 570219820Sjeff 571219820Sjeffstruct mlx4_bf { 572219820Sjeff unsigned long offset; 573219820Sjeff int buf_size; 574219820Sjeff struct mlx4_uar *uar; 575219820Sjeff void __iomem *reg; 576219820Sjeff}; 577219820Sjeff 578219820Sjeffstruct mlx4_cq { 579219820Sjeff void (*comp) (struct mlx4_cq *); 580219820Sjeff void (*event) (struct mlx4_cq *, enum mlx4_event); 581219820Sjeff 582219820Sjeff struct mlx4_uar *uar; 583219820Sjeff 584219820Sjeff u32 cons_index; 585219820Sjeff 586219820Sjeff __be32 *set_ci_db; 587219820Sjeff __be32 *arm_db; 588219820Sjeff int arm_sn; 589219820Sjeff 590219820Sjeff int cqn; 591219820Sjeff unsigned vector; 592219820Sjeff 593219820Sjeff atomic_t refcount; 594219820Sjeff struct completion free; 595255932Salfred int eqn; 596255932Salfred u16 irq; 597219820Sjeff}; 598219820Sjeff 599219820Sjeffstruct mlx4_qp { 600219820Sjeff void (*event) (struct mlx4_qp *, enum mlx4_event); 601219820Sjeff 602219820Sjeff int qpn; 603219820Sjeff 604219820Sjeff atomic_t refcount; 605219820Sjeff struct completion free; 606219820Sjeff}; 607219820Sjeff 608219820Sjeffstruct mlx4_srq { 609219820Sjeff void (*event) (struct mlx4_srq *, enum mlx4_event); 610219820Sjeff 611219820Sjeff int srqn; 612219820Sjeff int max; 613219820Sjeff int max_gs; 614219820Sjeff int wqe_shift; 615219820Sjeff 616219820Sjeff atomic_t refcount; 617219820Sjeff struct completion free; 618219820Sjeff}; 619219820Sjeff 620219820Sjeffstruct mlx4_av { 621219820Sjeff __be32 port_pd; 622219820Sjeff u8 reserved1; 623219820Sjeff u8 g_slid; 624219820Sjeff __be16 dlid; 625219820Sjeff u8 reserved2; 626219820Sjeff u8 gid_index; 627219820Sjeff u8 stat_rate; 628219820Sjeff u8 hop_limit; 629219820Sjeff __be32 sl_tclass_flowlabel; 630219820Sjeff u8 dgid[16]; 631219820Sjeff}; 632219820Sjeff 633219820Sjeffstruct mlx4_eth_av { 634219820Sjeff __be32 port_pd; 635219820Sjeff u8 reserved1; 636219820Sjeff u8 smac_idx; 637219820Sjeff u16 reserved2; 638219820Sjeff u8 reserved3; 639219820Sjeff u8 gid_index; 640219820Sjeff u8 stat_rate; 641219820Sjeff u8 hop_limit; 642219820Sjeff __be32 sl_tclass_flowlabel; 643219820Sjeff u8 dgid[16]; 644219820Sjeff u32 reserved4[2]; 645219820Sjeff __be16 vlan; 646219820Sjeff u8 mac[6]; 647219820Sjeff}; 648219820Sjeff 649219820Sjeffunion mlx4_ext_av { 650219820Sjeff struct mlx4_av ib; 651219820Sjeff struct mlx4_eth_av eth; 652219820Sjeff}; 653219820Sjeff 654255932Salfredstruct mlx4_if_stat_control { 655255932Salfred u8 reserved1[3]; 656255932Salfred /* Extended counters enabled */ 657255932Salfred u8 cnt_mode; 658255932Salfred /* Number of interfaces */ 659255932Salfred __be32 num_of_if; 660255932Salfred __be32 reserved[2]; 661219820Sjeff}; 662219820Sjeff 663255932Salfredstruct mlx4_if_stat_basic { 664255932Salfred struct mlx4_if_stat_control control; 665255932Salfred struct { 666255932Salfred __be64 IfRxFrames; 667255932Salfred __be64 IfRxOctets; 668255932Salfred __be64 IfTxFrames; 669255932Salfred __be64 IfTxOctets; 670255932Salfred } counters[]; 671219820Sjeff}; 672255932Salfred#define MLX4_IF_STAT_BSC_SZ(ports)(sizeof(struct mlx4_if_stat_extended) +\ 673255932Salfred sizeof(((struct mlx4_if_stat_extended *)0)->\ 674255932Salfred counters[0]) * ports) 675219820Sjeff 676255932Salfredstruct mlx4_if_stat_extended { 677255932Salfred struct mlx4_if_stat_control control; 678255932Salfred struct { 679255932Salfred __be64 IfRxUnicastFrames; 680255932Salfred __be64 IfRxUnicastOctets; 681255932Salfred __be64 IfRxMulticastFrames; 682255932Salfred __be64 IfRxMulticastOctets; 683255932Salfred __be64 IfRxBroadcastFrames; 684255932Salfred __be64 IfRxBroadcastOctets; 685255932Salfred __be64 IfRxNoBufferFrames; 686255932Salfred __be64 IfRxNoBufferOctets; 687255932Salfred __be64 IfRxErrorFrames; 688255932Salfred __be64 IfRxErrorOctets; 689255932Salfred __be32 reserved[39]; 690255932Salfred __be64 IfTxUnicastFrames; 691255932Salfred __be64 IfTxUnicastOctets; 692255932Salfred __be64 IfTxMulticastFrames; 693255932Salfred __be64 IfTxMulticastOctets; 694255932Salfred __be64 IfTxBroadcastFrames; 695255932Salfred __be64 IfTxBroadcastOctets; 696255932Salfred __be64 IfTxDroppedFrames; 697255932Salfred __be64 IfTxDroppedOctets; 698255932Salfred __be64 IfTxRequestedFramesSent; 699255932Salfred __be64 IfTxGeneratedFramesSent; 700255932Salfred __be64 IfTxTsoOctets; 701255932Salfred } __packed counters[]; 702255932Salfred}; 703255932Salfred#define MLX4_IF_STAT_EXT_SZ(ports) (sizeof(struct mlx4_if_stat_extended) +\ 704255932Salfred sizeof(((struct mlx4_if_stat_extended *)\ 705255932Salfred 0)->counters[0]) * ports) 706255932Salfred 707255932Salfredunion mlx4_counter { 708255932Salfred struct mlx4_if_stat_control control; 709255932Salfred struct mlx4_if_stat_basic basic; 710255932Salfred struct mlx4_if_stat_extended ext; 711255932Salfred}; 712255932Salfred#define MLX4_IF_STAT_SZ(ports) MLX4_IF_STAT_EXT_SZ(ports) 713255932Salfred 714255932Salfredstruct mlx4_quotas { 715255932Salfred int qp; 716255932Salfred int cq; 717255932Salfred int srq; 718255932Salfred int mpt; 719255932Salfred int mtt; 720255932Salfred int counter; 721255932Salfred int xrcd; 722255932Salfred}; 723255932Salfred 724219820Sjeffstruct mlx4_dev { 725219820Sjeff struct pci_dev *pdev; 726219820Sjeff unsigned long flags; 727255932Salfred unsigned long num_slaves; 728219820Sjeff struct mlx4_caps caps; 729255932Salfred struct mlx4_phys_caps phys_caps; 730255932Salfred struct mlx4_quotas quotas; 731219820Sjeff struct radix_tree_root qp_table_tree; 732255932Salfred u8 rev_id; 733219820Sjeff char board_id[MLX4_BOARD_ID_LEN]; 734255932Salfred int num_vfs; 735255932Salfred int numa_node; 736255932Salfred int oper_log_mgm_entry_size; 737255932Salfred u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 738255932Salfred u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 739219820Sjeff}; 740219820Sjeff 741255932Salfredstruct mlx4_eqe { 742255932Salfred u8 reserved1; 743255932Salfred u8 type; 744255932Salfred u8 reserved2; 745255932Salfred u8 subtype; 746255932Salfred union { 747255932Salfred u32 raw[6]; 748255932Salfred struct { 749255932Salfred __be32 cqn; 750255932Salfred } __packed comp; 751255932Salfred struct { 752255932Salfred u16 reserved1; 753255932Salfred __be16 token; 754255932Salfred u32 reserved2; 755255932Salfred u8 reserved3[3]; 756255932Salfred u8 status; 757255932Salfred __be64 out_param; 758255932Salfred } __packed cmd; 759255932Salfred struct { 760255932Salfred __be32 qpn; 761255932Salfred } __packed qp; 762255932Salfred struct { 763255932Salfred __be32 srqn; 764255932Salfred } __packed srq; 765255932Salfred struct { 766255932Salfred __be32 cqn; 767255932Salfred u32 reserved1; 768255932Salfred u8 reserved2[3]; 769255932Salfred u8 syndrome; 770255932Salfred } __packed cq_err; 771255932Salfred struct { 772255932Salfred u32 reserved1[2]; 773255932Salfred __be32 port; 774255932Salfred } __packed port_change; 775255932Salfred struct { 776255932Salfred #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 777255932Salfred u32 reserved; 778255932Salfred u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 779255932Salfred } __packed comm_channel_arm; 780255932Salfred struct { 781255932Salfred u8 port; 782255932Salfred u8 reserved[3]; 783255932Salfred __be64 mac; 784255932Salfred } __packed mac_update; 785255932Salfred struct { 786255932Salfred __be32 slave_id; 787255932Salfred } __packed flr_event; 788255932Salfred struct { 789255932Salfred __be16 current_temperature; 790255932Salfred __be16 warning_threshold; 791255932Salfred } __packed warming; 792255932Salfred struct { 793255932Salfred u8 reserved[3]; 794255932Salfred u8 port; 795255932Salfred union { 796255932Salfred struct { 797255932Salfred __be16 mstr_sm_lid; 798255932Salfred __be16 port_lid; 799255932Salfred __be32 changed_attr; 800255932Salfred u8 reserved[3]; 801255932Salfred u8 mstr_sm_sl; 802255932Salfred __be64 gid_prefix; 803255932Salfred } __packed port_info; 804255932Salfred struct { 805255932Salfred __be32 block_ptr; 806255932Salfred __be32 tbl_entries_mask; 807255932Salfred } __packed tbl_change_info; 808255932Salfred } params; 809255932Salfred } __packed port_mgmt_change; 810255932Salfred } event; 811255932Salfred u8 slave_id; 812255932Salfred u8 reserved3[2]; 813255932Salfred u8 owner; 814255932Salfred} __packed; 815255932Salfred 816219820Sjeffstruct mlx4_init_port_param { 817219820Sjeff int set_guid0; 818219820Sjeff int set_node_guid; 819219820Sjeff int set_si_guid; 820219820Sjeff u16 mtu; 821219820Sjeff int port_width_cap; 822219820Sjeff u16 vl_cap; 823219820Sjeff u16 max_gid; 824219820Sjeff u16 max_pkey; 825219820Sjeff u64 guid0; 826219820Sjeff u64 node_guid; 827219820Sjeff u64 si_guid; 828219820Sjeff}; 829219820Sjeff 830219820Sjeff#define mlx4_foreach_port(port, dev, type) \ 831219820Sjeff for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 832219820Sjeff if ((type) == (dev)->caps.port_mask[(port)]) 833219820Sjeff 834255932Salfred#define mlx4_foreach_non_ib_transport_port(port, dev) \ 835255932Salfred for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 836255932Salfred if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) 837255932Salfred 838219820Sjeff#define mlx4_foreach_ib_transport_port(port, dev) \ 839255932Salfred for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 840219820Sjeff if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 841219820Sjeff ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 842219820Sjeff 843255932Salfred#define MLX4_INVALID_SLAVE_ID 0xFF 844255932Salfred 845255932Salfredvoid handle_port_mgmt_change_event(struct work_struct *work); 846255932Salfred 847255932Salfredstatic inline int mlx4_master_func_num(struct mlx4_dev *dev) 848255932Salfred{ 849255932Salfred return dev->caps.function; 850255932Salfred} 851255932Salfred 852255932Salfredstatic inline int mlx4_is_master(struct mlx4_dev *dev) 853255932Salfred{ 854255932Salfred return dev->flags & MLX4_FLAG_MASTER; 855255932Salfred} 856255932Salfred 857255932Salfredstatic inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) 858255932Salfred{ 859255932Salfred return dev->phys_caps.base_sqpn + 8 + 860255932Salfred 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); 861255932Salfred} 862255932Salfred 863255932Salfredstatic inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) 864255932Salfred{ 865255932Salfred return (qpn < dev->phys_caps.base_sqpn + 8 + 866255932Salfred 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); 867255932Salfred} 868255932Salfred 869255932Salfredstatic inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) 870255932Salfred{ 871255932Salfred int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; 872255932Salfred 873255932Salfred if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) 874255932Salfred return 1; 875255932Salfred 876255932Salfred return 0; 877255932Salfred} 878255932Salfred 879255932Salfredstatic inline int mlx4_is_mfunc(struct mlx4_dev *dev) 880255932Salfred{ 881255932Salfred return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); 882255932Salfred} 883255932Salfred 884255932Salfredstatic inline int mlx4_is_slave(struct mlx4_dev *dev) 885255932Salfred{ 886255932Salfred return dev->flags & MLX4_FLAG_SLAVE; 887255932Salfred} 888255932Salfred 889219820Sjeffint mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 890219820Sjeff struct mlx4_buf *buf); 891219820Sjeffvoid mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 892219820Sjeffstatic inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 893219820Sjeff{ 894255932Salfred if (BITS_PER_LONG == 64 || buf->nbufs == 1) 895219820Sjeff return buf->direct.buf + offset; 896219820Sjeff else 897219820Sjeff return buf->page_list[offset >> PAGE_SHIFT].buf + 898219820Sjeff (offset & (PAGE_SIZE - 1)); 899219820Sjeff} 900219820Sjeff 901219820Sjeffint mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 902219820Sjeffvoid mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 903219820Sjeffint mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 904219820Sjeffvoid mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 905219820Sjeff 906219820Sjeffint mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 907219820Sjeffvoid mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 908255932Salfredint mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); 909219820Sjeffvoid mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 910219820Sjeff 911219820Sjeffint mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 912219820Sjeff struct mlx4_mtt *mtt); 913219820Sjeffvoid mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 914219820Sjeffu64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 915219820Sjeff 916219820Sjeffint mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 917219820Sjeff int npages, int page_shift, struct mlx4_mr *mr); 918219820Sjeffvoid mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 919219820Sjeffint mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 920219820Sjeffint mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 921219820Sjeff int start_index, int npages, u64 *page_list); 922219820Sjeffint mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 923219820Sjeff struct mlx4_buf *buf); 924219820Sjeff 925219820Sjeffint mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 926219820Sjeffvoid mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 927219820Sjeff 928219820Sjeffint mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 929219820Sjeff int size, int max_direct); 930219820Sjeffvoid mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 931219820Sjeff int size); 932219820Sjeff 933219820Sjeffint mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 934219820Sjeff struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 935255932Salfred unsigned vector, int collapsed, int timestamp_en); 936219820Sjeffvoid mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 937219820Sjeff 938255932Salfredint mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 939255932Salfred int *base, u8 bf_qp); 940219820Sjeffvoid mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 941219820Sjeff 942219820Sjeffint mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 943219820Sjeffvoid mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 944219820Sjeff 945255932Salfredint mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, 946219820Sjeff struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 947219820Sjeffvoid mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 948219820Sjeffint mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 949219820Sjeffint mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 950219820Sjeff 951219820Sjeffint mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 952219820Sjeffint mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 953219820Sjeff 954255932Salfredint mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 955255932Salfred int block_mcast_loopback, enum mlx4_protocol prot); 956255932Salfredint mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 957255932Salfred enum mlx4_protocol prot); 958219820Sjeffint mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 959255932Salfred u8 port, int block_mcast_loopback, 960255932Salfred enum mlx4_protocol protocol, u64 *reg_id); 961219820Sjeffint mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 962255932Salfred enum mlx4_protocol protocol, u64 reg_id); 963219820Sjeff 964255932Salfredenum { 965255932Salfred MLX4_DOMAIN_UVERBS = 0x1000, 966255932Salfred MLX4_DOMAIN_ETHTOOL = 0x2000, 967255932Salfred MLX4_DOMAIN_RFS = 0x3000, 968255932Salfred MLX4_DOMAIN_NIC = 0x5000, 969255932Salfred}; 970219820Sjeff 971255932Salfredenum mlx4_net_trans_rule_id { 972255932Salfred MLX4_NET_TRANS_RULE_ID_ETH = 0, 973255932Salfred MLX4_NET_TRANS_RULE_ID_IB, 974255932Salfred MLX4_NET_TRANS_RULE_ID_IPV6, 975255932Salfred MLX4_NET_TRANS_RULE_ID_IPV4, 976255932Salfred MLX4_NET_TRANS_RULE_ID_TCP, 977255932Salfred MLX4_NET_TRANS_RULE_ID_UDP, 978255932Salfred MLX4_NET_TRANS_RULE_NUM, /* should be last */ 979255932Salfred}; 980255932Salfred 981255932Salfredextern const u16 __sw_id_hw[]; 982255932Salfred 983255932Salfredstatic inline int map_hw_to_sw_id(u16 header_id) 984255932Salfred{ 985255932Salfred 986255932Salfred int i; 987255932Salfred for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { 988255932Salfred if (header_id == __sw_id_hw[i]) 989255932Salfred return i; 990255932Salfred } 991255932Salfred return -EINVAL; 992255932Salfred} 993255932Salfredenum mlx4_net_trans_promisc_mode { 994255932Salfred MLX4_FS_REGULAR = 0, 995255932Salfred MLX4_FS_ALL_DEFAULT = 1, 996255932Salfred MLX4_FS_MC_DEFAULT = 3, 997255932Salfred MLX4_FS_UC_SNIFFER = 4, 998255932Salfred MLX4_FS_MC_SNIFFER = 5, 999255932Salfred}; 1000255932Salfred 1001255932Salfredstruct mlx4_spec_eth { 1002255932Salfred u8 dst_mac[6]; 1003255932Salfred u8 dst_mac_msk[6]; 1004255932Salfred u8 src_mac[6]; 1005255932Salfred u8 src_mac_msk[6]; 1006255932Salfred u8 ether_type_enable; 1007255932Salfred __be16 ether_type; 1008255932Salfred __be16 vlan_id_msk; 1009255932Salfred __be16 vlan_id; 1010255932Salfred}; 1011255932Salfred 1012255932Salfredstruct mlx4_spec_tcp_udp { 1013255932Salfred __be16 dst_port; 1014255932Salfred __be16 dst_port_msk; 1015255932Salfred __be16 src_port; 1016255932Salfred __be16 src_port_msk; 1017255932Salfred}; 1018255932Salfred 1019255932Salfredstruct mlx4_spec_ipv4 { 1020255932Salfred __be32 dst_ip; 1021255932Salfred __be32 dst_ip_msk; 1022255932Salfred __be32 src_ip; 1023255932Salfred __be32 src_ip_msk; 1024255932Salfred}; 1025255932Salfred 1026255932Salfredstruct mlx4_spec_ib { 1027255932Salfred __be32 r_u_qpn; 1028255932Salfred __be32 qpn_msk; 1029255932Salfred u8 dst_gid[16]; 1030255932Salfred u8 dst_gid_msk[16]; 1031255932Salfred}; 1032255932Salfred 1033255932Salfredstruct mlx4_spec_list { 1034255932Salfred struct list_head list; 1035255932Salfred enum mlx4_net_trans_rule_id id; 1036255932Salfred union { 1037255932Salfred struct mlx4_spec_eth eth; 1038255932Salfred struct mlx4_spec_ib ib; 1039255932Salfred struct mlx4_spec_ipv4 ipv4; 1040255932Salfred struct mlx4_spec_tcp_udp tcp_udp; 1041255932Salfred }; 1042255932Salfred}; 1043255932Salfred 1044255932Salfredenum mlx4_net_trans_hw_rule_queue { 1045255932Salfred MLX4_NET_TRANS_Q_FIFO, 1046255932Salfred MLX4_NET_TRANS_Q_LIFO, 1047255932Salfred}; 1048255932Salfred 1049255932Salfredstruct mlx4_net_trans_rule { 1050255932Salfred struct list_head list; 1051255932Salfred enum mlx4_net_trans_hw_rule_queue queue_mode; 1052255932Salfred bool exclusive; 1053255932Salfred bool allow_loopback; 1054255932Salfred enum mlx4_net_trans_promisc_mode promisc_mode; 1055255932Salfred u8 port; 1056255932Salfred u16 priority; 1057255932Salfred u32 qpn; 1058255932Salfred}; 1059255932Salfred 1060255932Salfredint mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1061255932Salfred enum mlx4_net_trans_promisc_mode mode); 1062255932Salfredint mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1063255932Salfred enum mlx4_net_trans_promisc_mode mode); 1064255932Salfredint mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1065255932Salfredint mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1066255932Salfredint mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); 1067255932Salfredint mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); 1068255932Salfredint mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 1069255932Salfred 1070255932Salfredint mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1071255932Salfredvoid mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1072255932Salfredint mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); 1073255932Salfredint __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 1074255932Salfredvoid mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); 1075255932Salfredint mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 1076255932Salfred u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 1077255932Salfredint mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 1078255932Salfred u8 promisc); 1079255932Salfredint mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); 1080255932Salfredint mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, 1081255932Salfred u8 *pg, u16 *ratelimit); 1082219820Sjeffint mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1083219820Sjeffint mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1084255932Salfredvoid mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1085219820Sjeff 1086219820Sjeffint mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 1087219820Sjeff int npages, u64 iova, u32 *lkey, u32 *rkey); 1088219820Sjeffint mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 1089219820Sjeff int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 1090219820Sjeffint mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1091219820Sjeffvoid mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 1092219820Sjeff u32 *lkey, u32 *rkey); 1093219820Sjeffint mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 1094219820Sjeffint mlx4_SYNC_TPT(struct mlx4_dev *dev); 1095219820Sjeffint mlx4_query_diag_counters(struct mlx4_dev *mlx4_dev, int array_length, 1096255932Salfred u8 op_modifier, u32 in_offset[], 1097255932Salfred u32 counter_out[]); 1098255932Salfred 1099219820Sjeffint mlx4_test_interrupts(struct mlx4_dev *dev); 1100255932Salfredint mlx4_assign_eq(struct mlx4_dev *dev, char *name, int *vector); 1101255932Salfredvoid mlx4_release_eq(struct mlx4_dev *dev, int vec); 1102219820Sjeff 1103255932Salfredint mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1104255932Salfredint mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1105219820Sjeff 1106219820Sjeffint mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1107219820Sjeffvoid mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1108219820Sjeff 1109255932Salfredint mlx4_flow_attach(struct mlx4_dev *dev, 1110255932Salfred struct mlx4_net_trans_rule *rule, u64 *reg_id); 1111255932Salfredint mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); 1112255932Salfred 1113255932Salfredvoid mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, 1114255932Salfred int i, int val); 1115255932Salfred 1116255932Salfredint mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); 1117255932Salfred 1118255932Salfredint mlx4_is_slave_active(struct mlx4_dev *dev, int slave); 1119255932Salfredint mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); 1120255932Salfredint mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); 1121255932Salfredint mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); 1122255932Salfredint mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); 1123255932Salfredenum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); 1124255932Salfredint set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); 1125255932Salfred 1126255932Salfredvoid mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); 1127255932Salfred__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); 1128255932Salfredint mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, int *slave_id); 1129255932Salfredint mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, u8 *gid); 1130255932Salfred 1131255932Salfredint mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, u32 max_range_qpn); 1132255932Salfred 1133255932Salfredcycle_t mlx4_read_clock(struct mlx4_dev *dev); 1134255932Salfred 1135219820Sjeff#endif /* MLX4_DEVICE_H */ 1136