rt305xreg.h revision 220297
1/*- 2 * Copyright (c) 2010 Aleksandr Rybalko. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/mips/rt305x/rt305xreg.h 220297 2011-04-03 14:39:55Z adrian $ 27 */ 28 29#ifndef _RT305XREG_H_ 30#define _RT305XREG_H_ 31 32/* XXX: must move to config */ 33#define RT305X 1 34#define RT305XF 1 35#define RT3052F 1 36#define __U_BOOT__ 1 37/* XXX: must move to config */ 38 39#ifdef RT3052F 40#define PLATFORM_COUNTER_FREQ (384 * 1000 * 1000) 41#endif 42#ifdef RT3050F 43#define PLATFORM_COUNTER_FREQ (320 * 1000 * 1000) 44#endif 45#ifndef PLATFORM_COUNTER_FREQ 46#error "Nor RT3052F nor RT3050F defined" 47#endif 48 49#define SYSTEM_CLOCK (PLATFORM_COUNTER_FREQ/3) 50 51 52#define SDRAM_BASE 0x00000000 53#define SDRAM_END 0x03FFFFFF 54 55#define SYSCTL_BASE 0x10000000 56#define SYSCTL_END 0x100000FF 57#define TIMER_BASE 0x10000100 58#define TIMER_END 0x100001FF 59#define INTCTL_BASE 0x10000200 60#define INTCTL_END 0x100002FF 61#define MEMCTRL_BASE 0x10000300 62#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */ 63#define PCM_BASE 0x10000400 64#define PCM_END 0x100004FF 65#define UART_BASE 0x10000500 66#define UART_END 0x100005FF 67#define PIO_BASE 0x10000600 68#define PIO_END 0x100006FF 69#define GDMA_BASE 0x10000700 70#define GDMA_END 0x100007FF /* Generic DMA */ 71#define NANDFC_BASE 0x10000800 72#define NANDFC_END 0x100008FF /* NAND Flash Controller */ 73#define I2C_BASE 0x10000900 74#define I2C_END 0x100009FF 75#define I2S_BASE 0x10000A00 76#define I2S_END 0x10000AFF 77#define SPI_BASE 0x10000B00 78#define SPI_END 0x10000BFF 79#define UARTLITE_BASE 0x10000C00 80#define UARTLITE_END 0x10000CFF 81 82#define FRENG_BASE 0x10100000 83#define FRENG_END 0x1010FFFF /* Frame Engine */ 84#define ETHSW_BASE 0x10110000 85#define ETHSW_END 0x10117FFF /* Ethernet Switch */ 86#define ROM_BASE 0x10118000 87#define ROM_END 0x10119FFF 88#define WLAN_BASE 0x10180000 89#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */ 90#define USB_OTG_BASE 0x101C0000 91#define USB_OTG_END 0x101FFFFF 92#define EMEM_BASE 0x1B000000 93#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */ 94#define FLASH_BASE 0x1F000000 95#define FLASH_END 0x1FFFFFFF /* Flash window */ 96 97#define OBIO_MEM_BASE SYSCTL_BASE 98#define OBIO_MEM_START OBIO_MEM_BASE 99#define OBIO_MEM_END FLASH_END 100 101 102 103/* System Control */ 104#define SYSCTL_CHIPID0_3 0x00 /* 'R''T''3''0' */ 105#define SYSCTL_CHIPID4_7 0x04 /* '5''2'' '' ' */ 106#define SYSCTL_SYSCFG 0x10 107#define SYSCTL_SYSCFG_INIC_EE_SDRAM (1<<29) 108#define SYSCTL_SYSCFG_INIC_8MB_SDRAM (1<<28) 109#define SYSCTL_SYSCFG_GE0_MODE_MASK 0x03000000 110#define SYSCTL_SYSCFG_GE0_MODE_SHIFT 24 111#define SYSCTL_SYSCFG_GE0_MODE_RGMII 0 /* RGMII Mode */ 112#define SYSCTL_SYSCFG_GE0_MODE_MII 1 /* MII Mode */ 113#define SYSCTL_SYSCFG_GE0_MODE_REV_MII 2 /*Reversed MII Mode*/ 114#define SYSCTL_SYSCFG_BOOT_ADDR_1F00 (1<<22) 115#define SYSCTL_SYSCFG_BYPASS_PLL (1<<21) 116#define SYSCTL_SYSCFG_BIG_ENDIAN (1<<20) 117#define SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ (1<<18) 118#define SYSCTL_SYSCFG_BOOT_FROM_MASK 0x00030000 119#define SYSCTL_SYSCFG_BOOT_FROM_SHIFT 16 120#define SYSCTL_SYSCFG_BOOT_FROM_FLASH16 0 121#define SYSCTL_SYSCFG_BOOT_FROM_FLASH8 1 122#define SYSCTL_SYSCFG_BOOT_FROM_NANDFLASH 2 123#define SYSCTL_SYSCFG_BOOT_FROM_ROM 3 124#define SYSCTL_SYSCFG_TEST_CODE_MASK 0x0000ff00 125#define SYSCTL_SYSCFG_TEST_CODE_SHIFT 8 126#define SYSCTL_SYSCFG_SRAM_CS_MODE_MASK 0x0000000c 127#define SYSCTL_SYSCFG_SRAM_CS_MODE_SHIFT 2 128#define SYSCTL_SYSCFG_SRAM_CS_MODE_SRAM 0 129#define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST 1 130#define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX 2 131#define SYSCTL_SYSCFG_SDRAM_CLK_DRV (1<<0) /* 8mA/12mA */ 132 133#define SYSCTL_TESTSTAT 0x18 134#define SYSCTL_TESTSTAT2 0x1C 135 136#define SYSCTL_CLKCFG0 0x2C 137#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_MASK 0xc0000000 138#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_SHIFT 30 139#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_ZERO_DELAY 0 140#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_1NS_DELAY 1 141#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_2NS_DELAY 2 142#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY 3 143 144#define SYSCTL_CLKCFG1 0x30 145#define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2 (1<<30) 146#define SYSCTL_CLKCFG1_OTG_CLK_EN (1<<18) 147#define SYSCTL_CLKCFG1_I2S_CLK_EN (1<<15) 148#define SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT (1<<14) 149#define SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK 0x00003f00 150#define SYSCTL_CLKCFG1_I2S_CLK_DIV_SHIFT 8 151#define SYSCTL_CLKCFG1_PCM_CLK_EN (1<<7) 152#define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT (1<<6) 153#define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 0x0000003f 154#define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 0 155 156#define SYSCTL_RSTCTRL 0x34 157#define SYSCTL_RSTCTRL_ETHSW (1<<23) 158#define SYSCTL_RSTCTRL_OTG (1<<22) 159#define SYSCTL_RSTCTRL_FRENG (1<<21) 160#define SYSCTL_RSTCTRL_WLAN (1<<20) 161#define SYSCTL_RSTCTRL_UARTL (1<<19) 162#define SYSCTL_RSTCTRL_SPI (1<<18) 163#define SYSCTL_RSTCTRL_I2S (1<<17) 164#define SYSCTL_RSTCTRL_I2C (1<<16) 165#define SYSCTL_RSTCTRL_DMA (1<<14) 166#define SYSCTL_RSTCTRL_PIO (1<<13) 167#define SYSCTL_RSTCTRL_UART (1<<12) 168#define SYSCTL_RSTCTRL_PCM (1<<11) 169#define SYSCTL_RSTCTRL_MC (1<<10) 170#define SYSCTL_RSTCTRL_INTC (1<<9) 171#define SYSCTL_RSTCTRL_TIMER (1<<8) 172#define SYSCTL_RSTCTRL_SYS (1<<0) 173 174#define SYSCTL_RSTSTAT 0x38 175#define SYSCTL_RSTSTAT_SWCPURST (1<<3) 176#define SYSCTL_RSTSTAT_SWSYSRST (1<<2) 177#define SYSCTL_RSTSTAT_WDRST (1<<1) 178 179#define SYSCTL_GPIOMODE 0x60 180#define SYSCTL_GPIOMODE_RGMII_GPIO_MODE (1<<9) 181#define SYSCTL_GPIOMODE_SDRAM_GPIO_MODE (1<<8) 182#define SYSCTL_GPIOMODE_MDIO_GPIO_MODE (1<<7) 183#define SYSCTL_GPIOMODE_JTAG_GPIO_MODE (1<<6) 184#define SYSCTL_GPIOMODE_UARTL_GPIO_MODE (1<<5) 185#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_UARTF (0<<2) 186#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_UARTF (1<<2) 187#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_I2S (2<<2) 188#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_I2S_UARTF (3<<2) 189#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_GPIO (4<<2) 190#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_UARTF (5<<2) 191#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_I2S (6<<2) 192#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO (7<<2) 193#define SYSCTL_GPIOMODE_SPI_GPIO_MODE (1<<1) 194#define SYSCTL_GPIOMODE_I2C_GPIO_MODE (1<<0) 195 196#define SYSCTL_MEMO0 0x68 197#define SYSCTL_MEMO1 0x6C 198 199/* Timer */ 200#define TIMER_TMRSTAT 0x00 201#define TIMER_TMRSTAT_TMR1RST (1<<5) 202#define TIMER_TMRSTAT_TMR0RST (1<<4) 203#define TIMER_TMRSTAT_TMR1INT (1<<1) 204#define TIMER_TMRSTAT_TMR0INT (1<<0) 205#define TIMER_TMR0LOAD 0x10 206#define TIMER_TMR0VAL 0x14 207#define TIMER_TMR0CTL 0x18 208#define TIMER_TMR1LOAD 0x20 209#define TIMER_TMR1VAL 0x24 210#define TIMER_TMR1CTL 0x28 211 212#define TIMER_TMRLOAD_TMR0LOAD_MASK 0xffff 213 214#define TIMER_TMRVAL_TMR0VAL_MASK 0xffff 215 216#define TIMER_TMRCTL_ENABLE (1<<7) 217#define TIMER_TMRCTL_MODE_MASK 0x00000030 218#define TIMER_TMRCTL_MODE_SHIFT 4 219#define TIMER_TMRCTL_MODE_FREE 0 220#define TIMER_TMRCTL_MODE_PERIODIC 1 221#define TIMER_TMRCTL_MODE_TIMOUT 2 222#define TIMER_TMRCTL_MODE_TIMOUT3 3 223#define TIMER_TMRCTL_PRESCALE_MASK 0x0000000f 224#define TIMER_TMRCTL_PRESCALE_SHIFT 0 225#define TIMER_TMRCTL_PRESCALE_NONE 0 226#define TIMER_TMRCTL_PRESCALE_BY_4 1 227#define TIMER_TMRCTL_PRESCALE_BY_8 2 228#define TIMER_TMRCTL_PRESCALE_BY_16 3 229#define TIMER_TMRCTL_PRESCALE_BY_32 4 230#define TIMER_TMRCTL_PRESCALE_BY_64 5 231#define TIMER_TMRCTL_PRESCALE_BY_128 6 232#define TIMER_TMRCTL_PRESCALE_BY_256 7 233#define TIMER_TMRCTL_PRESCALE_BY_512 8 234#define TIMER_TMRCTL_PRESCALE_BY_1K 9 235#define TIMER_TMRCTL_PRESCALE_BY_2K 10 236#define TIMER_TMRCTL_PRESCALE_BY_4K 11 237#define TIMER_TMRCTL_PRESCALE_BY_8K 12 238#define TIMER_TMRCTL_PRESCALE_BY_16K 13 239#define TIMER_TMRCTL_PRESCALE_BY_32K 14 240#define TIMER_TMRCTL_PRESCALE_BY_64K 15 241 242/* Interrupt Controller */ 243#define IC_IRQ0STAT 0x00 244#define IC_IRQ1STAT 0x04 245#define IC_INTTYPE 0x20 246#define IC_INTRAW 0x30 247#define IC_INT_ENA 0x34 248#define IC_INT_DIS 0x38 249 250#define IC_OTG 18 251#define IC_ETHSW 17 252#define IC_UARTLITE 12 253#define IC_I2S 10 254#define IC_PERFC 9 255#define IC_NAND 8 256#define IC_DMA 7 257#define IC_PIO 6 258#define IC_UART 5 259#define IC_PCM 4 260#define IC_ILL_ACCESS 3 261#define IC_WDTIMER 2 262#define IC_TIMER0 1 263#define IC_SYSCTL 0 264 265#define IC_LINE_GLOBAL (1<<31) /* Only for DIS/ENA regs */ 266#define IC_LINE_OTG (1<<18) 267#define IC_LINE_ETHSW (1<<17) 268#define IC_LINE_UARTLITE (1<<12) 269#define IC_LINE_I2S (1<<10) 270#define IC_LINE_PERFC (1<<9) 271#define IC_LINE_NAND (1<<8) 272#define IC_LINE_DMA (1<<7) 273#define IC_LINE_PIO (1<<6) 274#define IC_LINE_UART (1<<5) 275#define IC_LINE_PCM (1<<4) 276#define IC_LINE_ILL_ACCESS (1<<3) 277#define IC_LINE_WDTIMER (1<<2) 278#define IC_LINE_TIMER0 (1<<1) 279#define IC_LINE_SYSCTL (1<<0) 280 281#define IC_INT_MASK 0x000617ff 282 283/* GPIO */ 284 285#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */ 286#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */ 287#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */ 288#define GPIO23_00_FENA 0x0C /* Programmed I/O Int on Falling */ 289#define GPIO23_00_DATA 0x20 /* Programmed I/O Data */ 290#define GPIO23_00_DIR 0x24 /* Programmed I/O Direction */ 291#define GPIO23_00_POL 0x28 /* Programmed I/O Pin Polarity */ 292#define GPIO23_00_SET 0x2C /* Set PIO Data Bit */ 293#define GPIO23_00_RESET 0x30 /* Clear PIO Data bit */ 294#define GPIO23_00_TOG 0x34 /* Toggle PIO Data bit */ 295 296#define GPIO39_24_INT 0x38 297#define GPIO39_24_EDGE 0x3c 298#define GPIO39_24_RENA 0x40 299#define GPIO39_24_FENA 0x44 300#define GPIO39_24_DATA 0x48 301#define GPIO39_24_DIR 0x4c 302#define GPIO39_24_POL 0x50 303#define GPIO39_24_SET 0x54 304#define GPIO39_24_RESET 0x58 305#define GPIO39_24_TOG 0x5c 306 307#define GPIO51_40_INT 0x60 308#define GPIO51_40_EDGE 0x64 309#define GPIO51_40_RENA 0x68 310#define GPIO51_40_FENA 0x6C 311#define GPIO51_40_DATA 0x70 312#define GPIO51_40_DIR 0x74 313#define GPIO51_40_POL 0x78 314#define GPIO51_40_SET 0x7C 315#define GPIO51_40_RESET 0x80 316#define GPIO51_40_TOG 0x84 317 318 319 320 321#define GDMA_CHANNEL_REQ0 0 322#define GDMA_CHANNEL_REQ1 1 /* (NAND-flash) */ 323#define GDMA_CHANNEL_REQ2 2 /* (I2S) */ 324#define GDMA_CHANNEL_REQ3 3 /* (PCM0-RX) */ 325#define GDMA_CHANNEL_REQ4 4 /* (PCM1-RX) */ 326#define GDMA_CHANNEL_REQ5 5 /* (PCM0-TX) */ 327#define GDMA_CHANNEL_REQ6 6 /* (PCM1-TX) */ 328#define GDMA_CHANNEL_REQ7 7 329#define GDMA_CHANNEL_MEM 8 330 331/* Generic DMA Controller */ 332/* GDMA Channel n Source Address */ 333#define GDMASA(n) (0x00 + 0x10*n) 334 /* GDMA Channel n Destination Address */ 335#define GDMADA(n) (0x04 + 0x10*n) 336 /* GDMA Channel n Control Register 0 */ 337#define GDMACT0(n) (0x08 + 0x10*n) 338 339#define GDMACT0_TR_COUNT_MASK 0x0fff0000 340#define GDMACT0_TR_COUNT_SHIFT 16 341#define GDMACT0_SRC_CHAN_SHIFT 12 342#define GDMACT0_SRC_CHAN_MASK 0x0000f000 343#define GDMACT0_DST_CHAN_SHIFT 8 344#define GDMACT0_DST_CHAN_MASK 0x00000f00 345#define GDMACT0_SRC_BURST_MODE (1<<7) 346#define GDMACT0_DST_BURST_MODE (1<<6) 347#define GDMACT0_BURST_SIZE_SHIFT 3 348#define GDMACT0_BURST_SIZE_MASK 0x00000038 349#define GDMACT0_BURST_SIZE_1 0 350#define GDMACT0_BURST_SIZE_2 1 351#define GDMACT0_BURST_SIZE_4 2 352#define GDMACT0_BURST_SIZE_8 3 353#define GDMACT0_BURST_SIZE_16 4 354 355#define GDMACT0_DONE_INT_EN (1<<2) 356#define GDMACT0_CHAN_EN (1<<1) 357/* 358 * In software mode, the data transfer will start when the Channel Enable bit 359 * is set. 360 * In hardware mode, the data transfer will start when the DMA Request is 361 * asserted. 362*/ 363#define GDMACT0_SWMODE (1<<0) 364 365 366 367 368#endif /* _RT305XREG_H_ */ 369