1198160Srrs/*- 2198160Srrs * Copyright (c) 2003-2009 RMI Corporation 3198160Srrs * All rights reserved. 4198160Srrs * 5198160Srrs * Redistribution and use in source and binary forms, with or without 6198160Srrs * modification, are permitted provided that the following conditions 7198160Srrs * are met: 8198160Srrs * 1. Redistributions of source code must retain the above copyright 9198160Srrs * notice, this list of conditions and the following disclaimer. 10198160Srrs * 2. Redistributions in binary form must reproduce the above copyright 11198160Srrs * notice, this list of conditions and the following disclaimer in the 12198160Srrs * documentation and/or other materials provided with the distribution. 13198160Srrs * 3. Neither the name of RMI Corporation, nor the names of its contributors, 14198160Srrs * may be used to endorse or promote products derived from this software 15198160Srrs * without specific prior written permission. 16198160Srrs * 17198160Srrs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18198160Srrs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19198160Srrs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20198160Srrs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21198160Srrs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22198160Srrs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23198160Srrs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24198160Srrs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25198160Srrs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26198160Srrs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27198160Srrs * SUCH DAMAGE. 28198160Srrs * 29209318Sjchandra * RMI_BSD 30209318Sjchandra * $FreeBSD$ 31209318Sjchandra */ 32198160Srrs#ifndef _RMI_BOARD_H_ 33213199Sjchandra#define _RMI_BOARD_H_ 34198160Srrs 35209318Sjchandra/* 36209318Sjchandra * Engineering boards have a major/minor number in their EEPROM to 37209318Sjchandra * identify their configuration 38209318Sjchandra */ 39213199Sjchandra#define RMI_XLR_BOARD_ARIZONA_I 1 40213199Sjchandra#define RMI_XLR_BOARD_ARIZONA_II 2 41213199Sjchandra#define RMI_XLR_BOARD_ARIZONA_III 3 42213199Sjchandra#define RMI_XLR_BOARD_ARIZONA_IV 4 43213199Sjchandra#define RMI_XLR_BOARD_ARIZONA_V 5 44213199Sjchandra#define RMI_XLR_BOARD_ARIZONA_VI 6 45213199Sjchandra#define RMI_XLR_BOARD_ARIZONA_VII 7 46213199Sjchandra#define RMI_XLR_BOARD_ARIZONA_VIII 8 47213199Sjchandra#define RMI_XLR_BOARD_ARIZONA_XI 11 48213199Sjchandra#define RMI_XLR_BOARD_ARIZONA_XII 12 49198160Srrs 50209318Sjchandra/* 51209318Sjchandra * RMI Chips - Values in Processor ID field 52209318Sjchandra */ 53209318Sjchandra#define RMI_CHIP_XLR732 0x00 54209318Sjchandra#define RMI_CHIP_XLR716 0x02 55209318Sjchandra#define RMI_CHIP_XLR308 0x06 56209318Sjchandra#define RMI_CHIP_XLR532 0x09 57198160Srrs 58213199Sjchandra/* 59213199Sjchandra * XLR C revisions 60213199Sjchandra */ 61213199Sjchandra#define RMI_CHIP_XLR308_C 0x0F 62213199Sjchandra#define RMI_CHIP_XLR508_C 0x0b 63213199Sjchandra#define RMI_CHIP_XLR516_C 0x0a 64213199Sjchandra#define RMI_CHIP_XLR532_C 0x08 65198160Srrs 66213199Sjchandra/* 67213199Sjchandra * XLS processors 68213199Sjchandra */ 69213199Sjchandra#define RMI_CHIP_XLS408 0x88 /* Lite "Condor" */ 70213199Sjchandra#define RMI_CHIP_XLS608 0x80 /* Internal */ 71213199Sjchandra#define RMI_CHIP_XLS404 0x8c /* Lite "Condor" */ 72213199Sjchandra#define RMI_CHIP_XLS208 0x8e 73213199Sjchandra#define RMI_CHIP_XLS204 0x8f 74213199Sjchandra#define RMI_CHIP_XLS108 0xce 75213199Sjchandra#define RMI_CHIP_XLS104 0xcf 76213199Sjchandra 77213199Sjchandra/* 78213199Sjchandra * XLS B revision chips 79213199Sjchandra */ 80213199Sjchandra#define RMI_CHIP_XLS616_B0 0x40 81213199Sjchandra#define RMI_CHIP_XLS608_B0 0x4a 82213199Sjchandra#define RMI_CHIP_XLS416_B0 0x44 83213199Sjchandra#define RMI_CHIP_XLS412_B0 0x4c 84213199Sjchandra#define RMI_CHIP_XLS408_B0 0x4e 85213199Sjchandra#define RMI_CHIP_XLS404_B0 0x4f 86213199Sjchandra 87209318Sjchandra/* 88209318Sjchandra * The XLS product line has chip versions 0x4x and 0x8x 89209318Sjchandra */ 90213199Sjchandrastatic __inline unsigned int 91198160Srrsxlr_is_xls(void) 92198160Srrs{ 93198160Srrs uint32_t prid = mips_rd_prid(); 94198160Srrs 95209646Sjchandra return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 || 96209646Sjchandra (prid & 0xf000) == 0xc000); 97198160Srrs} 98198160Srrs 99209318Sjchandra/* 100209318Sjchandra * The last byte of the processor id field is revision 101209318Sjchandra */ 102213199Sjchandrastatic __inline unsigned int 103209318Sjchandraxlr_revision(void) 104198160Srrs{ 105213199Sjchandra 106213199Sjchandra return (mips_rd_prid() & 0xff); 107198160Srrs} 108198160Srrs 109209318Sjchandra/* 110209318Sjchandra * The 15:8 byte of the PR Id register is the Processor ID 111209318Sjchandra */ 112213199Sjchandrastatic __inline unsigned int 113209318Sjchandraxlr_processor_id(void) 114198160Srrs{ 115213199Sjchandra 116209318Sjchandra return ((mips_rd_prid() & 0xff00) >> 8); 117198160Srrs} 118198160Srrs 119209318Sjchandra/* 120213484Sjchandra * The processor is XLR and C-Series 121213484Sjchandra */ 122213484Sjchandrastatic __inline unsigned int 123213484Sjchandraxlr_is_c_revision(void) 124213484Sjchandra{ 125213484Sjchandra int processor_id = xlr_processor_id(); 126213484Sjchandra int revision_id = xlr_revision(); 127213484Sjchandra 128213484Sjchandra switch (processor_id) { 129213484Sjchandra /* 130213484Sjchandra * These are the relevant PIDs for XLR 131213484Sjchandra * steppings (hawk and above). For these, 132213484Sjchandra * PIDs, Rev-Ids of [5-9] indicate 'C'. 133213484Sjchandra */ 134213484Sjchandra case RMI_CHIP_XLR308_C: 135213484Sjchandra case RMI_CHIP_XLR508_C: 136213484Sjchandra case RMI_CHIP_XLR516_C: 137213484Sjchandra case RMI_CHIP_XLR532_C: 138213484Sjchandra case RMI_CHIP_XLR716: 139213484Sjchandra case RMI_CHIP_XLR732: 140213484Sjchandra if (revision_id >= 5 && revision_id <= 9) 141213484Sjchandra return (1); 142213484Sjchandra default: 143213484Sjchandra return (0); 144213484Sjchandra } 145213484Sjchandra return (0); 146213484Sjchandra} 147213484Sjchandra 148213484Sjchandra/* 149209318Sjchandra * RMI Engineering boards which are PCI cards 150209318Sjchandra * These should come up in PCI device mode (not yet) 151209318Sjchandra */ 152213199Sjchandrastatic __inline int 153211994Sjchandraxlr_board_pci(int board_major) 154198160Srrs{ 155213199Sjchandra 156211994Sjchandra return ((board_major == RMI_XLR_BOARD_ARIZONA_III) || 157211994Sjchandra (board_major == RMI_XLR_BOARD_ARIZONA_V)); 158198160Srrs} 159198160Srrs 160213199Sjchandrastatic __inline int 161209646Sjchandraxlr_is_xls1xx(void) 162209646Sjchandra{ 163209646Sjchandra uint32_t chipid = xlr_processor_id(); 164209646Sjchandra 165209646Sjchandra return (chipid == 0xce || chipid == 0xcf); 166209646Sjchandra} 167209646Sjchandra 168213199Sjchandrastatic __inline int 169198160Srrsxlr_is_xls2xx(void) 170198160Srrs{ 171209318Sjchandra uint32_t chipid = xlr_processor_id(); 172198160Srrs 173209318Sjchandra return (chipid == 0x8e || chipid == 0x8f); 174198160Srrs} 175198160Srrs 176213199Sjchandrastatic __inline int 177209318Sjchandraxlr_is_xls4xx_lite(void) 178198160Srrs{ 179209318Sjchandra uint32_t chipid = xlr_processor_id(); 180198160Srrs 181209318Sjchandra return (chipid == 0x88 || chipid == 0x8c); 182213199Sjchandra} 183213199Sjchandra 184213199Sjchandrastatic __inline unsigned int 185213199Sjchandraxlr_is_xls_b0(void) 186213199Sjchandra{ 187213199Sjchandra uint32_t chipid = xlr_processor_id(); 188213199Sjchandra 189213199Sjchandra return (chipid >= 0x40 && chipid <= 0x4f); 190213199Sjchandra} 191213199Sjchandra 192211946Sjchandra/* SPI-4 --> 8 ports, 1G MAC --> 4 ports and 10G MAC --> 1 port */ 193213199Sjchandra#define MAX_NA_PORTS 8 194198160Srrs 195198160Srrs/* all our knowledge of chip and board that cannot be detected run-time goes here */ 196211946Sjchandraenum gmac_block_types { XLR_GMAC, XLR_XGMAC, XLR_SPI4}; 197211946Sjchandraenum gmac_port_types { XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII, XLR_XGMII, XLR_XAUI }; 198216390Sjchandraenum i2c_dev_types { I2C_RTC, I2C_THERMAL, I2C_EEPROM }; 199209318Sjchandra 200198160Srrsstruct xlr_board_info { 201198160Srrs int is_xls; 202198160Srrs int nr_cpus; 203211946Sjchandra int usb; /* usb enabled ? */ 204211946Sjchandra int cfi; /* compact flash driver for NOR? */ 205211946Sjchandra int ata; /* ata driver */ 206198160Srrs int pci_irq; 207211946Sjchandra struct stn_cc **credit_configs; /* pointer to Core station credits */ 208211946Sjchandra struct bucket_size *bucket_sizes; /* pointer to Core station bucket */ 209211946Sjchandra int *msgmap; /* mapping of message station to devices */ 210211946Sjchandra int gmacports; /* number of gmac ports on the board */ 211216390Sjchandra struct xlr_i2c_dev_t { 212216390Sjchandra uint32_t addr; 213216390Sjchandra unsigned int enabled; /* mask of devs enabled */ 214216390Sjchandra int type; 215216390Sjchandra int unit; 216216390Sjchandra char *dev_name; 217216390Sjchandra } xlr_i2c_device[3]; 218211946Sjchandra struct xlr_gmac_block_t { /* refers to the set of GMACs controlled by a 219211946Sjchandra network accelarator */ 220211946Sjchandra int type; /* see enum gmac_block_types */ 221211946Sjchandra unsigned int enabled; /* mask of ports enabled */ 222211946Sjchandra struct stn_cc *credit_config; /* credit configuration */ 223211946Sjchandra int station_id; /* station id for sending msgs */ 224211946Sjchandra int station_txbase; /* station id for tx */ 225211946Sjchandra int station_rfr; /* free desc bucket */ 226211946Sjchandra int mode; /* see gmac_block_modes */ 227211946Sjchandra uint32_t baseaddr; /* IO base */ 228211946Sjchandra int baseirq; /* first irq for this block, the rest are in sequence */ 229211946Sjchandra int baseinst; /* the first rge unit for this block */ 230211946Sjchandra int num_ports; 231211946Sjchandra struct xlr_gmac_port { 232211946Sjchandra int valid; 233211946Sjchandra int type; /* see enum gmac_port_types */ 234211946Sjchandra uint32_t instance; /* identifies the GMAC to which 235211946Sjchandra this port is bound to. */ 236211946Sjchandra uint32_t phy_addr; 237211946Sjchandra uint32_t base_addr; 238211946Sjchandra uint32_t mii_addr; 239211946Sjchandra uint32_t pcs_addr; 240211946Sjchandra uint32_t serdes_addr; 241211946Sjchandra uint32_t tx_bucket_id; 242211946Sjchandra uint32_t mdint_id; 243211946Sjchandra } gmac_port[MAX_NA_PORTS]; 244211946Sjchandra } gmac_block [3]; 245198160Srrs}; 246198160Srrs 247198160Srrsextern struct xlr_board_info xlr_board_info; 248198160Srrsint xlr_board_info_setup(void); 249198160Srrs 250198160Srrs#endif 251