1224110Sjchandra/*- 2224110Sjchandra * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3224110Sjchandra * reserved. 4224110Sjchandra * 5224110Sjchandra * Redistribution and use in source and binary forms, with or without 6224110Sjchandra * modification, are permitted provided that the following conditions are 7224110Sjchandra * met: 8224110Sjchandra * 9224110Sjchandra * 1. Redistributions of source code must retain the above copyright 10224110Sjchandra * notice, this list of conditions and the following disclaimer. 11224110Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 12224110Sjchandra * notice, this list of conditions and the following disclaimer in 13224110Sjchandra * the documentation and/or other materials provided with the 14224110Sjchandra * distribution. 15224110Sjchandra * 16224110Sjchandra * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17224110Sjchandra * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18224110Sjchandra * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19224110Sjchandra * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20224110Sjchandra * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21224110Sjchandra * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22224110Sjchandra * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23224110Sjchandra * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24224110Sjchandra * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25224110Sjchandra * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26224110Sjchandra * THE POSSIBILITY OF SUCH DAMAGE. 27224110Sjchandra * 28225394Sjchandra * NETLOGIC_BSD 29224110Sjchandra * $FreeBSD$ 30225394Sjchandra */ 31224110Sjchandra 32224110Sjchandra#ifndef __NLM_FMNV2_H__ 33227783Sjchandra#define __NLM_FMNV2_H__ 34224110Sjchandra 35224110Sjchandra/** 36224110Sjchandra* @file_name fmn.h 37224110Sjchandra* @author Netlogic Microsystems 38224110Sjchandra* @brief HAL for Fast message network V2 39224110Sjchandra*/ 40224110Sjchandra 41224110Sjchandra/* FMN configuration registers */ 42227783Sjchandra#define CMS_OUTPUTQ_CONFIG(i) ((i)*2) 43227783Sjchandra#define CMS_MAX_OUTPUTQ 1024 44227783Sjchandra#define CMS_OUTPUTQ_CREDIT_CFG (0x2000/4) 45227783Sjchandra#define CMS_MSG_CONFIG (0x2008/4) 46227783Sjchandra#define CMS_MSG_ERR (0x2010/4) 47227783Sjchandra#define CMS_TRACE_CONFIG (0x2018/4) 48227783Sjchandra#define CMS_TRACE_BASE_ADDR (0x2020/4) 49227783Sjchandra#define CMS_TRACE_LIMIT_ADDR (0x2028/4) 50227783Sjchandra#define CMS_TRACE_CURRENT_ADDR (0x2030/4) 51227783Sjchandra#define CMS_MSG_ENDIAN_SWAP (0x2038/4) 52224110Sjchandra 53227783Sjchandra#define CMS_CPU_PUSHQ(node, core, thread, vc) \ 54224110Sjchandra (((node)<<10) | ((core)<<4) | ((thread)<<2) | ((vc)<<0)) 55227783Sjchandra#define CMS_POPQ(node, queue) (((node)<<10) | (queue)) 56227783Sjchandra#define CMS_IO_PUSHQ(node, queue) (((node)<<10) | (queue)) 57224110Sjchandra 58227783Sjchandra#define CMS_POPQ_QID(i) (128+(i)) 59224110Sjchandra 60224110Sjchandra/* FMN Level Interrupt Type */ 61227783Sjchandra#define CMS_LVL_INTR_DISABLE 0 62227783Sjchandra#define CMS_LVL_LOW_WATERMARK 1 63227783Sjchandra#define CMS_LVL_HI_WATERMARK 2 64224110Sjchandra 65224110Sjchandra/* FMN Level interrupt trigger values */ 66227783Sjchandra#define CMS_QUEUE_NON_EMPTY 0 67227783Sjchandra#define CMS_QUEUE_QUARTER_FULL 1 68227783Sjchandra#define CMS_QUEUE_HALF_FULL 2 69227783Sjchandra#define CMS_QUEUE_THREE_QUARTER_FULL 3 70227783Sjchandra#define CMS_QUEUE_FULL 4 71224110Sjchandra 72224110Sjchandra/* FMN Timer Interrupt Type */ 73227783Sjchandra#define CMS_TIMER_INTR_DISABLE 0 74227783Sjchandra#define CMS_TIMER_CONSUMER 1 75227783Sjchandra#define CMS_TIMER_PRODUCER 1 76224110Sjchandra 77224110Sjchandra/* FMN timer interrupt trigger values */ 78227783Sjchandra#define CMS_TWO_POW_EIGHT_CYCLES 0 79227783Sjchandra#define CMS_TWO_POW_TEN_CYCLES 1 80227783Sjchandra#define CMS_TWO_POW_TWELVE_CYCLES 2 81227783Sjchandra#define CMS_TWO_POW_FOURTEEN_CYCLES 3 82227783Sjchandra#define CMS_TWO_POW_SIXTEEN_CYCLES 4 83227783Sjchandra#define CMS_TWO_POW_EIGHTTEEN_CYCLES 5 84227783Sjchandra#define CMS_TWO_POW_TWENTY_CYCLES 6 85227783Sjchandra#define CMS_TWO_POW_TWENTYTWO_CYCLES 7 86224110Sjchandra 87227783Sjchandra#define CMS_QUEUE_ENA 1ULL 88227783Sjchandra#define CMS_QUEUE_DIS 0 89227783Sjchandra#define CMS_SPILL_ENA 1ULL 90227783Sjchandra#define CMS_SPILL_DIS 0 91224110Sjchandra 92227783Sjchandra#define CMS_MAX_VCPU_VC 4 93224110Sjchandra 94224110Sjchandra/* Each XLP chip can hold upto 32K messages on the chip itself */ 95227783Sjchandra#define CMS_ON_CHIP_MESG_SPACE (32*1024) 96227783Sjchandra#define CMS_MAX_ONCHIP_SEGMENTS 1024 97227783Sjchandra#define CMS_MAX_SPILL_SEGMENTS_PER_QUEUE 64 98224110Sjchandra 99224110Sjchandra/* FMN Network error */ 100227783Sjchandra#define CMS_ILLEGAL_DST_ERROR 0x100 101227783Sjchandra#define CMS_BIU_TIMEOUT_ERROR 0x080 102227783Sjchandra#define CMS_BIU_ERROR 0x040 103227783Sjchandra#define CMS_SPILL_FILL_UNCORRECT_ECC_ERROR 0x020 104227783Sjchandra#define CMS_SPILL_FILL_CORRECT_ECC_ERROR 0x010 105227783Sjchandra#define CMS_SPILL_UNCORRECT_ECC_ERROR 0x008 106227783Sjchandra#define CMS_SPILL_CORRECT_ECC_ERROR 0x004 107227783Sjchandra#define CMS_OUTPUTQ_UNCORRECT_ECC_ERROR 0x002 108227783Sjchandra#define CMS_OUTPUTQ_CORRECT_ECC_ERROR 0x001 109224110Sjchandra 110224110Sjchandra/* worst case, a single entry message consists of a 4 byte header 111224110Sjchandra * and an 8-byte entry = 12 bytes in total 112224110Sjchandra */ 113227783Sjchandra#define CMS_SINGLE_ENTRY_MSG_SIZE 12 114224110Sjchandra/* total spill memory needed for one FMN queue */ 115227783Sjchandra#define CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs) \ 116225394Sjchandra ((spilltotmsgs) * (CMS_SINGLE_ENTRY_MSG_SIZE)) 117224110Sjchandra 118224110Sjchandra/* FMN Src station id's */ 119227783Sjchandra#define CMS_CPU0_SRC_STID (0 << 4) 120227783Sjchandra#define CMS_CPU1_SRC_STID (1 << 4) 121227783Sjchandra#define CMS_CPU2_SRC_STID (2 << 4) 122227783Sjchandra#define CMS_CPU3_SRC_STID (3 << 4) 123227783Sjchandra#define CMS_CPU4_SRC_STID (4 << 4) 124227783Sjchandra#define CMS_CPU5_SRC_STID (5 << 4) 125227783Sjchandra#define CMS_CPU6_SRC_STID (6 << 4) 126227783Sjchandra#define CMS_CPU7_SRC_STID (7 << 4) 127227783Sjchandra#define CMS_PCIE0_SRC_STID 256 128227783Sjchandra#define CMS_PCIE1_SRC_STID 258 129227783Sjchandra#define CMS_PCIE2_SRC_STID 260 130227783Sjchandra#define CMS_PCIE3_SRC_STID 262 131227783Sjchandra#define CMS_DTE_SRC_STID 264 132227783Sjchandra#define CMS_RSA_ECC_SRC_STID 272 133227783Sjchandra#define CMS_CRYPTO_SRC_STID 281 134227783Sjchandra#define CMS_CMP_SRC_STID 298 135227783Sjchandra#define CMS_POE_SRC_STID 384 136227783Sjchandra#define CMS_NAE_SRC_STID 476 137224110Sjchandra 138224110Sjchandra/* POPQ related defines */ 139227783Sjchandra#define CMS_POPQID_START 128 140227783Sjchandra#define CMS_POPQID_END 255 141224110Sjchandra 142227783Sjchandra#define CMS_INT_RCVD 0x800000000000000ULL 143224110Sjchandra 144225394Sjchandra#define nlm_read_cms_reg(b, r) nlm_read_reg64_xkphys(b,r) 145225394Sjchandra#define nlm_write_cms_reg(b, r, v) nlm_write_reg64_xkphys(b,r,v) 146227783Sjchandra#define nlm_get_cms_pcibase(node) \ 147227783Sjchandra nlm_pcicfg_base(XLP_IO_CMS_OFFSET(node)) 148227783Sjchandra#define nlm_get_cms_regbase(node) \ 149227783Sjchandra nlm_xkphys_map_pcibar0(nlm_get_cms_pcibase(node)) 150224110Sjchandra 151227783Sjchandra#define XLP_CMS_ON_CHIP_PER_QUEUE_SPACE(node) \ 152227783Sjchandra ((XLP_CMS_ON_CHIP_MESG_SPACE)/ \ 153227783Sjchandra (nlm_read_reg(nlm_pcibase_cms(node), \ 154227783Sjchandra XLP_PCI_DEVINFO_REG0)) 155227783Sjchandra/* total spill memory needed */ 156227783Sjchandra#define XLP_CMS_TOTAL_SPILL_MEM(node, spilltotmsgs) \ 157227783Sjchandra ((XLP_CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs)) * \ 158227783Sjchandra (nlm_read_reg(nlm_pcibase_cms(node), \ 159227783Sjchandra XLP_PCI_DEVINFO_REG0)) 160227783Sjchandra#define CMS_TOTAL_QUEUE_SIZE(node, spilltotmsgs) \ 161227783Sjchandra ((spilltotmsgs) + (CMS_ON_CHIP_PER_QUEUE_SPACE(node))) 162227783Sjchandra 163224110Sjchandraenum fmn_swcode { 164224110Sjchandra FMN_SWCODE_CPU0=1, 165224110Sjchandra FMN_SWCODE_CPU1, 166224110Sjchandra FMN_SWCODE_CPU2, 167224110Sjchandra FMN_SWCODE_CPU3, 168224110Sjchandra FMN_SWCODE_CPU4, 169224110Sjchandra FMN_SWCODE_CPU5, 170224110Sjchandra FMN_SWCODE_CPU6, 171224110Sjchandra FMN_SWCODE_CPU7, 172224110Sjchandra FMN_SWCODE_CPU8, 173224110Sjchandra FMN_SWCODE_CPU9, 174224110Sjchandra FMN_SWCODE_CPU10, 175224110Sjchandra FMN_SWCODE_CPU11, 176224110Sjchandra FMN_SWCODE_CPU12, 177224110Sjchandra FMN_SWCODE_CPU13, 178224110Sjchandra FMN_SWCODE_CPU14, 179224110Sjchandra FMN_SWCODE_CPU15, 180224110Sjchandra FMN_SWCODE_CPU16, 181224110Sjchandra FMN_SWCODE_CPU17, 182224110Sjchandra FMN_SWCODE_CPU18, 183224110Sjchandra FMN_SWCODE_CPU19, 184224110Sjchandra FMN_SWCODE_CPU20, 185224110Sjchandra FMN_SWCODE_CPU21, 186224110Sjchandra FMN_SWCODE_CPU22, 187224110Sjchandra FMN_SWCODE_CPU23, 188224110Sjchandra FMN_SWCODE_CPU24, 189224110Sjchandra FMN_SWCODE_CPU25, 190224110Sjchandra FMN_SWCODE_CPU26, 191224110Sjchandra FMN_SWCODE_CPU27, 192224110Sjchandra FMN_SWCODE_CPU28, 193224110Sjchandra FMN_SWCODE_CPU29, 194224110Sjchandra FMN_SWCODE_CPU30, 195224110Sjchandra FMN_SWCODE_CPU31, 196224110Sjchandra FMN_SWCODE_CPU32, 197224110Sjchandra FMN_SWCODE_PCIE0, 198224110Sjchandra FMN_SWCODE_PCIE1, 199224110Sjchandra FMN_SWCODE_PCIE2, 200224110Sjchandra FMN_SWCODE_PCIE3, 201224110Sjchandra FMN_SWCODE_DTE, 202224110Sjchandra FMN_SWCODE_CRYPTO, 203224110Sjchandra FMN_SWCODE_RSA, 204224110Sjchandra FMN_SWCODE_CMP, 205224110Sjchandra FMN_SWCODE_POE, 206224110Sjchandra FMN_SWCODE_NAE, 207224110Sjchandra}; 208224110Sjchandra 209224110Sjchandraextern uint64_t nlm_cms_spill_total_messages; 210224110Sjchandraextern uint32_t nlm_cms_total_stations; 211224110Sjchandra 212224110Sjchandraextern uint64_t cms_base_addr(int node); 213224110Sjchandraextern int nlm_cms_verify_credit_config (int spill_en, int tot_credit); 214224110Sjchandraextern int nlm_cms_get_oc_space(int qsize, int max_queues, int qid, int *ocbase, int *ocstart, int *ocend); 215224110Sjchandraextern void nlm_cms_setup_credits (uint64_t base, int destid, int srcid, int credit); 216224110Sjchandraextern int nlm_cms_config_onchip_queue (uint64_t base, uint64_t cms_spill_base, int qid, int spill_en); 217224110Sjchandraextern void nlm_cms_default_setup(int node, uint64_t spill_base, int spill_en, int popq_en); 218224110Sjchandraextern uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid); 219224110Sjchandraextern void nlm_cms_set_onchip_queue (uint64_t base, int qid, uint64_t val); 220224110Sjchandraextern void nlm_cms_per_queue_level_intr(uint64_t base, int qid, int sub_type, int intr_val); 221224110Sjchandraextern void nlm_cms_level_intr(int node, int sub_type, int intr_val); 222224110Sjchandraextern void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type, int intr_val); 223224110Sjchandraextern void nlm_cms_timer_intr(int node, int en, int sub_type, int intr_val); 224224110Sjchandraextern int nlm_cms_outputq_intr_check(uint64_t base, int qid); 225224110Sjchandraextern void nlm_cms_outputq_clr_intr(uint64_t base, int qid); 226224110Sjchandraextern void nlm_cms_illegal_dst_error_intr(uint64_t base, int en); 227224110Sjchandraextern void nlm_cms_timeout_error_intr(uint64_t base, int en); 228224110Sjchandraextern void nlm_cms_biu_error_resp_intr(uint64_t base, int en); 229224110Sjchandraextern void nlm_cms_spill_uncorrectable_ecc_error_intr(uint64_t base, int en); 230224110Sjchandraextern void nlm_cms_spill_correctable_ecc_error_intr(uint64_t base, int en); 231224110Sjchandraextern void nlm_cms_outputq_uncorrectable_ecc_error_intr(uint64_t base, int en); 232224110Sjchandraextern void nlm_cms_outputq_correctable_ecc_error_intr(uint64_t base, int en); 233224110Sjchandraextern uint64_t nlm_cms_network_error_status(uint64_t base); 234224110Sjchandraextern int nlm_cms_get_net_error_code(uint64_t err); 235224110Sjchandraextern int nlm_cms_get_net_error_syndrome(uint64_t err); 236224110Sjchandraextern int nlm_cms_get_net_error_ramindex(uint64_t err); 237224110Sjchandraextern int nlm_cms_get_net_error_outputq(uint64_t err); 238224110Sjchandraextern void nlm_cms_trace_setup(uint64_t base, int en, uint64_t trace_base, uint64_t trace_limit, int match_dstid_en, int dst_id, int match_srcid_en, int src_id, int wrap); 239224110Sjchandraextern void nlm_cms_endian_byte_swap (uint64_t base, int en); 240224110Sjchandraextern uint8_t xlp_msg_send(uint8_t vc, uint8_t size); 241224110Sjchandraextern int nlm_cms_alloc_spill_q(uint64_t base, int qid, uint64_t spill_base, 242224110Sjchandra int nsegs); 243224110Sjchandraextern int nlm_cms_alloc_onchip_q(uint64_t base, int qid, int nsegs); 244224110Sjchandra 245224110Sjchandra#endif 246