ar71xx_cpudef.h revision 228018
1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* $FreeBSD: head/sys/mips/atheros/ar71xx_cpudef.h 228018 2011-11-27 11:15:59Z ray $ */ 28 29#ifndef __AR71XX_CPUDEF_H__ 30#define __AR71XX_CPUDEF_H__ 31 32struct ar71xx_cpu_def { 33 void (* detect_mem_size) (void); 34 void (* detect_sys_frequency) (void); 35 void (* ar71xx_chip_device_stop) (uint32_t); 36 void (* ar71xx_chip_device_start) (uint32_t); 37 int (* ar71xx_chip_device_stopped) (uint32_t); 38 void (* ar71xx_chip_set_pll_ge) (int, int); 39 void (* ar71xx_chip_ddr_flush_ge) (int); 40 uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int); 41 42 /* 43 * From Linux - Handling this IRQ is a bit special. 44 * AR71xx - AR71XX_DDR_REG_FLUSH_PCI 45 * AR724x - AR724X_DDR_REG_FLUSH_PCIE 46 * AR91xx - AR91XX_DDR_REG_FLUSH_WMAC 47 * 48 * These are set when STATUSF_IP2 is set in regiser c0. 49 * This flush is done before the IRQ is handled to make 50 * sure the driver correctly sees any memory updates. 51 */ 52 void (* ar71xx_chip_ddr_flush_ip2) (void); 53 /* 54 * The USB peripheral init code is subtly different for 55 * each chip. 56 */ 57 void (* ar71xx_chip_init_usb_peripheral) (void); 58}; 59 60extern struct ar71xx_cpu_def * ar71xx_cpu_ops; 61 62static inline void ar71xx_detect_sys_frequency(void) 63{ 64 ar71xx_cpu_ops->detect_sys_frequency(); 65} 66 67static inline void ar71xx_device_stop(uint32_t mask) 68{ 69 ar71xx_cpu_ops->ar71xx_chip_device_stop(mask); 70} 71 72static inline void ar71xx_device_start(uint32_t mask) 73{ 74 ar71xx_cpu_ops->ar71xx_chip_device_start(mask); 75} 76 77static inline int ar71xx_device_stopped(uint32_t mask) 78{ 79 return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask); 80} 81 82static inline void ar71xx_device_set_pll_ge(int unit, int speed) 83{ 84 ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed); 85} 86 87static inline void ar71xx_device_flush_ddr_ge(int unit) 88{ 89 ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge(unit); 90} 91 92static inline void ar71xx_init_usb_peripheral(void) 93{ 94 ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral(); 95} 96 97static inline void ar71xx_device_ddr_flush_ip2(void) 98{ 99 ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2(); 100} 101 102/* XXX shouldn't be here! */ 103extern uint32_t u_ar71xx_cpu_freq; 104extern uint32_t u_ar71xx_ahb_freq; 105extern uint32_t u_ar71xx_ddr_freq; 106 107static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; } 108static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; } 109static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; } 110 111#endif 112