ar71xx_cpudef.h revision 211509
1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* $FreeBSD: head/sys/mips/atheros/ar71xx_cpudef.h 211509 2010-08-19 16:15:30Z adrian $ */ 28 29#ifndef __AR71XX_CPUDEF_H__ 30#define __AR71XX_CPUDEF_H__ 31 32struct ar71xx_cpu_def { 33 void (* detect_mem_size) (void); 34 void (* detect_sys_frequency) (void); 35 void (* ar71xx_chip_device_stop) (uint32_t); 36 void (* ar71xx_chip_device_start) (uint32_t); 37 int (* ar71xx_chip_device_stopped) (uint32_t); 38 void (* ar71xx_chip_set_pll_ge0) (int); 39 void (* ar71xx_chip_set_pll_ge1) (int); 40 void (* ar71xx_chip_ddr_flush_ge0) (void); 41 void (* ar71xx_chip_ddr_flush_ge1) (void); 42 uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int); 43 44 /* 45 * From Linux - Handling this IRQ is a bit special. 46 * AR71xx - AR71XX_DDR_REG_FLUSH_PCI 47 * AR724x - AR724X_DDR_REG_FLUSH_PCIE 48 * AR91xx - AR91XX_DDR_REG_FLUSH_WMAC 49 * 50 * These are set when STATUSF_IP2 is set in regiser c0. 51 * This flush is done before the IRQ is handled to make 52 * sure the driver correctly sees any memory updates. 53 */ 54 void (* ar71xx_chip_irq_flush_ip2) (void); 55 /* 56 * The USB peripheral init code is subtly different for 57 * each chip. 58 */ 59 void (* ar71xx_chip_init_usb_peripheral) (void); 60}; 61 62extern struct ar71xx_cpu_def * ar71xx_cpu_ops; 63 64static inline void ar71xx_detect_sys_frequency(void) 65{ 66 ar71xx_cpu_ops->detect_sys_frequency(); 67} 68 69static inline void ar71xx_device_stop(uint32_t mask) 70{ 71 ar71xx_cpu_ops->ar71xx_chip_device_stop(mask); 72} 73 74static inline void ar71xx_device_start(uint32_t mask) 75{ 76 ar71xx_cpu_ops->ar71xx_chip_device_start(mask); 77} 78 79static inline int ar71xx_device_stopped(uint32_t mask) 80{ 81 return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask); 82} 83 84static inline void ar71xx_device_set_pll_ge0(int speed) 85{ 86 ar71xx_cpu_ops->ar71xx_chip_set_pll_ge0(speed); 87} 88 89static inline void ar71xx_device_set_pll_ge1(int speed) 90{ 91 ar71xx_cpu_ops->ar71xx_chip_set_pll_ge1(speed); 92} 93 94static inline void ar71xx_device_flush_ddr_ge0(void) 95{ 96 ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge0(); 97} 98 99static inline void ar71xx_device_flush_ddr_ge1(void) 100{ 101 ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge1(); 102} 103 104static inline void ar71xx_init_usb_peripheral(void) 105{ 106 ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral(); 107} 108 109/* XXX shouldn't be here! */ 110extern uint32_t u_ar71xx_cpu_freq; 111extern uint32_t u_ar71xx_ahb_freq; 112extern uint32_t u_ar71xx_ddr_freq; 113 114static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; } 115static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; } 116static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; } 117 118#endif 119