ar71xx_cpudef.h revision 248781
130036Sache/*- 237Srgrimes * Copyright (c) 2010 Adrian Chadd 337Srgrimes * All rights reserved. 4204Snate * 52878Srgrimes * Redistribution and use in source and binary forms, with or without 68571Srgrimes * modification, are permitted provided that the following conditions 72878Srgrimes * are met: 88571Srgrimes * 1. Redistributions of source code must retain the above copyright 98571Srgrimes * notice, this list of conditions and the following disclaimer. 108571Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 112878Srgrimes * notice, this list of conditions and the following disclaimer in the 128571Srgrimes * documentation and/or other materials provided with the distribution. 138571Srgrimes * 142878Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 158571Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 162878Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 178571Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 182878Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 192878Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 202878Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 218571Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 222878Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 232878Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 242878Srgrimes * SUCH DAMAGE. 252878Srgrimes */ 2628979Seivind 2728979Seivind/* $FreeBSD: head/sys/mips/atheros/ar71xx_cpudef.h 248781 2013-03-27 03:33:19Z adrian $ */ 2829807Sache 2929807Sache#ifndef __AR71XX_CPUDEF_H__ 3029791Sache#define __AR71XX_CPUDEF_H__ 312878Srgrimes 3228979Seivindstruct ar71xx_cpu_def { 3323120Smpp void (* detect_mem_size) (void); 3428979Seivind void (* detect_sys_frequency) (void); 352878Srgrimes void (* ar71xx_chip_device_stop) (uint32_t); 362878Srgrimes void (* ar71xx_chip_device_start) (uint32_t); 372878Srgrimes int (* ar71xx_chip_device_stopped) (uint32_t); 382878Srgrimes void (* ar71xx_chip_set_pll_ge) (int, int, uint32_t); 3925425Sjkh void (* ar71xx_chip_set_mii_speed) (uint32_t, uint32_t); 402878Srgrimes void (* ar71xx_chip_set_mii_if) (uint32_t, ar71xx_mii_mode); 4112388Sache void (* ar71xx_chip_ddr_flush_ge) (int); 422878Srgrimes uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int); 432878Srgrimes 442878Srgrimes /* 4527755Sache * From Linux - Handling this IRQ is a bit special. 462878Srgrimes * AR71xx - AR71XX_DDR_REG_FLUSH_PCI 4717829Spst * AR724x - AR724X_DDR_REG_FLUSH_PCIE 482878Srgrimes * AR91xx - AR91XX_DDR_REG_FLUSH_WMAC 492878Srgrimes * 502878Srgrimes * These are set when STATUSF_IP2 is set in regiser c0. 512878Srgrimes * This flush is done before the IRQ is handled to make 522878Srgrimes * sure the driver correctly sees any memory updates. 532878Srgrimes */ 542878Srgrimes void (* ar71xx_chip_ddr_flush_ip2) (void); 552878Srgrimes /* 562878Srgrimes * The USB peripheral init code is subtly different for 5730036Sache * each chip. 5830036Sache */ 592878Srgrimes void (* ar71xx_chip_init_usb_peripheral) (void); 6018912Sjoerg}; 6118912Sjoerg 622878Srgrimesextern struct ar71xx_cpu_def * ar71xx_cpu_ops; 632878Srgrimes 648571Srgrimesstatic inline void ar71xx_detect_sys_frequency(void) 658571Srgrimes{ 662878Srgrimes ar71xx_cpu_ops->detect_sys_frequency(); 678571Srgrimes} 682878Srgrimes 698571Srgrimesstatic inline void ar71xx_device_stop(uint32_t mask) 702878Srgrimes{ 718571Srgrimes ar71xx_cpu_ops->ar71xx_chip_device_stop(mask); 722878Srgrimes} 738571Srgrimes 742878Srgrimesstatic inline void ar71xx_device_start(uint32_t mask) 752878Srgrimes{ 762878Srgrimes ar71xx_cpu_ops->ar71xx_chip_device_start(mask); 772878Srgrimes} 782878Srgrimes 798571Srgrimesstatic inline int ar71xx_device_stopped(uint32_t mask) 808571Srgrimes{ 818571Srgrimes return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask); 828571Srgrimes} 832878Srgrimes 848571Srgrimesstatic inline void ar71xx_device_set_pll_ge(int unit, int speed, uint32_t pll) 858571Srgrimes{ 86949Snate ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed, pll); 87} 88 89static inline void ar71xx_device_set_mii_speed(int unit, int speed) 90{ 91 ar71xx_cpu_ops->ar71xx_chip_set_mii_speed(unit, speed); 92} 93 94static inline void ar71xx_device_set_mii_if(int unit, ar71xx_mii_mode mii_cfg) 95{ 96 ar71xx_cpu_ops->ar71xx_chip_set_mii_if(unit, mii_cfg); 97} 98 99static inline void ar71xx_device_flush_ddr_ge(int unit) 100{ 101 ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge(unit); 102} 103 104static inline uint32_t ar71xx_device_get_eth_pll(unsigned int unit, int speed) 105{ 106 return (ar71xx_cpu_ops->ar71xx_chip_get_eth_pll(unit, speed)); 107} 108 109static inline void ar71xx_init_usb_peripheral(void) 110{ 111 ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral(); 112} 113 114static inline void ar71xx_device_ddr_flush_ip2(void) 115{ 116 ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2(); 117} 118 119/* XXX shouldn't be here! */ 120extern uint32_t u_ar71xx_refclk; 121extern uint32_t u_ar71xx_cpu_freq; 122extern uint32_t u_ar71xx_ahb_freq; 123extern uint32_t u_ar71xx_ddr_freq; 124 125static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; } 126static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; } 127static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; } 128static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; } 129 130#endif 131