1178173Simp/* $NetBSD: uart.h,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */ 2178173Simp 3178173Simp/*- 4178173Simp * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5178173Simp * All rights reserved. 6178173Simp * 7178173Simp * Redistribution and use in source and binary forms, with or 8178173Simp * without modification, are permitted provided that the following 9178173Simp * conditions are met: 10178173Simp * 1. Redistributions of source code must retain the above copyright 11178173Simp * notice, this list of conditions and the following disclaimer. 12178173Simp * 2. Redistributions in binary form must reproduce the above 13178173Simp * copyright notice, this list of conditions and the following 14178173Simp * disclaimer in the documentation and/or other materials provided 15178173Simp * with the distribution. 16178173Simp * 3. The names of the authors may not be used to endorse or promote 17178173Simp * products derived from this software without specific prior 18178173Simp * written permission. 19178173Simp * 20178173Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21178173Simp * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22178173Simp * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23178173Simp * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24178173Simp * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25178173Simp * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26178173Simp * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27178173Simp * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28178173Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29178173Simp * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30178173Simp * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31178173Simp * OF SUCH DAMAGE. 32178173Simp * 33178173Simp * $FreeBSD$ 34178173Simp */ 35178173Simp#ifndef _ADMUART_H 36178173Simp#define _ADMUART_H 37178173Simp/* UART registers */ 38178173Simp#define UART_DR_REG 0x00 39178173Simp#define UART_RSR_REG 0x04 40178173Simp#define UART_RSR_FE 0x01 41178173Simp#define UART_RSR_PE 0x02 42178173Simp#define UART_RSR_BE 0x04 43178173Simp#define UART_RSR_OE 0x08 44178173Simp#define UART_ECR_REG 0x04 45178173Simp#define UART_ECR_RSR 0x80 46178173Simp#define UART_LCR_H_REG 0x08 47178173Simp#define UART_LCR_H_FEN 0x10 48178173Simp#define UART_LCR_M_REG 0x0c 49178173Simp#define UART_LCR_L_REG 0x10 50178173Simp#define UART_CR_REG 0x14 51178173Simp#define UART_CR_PORT_EN 0x01 52178173Simp#define UART_CR_SIREN 0x02 53178173Simp#define UART_CR_SIRLP 0x04 54178173Simp#define UART_CR_MODEM_STATUS_INT_EN 0x08 55178173Simp#define UART_CR_RX_INT_EN 0x10 56178173Simp#define UART_CR_TX_INT_EN 0x20 57178173Simp#define UART_CR_RX_TIMEOUT_INT_EN 0x40 58178173Simp#define UART_CR_LOOPBACK_EN 0x80 59178173Simp#define UART_FR_REG 0x18 60178173Simp#define UART_FR_CTS 0x01 61178173Simp#define UART_FR_DSR 0x02 62178173Simp#define UART_FR_DCD 0x04 63178173Simp#define UART_FR_BUSY 0x08 64178173Simp#define UART_FR_RX_FIFO_EMPTY 0x10 65178173Simp#define UART_FR_TX_FIFO_FULL 0x20 66178173Simp#define UART_FR_RX_FIFO_FULL 0x40 67178173Simp#define UART_FR_TX_FIFO_EMPTY 0x80 68178173Simp#define UART_IR_REG 0x1c 69178173Simp#define UART_IR_MODEM_STATUS_INT 0x01 70178173Simp#define UART_IR_RX_INT 0x02 71178173Simp#define UART_IR_TX_INT 0x04 72178173Simp#define UART_IR_RX_TIMEOUT_INT 0x08 73178173Simp#define UART_IR_INT_MASK 0x0f 74178173Simp#define UART_IR_UICR 0x80 75178173Simp#define UART_ILPR_REG 0x20 76178173Simp 77178173Simp/* UART interrupts */ 78178173Simp 79178173Simpint uart_cnattach(void); 80178173Simp#endif /* _ADMUART_H */ 81