if_admswreg.h revision 256281
1/* $NetBSD: if_admswreg.h,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */ 2 3/*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 * 33 * $FreeBSD: stable/10/sys/mips/adm5120/if_admswreg.h 202175 2010-01-12 21:36:08Z imp $ 34 */ 35#ifndef _IF_ADMSWREG_H_ 36#define _IF_ADMSWREG_H_ 37 38#define ADMSW_BOOT_DONE 0x0008 39#define ADMSW_BOOT_DONE_BO __BIT(0) 40#define ADMSW_SW_RES 0x000c 41#define ADMSW_SW_RES_SWR __BITS(31, 0) 42#define ADMSW_INT_ST 0x00b0 43#define ADMSW_INT_MASK 0x00b4 44 45#define ADMSW_INTR_RSVD __BITS(31, 25) 46#define ADMSW_INTR_CPUH __BIT(24) 47#define ADMSW_INTR_SDE __BIT(23) 48#define ADMSW_INTR_RDE __BIT(22) 49#define ADMSW_INTR_W1TE __BIT(21) 50#define ADMSW_INTR_W0TE __BIT(20) 51#define ADMSW_INTR_MI __BIT(19) 52#define ADMSW_INTR_PSC __BIT(18) 53#define ADMSW_INTR_BCS __BIT(16) 54#define ADMSW_INTR_MD __BIT(15) 55#define ADMSW_INTR_GQF __BIT(14) 56#define ADMSW_INTR_CPQ __BIT(13) 57#define ADMSW_INTR_P5QF __BIT(11) 58#define ADMSW_INTR_P4QF __BIT(10) 59#define ADMSW_INTR_P3QF __BIT(9) 60#define ADMSW_INTR_P2QF __BIT(8) 61#define ADMSW_INTR_P1QF __BIT(7) 62#define ADMSW_INTR_P0QF __BIT(6) 63#define ADMSW_INTR_LDF __BIT(5) 64#define ADMSW_INTR_HDF __BIT(4) 65#define ADMSW_INTR_RLD __BIT(3) 66#define ADMSW_INTR_RHD __BIT(2) 67#define ADMSW_INTR_SLD __BIT(1) 68#define ADMSW_INTR_SHD __BIT(0) 69 70#define ADMSW_INT_FMT \ 71 "\x10"\ 72 "\x01SHD"\ 73 "\x02SLD"\ 74 "\x03RHD"\ 75 "\x04RLD"\ 76 "\x05HDF"\ 77 "\x06LDF"\ 78 "\x07P0QF"\ 79 "\x08P1QF"\ 80 "\x09P2QF"\ 81 "\x0aP3QF"\ 82 "\x0bP4QF"\ 83 "\x0cP5QF"\ 84 "\x0e"\ 85 "CPQ"\ 86 "\x0fGQF"\ 87 "\x10MD"\ 88 "\x11"\ 89 "BCS"\ 90 "\x13PSC"\ 91 "\x14MI"\ 92 "\x15W0TE"\ 93 "\x16W1TE"\ 94 "\x17RDE"\ 95 "\x18SDE"\ 96 "\x19"\ 97 "CPUH" 98 99#define CODE_REG 0x0000 100#define SFTREST_REG 0x0004 101#define BOOT_DONE_REG 0x0008 102#define GLOBAL_ST_REG 0x0010 103#define PHY_ST_REG 0x0014 104#define PHY_ST_LINKUP (1 << 0) 105#define PHY_ST_100M (1 << 8) 106#define PHY_ST_FDX (1 << 16) 107#define PORT_ST_REG 0x0018 108#define MEM_CONTROL_REG 0x001C 109#define SW_CONF_REG 0x0020 110 111#define CPUP_CONF_REG 0x0024 112#define CPUP_CONF_DCPUP 0x00000001 113#define CPUP_CONF_CRCP 0x00000002 114#define CPUP_CONF_BTM 0x00000004 115#define CPUP_CONF_DUNP_SHIFT 9 116#define CPUP_CONF_DUNP_MASK (0x3F << CPUP_CONF_DUNP_SHIFT) 117#define CPUP_CONF_DMCP_SHIFT 16 118#define CPUP_CONF_DMCP_MASK (0x3F << CPUP_CONF_DMCP_SHIFT) 119#define CPUP_CONF_DBCP_SHIFT 24 120#define CPUP_CONF_DBCP_MASK (0x3F << CPUP_CONF_DBCP_SHIFT) 121 122#define PORT_CONF0_REG 0x0028 123#define PORT_CONF0_DP_MASK 0x0000003F 124#define PORT_CONF0_EMCP_MASK 0x00003F00 125#define PORT_CONF0_EMCP_SHIFT 8 126#define PORT_CONF0_EMBP_MASK 0x003F0000 127#define PORT_CONF0_EMBP_SHIFT 16 128#define PORT_CONF1_REG 0x002C 129#define PORT_CONF2_REG 0x0030 130 131#define VLAN_G1_REG 0x0040 132#define VLAN_G2_REG 0x0044 133#define SEND_TRIG_REG 0x0048 134#define SRCH_CMD_REG 0x004C 135#define ADDR_ST0_REG 0x0050 136#define ADDR_ST1_REG 0x0054 137#define MAC_WT0_REG 0x0058 138#define MAC_WT0_WRITE 0x00000001 139#define MAC_WT0_WRITE_DONE 0x00000002 140#define MAC_WT0_FILTER_EN 0x00000004 141#define MAC_WT0_VLANID_SHIFT 3 142#define MAC_WT0_VLANID_MASK 0x00000038 143#define MAC_WT0_VLANID_EN 0x00000040 144#define MAC_WT0_PORTMAP_MASK 0x00001F80 145#define MAC_WT0_PORTMAP_SHIFT 7 146#define MAC_WT0_AGE_MASK (0x7 << 13) 147#define MAC_WT0_AGE_STATIC (0x7 << 13) 148#define MAC_WT0_AGE_VALID (0x1 << 13) 149#define MAC_WT0_AGE_EMPTY 0 150#define MAC_WT1_REG 0x005C 151#define BW_CNTL0_REG 0x0060 152#define BW_CNTL1_REG 0x0064 153#define PHY_CNTL0_REG 0x0068 154#define PHY_CNTL1_REG 0x006C 155#define FC_TH_REG 0x0070 156#define FC_TH_FCS_MASK 0x01FF0000 157#define FC_TH_D2R_MASK 0x0000FF00 158#define FC_TH_D2S_MASK 0x000000FF 159#define ADJ_PORT_TH_REG 0x0074 160#define PORT_TH_REG 0x0078 161#define PHY_CNTL2_REG 0x007C 162#define PHY_CNTL2_AUTONEG (1 << 0) 163#define PHY_CNTL2_ANE_MASK 0x0000001F 164#define PHY_CNTL2_SC_MASK 0x000003E0 165#define PHY_CNTL2_SC_SHIFT 5 166#define PHY_CNTL2_100M (1 << PHY_CNTL2_SC_SHIFT) 167#define PHY_CNTL2_DC_MASK 0x00007C00 168#define PHY_CNTL2_DC_SHIFT 10 169#define PHY_CNTL2_FDX (1 << PHY_CNTL2_DC_SHIFT) 170#define PHY_CNTL2_RFCV_MASK 0x000F8000 171#define PHY_CNTL2_RFCV_SHIFT 15 172#define PHY_CNTL2_PHYR_MASK 0x01F00000 173#define PHY_CNTL2_PHYR_SHIFT 20 174#define PHY_CNTL2_AMDIX_MASK 0x3E000000 175#define PHY_CNTL2_AMDIX_SHIFT 25 176#define PHY_CNTL2_RMAE 0x40000000 177#define PHY_CNTL3_REG 0x0080 178#define PHY_CNTL3_RNT 0x00000400 179 180#define PRI_CNTL_REG 0x0084 181#define VLAN_PRI_REG 0x0088 182#define TOS_EN_REG 0x008C 183#define TOS_MAP0_REG 0x0090 184#define TOS_MAP1_REG 0x0094 185#define CUSTOM_PRI1_REG 0x0098 186#define CUSTOM_PRI2_REG 0x009C 187 188#define EMPTY_CNT_REG 0x00A4 189#define PORT_CNT_SEL_REG 0x00A8 190#define PORT_CNT_REG 0x00AC 191 192#define INT_MASK 0x1FDEFFF 193 194#define GPIO_CONF0_REG 0x00B8 195#define GPIO_CONF2_REG 0x00BC 196 197#define SWAP_IN_REG 0x00C8 198#define SWAP_OUT_REG 0x00CC 199 200#define SEND_HBADDR_REG 0x00D0 201#define SEND_LBADDR_REG 0x00D4 202#define RECV_HBADDR_REG 0x00D8 203#define RECV_LBADDR_REG 0x00DC 204#define SEND_HWADDR_REG 0x00E0 205#define SEND_LWADDR_REG 0x00E4 206#define RECV_HWADDR_REG 0x00E8 207#define RECV_LWADDR_REG 0x00EC 208 209#define TIMER_INT_REG 0x00F0 210#define TIMER_REG 0x00F4 211 212#define PORT0_LED_REG 0x0100 213#define PORT1_LED_REG 0x0104 214#define PORT2_LED_REG 0x0108 215#define PORT3_LED_REG 0x010c 216#define PORT4_LED_REG 0x0110 217 218/* Hardware descriptor format */ 219struct admsw_desc { 220 volatile uint32_t data; 221 volatile uint32_t cntl; 222 volatile uint32_t len; 223 volatile uint32_t status; 224} __attribute__((__packed__, __aligned__(4))); 225 226#define ADM5120_DMA_MASK 0x01ffffff 227#define ADM5120_DMA_OWN 0x80000000 /* buffer owner */ 228#define ADM5120_DMA_RINGEND 0x10000000 /* Last in DMA ring */ 229#define ADM5120_DMA_BUF2ENABLE 0x80000000 230 231#define ADM5120_DMA_PORTID 0x00007000 232#define ADM5120_DMA_PORTSHIFT 12 233#define ADM5120_DMA_LEN 0x07ff0000 234#define ADM5120_DMA_LENSHIFT 16 235#define ADM5120_DMA_TYPE 0x00000003 236#define ADM5120_DMA_TYPE_IP 0x00000000 237#define ADM5120_DMA_TYPE_PPPOE 0x00000001 238#define ADM5120_DMA_CSUM 0x80000000 239#define ADM5120_DMA_CSUMFAIL 0x00000008 240 241#define SW_DEVS 6 242 243#if 0 244/* CODE_REG */ 245#define CODE_ID_MASK 0x00FFFF 246#define CODE_ADM5120_ID 0x5120 247 248#define CODE_REV_MASK 0x0F0000 249#define CODE_REV_SHIFT 16 250#define CODE_REV_ADM5120_0 0x8 251 252#define CODE_CLK_MASK 0x300000 253#define CODE_CLK_SHIFT 20 254 255#define CPU_CLK_175MHZ 0x0 256#define CPU_CLK_200MHZ 0x1 257#define CPU_CLK_225MHZ 0x2 258#define CPU_CLK_250MHZ 0x3 259 260#define CPU_SPEED_175M (175000000/2) 261#define CPU_SPEED_200M (200000000/2) 262#define CPU_SPEED_225M (225000000/2) 263#define CPU_SPEED_250M (250000000/2) 264 265#define CPU_NAND_BOOT 0x01000000 266#define CPU_DCACHE_2K_WAY (0x1 << 25) 267#define CPU_DCACHE_2WAY (0x1 << 26) 268#define CPU_ICACHE_2K_WAY (0x1 << 27) 269#define CPU_ICACHE_2WAY (0x1 << 28) 270 271#define CPU_GMII_SUPPORT 0x20000000 272 273#define CPU_PQFP_MODE (0x1 << 29) 274 275#define CPU_CACHE_LINE_SIZE 16 276 277/* SftRest_REG */ 278#define SOFTWARE_RESET 0x1 279 280/* Boot_done_REG */ 281#define BOOT_DONE 0x1 282 283/* SWReset_REG */ 284#define SWITCH_RESET 0x1 285 286/* Global_St_REG */ 287#define DATA_BUF_BIST_FAILED (0x1 << 0) 288#define LINK_TAB_BIST_FAILED (0x1 << 1) 289#define MC_TAB_BIST_FAILED (0x1 << 2) 290#define ADDR_TAB_BIST_FAILED (0x1 << 3) 291#define DCACHE_D_FAILED (0x3 << 4) 292#define DCACHE_T_FAILED (0x1 << 6) 293#define ICACHE_D_FAILED (0x3 << 7) 294#define ICACHE_T_FAILED (0x1 << 9) 295#define BIST_FAILED_MASK 0x03FF 296 297#define ALLMEM_TEST_DONE (0x1 << 10) 298 299#define SKIP_BLK_CNT_MASK 0x1FF000 300#define SKIP_BLK_CNT_SHIFT 12 301 302 303/* PHY_st_REG */ 304#define PORT_LINK_MASK 0x0000001F 305#define PORT_MII_LINKFAIL 0x00000020 306#define PORT_SPEED_MASK 0x00001F00 307 308#define PORT_GMII_SPD_MASK 0x00006000 309#define PORT_GMII_SPD_10M 0 310#define PORT_GMII_SPD_100M 0x00002000 311#define PORT_GMII_SPD_1000M 0x00004000 312 313#define PORT_DUPLEX_MASK 0x003F0000 314#define PORT_FLOWCTRL_MASK 0x1F000000 315 316#define PORT_GMII_FLOWCTRL_MASK 0x60000000 317#define PORT_GMII_FC_ON 0x20000000 318#define PORT_GMII_RXFC_ON 0x20000000 319#define PORT_GMII_TXFC_ON 0x40000000 320 321/* Port_st_REG */ 322#define PORT_SECURE_ST_MASK 0x001F 323#define MII_PORT_TXC_ERR 0x0080 324 325/* Mem_control_REG */ 326#define SDRAM_SIZE_4MBYTES 0x0001 327#define SDRAM_SIZE_8MBYTES 0x0002 328#define SDRAM_SIZE_16MBYTES 0x0003 329#define SDRAM_SIZE_64MBYTES 0x0004 330#define SDRAM_SIZE_128MBYTES 0x0005 331#define SDRAM_SIZE_MASK 0x0007 332 333#define MEMCNTL_SDRAM1_EN (0x1 << 5) 334 335#define ROM_SIZE_DISABLE 0x0000 336#define ROM_SIZE_512KBYTES 0x0001 337#define ROM_SIZE_1MBYTES 0x0002 338#define ROM_SIZE_2MBYTES 0x0003 339#define ROM_SIZE_4MBYTES 0x0004 340#define ROM_SIZE_8MBYTES 0x0005 341#define ROM_SIZE_MASK 0x0007 342 343#define ROM0_SIZE_SHIFT 8 344#define ROM1_SIZE_SHIFT 16 345 346 347/* SW_conf_REG */ 348#define SW_AGE_TIMER_MASK 0x000000F0 349#define SW_AGE_TIMER_DISABLE 0x0 350#define SW_AGE_TIMER_FAST 0x00000080 351#define SW_AGE_TIMER_300SEC 0x00000010 352#define SW_AGE_TIMER_600SEC 0x00000020 353#define SW_AGE_TIMER_1200SEC 0x00000030 354#define SW_AGE_TIMER_2400SEC 0x00000040 355#define SW_AGE_TIMER_4800SEC 0x00000050 356#define SW_AGE_TIMER_9600SEC 0x00000060 357#define SW_AGE_TIMER_19200SEC 0x00000070 358//#define SW_AGE_TIMER_38400SEC 0x00000070 359 360#define SW_BC_PREV_MASK 0x00000300 361#define SW_BC_PREV_DISABLE 0 362#define SW_BC_PREV_64BC 0x00000100 363#define SW_BC_PREV_48BC 0x00000200 364#define SW_BC_PREV_32BC 0x00000300 365 366#define SW_MAX_LEN_MASK 0x00000C00 367#define SW_MAX_LEN_1536 0 368#define SW_MAX_LEN_1522 0x00000800 369#define SW_MAX_LEN_1518 0x00000400 370 371#define SW_DIS_COLABT 0x00001000 372 373#define SW_HASH_ALG_MASK 0x00006000 374#define SW_HASH_ALG_DIRECT 0 375#define SW_HASH_ALG_XOR48 0x00002000 376#define SW_HASH_ALG_XOR32 0x00004000 377 378#define SW_DISABLE_BACKOFF_TIMER 0x00008000 379 380#define SW_BP_NUM_MASK 0x000F0000 381#define SW_BP_NUM_SHIFT 16 382#define SW_BP_MODE_MASK 0x00300000 383#define SW_BP_MODE_DISABLE 0 384#define SW_BP_MODE_JAM 0x00100000 385#define SW_BP_MODE_JAMALL 0x00200000 386#define SW_BP_MODE_CARRIER 0x00300000 387#define SW_RESRV_MC_FILTER 0x00400000 388#define SW_BISR_DISABLE 0x00800000 389 390#define SW_DIS_MII_WAS_TX 0x01000000 391#define SW_BISS_EN 0x02000000 392#define SW_BISS_TH_MASK 0x0C000000 393#define SW_BISS_TH_SHIFT 26 394#define SW_REQ_LATENCY_MASK 0xF0000000 395#define SW_REQ_LATENCY_SHIFT 28 396 397 398/* CPUp_conf_REG */ 399#define SW_CPU_PORT_DISABLE 0x00000001 400#define SW_PADING_CRC 0x00000002 401#define SW_BRIDGE_MODE 0x00000004 402 403#define SW_DIS_UN_SHIFT 9 404#define SW_DIS_UN_MASK (0x3F << SW_DIS_UN_SHIFT) 405#define SW_DIS_MC_SHIFT 16 406#define SW_DIS_MC_MASK (0x3F << SW_DIS_MC_SHIFT) 407#define SW_DIS_BC_SHIFT 24 408#define SW_DIS_BC_MASK (0x3F << SW_DIS_BC_SHIFT) 409 410 411/* Port_conf0_REG */ 412#define SW_DISABLE_PORT_MASK 0x0000003F 413#define SW_EN_MC_MASK 0x00003F00 414#define SW_EN_MC_SHIFT 8 415#define SW_EN_BP_MASK 0x003F0000 416#define SW_EN_BP_SHIFT 16 417#define SW_EN_FC_MASK 0x3F000000 418#define SW_EN_FC_SHIFT 24 419 420 421/* Port_conf1_REG */ 422#define SW_DIS_SA_LEARN_MASK 0x0000003F 423#define SW_PORT_BLOCKING_MASK 0x00000FC0 424#define SW_PORT_BLOCKING_SHIFT 6 425#define SW_PORT_BLOCKING_ON 0x1 426 427#define SW_PORT_BLOCKING_MODE_MASK 0x0003F000 428#define SW_PORT_BLOCKING_MODE_SHIFT 12 429#define SW_PORT_BLOCKING_CTRLONLY 0x1 430 431#define SW_EN_PORT_AGE_MASK 0x03F00000 432#define SW_EN_PORT_AGE_SHIFT 20 433#define SW_EN_SA_SECURED_MASK 0xFC000000 434#define SW_EN_SA_SECURED_SHIFT 26 435 436 437/* Port_conf2_REG */ 438#define SW_GMII_AN_EN 0x00000001 439#define SW_GMII_FORCE_SPD_MASK 0x00000006 440#define SW_GMII_FORCE_SPD_10M 0 441#define SW_GMII_FORCE_SPD_100M 0x2 442#define SW_GMII_FORCE_SPD_1000M 0x4 443 444#define SW_GMII_FORCE_FULL_DUPLEX 0x00000008 445 446#define SW_GMII_FORCE_RXFC 0x00000010 447#define SW_GMII_FORCE_TXFC 0x00000020 448 449#define SW_GMII_EN 0x00000040 450#define SW_GMII_REVERSE 0x00000080 451 452#define SW_GMII_TXC_CHECK_EN 0x00000100 453 454#define SW_LED_FLASH_TIME_MASK 0x00030000 455#define SW_LED_FLASH_TIME_30MS 0 456#define SW_LED_FLASH_TIME_60MS 0x00010000 457#define SW_LED_FLASH_TIME_240MS 0x00020000 458#define SW_LED_FLASH_TIME_480MS 0x00030000 459 460 461/* Send_trig_REG */ 462#define SEND_TRIG_LOW 0x0001 463#define SEND_TRIG_HIGH 0x0002 464 465 466/* Srch_cmd_REG */ 467#define SW_MAC_SEARCH_START 0x000001 468#define SW_MAX_SEARCH_AGAIN 0x000002 469 470 471/* MAC_wt0_REG */ 472#define SW_MAC_WRITE 0x00000001 473#define SW_MAC_WRITE_DONE 0x00000002 474#define SW_MAC_FILTER_EN 0x00000004 475#define SW_MAC_VLANID_SHIFT 3 476#define SW_MAC_VLANID_MASK 0x00000038 477#define SW_MAC_VLANID_EN 0x00000040 478#define SW_MAC_PORTMAP_MASK 0x00001F80 479#define SW_MAC_PORTMAP_SHIFT 7 480#define SW_MAC_AGE_MASK (0x7 << 13) 481#define SW_MAC_AGE_STATIC (0x7 << 13) 482#define SW_MAC_AGE_VALID (0x1 << 13) 483#define SW_MAC_AGE_EMPTY 0 484 485/* BW_cntl0_REG */ 486#define SW_PORT_TX_NOLIMIT 0 487#define SW_PORT_TX_64K 1 488#define SW_PORT_TX_128K 2 489#define SW_PORT_TX_256K 3 490#define SW_PORT_TX_512K 4 491#define SW_PORT_TX_1M 5 492#define SW_PORT_TX_4M 6 493#define SW_PORT_TX_10MK 7 494 495/* BW_cntl1_REG */ 496#define SW_TRAFFIC_SHAPE_IPG (0x1 << 31) 497 498/* PHY_cntl0_REG */ 499#define SW_PHY_ADDR_MASK 0x0000001F 500#define PHY_ADDR_MAX 0x1f 501#define SW_PHY_REG_ADDR_MASK 0x00001F00 502#define SW_PHY_REG_ADDR_SHIFT 8 503#define PHY_REG_ADDR_MAX 0x1f 504#define SW_PHY_WRITE 0x00002000 505#define SW_PHY_READ 0x00004000 506#define SW_PHY_WDATA_MASK 0xFFFF0000 507#define SW_PHY_WDATA_SHIFT 16 508 509 510/* PHY_cntl1_REG */ 511#define SW_PHY_WRITE_DONE 0x00000001 512#define SW_PHY_READ_DONE 0x00000002 513#define SW_PHY_RDATA_MASK 0xFFFF0000 514#define SW_PHY_RDATA_SHIFT 16 515 516/* FC_th_REG */ 517/* Adj_port_th_REG */ 518/* Port_th_REG */ 519 520/* PHY_cntl2_REG */ 521#define SW_PHY_AN_MASK 0x0000001F 522#define SW_PHY_SPD_MASK 0x000003E0 523#define SW_PHY_SPD_SHIFT 5 524#define SW_PHY_DPX_MASK 0x00007C00 525#define SW_PHY_DPX_SHIFT 10 526#define SW_FORCE_FC_MASK 0x000F8000 527#define SW_FORCE_FC_SHIFT 15 528#define SW_PHY_NORMAL_MASK 0x01F00000 529#define SW_PHY_NORMAL_SHIFT 20 530#define SW_PHY_AUTOMDIX_MASK 0x3E000000 531#define SW_PHY_AUTOMDIX_SHIFT 25 532#define SW_PHY_REC_MCCAVERAGE 0x40000000 533 534 535/* PHY_cntl3_REG */ 536/* Pri_cntl_REG */ 537/* VLAN_pri_REG */ 538/* TOS_en_REG */ 539/* TOS_map0_REG */ 540/* TOS_map1_REG */ 541/* Custom_pri1_REG */ 542/* Custom_pri2_REG */ 543/* Empty_cnt_REG */ 544/* Port_cnt_sel_REG */ 545/* Port_cnt_REG */ 546 547 548/* SW_Int_st_REG & SW_Int_mask_REG */ 549#define SEND_H_DONE_INT 0x0000001 550#define SEND_L_DONE_INT 0x0000002 551#define RX_H_DONE_INT 0x0000004 552#define RX_L_DONE_INT 0x0000008 553#define RX_H_DESC_FULL_INT 0x0000010 554#define RX_L_DESC_FULL_INT 0x0000020 555#define PORT0_QUE_FULL_INT 0x0000040 556#define PORT1_QUE_FULL_INT 0x0000080 557#define PORT2_QUE_FULL_INT 0x0000100 558#define PORT3_QUE_FULL_INT 0x0000200 559#define PORT4_QUE_FULL_INT 0x0000400 560#define PORT5_QUE_FULL_INT 0x0000800 561 562#define CPU_QUE_FULL_INT 0x0002000 563#define GLOBAL_QUE_FULL_INT 0x0004000 564#define MUST_DROP_INT 0x0008000 565#define BC_STORM_INT 0x0010000 566 567#define PORT_STATUS_CHANGE_INT 0x0040000 568#define INTRUDER_INT 0x0080000 569#define WATCHDOG0_EXPR_INT 0x0100000 570#define WATCHDOG1_EXPR_INT 0x0200000 571#define RX_DESC_ERR_INT 0x0400000 572#define SEND_DESC_ERR_INT 0x0800000 573#define CPU_HOLD_INT 0x1000000 574#define SWITCH_INT_MASK 0x1FDEFFF 575 576 577/* GPIO_conf0_REG */ 578#define GPIO0_INPUT_MODE 0x00000001 579#define GPIO1_INPUT_MODE 0x00000002 580#define GPIO2_INPUT_MODE 0x00000004 581#define GPIO3_INPUT_MODE 0x00000008 582#define GPIO4_INPUT_MODE 0x00000010 583#define GPIO5_INPUT_MODE 0x00000020 584#define GPIO6_INPUT_MODE 0x00000040 585#define GPIO7_INPUT_MODE 0x00000080 586 587#define GPIO0_OUTPUT_MODE 0 588#define GPIO1_OUTPUT_MODE 0 589#define GPIO2_OUTPUT_MODE 0 590#define GPIO3_OUTPUT_MODE 0 591#define GPIO4_OUTPUT_MODE 0 592#define GPIO5_OUTPUT_MODE 0 593#define GPIO6_OUTPUT_MODE 0 594#define GPIO7_OUTPUT_MODE 0 595 596#define GPIO0_INPUT_MASK 0x00000100 597#define GPIO1_INPUT_MASK 0x00000200 598#define GPIO2_INPUT_MASK 0x00000400 599#define GPIO3_INPUT_MASK 0x00000800 600#define GPIO4_INPUT_MASK 0x00001000 601#define GPIO5_INPUT_MASK 0x00002000 602#define GPIO6_INPUT_MASK 0x00004000 603#define GPIO7_INPUT_MASK 0x00008000 604 605#define GPIO0_OUTPUT_EN 0x00010000 606#define GPIO1_OUTPUT_EN 0x00020000 607#define GPIO2_OUTPUT_EN 0x00040000 608#define GPIO3_OUTPUT_EN 0x00080000 609#define GPIO4_OUTPUT_EN 0x00100000 610#define GPIO5_OUTPUT_EN 0x00200000 611#define GPIO6_OUTPUT_EN 0x00400000 612#define GPIO7_OUTPUT_EN 0x00800000 613 614#define GPIO_CONF0_OUTEN_MASK 0x00ff0000 615 616#define GPIO0_OUTPUT_HI 0x01000000 617#define GPIO1_OUTPUT_HI 0x02000000 618#define GPIO2_OUTPUT_HI 0x04000000 619#define GPIO3_OUTPUT_HI 0x08000000 620#define GPIO4_OUTPUT_HI 0x10000000 621#define GPIO5_OUTPUT_HI 0x20000000 622#define GPIO6_OUTPUT_HI 0x40000000 623#define GPIO7_OUTPUT_HI 0x80000000 624 625#define GPIO0_OUTPUT_LOW 0 626#define GPIO1_OUTPUT_LOW 0 627#define GPIO2_OUTPUT_LOW 0 628#define GPIO3_OUTPUT_LOW 0 629#define GPIO4_OUTPUT_LOW 0 630#define GPIO5_OUTPUT_LOW 0 631#define GPIO6_OUTPUT_LOW 0 632#define GPIO7_OUTPUT_LOW 0 633 634 635/* GPIO_conf2_REG */ 636#define EXTIO_WAIT_EN (0x1 << 6) 637#define EXTIO_CS1_INT1_EN (0x1 << 5) 638#define EXTIO_CS0_INT0_EN (0x1 << 4) 639 640/* Timer_int_REG */ 641#define SW_TIMER_INT_DISABLE 0x10000 642#define SW_TIMER_INT 0x1 643 644/* Timer_REG */ 645#define SW_TIMER_EN 0x10000 646#define SW_TIMER_MASK 0xffff 647#define SW_TIMER_10MS_TICKS 0x3D09 648#define SW_TIMER_1MS_TICKS 0x61A 649#define SW_TIMER_100US_TICKS 0x9D 650 651 652/* Port0_LED_REG, Port1_LED_REG, Port2_LED_REG, Port3_LED_REG, Port4_LED_REG*/ 653#define GPIOL_INPUT_MODE 0x00 654#define GPIOL_OUTPUT_FLASH 0x01 655#define GPIOL_OUTPUT_LOW 0x02 656#define GPIOL_OUTPUT_HIGH 0x03 657#define GPIOL_LINK_LED 0x04 658#define GPIOL_SPEED_LED 0x05 659#define GPIOL_DUPLEX_LED 0x06 660#define GPIOL_ACT_LED 0x07 661#define GPIOL_COL_LED 0x08 662#define GPIOL_LINK_ACT_LED 0x09 663#define GPIOL_DUPLEX_COL_LED 0x0A 664#define GPIOL_10MLINK_ACT_LED 0x0B 665#define GPIOL_100MLINK_ACT_LED 0x0C 666#define GPIOL_CTRL_MASK 0x0F 667 668#define GPIOL_INPUT_MASK 0x7000 669#define GPIOL_INPUT_0_MASK 0x1000 670#define GPIOL_INPUT_1_MASK 0x2000 671#define GPIOL_INPUT_2_MASK 0x4000 672 673#define PORT_LED0_SHIFT 0 674#define PORT_LED1_SHIFT 4 675#define PORT_LED2_SHIFT 8 676#endif 677 678#endif /* _IF_ADMSWREG_H_ */ 679