166458Sdfr/*- 266458Sdfr * Copyright (c) 1998 Doug Rabson 366458Sdfr * All rights reserved. 466458Sdfr * 566458Sdfr * Redistribution and use in source and binary forms, with or without 666458Sdfr * modification, are permitted provided that the following conditions 766458Sdfr * are met: 866458Sdfr * 1. Redistributions of source code must retain the above copyright 966458Sdfr * notice, this list of conditions and the following disclaimer. 1066458Sdfr * 2. Redistributions in binary form must reproduce the above copyright 1166458Sdfr * notice, this list of conditions and the following disclaimer in the 1266458Sdfr * documentation and/or other materials provided with the distribution. 1366458Sdfr * 1466458Sdfr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1566458Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1666458Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1766458Sdfr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1866458Sdfr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1966458Sdfr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2066458Sdfr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2166458Sdfr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2266458Sdfr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2366458Sdfr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2466458Sdfr * SUCH DAMAGE. 2566458Sdfr * 2666458Sdfr * $FreeBSD$ 2766458Sdfr */ 2866458Sdfr 2966458Sdfr#ifndef _MACHINE_FPU_H_ 3066458Sdfr#define _MACHINE_FPU_H_ 3166458Sdfr 3266458Sdfr/* 3366458Sdfr * Floating point status register bits. 3466458Sdfr */ 3566458Sdfr 3666458Sdfr#define IA64_FPSR_TRAP_VD 0x0000000000000001L 3766458Sdfr#define IA64_FPSR_TRAP_DD 0x0000000000000002L 3866458Sdfr#define IA64_FPSR_TRAP_ZD 0x0000000000000004L 3966458Sdfr#define IA64_FPSR_TRAP_OD 0x0000000000000008L 4066458Sdfr#define IA64_FPSR_TRAP_UD 0x0000000000000010L 4166458Sdfr#define IA64_FPSR_TRAP_ID 0x0000000000000020L 4266458Sdfr#define IA64_FPSR_SF(i,v) ((v) << ((i)*13+6)) 4366458Sdfr 4466458Sdfr#define IA64_SF_FTZ 0x0001L 4566458Sdfr#define IA64_SF_WRE 0x0002L 4666458Sdfr#define IA64_SF_PC 0x000cL 4766458Sdfr#define IA64_SF_PC_0 0x0000L 4866458Sdfr#define IA64_SF_PC_1 0x0004L 4966458Sdfr#define IA64_SF_PC_2 0x0008L 5066458Sdfr#define IA64_SF_PC_3 0x000cL 5166458Sdfr#define IA64_SF_RC 0x0030L 5266458Sdfr#define IA64_SF_RC_NEAREST 0x0000L 5366458Sdfr#define IA64_SF_RC_NEGINF 0x0010L 5466458Sdfr#define IA64_SF_RC_POSINF 0x0020L 5566458Sdfr#define IA64_SF_RC_TRUNC 0x0030L 5666458Sdfr#define IA64_SF_TD 0x0040L 5766458Sdfr#define IA64_SF_V 0x0080L 5866458Sdfr#define IA64_SF_D 0x0100L 5966458Sdfr#define IA64_SF_Z 0x0200L 6066458Sdfr#define IA64_SF_O 0x0400L 6166458Sdfr#define IA64_SF_U 0x0800L 6266458Sdfr#define IA64_SF_I 0x1000L 6366458Sdfr 6466458Sdfr#define IA64_SF_DEFAULT (IA64_SF_PC_3 | IA64_SF_RC_NEAREST) 6566458Sdfr 6666458Sdfr#define IA64_FPSR_DEFAULT (IA64_FPSR_TRAP_VD \ 6766458Sdfr | IA64_FPSR_TRAP_DD \ 6866458Sdfr | IA64_FPSR_TRAP_ZD \ 6966458Sdfr | IA64_FPSR_TRAP_OD \ 7066458Sdfr | IA64_FPSR_TRAP_UD \ 7166458Sdfr | IA64_FPSR_TRAP_ID \ 7266458Sdfr | IA64_FPSR_SF(0, IA64_SF_DEFAULT) \ 7366458Sdfr | IA64_FPSR_SF(1, (IA64_SF_DEFAULT \ 7466458Sdfr | IA64_SF_TD \ 7566458Sdfr | IA64_SF_WRE)) \ 7666458Sdfr | IA64_FPSR_SF(2, (IA64_SF_DEFAULT \ 7766458Sdfr | IA64_SF_TD)) \ 7866458Sdfr | IA64_FPSR_SF(3, (IA64_SF_DEFAULT \ 7966458Sdfr | IA64_SF_TD))) 8066458Sdfr 81135405Smarcelstruct fpswa_ret { 82138674Smarcel unsigned long status; 83138674Smarcel unsigned long err1; 84138674Smarcel unsigned long err2; 85138674Smarcel unsigned long err3; 86135405Smarcel}; 87135405Smarcel 88135405Smarcelstruct fpswa_bundle { 89135405Smarcel long double bits; /* Force 16-byte alignment. */ 90135405Smarcel}; 91135405Smarcel 92135405Smarcelstruct fpswa_fpctx { 93138674Smarcel unsigned long mask_low; /* f63 - f2 */ 94138674Smarcel unsigned long mask_high; /* f127 - f64 */ 95135405Smarcel union _ia64_fpreg *fp_low_preserved; /* f2 - f5 */ 96135405Smarcel union _ia64_fpreg *fp_low_volatile; /* f6 - f15 */ 97135405Smarcel union _ia64_fpreg *fp_high_preserved; /* f16 - f31 */ 98135405Smarcel union _ia64_fpreg *fp_high_volatile; /* f32 - f127 */ 99135405Smarcel}; 100135405Smarcel 101135405Smarcelstruct fpswa_iface { 102138674Smarcel unsigned int if_rev; 103138674Smarcel unsigned int __res; 104138674Smarcel struct fpswa_ret (*if_fpswa)(unsigned long, struct fpswa_bundle *, 105138674Smarcel unsigned long *, unsigned long *, unsigned long *, unsigned long *, 106138674Smarcel unsigned long *, struct fpswa_fpctx *); 107135405Smarcel}; 108135405Smarcel 10966458Sdfr#endif /* ! _MACHINE_FPU_H_ */ 110