bus.h revision 108728
1/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */ 2 3/*- 4 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/* 41 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 42 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Christopher G. Demetriou 55 * for the NetBSD Project. 56 * 4. The name of the author may not be used to endorse or promote products 57 * derived from this software without specific prior written permission 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 */ 70/* $FreeBSD: head/sys/ia64/include/bus.h 108728 2003-01-05 21:34:05Z marcel $ */ 71 72#ifndef _MACHINE_BUS_H_ 73#define _MACHINE_BUS_H_ 74 75#include <machine/cpufunc.h> 76 77/* 78 * To remain compatible with NetBSD's interface, default to both memio and 79 * pio when neither of them is defined. 80 */ 81#if !defined(_MACHINE_BUS_PIO_H_) && !defined(_IA64_BUS_MEMIO_H_) 82#define _MACHINE_BUS_PIO_H_ 83#define _MACHINE_BUS_MEMIO_H_ 84#endif 85 86/* 87 * Values for the ia64 bus space tag, not to be used directly by MI code. 88 */ 89#define IA64_BUS_SPACE_IO 0 /* space is i/o space */ 90#define IA64_BUS_SPACE_MEM 1 /* space is mem space */ 91 92/* 93 * Bus address and size types 94 */ 95typedef u_long bus_addr_t; 96typedef u_long bus_size_t; 97 98#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF 99#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF 100#define BUS_SPACE_MAXSIZE (64 * 1024) /* Maximum supported size */ 101#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF 102#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF 103#define BUS_SPACE_MAXADDR 0xFFFFFFFF 104 105#define BUS_SPACE_UNRESTRICTED (~0) 106 107/* 108 * Access methods for bus resources and address space. 109 */ 110typedef int bus_space_tag_t; 111typedef u_long bus_space_handle_t; 112 113/* 114 * Map a region of device bus space into CPU virtual address space. 115 */ 116 117#define BUS_SPACE_MAP_CACHEABLE 0x01 118#define BUS_SPACE_MAP_LINEAR 0x02 119 120int bus_space_map(bus_space_tag_t t, bus_addr_t addr, bus_size_t size, 121 int flags, bus_space_handle_t *bshp); 122 123/* 124 * Unmap a region of device bus space. 125 */ 126 127static __inline void 128bus_space_unmap(bus_space_tag_t t __unused, bus_space_handle_t bsh __unused, 129 bus_size_t size __unused) 130{ 131} 132 133/* 134 * Get a new handle for a subregion of an already-mapped area of bus space. 135 */ 136 137static __inline int 138bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh, 139 bus_size_t offset, bus_size_t size, 140 bus_space_handle_t *nbshp) 141{ 142 *nbshp = bsh + offset; 143 return (0); 144} 145 146/* 147 * Allocate a region of memory that is accessible to devices in bus space. 148 */ 149 150int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, 151 bus_addr_t rend, bus_size_t size, bus_size_t align, 152 bus_size_t boundary, int flags, bus_addr_t *addrp, 153 bus_space_handle_t *bshp); 154 155/* 156 * Free a region of bus space accessible memory. 157 */ 158 159void bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, 160 bus_size_t size); 161 162#if defined(_MACHINE_BUS_PIO_H_) || defined(_MACHINE_BUS_MEMIO_H_) 163 164/* 165 * Read a 1, 2, 4, or 8 byte quantity from bus space 166 * described by tag/handle/offset. 167 */ 168static __inline u_int8_t bus_space_read_1(bus_space_tag_t tag, 169 bus_space_handle_t handle, 170 bus_size_t offset); 171 172static __inline u_int16_t bus_space_read_2(bus_space_tag_t tag, 173 bus_space_handle_t handle, 174 bus_size_t offset); 175 176static __inline u_int32_t bus_space_read_4(bus_space_tag_t tag, 177 bus_space_handle_t handle, 178 bus_size_t offset); 179 180static __inline u_int8_t 181bus_space_read_1(bus_space_tag_t tag, bus_space_handle_t handle, 182 bus_size_t offset) 183{ 184#if defined (_MACHINE_BUS_PIO_H_) 185#if defined (_MACHINE_BUS_MEMIO_H_) 186 if (tag == IA64_BUS_SPACE_IO) 187#endif 188 return (inb(handle + offset)); 189#endif 190#if defined (_MACHINE_BUS_MEMIO_H_) 191 return (readb(handle + offset)); 192#endif 193} 194 195static __inline u_int16_t 196bus_space_read_2(bus_space_tag_t tag, bus_space_handle_t handle, 197 bus_size_t offset) 198{ 199#if defined(_MACHINE_BUS_PIO_H_) 200#if defined(_MACHINE_BUS_MEMIO_H_) 201 if (tag == IA64_BUS_SPACE_IO) 202#endif 203 return (inw(handle + offset)); 204#endif 205#if defined(_MACHINE_BUS_MEMIO_H_) 206 return (readw(handle + offset)); 207#endif 208} 209 210static __inline u_int32_t 211bus_space_read_4(bus_space_tag_t tag, bus_space_handle_t handle, 212 bus_size_t offset) 213{ 214#if defined(_MACHINE_BUS_PIO_H_) 215#if defined(_MACHINE_BUS_MEMIO_H_) 216 if (tag == IA64_BUS_SPACE_IO) 217#endif 218 return (inl(handle + offset)); 219#endif 220#if defined(_MACHINE_BUS_MEMIO_H_) 221 return (readl(handle + offset)); 222#endif 223} 224 225#if 0 /* Cause a link error for bus_space_read_8 */ 226#define bus_space_read_8(t, h, o) !!! bus_space_read_8 unimplemented !!! 227#endif 228 229/* 230 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 231 * described by tag/handle/offset and copy into buffer provided. 232 */ 233static __inline void bus_space_read_multi_1(bus_space_tag_t tag, 234 bus_space_handle_t bsh, 235 bus_size_t offset, u_int8_t *addr, 236 size_t count); 237 238static __inline void bus_space_read_multi_2(bus_space_tag_t tag, 239 bus_space_handle_t bsh, 240 bus_size_t offset, u_int16_t *addr, 241 size_t count); 242 243static __inline void bus_space_read_multi_4(bus_space_tag_t tag, 244 bus_space_handle_t bsh, 245 bus_size_t offset, u_int32_t *addr, 246 size_t count); 247 248static __inline void 249bus_space_read_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, 250 bus_size_t offset, u_int8_t *addr, size_t count) 251{ 252#if defined(_MACHINE_BUS_PIO_H_) 253#if defined(_MACHINE_BUS_MEMIO_H_) 254 if (tag == IA64_BUS_SPACE_IO) 255#endif 256 while (count--) 257 *addr++ = inb(bsh + offset); 258#endif 259#if defined(_MACHINE_BUS_MEMIO_H_) 260#if defined(_MACHINE_BUS_PIO_H_) 261 else 262#endif 263 while (count--) 264 *addr++ = readb(bsh + offset); 265#endif 266} 267 268static __inline void 269bus_space_read_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, 270 bus_size_t offset, u_int16_t *addr, size_t count) 271{ 272 bus_addr_t baddr = bsh + offset; 273#if defined(_MACHINE_BUS_PIO_H_) 274#if defined(_MACHINE_BUS_MEMIO_H_) 275 if (tag == IA64_BUS_SPACE_IO) 276#endif 277 while (count--) 278 *addr++ = inw(baddr); 279#endif 280#if defined(_MACHINE_BUS_MEMIO_H_) 281#if defined(_MACHINE_BUS_PIO_H_) 282 else 283#endif 284 while (count--) 285 *addr++ = readw(baddr); 286#endif 287} 288 289static __inline void 290bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, 291 bus_size_t offset, u_int32_t *addr, size_t count) 292{ 293 bus_addr_t baddr = bsh + offset; 294#if defined(_MACHINE_BUS_PIO_H_) 295#if defined(_MACHINE_BUS_MEMIO_H_) 296 if (tag == IA64_BUS_SPACE_IO) 297#endif 298 while (count--) 299 *addr++ = inl(baddr); 300#endif 301#if defined(_MACHINE_BUS_MEMIO_H_) 302#if defined(_MACHINE_BUS_PIO_H_) 303 else 304#endif 305 while (count--) 306 *addr++ = readl(baddr); 307#endif 308} 309 310#if 0 /* Cause a link error for bus_space_read_multi_8 */ 311#define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!! 312#endif 313 314/* 315 * Read `count' 1, 2, 4, or 8 byte quantities from bus space 316 * described by tag/handle and starting at `offset' and copy into 317 * buffer provided. 318 */ 319static __inline void bus_space_read_region_1(bus_space_tag_t tag, 320 bus_space_handle_t bsh, 321 bus_size_t offset, u_int8_t *addr, 322 size_t count); 323 324static __inline void bus_space_read_region_2(bus_space_tag_t tag, 325 bus_space_handle_t bsh, 326 bus_size_t offset, u_int16_t *addr, 327 size_t count); 328 329static __inline void bus_space_read_region_4(bus_space_tag_t tag, 330 bus_space_handle_t bsh, 331 bus_size_t offset, u_int32_t *addr, 332 size_t count); 333 334 335static __inline void 336bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, 337 bus_size_t offset, u_int8_t *addr, size_t count) 338{ 339 bus_addr_t baddr = bsh + offset; 340#if defined(_MACHINE_BUS_PIO_H_) 341#if defined(_MACHINE_BUS_MEMIO_H_) 342 if (tag == IA64_BUS_SPACE_IO) 343#endif 344 while (count--) { 345 *addr++ = inb(baddr); 346 baddr += 1; 347 } 348#endif 349#if defined(_MACHINE_BUS_MEMIO_H_) 350#if defined(_MACHINE_BUS_PIO_H_) 351 else 352#endif 353 while (count--) { 354 *addr++ = readb(baddr); 355 baddr += 1; 356 } 357#endif 358} 359 360static __inline void 361bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, 362 bus_size_t offset, u_int16_t *addr, size_t count) 363{ 364 bus_addr_t baddr = bsh + offset; 365#if defined(_MACHINE_BUS_PIO_H_) 366#if defined(_MACHINE_BUS_MEMIO_H_) 367 if (tag == IA64_BUS_SPACE_IO) 368#endif 369 while (count--) { 370 *addr++ = inw(baddr); 371 baddr += 2; 372 } 373#endif 374#if defined(_MACHINE_BUS_MEMIO_H_) 375#if defined(_MACHINE_BUS_PIO_H_) 376 else 377#endif 378 while (count--) { 379 *addr++ = readw(baddr); 380 baddr += 2; 381 } 382#endif 383} 384 385static __inline void 386bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, 387 bus_size_t offset, u_int32_t *addr, size_t count) 388{ 389 bus_addr_t baddr = bsh + offset; 390#if defined(_MACHINE_BUS_PIO_H_) 391#if defined(_MACHINE_BUS_MEMIO_H_) 392 if (tag == IA64_BUS_SPACE_IO) 393#endif 394 while (count--) { 395 *addr++ = inl(baddr); 396 baddr += 4; 397 } 398#endif 399#if defined(_MACHINE_BUS_MEMIO_H_) 400#if defined(_MACHINE_BUS_PIO_H_) 401 else 402#endif 403 while (count--) { 404 *addr++ = readb(baddr); 405 baddr += 4; 406 } 407#endif 408} 409 410#if 0 /* Cause a link error for bus_space_read_region_8 */ 411#define bus_space_read_region_8 !!! bus_space_read_region_8 unimplemented !!! 412#endif 413 414/* 415 * Write the 1, 2, 4, or 8 byte value `value' to bus space 416 * described by tag/handle/offset. 417 */ 418 419static __inline void bus_space_write_1(bus_space_tag_t tag, 420 bus_space_handle_t bsh, 421 bus_size_t offset, u_int8_t value); 422 423static __inline void bus_space_write_2(bus_space_tag_t tag, 424 bus_space_handle_t bsh, 425 bus_size_t offset, u_int16_t value); 426 427static __inline void bus_space_write_4(bus_space_tag_t tag, 428 bus_space_handle_t bsh, 429 bus_size_t offset, u_int32_t value); 430 431static __inline void 432bus_space_write_1(bus_space_tag_t tag, bus_space_handle_t bsh, 433 bus_size_t offset, u_int8_t value) 434{ 435#if defined(_MACHINE_BUS_PIO_H_) 436#if defined(_MACHINE_BUS_MEMIO_H_) 437 if (tag == IA64_BUS_SPACE_IO) 438#endif 439 outb(bsh + offset, value); 440#endif 441#if defined(_MACHINE_BUS_MEMIO_H_) 442#if defined(_MACHINE_BUS_PIO_H_) 443 else 444#endif 445 writeb(bsh + offset, value); 446#endif 447} 448 449static __inline void 450bus_space_write_2(bus_space_tag_t tag, bus_space_handle_t bsh, 451 bus_size_t offset, u_int16_t value) 452{ 453#if defined(_MACHINE_BUS_PIO_H_) 454#if defined(_MACHINE_BUS_MEMIO_H_) 455 if (tag == IA64_BUS_SPACE_IO) 456#endif 457 outw(bsh + offset, value); 458#endif 459#if defined(_MACHINE_BUS_MEMIO_H_) 460#if defined(_MACHINE_BUS_PIO_H_) 461 else 462#endif 463 writew(bsh + offset, value); 464#endif 465} 466 467static __inline void 468bus_space_write_4(bus_space_tag_t tag, bus_space_handle_t bsh, 469 bus_size_t offset, u_int32_t value) 470{ 471#if defined(_MACHINE_BUS_PIO_H_) 472#if defined(_MACHINE_BUS_MEMIO_H_) 473 if (tag == IA64_BUS_SPACE_IO) 474#endif 475 outl(bsh + offset, value); 476#endif 477#if defined(_MACHINE_BUS_MEMIO_H_) 478#if defined(_MACHINE_BUS_PIO_H_) 479 else 480#endif 481 writel(bsh + offset, value); 482#endif 483} 484 485#if 0 /* Cause a link error for bus_space_write_8 */ 486#define bus_space_write_8 !!! bus_space_write_8 not implemented !!! 487#endif 488 489/* 490 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer 491 * provided to bus space described by tag/handle/offset. 492 */ 493 494static __inline void bus_space_write_multi_1(bus_space_tag_t tag, 495 bus_space_handle_t bsh, 496 bus_size_t offset, 497 const u_int8_t *addr, 498 size_t count); 499static __inline void bus_space_write_multi_2(bus_space_tag_t tag, 500 bus_space_handle_t bsh, 501 bus_size_t offset, 502 const u_int16_t *addr, 503 size_t count); 504 505static __inline void bus_space_write_multi_4(bus_space_tag_t tag, 506 bus_space_handle_t bsh, 507 bus_size_t offset, 508 const u_int32_t *addr, 509 size_t count); 510 511static __inline void 512bus_space_write_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, 513 bus_size_t offset, const u_int8_t *addr, size_t count) 514{ 515 bus_addr_t baddr = bsh + offset; 516#if defined(_MACHINE_BUS_PIO_H_) 517#if defined(_MACHINE_BUS_MEMIO_H_) 518 if (tag == IA64_BUS_SPACE_IO) 519#endif 520 while (count--) 521 outb(baddr, *addr++); 522#endif 523#if defined(_MACHINE_BUS_MEMIO_H_) 524#if defined(_MACHINE_BUS_PIO_H_) 525 else 526#endif 527 while (count--) 528 writeb(baddr, *addr++); 529#endif 530} 531 532static __inline void 533bus_space_write_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, 534 bus_size_t offset, const u_int16_t *addr, size_t count) 535{ 536 bus_addr_t baddr = bsh + offset; 537#if defined(_MACHINE_BUS_PIO_H_) 538#if defined(_MACHINE_BUS_MEMIO_H_) 539 if (tag == IA64_BUS_SPACE_IO) 540#endif 541 while (count--) 542 outw(baddr, *addr++); 543#endif 544#if defined(_MACHINE_BUS_MEMIO_H_) 545#if defined(_MACHINE_BUS_PIO_H_) 546 else 547#endif 548 while (count--) 549 writew(baddr, *addr++); 550#endif 551} 552 553static __inline void 554bus_space_write_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, 555 bus_size_t offset, const u_int32_t *addr, size_t count) 556{ 557 bus_addr_t baddr = bsh + offset; 558#if defined(_MACHINE_BUS_PIO_H_) 559#if defined(_MACHINE_BUS_MEMIO_H_) 560 if (tag == IA64_BUS_SPACE_IO) 561#endif 562 while (count--) 563 outl(baddr, *addr++); 564#endif 565#if defined(_MACHINE_BUS_MEMIO_H_) 566#if defined(_MACHINE_BUS_PIO_H_) 567 else 568#endif 569 while (count--) 570 writel(baddr, *addr++); 571#endif 572} 573 574#if 0 /* Cause a link error for bus_space_write_multi_8 */ 575#define bus_space_write_multi_8(t, h, o, a, c) \ 576 !!! bus_space_write_multi_8 unimplemented !!! 577#endif 578 579/* 580 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided 581 * to bus space described by tag/handle starting at `offset'. 582 */ 583 584static __inline void bus_space_write_region_1(bus_space_tag_t tag, 585 bus_space_handle_t bsh, 586 bus_size_t offset, 587 const u_int8_t *addr, 588 size_t count); 589static __inline void bus_space_write_region_2(bus_space_tag_t tag, 590 bus_space_handle_t bsh, 591 bus_size_t offset, 592 const u_int16_t *addr, 593 size_t count); 594static __inline void bus_space_write_region_4(bus_space_tag_t tag, 595 bus_space_handle_t bsh, 596 bus_size_t offset, 597 const u_int32_t *addr, 598 size_t count); 599 600static __inline void 601bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, 602 bus_size_t offset, const u_int8_t *addr, size_t count) 603{ 604 bus_addr_t baddr = bsh + offset; 605#if defined(_MACHINE_BUS_PIO_H_) 606#if defined(_MACHINE_BUS_MEMIO_H_) 607 if (tag == IA64_BUS_SPACE_IO) 608#endif 609 while (count--) { 610 outb(baddr, *addr++); 611 baddr += 1; 612 } 613#endif 614#if defined(_MACHINE_BUS_MEMIO_H_) 615#if defined(_MACHINE_BUS_PIO_H_) 616 else 617#endif 618 while (count--) { 619 writeb(baddr, *addr++); 620 baddr += 1; 621 } 622#endif 623} 624 625static __inline void 626bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, 627 bus_size_t offset, const u_int16_t *addr, size_t count) 628{ 629 bus_addr_t baddr = bsh + offset; 630#if defined(_MACHINE_BUS_PIO_H_) 631#if defined(_MACHINE_BUS_MEMIO_H_) 632 if (tag == IA64_BUS_SPACE_IO) 633#endif 634 while (count--) { 635 outw(baddr, *addr++); 636 baddr += 2; 637 } 638#endif 639#if defined(_MACHINE_BUS_MEMIO_H_) 640#if defined(_MACHINE_BUS_PIO_H_) 641 else 642#endif 643 while (count--) { 644 writew(baddr, *addr++); 645 baddr += 2; 646 } 647#endif 648} 649 650static __inline void 651bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, 652 bus_size_t offset, const u_int32_t *addr, size_t count) 653{ 654 bus_addr_t baddr = bsh + offset; 655#if defined(_MACHINE_BUS_PIO_H_) 656#if defined(_MACHINE_BUS_MEMIO_H_) 657 if (tag == IA64_BUS_SPACE_IO) 658#endif 659 while (count--) { 660 outl(baddr, *addr++); 661 baddr += 4; 662 } 663#endif 664#if defined(_MACHINE_BUS_MEMIO_H_) 665#if defined(_MACHINE_BUS_PIO_H_) 666 else 667#endif 668 while (count--) { 669 writel(baddr, *addr++); 670 baddr += 4; 671 } 672#endif 673} 674 675#if 0 /* Cause a link error for bus_space_write_region_8 */ 676#define bus_space_write_region_8 \ 677 !!! bus_space_write_region_8 unimplemented !!! 678#endif 679 680/* 681 * Write the 1, 2, 4, or 8 byte value `val' to bus space described 682 * by tag/handle/offset `count' times. 683 */ 684 685static __inline void bus_space_set_multi_1(bus_space_tag_t tag, 686 bus_space_handle_t bsh, 687 bus_size_t offset, 688 u_int8_t value, size_t count); 689static __inline void bus_space_set_multi_2(bus_space_tag_t tag, 690 bus_space_handle_t bsh, 691 bus_size_t offset, 692 u_int16_t value, size_t count); 693static __inline void bus_space_set_multi_4(bus_space_tag_t tag, 694 bus_space_handle_t bsh, 695 bus_size_t offset, 696 u_int32_t value, size_t count); 697 698static __inline void 699bus_space_set_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, 700 bus_size_t offset, u_int8_t value, size_t count) 701{ 702 bus_addr_t addr = bsh + offset; 703 704#if defined(_MACHINE_BUS_PIO_H_) 705#if defined(_MACHINE_BUS_MEMIO_H_) 706 if (tag == IA64_BUS_SPACE_IO) 707#endif 708 while (count--) 709 outb(addr, value); 710#endif 711#if defined(_MACHINE_BUS_MEMIO_H_) 712#if defined(_MACHINE_BUS_PIO_H_) 713 else 714#endif 715 while (count--) 716 writeb(addr, value); 717#endif 718} 719 720static __inline void 721bus_space_set_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, 722 bus_size_t offset, u_int16_t value, size_t count) 723{ 724 bus_addr_t addr = bsh + offset; 725 726#if defined(_MACHINE_BUS_PIO_H_) 727#if defined(_MACHINE_BUS_MEMIO_H_) 728 if (tag == IA64_BUS_SPACE_IO) 729#endif 730 while (count--) 731 outw(addr, value); 732#endif 733#if defined(_MACHINE_BUS_MEMIO_H_) 734#if defined(_MACHINE_BUS_PIO_H_) 735 else 736#endif 737 while (count--) 738 writew(addr, value); 739#endif 740} 741 742static __inline void 743bus_space_set_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, 744 bus_size_t offset, u_int32_t value, size_t count) 745{ 746 bus_addr_t addr = bsh + offset; 747 748#if defined(_MACHINE_BUS_PIO_H_) 749#if defined(_MACHINE_BUS_MEMIO_H_) 750 if (tag == IA64_BUS_SPACE_IO) 751#endif 752 while (count--) 753 outl(addr, value); 754#endif 755#if defined(_MACHINE_BUS_MEMIO_H_) 756#if defined(_MACHINE_BUS_PIO_H_) 757 else 758#endif 759 while (count--) 760 writel(addr, value); 761#endif 762} 763 764#if 0 /* Cause a link error for bus_space_set_multi_8 */ 765#define bus_space_set_multi_8 !!! bus_space_set_multi_8 unimplemented !!! 766#endif 767 768/* 769 * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described 770 * by tag/handle starting at `offset'. 771 */ 772 773static __inline void bus_space_set_region_1(bus_space_tag_t tag, 774 bus_space_handle_t bsh, 775 bus_size_t offset, u_int8_t value, 776 size_t count); 777static __inline void bus_space_set_region_2(bus_space_tag_t tag, 778 bus_space_handle_t bsh, 779 bus_size_t offset, u_int16_t value, 780 size_t count); 781static __inline void bus_space_set_region_4(bus_space_tag_t tag, 782 bus_space_handle_t bsh, 783 bus_size_t offset, u_int32_t value, 784 size_t count); 785 786static __inline void 787bus_space_set_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, 788 bus_size_t offset, u_int8_t value, size_t count) 789{ 790 bus_addr_t addr = bsh + offset; 791 792#if defined(_MACHINE_BUS_PIO_H_) 793#if defined(_MACHINE_BUS_MEMIO_H_) 794 if (tag == IA64_BUS_SPACE_IO) 795#endif 796 for (; count != 0; count--, addr++) 797 outb(addr, value); 798#endif 799#if defined(_MACHINE_BUS_MEMIO_H_) 800#if defined(_MACHINE_BUS_PIO_H_) 801 else 802#endif 803 for (; count != 0; count--, addr++) 804 writeb(addr, value); 805#endif 806} 807 808static __inline void 809bus_space_set_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, 810 bus_size_t offset, u_int16_t value, size_t count) 811{ 812 bus_addr_t addr = bsh + offset; 813 814#if defined(_MACHINE_BUS_PIO_H_) 815#if defined(_MACHINE_BUS_MEMIO_H_) 816 if (tag == IA64_BUS_SPACE_IO) 817#endif 818 for (; count != 0; count--, addr += 2) 819 outw(addr, value); 820#endif 821#if defined(_MACHINE_BUS_MEMIO_H_) 822#if defined(_MACHINE_BUS_PIO_H_) 823 else 824#endif 825 for (; count != 0; count--, addr += 2) 826 writew(addr, value); 827#endif 828} 829 830static __inline void 831bus_space_set_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, 832 bus_size_t offset, u_int32_t value, size_t count) 833{ 834 bus_addr_t addr = bsh + offset; 835 836#if defined(_MACHINE_BUS_PIO_H_) 837#if defined(_MACHINE_BUS_MEMIO_H_) 838 if (tag == IA64_BUS_SPACE_IO) 839#endif 840 for (; count != 0; count--, addr += 4) 841 outl(addr, value); 842#endif 843#if defined(_MACHINE_BUS_MEMIO_H_) 844#if defined(_MACHINE_BUS_PIO_H_) 845 else 846#endif 847 for (; count != 0; count--, addr += 4) 848 writel(addr, value); 849#endif 850} 851 852#if 0 /* Cause a link error for bus_space_set_region_8 */ 853#define bus_space_set_region_8 !!! bus_space_set_region_8 unimplemented !!! 854#endif 855 856/* 857 * Copy `count' 1, 2, 4, or 8 byte values from bus space starting 858 * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. 859 */ 860 861static __inline void bus_space_copy_region_1(bus_space_tag_t tag, 862 bus_space_handle_t bsh1, 863 bus_size_t off1, 864 bus_space_handle_t bsh2, 865 bus_size_t off2, size_t count); 866 867static __inline void bus_space_copy_region_2(bus_space_tag_t tag, 868 bus_space_handle_t bsh1, 869 bus_size_t off1, 870 bus_space_handle_t bsh2, 871 bus_size_t off2, size_t count); 872 873static __inline void bus_space_copy_region_4(bus_space_tag_t tag, 874 bus_space_handle_t bsh1, 875 bus_size_t off1, 876 bus_space_handle_t bsh2, 877 bus_size_t off2, size_t count); 878 879static __inline void 880bus_space_copy_region_1(bus_space_tag_t tag, bus_space_handle_t bsh1, 881 bus_size_t off1, bus_space_handle_t bsh2, 882 bus_size_t off2, size_t count) 883{ 884 bus_addr_t addr1 = bsh1 + off1; 885 bus_addr_t addr2 = bsh2 + off2; 886 887#if defined(_MACHINE_BUS_PIO_H_) 888#if defined(_MACHINE_BUS_MEMIO_H_) 889 if (tag == IA64_BUS_SPACE_IO) 890#endif 891 { 892 if (addr1 >= addr2) { 893 /* src after dest: copy forward */ 894 for (; count != 0; count--, addr1++, addr2++) 895 outb(addr2, inb(addr1)); 896 } else { 897 /* dest after src: copy backwards */ 898 for (addr1 += (count - 1), addr2 += (count - 1); 899 count != 0; count--, addr1--, addr2--) 900 outb(addr2, inb(addr1)); 901 } 902 } 903#endif 904#if defined(_MACHINE_BUS_MEMIO_H_) 905#if defined(_MACHINE_BUS_PIO_H_) 906 else 907#endif 908 { 909 if (addr1 >= addr2) { 910 /* src after dest: copy forward */ 911 for (; count != 0; count--, addr1++, addr2++) 912 writeb(addr2, readb(addr1)); 913 } else { 914 /* dest after src: copy backwards */ 915 for (addr1 += (count - 1), addr2 += (count - 1); 916 count != 0; count--, addr1--, addr2--) 917 writeb(addr2, readb(addr1)); 918 } 919 } 920#endif 921} 922 923static __inline void 924bus_space_copy_region_2(bus_space_tag_t tag, bus_space_handle_t bsh1, 925 bus_size_t off1, bus_space_handle_t bsh2, 926 bus_size_t off2, size_t count) 927{ 928 bus_addr_t addr1 = bsh1 + off1; 929 bus_addr_t addr2 = bsh2 + off2; 930 931#if defined(_MACHINE_BUS_PIO_H_) 932#if defined(_MACHINE_BUS_MEMIO_H_) 933 if (tag == IA64_BUS_SPACE_IO) 934#endif 935 { 936 if (addr1 >= addr2) { 937 /* src after dest: copy forward */ 938 for (; count != 0; count--, addr1 += 2, addr2 += 2) 939 outw(addr2, inw(addr1)); 940 } else { 941 /* dest after src: copy backwards */ 942 for (addr1 += 2 * (count - 1), addr2 += 2 * (count - 1); 943 count != 0; count--, addr1 -= 2, addr2 -= 2) 944 outw(addr2, inw(addr1)); 945 } 946 } 947#endif 948#if defined(_MACHINE_BUS_MEMIO_H_) 949#if defined(_MACHINE_BUS_PIO_H_) 950 else 951#endif 952 { 953 if (addr1 >= addr2) { 954 /* src after dest: copy forward */ 955 for (; count != 0; count--, addr1 += 2, addr2 += 2) 956 writew(addr2, readw(addr1)); 957 } else { 958 /* dest after src: copy backwards */ 959 for (addr1 += 2 * (count - 1), addr2 += 2 * (count - 1); 960 count != 0; count--, addr1 -= 2, addr2 -= 2) 961 writew(addr2, readw(addr1)); 962 } 963 } 964#endif 965} 966 967static __inline void 968bus_space_copy_region_4(bus_space_tag_t tag, bus_space_handle_t bsh1, 969 bus_size_t off1, bus_space_handle_t bsh2, 970 bus_size_t off2, size_t count) 971{ 972 bus_addr_t addr1 = bsh1 + off1; 973 bus_addr_t addr2 = bsh2 + off2; 974 975#if defined(_MACHINE_BUS_PIO_H_) 976#if defined(_MACHINE_BUS_MEMIO_H_) 977 if (tag == IA64_BUS_SPACE_IO) 978#endif 979 { 980 if (addr1 >= addr2) { 981 /* src after dest: copy forward */ 982 for (; count != 0; count--, addr1 += 4, addr2 += 4) 983 outl(addr2, inl(addr1)); 984 } else { 985 /* dest after src: copy backwards */ 986 for (addr1 += 4 * (count - 1), addr2 += 4 * (count - 1); 987 count != 0; count--, addr1 -= 4, addr2 -= 4) 988 outl(addr2, inl(addr1)); 989 } 990 } 991#endif 992#if defined(_MACHINE_BUS_MEMIO_H_) 993#if defined(_MACHINE_BUS_PIO_H_) 994 else 995#endif 996 { 997 if (addr1 >= addr2) { 998 /* src after dest: copy forward */ 999 for (; count != 0; count--, addr1 += 4, addr2 += 4) 1000 writel(addr2, readl(addr1)); 1001 } else { 1002 /* dest after src: copy backwards */ 1003 for (addr1 += 4 * (count - 1), addr2 += 4 * (count - 1); 1004 count != 0; count--, addr1 -= 4, addr2 -= 4) 1005 writel(addr2, readl(addr1)); 1006 } 1007 } 1008#endif 1009} 1010 1011/* 1012 * Stream accesses are the same as normal accesses on ia64; there are no 1013 * supported bus systems with an endianess different from the host one. 1014 */ 1015#define bus_space_read_stream_1(t, h, o) bus_space_read_1((t), (h), (o)) 1016#define bus_space_read_stream_2(t, h, o) bus_space_read_2((t), (h), (o)) 1017#define bus_space_read_stream_4(t, h, o) bus_space_read_4((t), (h), (o)) 1018 1019#define bus_space_read_multi_stream_1(t, h, o, a, c) \ 1020 bus_space_read_multi_1((t), (h), (o), (a), (c)) 1021#define bus_space_read_multi_stream_2(t, h, o, a, c) \ 1022 bus_space_read_multi_2((t), (h), (o), (a), (c)) 1023#define bus_space_read_multi_stream_4(t, h, o, a, c) \ 1024 bus_space_read_multi_4((t), (h), (o), (a), (c)) 1025 1026#define bus_space_write_stream_1(t, h, o, v) \ 1027 bus_space_write_1((t), (h), (o), (v)) 1028#define bus_space_write_stream_2(t, h, o, v) \ 1029 bus_space_write_2((t), (h), (o), (v)) 1030#define bus_space_write_stream_4(t, h, o, v) \ 1031 bus_space_write_4((t), (h), (o), (v)) 1032 1033#define bus_space_write_multi_stream_1(t, h, o, a, c) \ 1034 bus_space_write_multi_1((t), (h), (o), (a), (c)) 1035#define bus_space_write_multi_stream_2(t, h, o, a, c) \ 1036 bus_space_write_multi_2((t), (h), (o), (a), (c)) 1037#define bus_space_write_multi_stream_4(t, h, o, a, c) \ 1038 bus_space_write_multi_4((t), (h), (o), (a), (c)) 1039 1040#define bus_space_set_multi_stream_1(t, h, o, v, c) \ 1041 bus_space_set_multi_1((t), (h), (o), (v), (c)) 1042#define bus_space_set_multi_stream_2(t, h, o, v, c) \ 1043 bus_space_set_multi_2((t), (h), (o), (v), (c)) 1044#define bus_space_set_multi_stream_4(t, h, o, v, c) \ 1045 bus_space_set_multi_4((t), (h), (o), (v), (c)) 1046 1047#define bus_space_read_region_stream_1(t, h, o, a, c) \ 1048 bus_space_read_region_1((t), (h), (o), (a), (c)) 1049#define bus_space_read_region_stream_2(t, h, o, a, c) \ 1050 bus_space_read_region_2((t), (h), (o), (a), (c)) 1051#define bus_space_read_region_stream_4(t, h, o, a, c) \ 1052 bus_space_read_region_4((t), (h), (o), (a), (c)) 1053 1054#define bus_space_write_region_stream_1(t, h, o, a, c) \ 1055 bus_space_write_region_1((t), (h), (o), (a), (c)) 1056#define bus_space_write_region_stream_2(t, h, o, a, c) \ 1057 bus_space_write_region_2((t), (h), (o), (a), (c)) 1058#define bus_space_write_region_stream_4(t, h, o, a, c) \ 1059 bus_space_write_region_4((t), (h), (o), (a), (c)) 1060 1061#define bus_space_set_region_stream_1(t, h, o, v, c) \ 1062 bus_space_set_region_1((t), (h), (o), (v), (c)) 1063#define bus_space_set_region_stream_2(t, h, o, v, c) \ 1064 bus_space_set_region_2((t), (h), (o), (v), (c)) 1065#define bus_space_set_region_stream_4(t, h, o, v, c) \ 1066 bus_space_set_region_4((t), (h), (o), (v), (c)) 1067 1068#define bus_space_copy_region_stream_1(t, h1, o1, h2, o2, c) \ 1069 bus_space_copy_region_1((t), (h1), (o1), (h2), (o2), (c)) 1070#define bus_space_copy_region_stream_2(t, h1, o1, h2, o2, c) \ 1071 bus_space_copy_region_2((t), (h1), (o1), (h2), (o2), (c)) 1072#define bus_space_copy_region_stream_4(t, h1, o1, h2, o2, c) \ 1073 bus_space_copy_region_4((t), (h1), (o1), (h2), (o2), (c)) 1074 1075#endif /* defined(_MACHINE_BUS_PIO_H_) || defined(_MACHINE_BUS_MEMIO_H_) */ 1076 1077#if 0 /* Cause a link error for bus_space_copy_8 */ 1078#define bus_space_copy_region_8 !!! bus_space_copy_region_8 unimplemented !!! 1079#endif 1080 1081/* 1082 * Bus read/write barrier methods. 1083 * 1084 * void bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, 1085 * bus_size_t offset, bus_size_t len, int flags); 1086 * 1087 */ 1088#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 1089#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 1090 1091static __inline void 1092bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, 1093 bus_size_t offset, bus_size_t len, int flags) 1094{ 1095 ia64_mf(); 1096} 1097 1098/* 1099 * Flags used in various bus DMA methods. 1100 */ 1101#define BUS_DMA_WAITOK 0x00 /* safe to sleep (pseudo-flag) */ 1102#define BUS_DMA_NOWAIT 0x01 /* not safe to sleep */ 1103#define BUS_DMA_ALLOCNOW 0x02 /* perform resource allocation now */ 1104#define BUS_DMAMEM_NOSYNC 0x04 /* map memory to not require sync */ 1105#define BUS_DMA_ISA 0x10 /* map memory for ISA dma */ 1106#define BUS_DMA_BUS2 0x20 /* placeholders for bus functions... */ 1107#define BUS_DMA_BUS3 0x40 1108#define BUS_DMA_BUS4 0x80 1109 1110/* Forwards needed by prototypes below. */ 1111struct mbuf; 1112struct uio; 1113 1114/* 1115 * bus_dmasync_op_t 1116 * 1117 * Operations performed by bus_dmamap_sync(). 1118 */ 1119typedef enum { 1120 BUS_DMASYNC_PREREAD, 1121 BUS_DMASYNC_POSTREAD, 1122 BUS_DMASYNC_PREWRITE, 1123 BUS_DMASYNC_POSTWRITE 1124} bus_dmasync_op_t; 1125 1126/* 1127 * bus_dma_tag_t 1128 * 1129 * A machine-dependent opaque type describing the characteristics 1130 * of how to perform DMA mappings. This structure encapsultes 1131 * information concerning address and alignment restrictions, number 1132 * of S/G segments, amount of data per S/G segment, etc. 1133 */ 1134typedef struct bus_dma_tag *bus_dma_tag_t; 1135 1136/* 1137 * bus_dmamap_t 1138 * 1139 * DMA mapping instance information. 1140 */ 1141typedef struct bus_dmamap *bus_dmamap_t; 1142 1143/* 1144 * bus_dma_segment_t 1145 * 1146 * Describes a single contiguous DMA transaction. Values 1147 * are suitable for programming into DMA registers. 1148 */ 1149typedef struct bus_dma_segment { 1150 bus_addr_t ds_addr; /* DMA address */ 1151 bus_size_t ds_len; /* length of transfer */ 1152} bus_dma_segment_t; 1153 1154/* 1155 * A function that returns 1 if the address cannot be accessed by 1156 * a device and 0 if it can be. 1157 */ 1158typedef int bus_dma_filter_t(void *, bus_addr_t); 1159 1160/* 1161 * Allocate a device specific dma_tag encapsulating the constraints of 1162 * the parent tag in addition to other restrictions specified: 1163 * 1164 * alignment: alignment for segments. 1165 * boundary: Boundary that segments cannot cross. 1166 * lowaddr: Low restricted address that cannot appear in a mapping. 1167 * highaddr: High restricted address that cannot appear in a mapping. 1168 * filtfunc: An optional function to further test if an address 1169 * within the range of lowaddr and highaddr cannot appear 1170 * in a mapping. 1171 * filtfuncarg: An argument that will be passed to filtfunc in addition 1172 * to the address to test. 1173 * maxsize: Maximum mapping size supported by this tag. 1174 * nsegments: Number of discontinuities allowed in maps. 1175 * maxsegsz: Maximum size of a segment in the map. 1176 * flags: Bus DMA flags. 1177 * dmat: A pointer to set to a valid dma tag should the return 1178 * value of this function indicate success. 1179 */ 1180/* XXX Should probably allow specification of alignment */ 1181int bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignemnt, 1182 bus_size_t boundary, bus_addr_t lowaddr, 1183 bus_addr_t highaddr, bus_dma_filter_t *filtfunc, 1184 void *filtfuncarg, bus_size_t maxsize, int nsegments, 1185 bus_size_t maxsegsz, int flags, bus_dma_tag_t *dmat); 1186 1187int bus_dma_tag_destroy(bus_dma_tag_t dmat); 1188 1189/* 1190 * Allocate a handle for mapping from kva/uva/physical 1191 * address space into bus device space. 1192 */ 1193int bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp); 1194 1195/* 1196 * Destroy a handle for mapping from kva/uva/physical 1197 * address space into bus device space. 1198 */ 1199int bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map); 1200 1201/* 1202 * Allocate a piece of memory that can be efficiently mapped into 1203 * bus device space based on the constraints lited in the dma tag. 1204 * A dmamap to for use with dmamap_load is also allocated. 1205 */ 1206int bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, 1207 bus_dmamap_t *mapp); 1208 1209/* 1210 * Free a piece of memory and it's allociated dmamap, that was allocated 1211 * via bus_dmamem_alloc. 1212 */ 1213void bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map); 1214 1215/* 1216 * A function that processes a successfully loaded dma map or an error 1217 * from a delayed load map. 1218 */ 1219typedef void bus_dmamap_callback_t(void *, bus_dma_segment_t *, int, int); 1220 1221/* 1222 * Map the buffer buf into bus space using the dmamap map. 1223 */ 1224int bus_dmamap_load(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf, 1225 bus_size_t buflen, bus_dmamap_callback_t *callback, 1226 void *callback_arg, int flags); 1227 1228/* 1229 * Like bus_dmamap_callback but includes map size in bytes. This is 1230 * defined as a separate interface to maintain compatiiblity for users 1231 * of bus_dmamap_callback_t--at some point these interfaces should be merged. 1232 */ 1233typedef void bus_dmamap_callback2_t(void *, bus_dma_segment_t *, int, bus_size_t, int); 1234/* 1235 * Like bus_dmamap_load but for mbufs. Note the use of the 1236 * bus_dmamap_callback2_t interface. 1237 */ 1238int bus_dmamap_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, 1239 struct mbuf *mbuf, 1240 bus_dmamap_callback2_t *callback, void *callback_arg, 1241 int flags); 1242/* 1243 * Like bus_dmamap_load but for uios. Note the use of the 1244 * bus_dmamap_callback2_t interface. 1245 */ 1246int bus_dmamap_load_uio(bus_dma_tag_t dmat, bus_dmamap_t map, 1247 struct uio *ui, 1248 bus_dmamap_callback2_t *callback, void *callback_arg, 1249 int flags); 1250 1251/* 1252 * Perform a syncronization operation on the given map. 1253 */ 1254void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_dmasync_op_t); 1255#define bus_dmamap_sync(dmat, dmamap, op) \ 1256 if ((dmamap) != NULL) \ 1257 _bus_dmamap_sync(dmat, dmamap, op) 1258 1259/* 1260 * Release the mapping held by map. 1261 */ 1262void _bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map); 1263#define bus_dmamap_unload(dmat, dmamap) \ 1264 if ((dmamap) != NULL) \ 1265 _bus_dmamap_unload(dmat, dmamap) 1266 1267#endif /* _MACHINE_BUS_H_ */ 1268