1/*- 2 * Copyright (c) 2000-2006 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32 33#include <ia64/disasm/disasm_int.h> 34#include <ia64/disasm/disasm.h> 35 36/* 37 * Template names. 38 */ 39static const char *asm_templname[] = { 40 "MII", "MII;", "MI;I", "MI;I;", "MLX", "MLX;", 0, 0, 41 "MMI", "MMI;", "M;MI", "M;MI;", "MFI", "MFI;", "MMF", "MMF;", 42 "MIB", "MIB;", "MBB", "MBB;", 0, 0, "BBB", "BBB;", 43 "MMB", "MMB;", 0, 0, "MFB", "MFB;", 0, 0 44}; 45 46/* 47 * Decode A-unit instructions. 48 */ 49static int 50asm_decodeA(uint64_t bits, struct asm_bundle *b, int slot) 51{ 52 enum asm_fmt fmt; 53 enum asm_op op; 54 55 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 56 switch((int)OPCODE(bits)) { 57 case 0x8: 58 switch (FIELD(bits, 34, 2)) { /* x2a */ 59 case 0x0: 60 if (FIELD(bits, 33, 1) == 0) { /* ve */ 61 switch (FIELD(bits, 29, 4)) { /* x4 */ 62 case 0x0: 63 if (FIELD(bits, 27, 2) <= 1) /* x2b */ 64 op = ASM_OP_ADD, 65 fmt = ASM_FMT_A1; 66 break; 67 case 0x1: 68 if (FIELD(bits, 27, 2) <= 1) /* x2b */ 69 op = ASM_OP_SUB, 70 fmt = ASM_FMT_A1; 71 break; 72 case 0x2: 73 if (FIELD(bits, 27, 2) == 0) /* x2b */ 74 op = ASM_OP_ADDP4, 75 fmt = ASM_FMT_A1; 76 break; 77 case 0x3: 78 switch (FIELD(bits, 27, 2)) { /* x2b */ 79 case 0x0: 80 op = ASM_OP_AND, 81 fmt = ASM_FMT_A1; 82 break; 83 case 0x1: 84 op = ASM_OP_ANDCM, 85 fmt = ASM_FMT_A1; 86 break; 87 case 0x2: 88 op = ASM_OP_OR, 89 fmt = ASM_FMT_A1; 90 break; 91 case 0x3: 92 op = ASM_OP_XOR, 93 fmt = ASM_FMT_A1; 94 break; 95 } 96 break; 97 case 0xB: 98 switch (FIELD(bits, 27, 2)) { /* x2b */ 99 case 0x0: 100 op = ASM_OP_AND, 101 fmt = ASM_FMT_A3; 102 break; 103 case 0x1: 104 op = ASM_OP_ANDCM, 105 fmt = ASM_FMT_A3; 106 break; 107 case 0x2: 108 op = ASM_OP_OR, 109 fmt = ASM_FMT_A3; 110 break; 111 case 0x3: 112 op = ASM_OP_XOR, 113 fmt = ASM_FMT_A3; 114 break; 115 } 116 break; 117 case 0x4: 118 op = ASM_OP_SHLADD, fmt = ASM_FMT_A2; 119 break; 120 case 0x6: 121 op = ASM_OP_SHLADDP4, fmt = ASM_FMT_A2; 122 break; 123 case 0x9: 124 if (FIELD(bits, 27, 2) == 1) /* x2b */ 125 op = ASM_OP_SUB, 126 fmt = ASM_FMT_A3; 127 break; 128 } 129 } 130 break; 131 case 0x1: 132 switch (FIELD(bits, 29, 8)) { /* za + x2a + zb + x4 */ 133 case 0x20: 134 switch (FIELD(bits, 27, 2)) { /* x2b */ 135 case 0x0: 136 op = ASM_OP_PADD1_, fmt = ASM_FMT_A9; 137 break; 138 case 0x1: 139 op = ASM_OP_PADD1_SSS, 140 fmt = ASM_FMT_A9; 141 break; 142 case 0x2: 143 op = ASM_OP_PADD1_UUU, 144 fmt = ASM_FMT_A9; 145 break; 146 case 0x3: 147 op = ASM_OP_PADD1_UUS, 148 fmt = ASM_FMT_A9; 149 break; 150 } 151 break; 152 case 0x21: 153 switch (FIELD(bits, 27, 2)) { /* x2b */ 154 case 0x0: 155 op = ASM_OP_PSUB1_, fmt = ASM_FMT_A9; 156 break; 157 case 0x1: 158 op = ASM_OP_PSUB1_SSS, 159 fmt = ASM_FMT_A9; 160 break; 161 case 0x2: 162 op = ASM_OP_PSUB1_UUU, 163 fmt = ASM_FMT_A9; 164 break; 165 case 0x3: 166 op = ASM_OP_PSUB1_UUS, 167 fmt = ASM_FMT_A9; 168 break; 169 } 170 break; 171 case 0x22: 172 switch (FIELD(bits, 27, 2)) { /* x2b */ 173 case 0x2: 174 op = ASM_OP_PAVG1_, fmt = ASM_FMT_A9; 175 break; 176 case 0x3: 177 op = ASM_OP_PAVG1_RAZ, 178 fmt = ASM_FMT_A9; 179 break; 180 } 181 break; 182 case 0x23: 183 if (FIELD(bits, 27, 2) == 2) /* x2b */ 184 op = ASM_OP_PAVGSUB1, fmt = ASM_FMT_A9; 185 break; 186 case 0x29: 187 switch (FIELD(bits, 27, 2)) { /* x2b */ 188 case 0x0: 189 op = ASM_OP_PCMP1_EQ, fmt = ASM_FMT_A9; 190 break; 191 case 0x1: 192 op = ASM_OP_PCMP1_GT, fmt = ASM_FMT_A9; 193 break; 194 } 195 break; 196 case 0x30: 197 switch (FIELD(bits, 27, 2)) { /* x2b */ 198 case 0x0: 199 op = ASM_OP_PADD2_, fmt = ASM_FMT_A9; 200 break; 201 case 0x1: 202 op = ASM_OP_PADD2_SSS, 203 fmt = ASM_FMT_A9; 204 break; 205 case 0x2: 206 op = ASM_OP_PADD2_UUU, 207 fmt = ASM_FMT_A9; 208 break; 209 case 0x3: 210 op = ASM_OP_PADD2_UUS, 211 fmt = ASM_FMT_A9; 212 break; 213 } 214 break; 215 case 0x31: 216 switch (FIELD(bits, 27, 2)) { /* x2b */ 217 case 0x0: 218 op = ASM_OP_PSUB2_, fmt = ASM_FMT_A9; 219 break; 220 case 0x1: 221 op = ASM_OP_PSUB2_SSS, 222 fmt = ASM_FMT_A9; 223 break; 224 case 0x2: 225 op = ASM_OP_PSUB2_UUU, 226 fmt = ASM_FMT_A9; 227 break; 228 case 0x3: 229 op = ASM_OP_PSUB2_UUS, 230 fmt = ASM_FMT_A9; 231 break; 232 } 233 break; 234 case 0x32: 235 switch (FIELD(bits, 27, 2)) { /* x2b */ 236 case 0x2: 237 op = ASM_OP_PAVG2_, fmt = ASM_FMT_A9; 238 break; 239 case 0x3: 240 op = ASM_OP_PAVG2_RAZ, 241 fmt = ASM_FMT_A9; 242 break; 243 } 244 break; 245 case 0x33: 246 if (FIELD(bits, 27, 2) == 2) /* x2b */ 247 op = ASM_OP_PAVGSUB2, fmt = ASM_FMT_A9; 248 break; 249 case 0x34: 250 op = ASM_OP_PSHLADD2, fmt = ASM_FMT_A10; 251 break; 252 case 0x36: 253 op = ASM_OP_PSHRADD2, fmt = ASM_FMT_A10; 254 break; 255 case 0x39: 256 switch (FIELD(bits, 27, 2)) { /* x2b */ 257 case 0x0: 258 op = ASM_OP_PCMP2_EQ, fmt = ASM_FMT_A9; 259 break; 260 case 0x1: 261 op = ASM_OP_PCMP2_GT, fmt = ASM_FMT_A9; 262 break; 263 } 264 break; 265 case 0xA0: 266 if (FIELD(bits, 27, 2) == 0) /* x2b */ 267 op = ASM_OP_PADD4, fmt = ASM_FMT_A9; 268 break; 269 case 0xA1: 270 if (FIELD(bits, 27, 2) == 0) /* x2b */ 271 op = ASM_OP_PSUB4, fmt = ASM_FMT_A9; 272 break; 273 case 0xA9: 274 switch (FIELD(bits, 27, 2)) { /* x2b */ 275 case 0x0: 276 op = ASM_OP_PCMP4_EQ, fmt = ASM_FMT_A9; 277 break; 278 case 0x1: 279 op = ASM_OP_PCMP4_GT, fmt = ASM_FMT_A9; 280 break; 281 } 282 break; 283 } 284 break; 285 case 0x2: 286 if (FIELD(bits, 33, 1) == 0) /* ve */ 287 op = ASM_OP_ADDS, fmt = ASM_FMT_A4; 288 break; 289 case 0x3: 290 if (FIELD(bits, 33, 1) == 0) /* ve */ 291 op = ASM_OP_ADDP4, fmt = ASM_FMT_A4; 292 break; 293 } 294 break; 295 case 0x9: 296 op = ASM_OP_ADDL, fmt = ASM_FMT_A5; 297 break; 298 case 0xC: case 0xD: case 0xE: 299 if (FIELD(bits, 12, 1) == 0) { /* c */ 300 switch (FIELD(bits, 33, 8)) { /* maj + tb + x2 + ta */ 301 case 0xC0: 302 op = ASM_OP_CMP_LT, fmt = ASM_FMT_A6; 303 break; 304 case 0xC1: 305 op = ASM_OP_CMP_EQ_AND, fmt = ASM_FMT_A6; 306 break; 307 case 0xC2: 308 op = ASM_OP_CMP4_LT, fmt = ASM_FMT_A6; 309 break; 310 case 0xC3: 311 op = ASM_OP_CMP4_EQ_AND, fmt = ASM_FMT_A6; 312 break; 313 case 0xC4: case 0xCC: 314 op = ASM_OP_CMP_LT, fmt = ASM_FMT_A8; 315 break; 316 case 0xC5: case 0xCD: 317 op = ASM_OP_CMP_EQ_AND, fmt = ASM_FMT_A8; 318 break; 319 case 0xC6: case 0xCE: 320 op = ASM_OP_CMP4_LT, fmt = ASM_FMT_A8; 321 break; 322 case 0xC7: case 0xCF: 323 op = ASM_OP_CMP4_EQ_AND, fmt = ASM_FMT_A8; 324 break; 325 case 0xC8: 326 op = ASM_OP_CMP_GT_AND, fmt = ASM_FMT_A7; 327 break; 328 case 0xC9: 329 op = ASM_OP_CMP_GE_AND, fmt = ASM_FMT_A7; 330 break; 331 case 0xCA: 332 op = ASM_OP_CMP4_GT_AND, fmt = ASM_FMT_A7; 333 break; 334 case 0xCB: 335 op = ASM_OP_CMP4_GE_AND, fmt = ASM_FMT_A7; 336 break; 337 case 0xD0: 338 op = ASM_OP_CMP_LTU, fmt = ASM_FMT_A6; 339 break; 340 case 0xD1: 341 op = ASM_OP_CMP_EQ_OR, fmt = ASM_FMT_A6; 342 break; 343 case 0xD2: 344 op = ASM_OP_CMP4_LTU, fmt = ASM_FMT_A6; 345 break; 346 case 0xD3: 347 op = ASM_OP_CMP4_EQ_OR, fmt = ASM_FMT_A6; 348 break; 349 case 0xD4: case 0xDC: 350 op = ASM_OP_CMP_LTU, fmt = ASM_FMT_A8; 351 break; 352 case 0xD5: case 0xDD: 353 op = ASM_OP_CMP_EQ_OR, fmt = ASM_FMT_A8; 354 break; 355 case 0xD6: case 0xDE: 356 op = ASM_OP_CMP4_LTU, fmt = ASM_FMT_A8; 357 break; 358 case 0xD7: case 0xDF: 359 op = ASM_OP_CMP4_EQ_OR, fmt = ASM_FMT_A8; 360 break; 361 case 0xD8: 362 op = ASM_OP_CMP_GT_OR, fmt = ASM_FMT_A7; 363 break; 364 case 0xD9: 365 op = ASM_OP_CMP_GE_OR, fmt = ASM_FMT_A7; 366 break; 367 case 0xDA: 368 op = ASM_OP_CMP4_GT_OR, fmt = ASM_FMT_A7; 369 break; 370 case 0xDB: 371 op = ASM_OP_CMP4_GE_OR, fmt = ASM_FMT_A7; 372 break; 373 case 0xE0: 374 op = ASM_OP_CMP_EQ, fmt = ASM_FMT_A6; 375 break; 376 case 0xE1: 377 op = ASM_OP_CMP_EQ_OR_ANDCM, fmt = ASM_FMT_A6; 378 break; 379 case 0xE2: 380 op = ASM_OP_CMP4_EQ, fmt = ASM_FMT_A6; 381 break; 382 case 0xE3: 383 op = ASM_OP_CMP4_EQ_OR_ANDCM, fmt = ASM_FMT_A6; 384 break; 385 case 0xE4: case 0xEC: 386 op = ASM_OP_CMP_EQ, fmt = ASM_FMT_A8; 387 break; 388 case 0xE5: case 0xED: 389 op = ASM_OP_CMP_EQ_OR_ANDCM, fmt = ASM_FMT_A8; 390 break; 391 case 0xE6: case 0xEE: 392 op = ASM_OP_CMP4_EQ, fmt = ASM_FMT_A8; 393 break; 394 case 0xE7: case 0xEF: 395 op = ASM_OP_CMP4_EQ_OR_ANDCM, fmt = ASM_FMT_A8; 396 break; 397 case 0xE8: 398 op = ASM_OP_CMP_GT_OR_ANDCM, fmt = ASM_FMT_A7; 399 break; 400 case 0xE9: 401 op = ASM_OP_CMP_GE_OR_ANDCM, fmt = ASM_FMT_A7; 402 break; 403 case 0xEA: 404 op = ASM_OP_CMP4_GT_OR_ANDCM, fmt = ASM_FMT_A7; 405 break; 406 case 0xEB: 407 op = ASM_OP_CMP4_GE_OR_ANDCM, fmt = ASM_FMT_A7; 408 break; 409 } 410 } else { 411 switch (FIELD(bits, 33, 8)) { /* maj + tb + x2 + ta */ 412 case 0xC0: 413 op = ASM_OP_CMP_LT_UNC, fmt = ASM_FMT_A6; 414 break; 415 case 0xC1: 416 op = ASM_OP_CMP_NE_AND, fmt = ASM_FMT_A6; 417 break; 418 case 0xC2: 419 op = ASM_OP_CMP4_LT_UNC, fmt = ASM_FMT_A6; 420 break; 421 case 0xC3: 422 op = ASM_OP_CMP4_NE_AND, fmt = ASM_FMT_A6; 423 break; 424 case 0xC4: case 0xCC: 425 op = ASM_OP_CMP_LT_UNC, fmt = ASM_FMT_A8; 426 break; 427 case 0xC5: case 0xCD: 428 op = ASM_OP_CMP_NE_AND, fmt = ASM_FMT_A8; 429 break; 430 case 0xC6: case 0xCE: 431 op = ASM_OP_CMP4_LT_UNC, fmt = ASM_FMT_A8; 432 break; 433 case 0xC7: case 0xCF: 434 op = ASM_OP_CMP4_NE_AND, fmt = ASM_FMT_A8; 435 break; 436 case 0xC8: 437 op = ASM_OP_CMP_LE_AND, fmt = ASM_FMT_A7; 438 break; 439 case 0xC9: 440 op = ASM_OP_CMP_LT_AND, fmt = ASM_FMT_A7; 441 break; 442 case 0xCA: 443 op = ASM_OP_CMP4_LE_AND, fmt = ASM_FMT_A7; 444 break; 445 case 0xCB: 446 op = ASM_OP_CMP4_LT_AND, fmt = ASM_FMT_A7; 447 break; 448 case 0xD0: 449 op = ASM_OP_CMP_LTU_UNC, fmt = ASM_FMT_A6; 450 break; 451 case 0xD1: 452 op = ASM_OP_CMP_NE_OR, fmt = ASM_FMT_A6; 453 break; 454 case 0xD2: 455 op = ASM_OP_CMP4_LTU_UNC, fmt = ASM_FMT_A6; 456 break; 457 case 0xD3: 458 op = ASM_OP_CMP4_NE_OR, fmt = ASM_FMT_A6; 459 break; 460 case 0xD4: case 0xDC: 461 op = ASM_OP_CMP_LTU_UNC, fmt = ASM_FMT_A8; 462 break; 463 case 0xD5: case 0xDD: 464 op = ASM_OP_CMP_NE_OR, fmt = ASM_FMT_A8; 465 break; 466 case 0xD6: case 0xDE: 467 op = ASM_OP_CMP4_LTU_UNC, fmt = ASM_FMT_A8; 468 break; 469 case 0xD7: case 0xDF: 470 op = ASM_OP_CMP4_NE_OR, fmt = ASM_FMT_A8; 471 break; 472 case 0xD8: 473 op = ASM_OP_CMP_LE_OR, fmt = ASM_FMT_A7; 474 break; 475 case 0xD9: 476 op = ASM_OP_CMP_LT_OR, fmt = ASM_FMT_A7; 477 break; 478 case 0xDA: 479 op = ASM_OP_CMP4_LE_OR, fmt = ASM_FMT_A7; 480 break; 481 case 0xDB: 482 op = ASM_OP_CMP4_LT_OR, fmt = ASM_FMT_A7; 483 break; 484 case 0xE0: 485 op = ASM_OP_CMP_EQ_UNC, fmt = ASM_FMT_A6; 486 break; 487 case 0xE1: 488 op = ASM_OP_CMP_NE_OR_ANDCM, fmt = ASM_FMT_A6; 489 break; 490 case 0xE2: 491 op = ASM_OP_CMP4_EQ_UNC, fmt = ASM_FMT_A6; 492 break; 493 case 0xE3: 494 op = ASM_OP_CMP4_NE_OR_ANDCM, fmt = ASM_FMT_A6; 495 break; 496 case 0xE4: case 0xEC: 497 op = ASM_OP_CMP_EQ_UNC, fmt = ASM_FMT_A8; 498 break; 499 case 0xE5: case 0xED: 500 op = ASM_OP_CMP_NE_OR_ANDCM, fmt = ASM_FMT_A8; 501 break; 502 case 0xE6: case 0xEE: 503 op = ASM_OP_CMP4_EQ_UNC, fmt = ASM_FMT_A8; 504 break; 505 case 0xE7: case 0xEF: 506 op = ASM_OP_CMP4_NE_OR_ANDCM, fmt = ASM_FMT_A8; 507 break; 508 case 0xE8: 509 op = ASM_OP_CMP_LE_OR_ANDCM, fmt = ASM_FMT_A7; 510 break; 511 case 0xE9: 512 op = ASM_OP_CMP_LT_OR_ANDCM, fmt = ASM_FMT_A7; 513 break; 514 case 0xEA: 515 op = ASM_OP_CMP4_LE_OR_ANDCM, fmt = ASM_FMT_A7; 516 break; 517 case 0xEB: 518 op = ASM_OP_CMP4_LT_OR_ANDCM, fmt = ASM_FMT_A7; 519 break; 520 } 521 } 522 break; 523 } 524 525 if (op != ASM_OP_NONE) 526 return (asm_extract(op, fmt, bits, b, slot)); 527 return (0); 528} 529 530/* 531 * Decode B-unit instructions. 532 */ 533static int 534asm_decodeB(uint64_t ip, struct asm_bundle *b, int slot) 535{ 536 uint64_t bits; 537 enum asm_fmt fmt; 538 enum asm_op op; 539 540 bits = SLOT(ip, slot); 541 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 542 543 switch((int)OPCODE(bits)) { 544 case 0x0: 545 switch (FIELD(bits, 27, 6)) { /* x6 */ 546 case 0x0: 547 op = ASM_OP_BREAK_B, fmt = ASM_FMT_B9; 548 break; 549 case 0x2: 550 op = ASM_OP_COVER, fmt = ASM_FMT_B8; 551 break; 552 case 0x4: 553 op = ASM_OP_CLRRRB_, fmt = ASM_FMT_B8; 554 break; 555 case 0x5: 556 op = ASM_OP_CLRRRB_PR, fmt = ASM_FMT_B8; 557 break; 558 case 0x8: 559 op = ASM_OP_RFI, fmt = ASM_FMT_B8; 560 break; 561 case 0xC: 562 op = ASM_OP_BSW_0, fmt = ASM_FMT_B8; 563 break; 564 case 0xD: 565 op = ASM_OP_BSW_1, fmt = ASM_FMT_B8; 566 break; 567 case 0x10: 568 op = ASM_OP_EPC, fmt = ASM_FMT_B8; 569 break; 570 case 0x18: 571 op = ASM_OP_VMSW_0, fmt = ASM_FMT_B8; 572 break; 573 case 0x19: 574 op = ASM_OP_VMSW_1, fmt = ASM_FMT_B8; 575 break; 576 case 0x20: 577 switch (FIELD(bits, 6, 3)) { /* btype */ 578 case 0x0: 579 op = ASM_OP_BR_COND, fmt = ASM_FMT_B4; 580 break; 581 case 0x1: 582 op = ASM_OP_BR_IA, fmt = ASM_FMT_B4; 583 break; 584 } 585 break; 586 case 0x21: 587 if (FIELD(bits, 6, 3) == 4) /* btype */ 588 op = ASM_OP_BR_RET, fmt = ASM_FMT_B4; 589 break; 590 } 591 break; 592 case 0x1: 593 op = ASM_OP_BR_CALL, fmt = ASM_FMT_B5; 594 break; 595 case 0x2: 596 switch (FIELD(bits, 27, 6)) { /* x6 */ 597 case 0x0: 598 op = ASM_OP_NOP_B, fmt = ASM_FMT_B9; 599 break; 600 case 0x1: 601 op = ASM_OP_HINT_B, fmt = ASM_FMT_B9; 602 break; 603 case 0x10: 604 op = ASM_OP_BRP_, fmt = ASM_FMT_B7; 605 break; 606 case 0x11: 607 op = ASM_OP_BRP_RET, fmt = ASM_FMT_B7; 608 break; 609 } 610 break; 611 case 0x4: 612 switch (FIELD(bits, 6, 3)) { /* btype */ 613 case 0x0: 614 op = ASM_OP_BR_COND, fmt = ASM_FMT_B1; 615 break; 616 case 0x2: 617 op = ASM_OP_BR_WEXIT, fmt = ASM_FMT_B1; 618 break; 619 case 0x3: 620 op = ASM_OP_BR_WTOP, fmt = ASM_FMT_B1; 621 break; 622 case 0x5: 623 op = ASM_OP_BR_CLOOP, fmt = ASM_FMT_B2; 624 break; 625 case 0x6: 626 op = ASM_OP_BR_CEXIT, fmt = ASM_FMT_B2; 627 break; 628 case 0x7: 629 op = ASM_OP_BR_CTOP, fmt = ASM_FMT_B2; 630 break; 631 } 632 break; 633 case 0x5: 634 op = ASM_OP_BR_CALL, fmt = ASM_FMT_B3; 635 break; 636 case 0x7: 637 op = ASM_OP_BRP_, fmt = ASM_FMT_B6; 638 break; 639 } 640 641 if (op != ASM_OP_NONE) 642 return (asm_extract(op, fmt, bits, b, slot)); 643 return (0); 644} 645 646/* 647 * Decode F-unit instructions. 648 */ 649static int 650asm_decodeF(uint64_t ip, struct asm_bundle *b, int slot) 651{ 652 uint64_t bits; 653 enum asm_fmt fmt; 654 enum asm_op op; 655 656 bits = SLOT(ip, slot); 657 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 658 659 switch((int)OPCODE(bits)) { 660 case 0x0: 661 if (FIELD(bits, 33, 1) == 0) { /* x */ 662 switch (FIELD(bits, 27, 6)) { /* x6 */ 663 case 0x0: 664 op = ASM_OP_BREAK_F, fmt = ASM_FMT_F15; 665 break; 666 case 0x1: 667 if (FIELD(bits, 26, 1) == 0) /* y */ 668 op = ASM_OP_NOP_F, fmt = ASM_FMT_F16; 669 else 670 op = ASM_OP_HINT_F, fmt = ASM_FMT_F16; 671 break; 672 case 0x4: 673 op = ASM_OP_FSETC, fmt = ASM_FMT_F12; 674 break; 675 case 0x5: 676 op = ASM_OP_FCLRF, fmt = ASM_FMT_F13; 677 break; 678 case 0x8: 679 op = ASM_OP_FCHKF, fmt = ASM_FMT_F14; 680 break; 681 case 0x10: 682 op = ASM_OP_FMERGE_S, fmt = ASM_FMT_F9; 683 break; 684 case 0x11: 685 op = ASM_OP_FMERGE_NS, fmt = ASM_FMT_F9; 686 break; 687 case 0x12: 688 op = ASM_OP_FMERGE_SE, fmt = ASM_FMT_F9; 689 break; 690 case 0x14: 691 op = ASM_OP_FMIN, fmt = ASM_FMT_F8; 692 break; 693 case 0x15: 694 op = ASM_OP_FMAX, fmt = ASM_FMT_F8; 695 break; 696 case 0x16: 697 op = ASM_OP_FAMIN, fmt = ASM_FMT_F8; 698 break; 699 case 0x17: 700 op = ASM_OP_FAMAX, fmt = ASM_FMT_F8; 701 break; 702 case 0x18: 703 op = ASM_OP_FCVT_FX, fmt = ASM_FMT_F10; 704 break; 705 case 0x19: 706 op = ASM_OP_FCVT_FXU, fmt = ASM_FMT_F10; 707 break; 708 case 0x1A: 709 op = ASM_OP_FCVT_FX_TRUNC, fmt = ASM_FMT_F10; 710 break; 711 case 0x1B: 712 op = ASM_OP_FCVT_FXU_TRUNC, fmt = ASM_FMT_F10; 713 break; 714 case 0x1C: 715 op = ASM_OP_FCVT_XF, fmt = ASM_FMT_F11; 716 break; 717 case 0x28: 718 op = ASM_OP_FPACK, fmt = ASM_FMT_F9; 719 break; 720 case 0x2C: 721 op = ASM_OP_FAND, fmt = ASM_FMT_F9; 722 break; 723 case 0x2D: 724 op = ASM_OP_FANDCM, fmt = ASM_FMT_F9; 725 break; 726 case 0x2E: 727 op = ASM_OP_FOR, fmt = ASM_FMT_F9; 728 break; 729 case 0x2F: 730 op = ASM_OP_FXOR, fmt = ASM_FMT_F9; 731 break; 732 case 0x34: 733 op = ASM_OP_FSWAP_, fmt = ASM_FMT_F9; 734 break; 735 case 0x35: 736 op = ASM_OP_FSWAP_NL, fmt = ASM_FMT_F9; 737 break; 738 case 0x36: 739 op = ASM_OP_FSWAP_NR, fmt = ASM_FMT_F9; 740 break; 741 case 0x39: 742 op = ASM_OP_FMIX_LR, fmt = ASM_FMT_F9; 743 break; 744 case 0x3A: 745 op = ASM_OP_FMIX_R, fmt = ASM_FMT_F9; 746 break; 747 case 0x3B: 748 op = ASM_OP_FMIX_L, fmt = ASM_FMT_F9; 749 break; 750 case 0x3C: 751 op = ASM_OP_FSXT_R, fmt = ASM_FMT_F9; 752 break; 753 case 0x3D: 754 op = ASM_OP_FSXT_L, fmt = ASM_FMT_F9; 755 break; 756 } 757 } else { 758 if (FIELD(bits, 36, 1) == 0) /* q */ 759 op = ASM_OP_FRCPA, fmt = ASM_FMT_F6; 760 else 761 op = ASM_OP_FRSQRTA, fmt = ASM_FMT_F7; 762 } 763 break; 764 case 0x1: 765 if (FIELD(bits, 33, 1) == 0) { /* x */ 766 switch (FIELD(bits, 27, 6)) { /* x6 */ 767 case 0x10: 768 op = ASM_OP_FPMERGE_S, fmt = ASM_FMT_F9; 769 break; 770 case 0x11: 771 op = ASM_OP_FPMERGE_NS, fmt = ASM_FMT_F9; 772 break; 773 case 0x12: 774 op = ASM_OP_FPMERGE_SE, fmt = ASM_FMT_F9; 775 break; 776 case 0x14: 777 op = ASM_OP_FPMIN, fmt = ASM_FMT_F8; 778 break; 779 case 0x15: 780 op = ASM_OP_FPMAX, fmt = ASM_FMT_F8; 781 break; 782 case 0x16: 783 op = ASM_OP_FPAMIN, fmt = ASM_FMT_F8; 784 break; 785 case 0x17: 786 op = ASM_OP_FPAMAX, fmt = ASM_FMT_F8; 787 break; 788 case 0x18: 789 op = ASM_OP_FPCVT_FX, fmt = ASM_FMT_F10; 790 break; 791 case 0x19: 792 op = ASM_OP_FPCVT_FXU, fmt = ASM_FMT_F10; 793 break; 794 case 0x1A: 795 op = ASM_OP_FPCVT_FX_TRUNC, fmt = ASM_FMT_F10; 796 break; 797 case 0x1B: 798 op = ASM_OP_FPCVT_FXU_TRUNC, fmt = ASM_FMT_F10; 799 break; 800 case 0x30: 801 op = ASM_OP_FPCMP_EQ, fmt = ASM_FMT_F8; 802 break; 803 case 0x31: 804 op = ASM_OP_FPCMP_LT, fmt = ASM_FMT_F8; 805 break; 806 case 0x32: 807 op = ASM_OP_FPCMP_LE, fmt = ASM_FMT_F8; 808 break; 809 case 0x33: 810 op = ASM_OP_FPCMP_UNORD, fmt = ASM_FMT_F8; 811 break; 812 case 0x34: 813 op = ASM_OP_FPCMP_NEQ, fmt = ASM_FMT_F8; 814 break; 815 case 0x35: 816 op = ASM_OP_FPCMP_NLT, fmt = ASM_FMT_F8; 817 break; 818 case 0x36: 819 op = ASM_OP_FPCMP_NLE, fmt = ASM_FMT_F8; 820 break; 821 case 0x37: 822 op = ASM_OP_FPCMP_ORD, fmt = ASM_FMT_F8; 823 break; 824 } 825 } else { 826 if (FIELD(bits, 36, 1) == 0) /* q */ 827 op = ASM_OP_FPRCPA, fmt = ASM_FMT_F6; 828 else 829 op = ASM_OP_FPRSQRTA, fmt = ASM_FMT_F7; 830 } 831 break; 832 case 0x4: 833 op = ASM_OP_FCMP, fmt = ASM_FMT_F4; 834 break; 835 case 0x5: 836 op = ASM_OP_FCLASS_M, fmt = ASM_FMT_F5; 837 break; 838 case 0x8: 839 if (FIELD(bits, 36, 1) == 0) /* x */ 840 op = ASM_OP_FMA_, fmt = ASM_FMT_F1; 841 else 842 op = ASM_OP_FMA_S, fmt = ASM_FMT_F1; 843 break; 844 case 0x9: 845 if (FIELD(bits, 36, 1) == 0) /* x */ 846 op = ASM_OP_FMA_D, fmt = ASM_FMT_F1; 847 else 848 op = ASM_OP_FPMA, fmt = ASM_FMT_F1; 849 break; 850 case 0xA: 851 if (FIELD(bits, 36, 1) == 0) /* x */ 852 op = ASM_OP_FMS_, fmt = ASM_FMT_F1; 853 else 854 op = ASM_OP_FMS_S, fmt = ASM_FMT_F1; 855 break; 856 case 0xB: 857 if (FIELD(bits, 36, 1) == 0) /* x */ 858 op = ASM_OP_FMS_D, fmt = ASM_FMT_F1; 859 else 860 op = ASM_OP_FPMS, fmt = ASM_FMT_F1; 861 break; 862 case 0xC: 863 if (FIELD(bits, 36, 1) == 0) /* x */ 864 op = ASM_OP_FNMA_, fmt = ASM_FMT_F1; 865 else 866 op = ASM_OP_FNMA_S, fmt = ASM_FMT_F1; 867 break; 868 case 0xD: 869 if (FIELD(bits, 36, 1) == 0) /* x */ 870 op = ASM_OP_FNMA_D, fmt = ASM_FMT_F1; 871 else 872 op = ASM_OP_FPNMA, fmt = ASM_FMT_F1; 873 break; 874 case 0xE: 875 if (FIELD(bits, 36, 1) == 1) { /* x */ 876 switch (FIELD(bits, 34, 2)) { /* x2 */ 877 case 0x0: 878 op = ASM_OP_XMA_L, fmt = ASM_FMT_F2; 879 break; 880 case 0x2: 881 op = ASM_OP_XMA_HU, fmt = ASM_FMT_F2; 882 break; 883 case 0x3: 884 op = ASM_OP_XMA_H, fmt = ASM_FMT_F2; 885 break; 886 } 887 } else 888 op = ASM_OP_FSELECT, fmt = ASM_FMT_F3; 889 break; 890 } 891 892 if (op != ASM_OP_NONE) 893 return (asm_extract(op, fmt, bits, b, slot)); 894 return (0); 895} 896 897/* 898 * Decode I-unit instructions. 899 */ 900static int 901asm_decodeI(uint64_t ip, struct asm_bundle *b, int slot) 902{ 903 uint64_t bits; 904 enum asm_fmt fmt; 905 enum asm_op op; 906 907 bits = SLOT(ip, slot); 908 if ((int)OPCODE(bits) >= 8) 909 return (asm_decodeA(bits, b, slot)); 910 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 911 912 switch((int)OPCODE(bits)) { 913 case 0x0: 914 switch (FIELD(bits, 33, 3)) { /* x3 */ 915 case 0x0: 916 switch (FIELD(bits, 27, 6)) { /* x6 */ 917 case 0x0: 918 op = ASM_OP_BREAK_I, fmt = ASM_FMT_I19; 919 break; 920 case 0x1: 921 if (FIELD(bits, 26, 1) == 0) /* y */ 922 op = ASM_OP_NOP_I, fmt = ASM_FMT_I18; 923 else 924 op = ASM_OP_HINT_I, fmt = ASM_FMT_I18; 925 break; 926 case 0xA: 927 op = ASM_OP_MOV_I, fmt = ASM_FMT_I27; 928 break; 929 case 0x10: 930 op = ASM_OP_ZXT1, fmt = ASM_FMT_I29; 931 break; 932 case 0x11: 933 op = ASM_OP_ZXT2, fmt = ASM_FMT_I29; 934 break; 935 case 0x12: 936 op = ASM_OP_ZXT4, fmt = ASM_FMT_I29; 937 break; 938 case 0x14: 939 op = ASM_OP_SXT1, fmt = ASM_FMT_I29; 940 break; 941 case 0x15: 942 op = ASM_OP_SXT2, fmt = ASM_FMT_I29; 943 break; 944 case 0x16: 945 op = ASM_OP_SXT4, fmt = ASM_FMT_I29; 946 break; 947 case 0x18: 948 op = ASM_OP_CZX1_L, fmt = ASM_FMT_I29; 949 break; 950 case 0x19: 951 op = ASM_OP_CZX2_L, fmt = ASM_FMT_I29; 952 break; 953 case 0x1C: 954 op = ASM_OP_CZX1_R, fmt = ASM_FMT_I29; 955 break; 956 case 0x1D: 957 op = ASM_OP_CZX2_R, fmt = ASM_FMT_I29; 958 break; 959 case 0x2A: 960 op = ASM_OP_MOV_I, fmt = ASM_FMT_I26; 961 break; 962 case 0x30: 963 op = ASM_OP_MOV_IP, fmt = ASM_FMT_I25; 964 break; 965 case 0x31: 966 op = ASM_OP_MOV_, fmt = ASM_FMT_I22; 967 break; 968 case 0x32: 969 op = ASM_OP_MOV_I, fmt = ASM_FMT_I28; 970 break; 971 case 0x33: 972 op = ASM_OP_MOV_PR, fmt = ASM_FMT_I25; 973 break; 974 } 975 break; 976 case 0x1: 977 op = ASM_OP_CHK_S_I, fmt = ASM_FMT_I20; 978 break; 979 case 0x2: 980 op = ASM_OP_MOV_, fmt = ASM_FMT_I24; 981 break; 982 case 0x3: 983 op = ASM_OP_MOV_, fmt = ASM_FMT_I23; 984 break; 985 case 0x7: 986 if (FIELD(bits, 22, 1) == 0) /* x */ 987 op = ASM_OP_MOV_, fmt = ASM_FMT_I21; 988 else 989 op = ASM_OP_MOV_RET, fmt = ASM_FMT_I21; 990 break; 991 } 992 break; 993 case 0x4: 994 op = ASM_OP_DEP_, fmt = ASM_FMT_I15; 995 break; 996 case 0x5: 997 switch (FIELD(bits, 33, 3)) { /* x + x2 */ 998 case 0x0: 999 if (FIELD(bits, 36, 1) == 0) { /* tb */ 1000 switch (FIELD(bits, 12, 2)) { /* c + y */ 1001 case 0x0: 1002 op = ASM_OP_TBIT_Z, fmt = ASM_FMT_I16; 1003 break; 1004 case 0x1: 1005 op = ASM_OP_TBIT_Z_UNC, 1006 fmt = ASM_FMT_I16; 1007 break; 1008 case 0x2: 1009 if (FIELD(bits, 19, 1) == 0) /* x */ 1010 op = ASM_OP_TNAT_Z, 1011 fmt = ASM_FMT_I17; 1012 else 1013 op = ASM_OP_TF_Z, 1014 fmt = ASM_FMT_I30; 1015 break; 1016 case 0x3: 1017 if (FIELD(bits, 19, 1) == 0) /* x */ 1018 op = ASM_OP_TNAT_Z_UNC, 1019 fmt = ASM_FMT_I17; 1020 else 1021 op = ASM_OP_TF_Z_UNC, 1022 fmt = ASM_FMT_I30; 1023 break; 1024 } 1025 } else { 1026 switch (FIELD(bits, 12, 2)) { /* c + y */ 1027 case 0x0: 1028 op = ASM_OP_TBIT_Z_AND, 1029 fmt = ASM_FMT_I16; 1030 break; 1031 case 0x1: 1032 op = ASM_OP_TBIT_NZ_AND, 1033 fmt = ASM_FMT_I16; 1034 break; 1035 case 0x2: 1036 if (FIELD(bits, 19, 1) == 0) /* x */ 1037 op = ASM_OP_TNAT_Z_AND, 1038 fmt = ASM_FMT_I17; 1039 else 1040 op = ASM_OP_TF_Z_AND, 1041 fmt = ASM_FMT_I30; 1042 break; 1043 case 0x3: 1044 if (FIELD(bits, 19, 1) == 0) /* x */ 1045 op = ASM_OP_TNAT_NZ_AND, 1046 fmt = ASM_FMT_I17; 1047 else 1048 op = ASM_OP_TF_NZ_AND, 1049 fmt = ASM_FMT_I30; 1050 break; 1051 } 1052 } 1053 break; 1054 case 0x1: 1055 if (FIELD(bits, 36, 1) == 0) { /* tb */ 1056 switch (FIELD(bits, 12, 2)) { /* c + y */ 1057 case 0x0: 1058 op = ASM_OP_TBIT_Z_OR, 1059 fmt = ASM_FMT_I16; 1060 break; 1061 case 0x1: 1062 op = ASM_OP_TBIT_NZ_OR, 1063 fmt = ASM_FMT_I16; 1064 break; 1065 case 0x2: 1066 if (FIELD(bits, 19, 1) == 0) /* x */ 1067 op = ASM_OP_TNAT_Z_OR, 1068 fmt = ASM_FMT_I17; 1069 else 1070 op = ASM_OP_TF_Z_OR, 1071 fmt = ASM_FMT_I30; 1072 break; 1073 case 0x3: 1074 if (FIELD(bits, 19, 1) == 0) /* x */ 1075 op = ASM_OP_TNAT_NZ_OR, 1076 fmt = ASM_FMT_I17; 1077 else 1078 op = ASM_OP_TF_NZ_OR, 1079 fmt = ASM_FMT_I30; 1080 break; 1081 } 1082 } else { 1083 switch (FIELD(bits, 12, 2)) { /* c + y */ 1084 case 0x0: 1085 op = ASM_OP_TBIT_Z_OR_ANDCM, 1086 fmt = ASM_FMT_I16; 1087 break; 1088 case 0x1: 1089 op = ASM_OP_TBIT_NZ_OR_ANDCM, 1090 fmt = ASM_FMT_I16; 1091 break; 1092 case 0x2: 1093 if (FIELD(bits, 19, 1) == 0) /* x */ 1094 op = ASM_OP_TNAT_Z_OR_ANDCM, 1095 fmt = ASM_FMT_I17; 1096 else 1097 op = ASM_OP_TF_Z_OR_ANDCM, 1098 fmt = ASM_FMT_I30; 1099 break; 1100 case 0x3: 1101 if (FIELD(bits, 19, 1) == 0) /* x */ 1102 op = ASM_OP_TNAT_NZ_OR_ANDCM, 1103 fmt = ASM_FMT_I17; 1104 else 1105 op = ASM_OP_TF_NZ_OR_ANDCM, 1106 fmt = ASM_FMT_I30; 1107 break; 1108 } 1109 } 1110 break; 1111 case 0x2: 1112 op = ASM_OP_EXTR, fmt = ASM_FMT_I11; 1113 break; 1114 case 0x3: 1115 if (FIELD(bits, 26, 1) == 0) /* y */ 1116 op = ASM_OP_DEP_Z, fmt = ASM_FMT_I12; 1117 else 1118 op = ASM_OP_DEP_Z, fmt = ASM_FMT_I13; 1119 break; 1120 case 0x6: 1121 op = ASM_OP_SHRP, fmt = ASM_FMT_I10; 1122 break; 1123 case 0x7: 1124 op = ASM_OP_DEP_, fmt = ASM_FMT_I14; 1125 break; 1126 } 1127 break; 1128 case 0x7: 1129 switch (FIELD(bits, 32, 5)) { /* ve + zb + x2a + za */ 1130 case 0x2: 1131 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1132 case 0x0: 1133 op = ASM_OP_PSHR2_U, fmt = ASM_FMT_I5; 1134 break; 1135 case 0x1: case 0x5: case 0x9: case 0xD: 1136 op = ASM_OP_PMPYSHR2_U, fmt = ASM_FMT_I1; 1137 break; 1138 case 0x2: 1139 op = ASM_OP_PSHR2_, fmt = ASM_FMT_I5; 1140 break; 1141 case 0x3: case 0x7: case 0xB: case 0xF: 1142 op = ASM_OP_PMPYSHR2_, fmt = ASM_FMT_I1; 1143 break; 1144 case 0x4: 1145 op = ASM_OP_PSHL2, fmt = ASM_FMT_I7; 1146 break; 1147 } 1148 break; 1149 case 0x6: 1150 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1151 case 0x1: 1152 op = ASM_OP_PSHR2_U, fmt = ASM_FMT_I6; 1153 break; 1154 case 0x3: 1155 op = ASM_OP_PSHR2_, fmt = ASM_FMT_I6; 1156 break; 1157 case 0x9: 1158 op = ASM_OP_POPCNT, fmt = ASM_FMT_I9; 1159 break; 1160 } 1161 break; 1162 case 0x8: 1163 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1164 case 0x1: 1165 op = ASM_OP_PMIN1_U, fmt = ASM_FMT_I2; 1166 break; 1167 case 0x4: 1168 op = ASM_OP_UNPACK1_H, fmt = ASM_FMT_I2; 1169 break; 1170 case 0x5: 1171 op = ASM_OP_PMAX1_U, fmt = ASM_FMT_I2; 1172 break; 1173 case 0x6: 1174 op = ASM_OP_UNPACK1_L, fmt = ASM_FMT_I2; 1175 break; 1176 case 0x8: 1177 op = ASM_OP_MIX1_R, fmt = ASM_FMT_I2; 1178 break; 1179 case 0xA: 1180 op = ASM_OP_MIX1_L, fmt = ASM_FMT_I2; 1181 break; 1182 case 0xB: 1183 op = ASM_OP_PSAD1, fmt = ASM_FMT_I2; 1184 break; 1185 } 1186 break; 1187 case 0xA: 1188 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1189 case 0x0: 1190 op = ASM_OP_PACK2_USS, fmt = ASM_FMT_I2; 1191 break; 1192 case 0x2: 1193 op = ASM_OP_PACK2_SSS, fmt = ASM_FMT_I2; 1194 break; 1195 case 0x3: 1196 op = ASM_OP_PMIN2, fmt = ASM_FMT_I2; 1197 break; 1198 case 0x4: 1199 op = ASM_OP_UNPACK2_H, fmt = ASM_FMT_I2; 1200 break; 1201 case 0x6: 1202 op = ASM_OP_UNPACK2_L, fmt = ASM_FMT_I2; 1203 break; 1204 case 0x7: 1205 op = ASM_OP_PMAX2, fmt = ASM_FMT_I2; 1206 break; 1207 case 0x8: 1208 op = ASM_OP_MIX2_R, fmt = ASM_FMT_I2; 1209 break; 1210 case 0xA: 1211 op = ASM_OP_MIX2_L, fmt = ASM_FMT_I2; 1212 break; 1213 case 0xD: 1214 op = ASM_OP_PMPY2_R, fmt = ASM_FMT_I2; 1215 break; 1216 case 0xF: 1217 op = ASM_OP_PMPY2_L, fmt = ASM_FMT_I2; 1218 break; 1219 } 1220 break; 1221 case 0xC: 1222 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1223 case 0xA: 1224 op = ASM_OP_MUX1, fmt = ASM_FMT_I3; 1225 break; 1226 } 1227 break; 1228 case 0xE: 1229 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1230 case 0x5: 1231 op = ASM_OP_PSHL2, fmt = ASM_FMT_I8; 1232 break; 1233 case 0xA: 1234 op = ASM_OP_MUX2, fmt = ASM_FMT_I4; 1235 break; 1236 } 1237 break; 1238 case 0x10: 1239 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1240 case 0x0: 1241 op = ASM_OP_PSHR4_U, fmt = ASM_FMT_I5; 1242 break; 1243 case 0x2: 1244 op = ASM_OP_PSHR4_, fmt = ASM_FMT_I5; 1245 break; 1246 case 0x4: 1247 op = ASM_OP_PSHL4, fmt = ASM_FMT_I7; 1248 break; 1249 } 1250 break; 1251 case 0x12: 1252 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1253 case 0x0: 1254 op = ASM_OP_SHR_U, fmt = ASM_FMT_I5; 1255 break; 1256 case 0x2: 1257 op = ASM_OP_SHR_, fmt = ASM_FMT_I5; 1258 break; 1259 case 0x4: 1260 op = ASM_OP_SHL, fmt = ASM_FMT_I7; 1261 break; 1262 } 1263 break; 1264 case 0x14: 1265 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1266 case 0x1: 1267 op = ASM_OP_PSHR4_U, fmt = ASM_FMT_I6; 1268 break; 1269 case 0x3: 1270 op = ASM_OP_PSHR4_, fmt = ASM_FMT_I6; 1271 break; 1272 } 1273 break; 1274 case 0x18: 1275 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1276 case 0x2: 1277 op = ASM_OP_PACK4_SSS, fmt = ASM_FMT_I2; 1278 break; 1279 case 0x4: 1280 op = ASM_OP_UNPACK4_H, fmt = ASM_FMT_I2; 1281 break; 1282 case 0x6: 1283 op = ASM_OP_UNPACK4_L, fmt = ASM_FMT_I2; 1284 break; 1285 case 0x8: 1286 op = ASM_OP_MIX4_R, fmt = ASM_FMT_I2; 1287 break; 1288 case 0xA: 1289 op = ASM_OP_MIX4_L, fmt = ASM_FMT_I2; 1290 break; 1291 } 1292 break; 1293 case 0x1C: 1294 switch (FIELD(bits, 28, 4)) { /* x2b + x2c */ 1295 case 0x5: 1296 op = ASM_OP_PSHL4, fmt = ASM_FMT_I8; 1297 break; 1298 } 1299 break; 1300 } 1301 break; 1302 } 1303 1304 if (op != ASM_OP_NONE) 1305 return (asm_extract(op, fmt, bits, b, slot)); 1306 return (0); 1307} 1308 1309/* 1310 * Decode M-unit instructions. 1311 */ 1312static int 1313asm_decodeM(uint64_t ip, struct asm_bundle *b, int slot) 1314{ 1315 uint64_t bits; 1316 enum asm_fmt fmt; 1317 enum asm_op op; 1318 1319 bits = SLOT(ip, slot); 1320 if ((int)OPCODE(bits) >= 8) 1321 return (asm_decodeA(bits, b, slot)); 1322 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 1323 1324 switch((int)OPCODE(bits)) { 1325 case 0x0: 1326 switch (FIELD(bits, 33, 3)) { /* x3 */ 1327 case 0x0: 1328 switch (FIELD(bits, 27, 6)) { /* x6 (x4 + x2) */ 1329 case 0x0: 1330 op = ASM_OP_BREAK_M, fmt = ASM_FMT_M37; 1331 break; 1332 case 0x1: 1333 if (FIELD(bits, 26, 1) == 0) /* y */ 1334 op = ASM_OP_NOP_M, fmt = ASM_FMT_M48; 1335 else 1336 op = ASM_OP_HINT_M, fmt = ASM_FMT_M48; 1337 break; 1338 case 0x4: case 0x14: case 0x24: case 0x34: 1339 op = ASM_OP_SUM, fmt = ASM_FMT_M44; 1340 break; 1341 case 0x5: case 0x15: case 0x25: case 0x35: 1342 op = ASM_OP_RUM, fmt = ASM_FMT_M44; 1343 break; 1344 case 0x6: case 0x16: case 0x26: case 0x36: 1345 op = ASM_OP_SSM, fmt = ASM_FMT_M44; 1346 break; 1347 case 0x7: case 0x17: case 0x27: case 0x37: 1348 op = ASM_OP_RSM, fmt = ASM_FMT_M44; 1349 break; 1350 case 0xA: 1351 op = ASM_OP_LOADRS, fmt = ASM_FMT_M25; 1352 break; 1353 case 0xC: 1354 op = ASM_OP_FLUSHRS, fmt = ASM_FMT_M25; 1355 break; 1356 case 0x10: 1357 op = ASM_OP_INVALA_, fmt = ASM_FMT_M24; 1358 break; 1359 case 0x12: 1360 op = ASM_OP_INVALA_E, fmt = ASM_FMT_M26; 1361 break; 1362 case 0x13: 1363 op = ASM_OP_INVALA_E, fmt = ASM_FMT_M27; 1364 break; 1365 case 0x20: 1366 op = ASM_OP_FWB, fmt = ASM_FMT_M24; 1367 break; 1368 case 0x22: 1369 op = ASM_OP_MF_, fmt = ASM_FMT_M24; 1370 break; 1371 case 0x23: 1372 op = ASM_OP_MF_A, fmt = ASM_FMT_M24; 1373 break; 1374 case 0x28: 1375 op = ASM_OP_MOV_M, fmt = ASM_FMT_M30; 1376 break; 1377 case 0x30: 1378 op = ASM_OP_SRLZ_D, fmt = ASM_FMT_M24; 1379 break; 1380 case 0x31: 1381 op = ASM_OP_SRLZ_I, fmt = ASM_FMT_M24; 1382 break; 1383 case 0x33: 1384 op = ASM_OP_SYNC_I, fmt = ASM_FMT_M24; 1385 break; 1386 } 1387 break; 1388 case 0x4: 1389 op = ASM_OP_CHK_A_NC, fmt = ASM_FMT_M22; 1390 break; 1391 case 0x5: 1392 op = ASM_OP_CHK_A_CLR, fmt = ASM_FMT_M22; 1393 break; 1394 case 0x6: 1395 op = ASM_OP_CHK_A_NC, fmt = ASM_FMT_M23; 1396 break; 1397 case 0x7: 1398 op = ASM_OP_CHK_A_CLR, fmt = ASM_FMT_M23; 1399 break; 1400 } 1401 break; 1402 case 0x1: 1403 switch (FIELD(bits, 33, 3)) { /* x3 */ 1404 case 0x0: 1405 switch (FIELD(bits, 27, 6)) { /* x6 (x4 + x2) */ 1406 case 0x0: 1407 op = ASM_OP_MOV_RR, fmt = ASM_FMT_M42; 1408 break; 1409 case 0x1: 1410 op = ASM_OP_MOV_DBR, fmt = ASM_FMT_M42; 1411 break; 1412 case 0x2: 1413 op = ASM_OP_MOV_IBR, fmt = ASM_FMT_M42; 1414 break; 1415 case 0x3: 1416 op = ASM_OP_MOV_PKR, fmt = ASM_FMT_M42; 1417 break; 1418 case 0x4: 1419 op = ASM_OP_MOV_PMC, fmt = ASM_FMT_M42; 1420 break; 1421 case 0x5: 1422 op = ASM_OP_MOV_PMD, fmt = ASM_FMT_M42; 1423 break; 1424 case 0x6: 1425 op = ASM_OP_MOV_MSR, fmt = ASM_FMT_M42; 1426 break; 1427 case 0x9: 1428 op = ASM_OP_PTC_L, fmt = ASM_FMT_M45; 1429 break; 1430 case 0xA: 1431 op = ASM_OP_PTC_G, fmt = ASM_FMT_M45; 1432 break; 1433 case 0xB: 1434 op = ASM_OP_PTC_GA, fmt = ASM_FMT_M45; 1435 break; 1436 case 0xC: 1437 op = ASM_OP_PTR_D, fmt = ASM_FMT_M45; 1438 break; 1439 case 0xD: 1440 op = ASM_OP_PTR_I, fmt = ASM_FMT_M45; 1441 break; 1442 case 0xE: 1443 op = ASM_OP_ITR_D, fmt = ASM_FMT_M42; 1444 break; 1445 case 0xF: 1446 op = ASM_OP_ITR_I, fmt = ASM_FMT_M42; 1447 break; 1448 case 0x10: 1449 op = ASM_OP_MOV_RR, fmt = ASM_FMT_M43; 1450 break; 1451 case 0x11: 1452 op = ASM_OP_MOV_DBR, fmt = ASM_FMT_M43; 1453 break; 1454 case 0x12: 1455 op = ASM_OP_MOV_IBR, fmt = ASM_FMT_M43; 1456 break; 1457 case 0x13: 1458 op = ASM_OP_MOV_PKR, fmt = ASM_FMT_M43; 1459 break; 1460 case 0x14: 1461 op = ASM_OP_MOV_PMC, fmt = ASM_FMT_M43; 1462 break; 1463 case 0x15: 1464 op = ASM_OP_MOV_PMD, fmt = ASM_FMT_M43; 1465 break; 1466 case 0x16: 1467 op = ASM_OP_MOV_MSR, fmt = ASM_FMT_M43; 1468 break; 1469 case 0x17: 1470 op = ASM_OP_MOV_CPUID, fmt = ASM_FMT_M43; 1471 break; 1472 case 0x18: 1473 op = ASM_OP_PROBE_R, fmt = ASM_FMT_M39; 1474 break; 1475 case 0x19: 1476 op = ASM_OP_PROBE_W, fmt = ASM_FMT_M39; 1477 break; 1478 case 0x1A: 1479 op = ASM_OP_THASH, fmt = ASM_FMT_M46; 1480 break; 1481 case 0x1B: 1482 op = ASM_OP_TTAG, fmt = ASM_FMT_M46; 1483 break; 1484 case 0x1E: 1485 op = ASM_OP_TPA, fmt = ASM_FMT_M46; 1486 break; 1487 case 0x1F: 1488 op = ASM_OP_TAK, fmt = ASM_FMT_M46; 1489 break; 1490 case 0x21: 1491 op = ASM_OP_MOV_PSR_UM, fmt = ASM_FMT_M36; 1492 break; 1493 case 0x22: 1494 op = ASM_OP_MOV_M, fmt = ASM_FMT_M31; 1495 break; 1496 case 0x24: 1497 op = ASM_OP_MOV_, fmt = ASM_FMT_M33; 1498 break; 1499 case 0x25: 1500 op = ASM_OP_MOV_PSR, fmt = ASM_FMT_M36; 1501 break; 1502 case 0x29: 1503 op = ASM_OP_MOV_PSR_UM, fmt = ASM_FMT_M35; 1504 break; 1505 case 0x2A: 1506 op = ASM_OP_MOV_M, fmt = ASM_FMT_M29; 1507 break; 1508 case 0x2C: 1509 op = ASM_OP_MOV_, fmt = ASM_FMT_M32; 1510 break; 1511 case 0x2D: 1512 op = ASM_OP_MOV_PSR_L, fmt = ASM_FMT_M35; 1513 break; 1514 case 0x2E: 1515 op = ASM_OP_ITC_D, fmt = ASM_FMT_M41; 1516 break; 1517 case 0x2F: 1518 op = ASM_OP_ITC_I, fmt = ASM_FMT_M41; 1519 break; 1520 case 0x30: 1521 if (FIELD(bits, 36, 1) == 0) /* x */ 1522 op = ASM_OP_FC_, fmt = ASM_FMT_M28; 1523 else 1524 op = ASM_OP_FC_I, fmt = ASM_FMT_M28; 1525 break; 1526 case 0x31: 1527 op = ASM_OP_PROBE_RW_FAULT, fmt = ASM_FMT_M40; 1528 break; 1529 case 0x32: 1530 op = ASM_OP_PROBE_R_FAULT, fmt = ASM_FMT_M40; 1531 break; 1532 case 0x33: 1533 op = ASM_OP_PROBE_W_FAULT, fmt = ASM_FMT_M40; 1534 break; 1535 case 0x34: 1536 op = ASM_OP_PTC_E, fmt = ASM_FMT_M47; 1537 break; 1538 case 0x38: 1539 op = ASM_OP_PROBE_R, fmt = ASM_FMT_M38; 1540 break; 1541 case 0x39: 1542 op = ASM_OP_PROBE_W, fmt = ASM_FMT_M38; 1543 break; 1544 } 1545 break; 1546 case 0x1: 1547 op = ASM_OP_CHK_S_M, fmt = ASM_FMT_M20; 1548 break; 1549 case 0x3: 1550 op = ASM_OP_CHK_S, fmt = ASM_FMT_M21; 1551 break; 1552 case 0x6: 1553 op = ASM_OP_ALLOC, fmt = ASM_FMT_M34; 1554 break; 1555 } 1556 break; 1557 case 0x4: 1558 if (FIELD(bits, 27, 1) == 0) { /* x */ 1559 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 1560 case 0x0: 1561 op = ASM_OP_LD1_, fmt = ASM_FMT_M1; 1562 break; 1563 case 0x1: 1564 op = ASM_OP_LD2_, fmt = ASM_FMT_M1; 1565 break; 1566 case 0x2: 1567 op = ASM_OP_LD4_, fmt = ASM_FMT_M1; 1568 break; 1569 case 0x3: 1570 op = ASM_OP_LD8_, fmt = ASM_FMT_M1; 1571 break; 1572 case 0x4: 1573 op = ASM_OP_LD1_S, fmt = ASM_FMT_M1; 1574 break; 1575 case 0x5: 1576 op = ASM_OP_LD2_S, fmt = ASM_FMT_M1; 1577 break; 1578 case 0x6: 1579 op = ASM_OP_LD4_S, fmt = ASM_FMT_M1; 1580 break; 1581 case 0x7: 1582 op = ASM_OP_LD8_S, fmt = ASM_FMT_M1; 1583 break; 1584 case 0x8: 1585 op = ASM_OP_LD1_A, fmt = ASM_FMT_M1; 1586 break; 1587 case 0x9: 1588 op = ASM_OP_LD2_A, fmt = ASM_FMT_M1; 1589 break; 1590 case 0xA: 1591 op = ASM_OP_LD4_A, fmt = ASM_FMT_M1; 1592 break; 1593 case 0xB: 1594 op = ASM_OP_LD8_A, fmt = ASM_FMT_M1; 1595 break; 1596 case 0xC: 1597 op = ASM_OP_LD1_SA, fmt = ASM_FMT_M1; 1598 break; 1599 case 0xD: 1600 op = ASM_OP_LD2_SA, fmt = ASM_FMT_M1; 1601 break; 1602 case 0xE: 1603 op = ASM_OP_LD4_SA, fmt = ASM_FMT_M1; 1604 break; 1605 case 0xF: 1606 op = ASM_OP_LD8_SA, fmt = ASM_FMT_M1; 1607 break; 1608 case 0x10: 1609 op = ASM_OP_LD1_BIAS, fmt = ASM_FMT_M1; 1610 break; 1611 case 0x11: 1612 op = ASM_OP_LD2_BIAS, fmt = ASM_FMT_M1; 1613 break; 1614 case 0x12: 1615 op = ASM_OP_LD4_BIAS, fmt = ASM_FMT_M1; 1616 break; 1617 case 0x13: 1618 op = ASM_OP_LD8_BIAS, fmt = ASM_FMT_M1; 1619 break; 1620 case 0x14: 1621 op = ASM_OP_LD1_ACQ, fmt = ASM_FMT_M1; 1622 break; 1623 case 0x15: 1624 op = ASM_OP_LD2_ACQ, fmt = ASM_FMT_M1; 1625 break; 1626 case 0x16: 1627 op = ASM_OP_LD4_ACQ, fmt = ASM_FMT_M1; 1628 break; 1629 case 0x17: 1630 op = ASM_OP_LD8_ACQ, fmt = ASM_FMT_M1; 1631 break; 1632 case 0x1B: 1633 op = ASM_OP_LD8_FILL, fmt = ASM_FMT_M1; 1634 break; 1635 case 0x20: 1636 op = ASM_OP_LD1_C_CLR, fmt = ASM_FMT_M1; 1637 break; 1638 case 0x21: 1639 op = ASM_OP_LD2_C_CLR, fmt = ASM_FMT_M1; 1640 break; 1641 case 0x22: 1642 op = ASM_OP_LD4_C_CLR, fmt = ASM_FMT_M1; 1643 break; 1644 case 0x23: 1645 op = ASM_OP_LD8_C_CLR, fmt = ASM_FMT_M1; 1646 break; 1647 case 0x24: 1648 op = ASM_OP_LD1_C_NC, fmt = ASM_FMT_M1; 1649 break; 1650 case 0x25: 1651 op = ASM_OP_LD2_C_NC, fmt = ASM_FMT_M1; 1652 break; 1653 case 0x26: 1654 op = ASM_OP_LD4_C_NC, fmt = ASM_FMT_M1; 1655 break; 1656 case 0x27: 1657 op = ASM_OP_LD8_C_NC, fmt = ASM_FMT_M1; 1658 break; 1659 case 0x28: 1660 op = ASM_OP_LD1_C_CLR_ACQ, fmt = ASM_FMT_M1; 1661 break; 1662 case 0x29: 1663 op = ASM_OP_LD2_C_CLR_ACQ, fmt = ASM_FMT_M1; 1664 break; 1665 case 0x2A: 1666 op = ASM_OP_LD4_C_CLR_ACQ, fmt = ASM_FMT_M1; 1667 break; 1668 case 0x2B: 1669 op = ASM_OP_LD8_C_CLR_ACQ, fmt = ASM_FMT_M1; 1670 break; 1671 case 0x30: 1672 op = ASM_OP_ST1_, fmt = ASM_FMT_M4; 1673 break; 1674 case 0x31: 1675 op = ASM_OP_ST2_, fmt = ASM_FMT_M4; 1676 break; 1677 case 0x32: 1678 op = ASM_OP_ST4_, fmt = ASM_FMT_M4; 1679 break; 1680 case 0x33: 1681 op = ASM_OP_ST8_, fmt = ASM_FMT_M4; 1682 break; 1683 case 0x34: 1684 op = ASM_OP_ST1_REL, fmt = ASM_FMT_M4; 1685 break; 1686 case 0x35: 1687 op = ASM_OP_ST2_REL, fmt = ASM_FMT_M4; 1688 break; 1689 case 0x36: 1690 op = ASM_OP_ST4_REL, fmt = ASM_FMT_M4; 1691 break; 1692 case 0x37: 1693 op = ASM_OP_ST8_REL, fmt = ASM_FMT_M4; 1694 break; 1695 case 0x3B: 1696 op = ASM_OP_ST8_SPILL, fmt = ASM_FMT_M4; 1697 break; 1698 case 0x40: 1699 op = ASM_OP_LD1_, fmt = ASM_FMT_M2; 1700 break; 1701 case 0x41: 1702 op = ASM_OP_LD2_, fmt = ASM_FMT_M2; 1703 break; 1704 case 0x42: 1705 op = ASM_OP_LD4_, fmt = ASM_FMT_M2; 1706 break; 1707 case 0x43: 1708 op = ASM_OP_LD8_, fmt = ASM_FMT_M2; 1709 break; 1710 case 0x44: 1711 op = ASM_OP_LD1_S, fmt = ASM_FMT_M2; 1712 break; 1713 case 0x45: 1714 op = ASM_OP_LD2_S, fmt = ASM_FMT_M2; 1715 break; 1716 case 0x46: 1717 op = ASM_OP_LD4_S, fmt = ASM_FMT_M2; 1718 break; 1719 case 0x47: 1720 op = ASM_OP_LD8_S, fmt = ASM_FMT_M2; 1721 break; 1722 case 0x48: 1723 op = ASM_OP_LD1_A, fmt = ASM_FMT_M2; 1724 break; 1725 case 0x49: 1726 op = ASM_OP_LD2_A, fmt = ASM_FMT_M2; 1727 break; 1728 case 0x4A: 1729 op = ASM_OP_LD4_A, fmt = ASM_FMT_M2; 1730 break; 1731 case 0x4B: 1732 op = ASM_OP_LD8_A, fmt = ASM_FMT_M2; 1733 break; 1734 case 0x4C: 1735 op = ASM_OP_LD1_SA, fmt = ASM_FMT_M2; 1736 break; 1737 case 0x4D: 1738 op = ASM_OP_LD2_SA, fmt = ASM_FMT_M2; 1739 break; 1740 case 0x4E: 1741 op = ASM_OP_LD4_SA, fmt = ASM_FMT_M2; 1742 break; 1743 case 0x4F: 1744 op = ASM_OP_LD8_SA, fmt = ASM_FMT_M2; 1745 break; 1746 case 0x50: 1747 op = ASM_OP_LD1_BIAS, fmt = ASM_FMT_M2; 1748 break; 1749 case 0x51: 1750 op = ASM_OP_LD2_BIAS, fmt = ASM_FMT_M2; 1751 break; 1752 case 0x52: 1753 op = ASM_OP_LD4_BIAS, fmt = ASM_FMT_M2; 1754 break; 1755 case 0x53: 1756 op = ASM_OP_LD8_BIAS, fmt = ASM_FMT_M2; 1757 break; 1758 case 0x54: 1759 op = ASM_OP_LD1_ACQ, fmt = ASM_FMT_M2; 1760 break; 1761 case 0x55: 1762 op = ASM_OP_LD2_ACQ, fmt = ASM_FMT_M2; 1763 break; 1764 case 0x56: 1765 op = ASM_OP_LD4_ACQ, fmt = ASM_FMT_M2; 1766 break; 1767 case 0x57: 1768 op = ASM_OP_LD8_ACQ, fmt = ASM_FMT_M2; 1769 break; 1770 case 0x5B: 1771 op = ASM_OP_LD8_FILL, fmt = ASM_FMT_M2; 1772 break; 1773 case 0x60: 1774 op = ASM_OP_LD1_C_CLR, fmt = ASM_FMT_M2; 1775 break; 1776 case 0x61: 1777 op = ASM_OP_LD2_C_CLR, fmt = ASM_FMT_M2; 1778 break; 1779 case 0x62: 1780 op = ASM_OP_LD4_C_CLR, fmt = ASM_FMT_M2; 1781 break; 1782 case 0x63: 1783 op = ASM_OP_LD8_C_CLR, fmt = ASM_FMT_M2; 1784 break; 1785 case 0x64: 1786 op = ASM_OP_LD1_C_NC, fmt = ASM_FMT_M2; 1787 break; 1788 case 0x65: 1789 op = ASM_OP_LD2_C_NC, fmt = ASM_FMT_M2; 1790 break; 1791 case 0x66: 1792 op = ASM_OP_LD4_C_NC, fmt = ASM_FMT_M2; 1793 break; 1794 case 0x67: 1795 op = ASM_OP_LD8_C_NC, fmt = ASM_FMT_M2; 1796 break; 1797 case 0x68: 1798 op = ASM_OP_LD1_C_CLR_ACQ, fmt = ASM_FMT_M2; 1799 break; 1800 case 0x69: 1801 op = ASM_OP_LD2_C_CLR_ACQ, fmt = ASM_FMT_M2; 1802 break; 1803 case 0x6A: 1804 op = ASM_OP_LD4_C_CLR_ACQ, fmt = ASM_FMT_M2; 1805 break; 1806 case 0x6B: 1807 op = ASM_OP_LD8_C_CLR_ACQ, fmt = ASM_FMT_M2; 1808 break; 1809 } 1810 } else { 1811 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 1812 case 0x0: 1813 op = ASM_OP_CMPXCHG1_ACQ, fmt = ASM_FMT_M16; 1814 break; 1815 case 0x1: 1816 op = ASM_OP_CMPXCHG2_ACQ, fmt = ASM_FMT_M16; 1817 break; 1818 case 0x2: 1819 op = ASM_OP_CMPXCHG4_ACQ, fmt = ASM_FMT_M16; 1820 break; 1821 case 0x3: 1822 op = ASM_OP_CMPXCHG8_ACQ, fmt = ASM_FMT_M16; 1823 break; 1824 case 0x4: 1825 op = ASM_OP_CMPXCHG1_REL, fmt = ASM_FMT_M16; 1826 break; 1827 case 0x5: 1828 op = ASM_OP_CMPXCHG2_REL, fmt = ASM_FMT_M16; 1829 break; 1830 case 0x6: 1831 op = ASM_OP_CMPXCHG4_REL, fmt = ASM_FMT_M16; 1832 break; 1833 case 0x7: 1834 op = ASM_OP_CMPXCHG8_REL, fmt = ASM_FMT_M16; 1835 break; 1836 case 0x8: 1837 op = ASM_OP_XCHG1, fmt = ASM_FMT_M16; 1838 break; 1839 case 0x9: 1840 op = ASM_OP_XCHG2, fmt = ASM_FMT_M16; 1841 break; 1842 case 0xA: 1843 op = ASM_OP_XCHG4, fmt = ASM_FMT_M16; 1844 break; 1845 case 0xB: 1846 op = ASM_OP_XCHG8, fmt = ASM_FMT_M16; 1847 break; 1848 case 0x12: 1849 op = ASM_OP_FETCHADD4_ACQ, fmt = ASM_FMT_M17; 1850 break; 1851 case 0x13: 1852 op = ASM_OP_FETCHADD8_ACQ, fmt = ASM_FMT_M17; 1853 break; 1854 case 0x16: 1855 op = ASM_OP_FETCHADD4_REL, fmt = ASM_FMT_M17; 1856 break; 1857 case 0x17: 1858 op = ASM_OP_FETCHADD8_REL, fmt = ASM_FMT_M17; 1859 break; 1860 case 0x1C: 1861 op = ASM_OP_GETF_SIG, fmt = ASM_FMT_M19; 1862 break; 1863 case 0x1D: 1864 op = ASM_OP_GETF_EXP, fmt = ASM_FMT_M19; 1865 break; 1866 case 0x1E: 1867 op = ASM_OP_GETF_S, fmt = ASM_FMT_M19; 1868 break; 1869 case 0x1F: 1870 op = ASM_OP_GETF_D, fmt = ASM_FMT_M19; 1871 break; 1872 case 0x20: 1873 op = ASM_OP_CMP8XCHG16_ACQ, fmt = ASM_FMT_M16; 1874 break; 1875 case 0x24: 1876 op = ASM_OP_CMP8XCHG16_REL, fmt = ASM_FMT_M16; 1877 break; 1878 case 0x28: 1879 op = ASM_OP_LD16_, fmt = ASM_FMT_M1; 1880 break; 1881 case 0x2C: 1882 op = ASM_OP_LD16_ACQ, fmt = ASM_FMT_M1; 1883 break; 1884 case 0x30: 1885 op = ASM_OP_ST16_, fmt = ASM_FMT_M4; 1886 break; 1887 case 0x34: 1888 op = ASM_OP_ST16_REL, fmt = ASM_FMT_M4; 1889 break; 1890 } 1891 } 1892 break; 1893 case 0x5: 1894 switch (FIELD(bits, 30, 6)) { /* x6 */ 1895 case 0x0: 1896 op = ASM_OP_LD1_, fmt = ASM_FMT_M3; 1897 break; 1898 case 0x1: 1899 op = ASM_OP_LD2_, fmt = ASM_FMT_M3; 1900 break; 1901 case 0x2: 1902 op = ASM_OP_LD4_, fmt = ASM_FMT_M3; 1903 break; 1904 case 0x3: 1905 op = ASM_OP_LD8_, fmt = ASM_FMT_M3; 1906 break; 1907 case 0x4: 1908 op = ASM_OP_LD1_S, fmt = ASM_FMT_M3; 1909 break; 1910 case 0x5: 1911 op = ASM_OP_LD2_S, fmt = ASM_FMT_M3; 1912 break; 1913 case 0x6: 1914 op = ASM_OP_LD4_S, fmt = ASM_FMT_M3; 1915 break; 1916 case 0x7: 1917 op = ASM_OP_LD8_S, fmt = ASM_FMT_M3; 1918 break; 1919 case 0x8: 1920 op = ASM_OP_LD1_A, fmt = ASM_FMT_M3; 1921 break; 1922 case 0x9: 1923 op = ASM_OP_LD2_A, fmt = ASM_FMT_M3; 1924 break; 1925 case 0xA: 1926 op = ASM_OP_LD4_A, fmt = ASM_FMT_M3; 1927 break; 1928 case 0xB: 1929 op = ASM_OP_LD8_A, fmt = ASM_FMT_M3; 1930 break; 1931 case 0xC: 1932 op = ASM_OP_LD1_SA, fmt = ASM_FMT_M3; 1933 break; 1934 case 0xD: 1935 op = ASM_OP_LD2_SA, fmt = ASM_FMT_M3; 1936 break; 1937 case 0xE: 1938 op = ASM_OP_LD4_SA, fmt = ASM_FMT_M3; 1939 break; 1940 case 0xF: 1941 op = ASM_OP_LD8_SA, fmt = ASM_FMT_M3; 1942 break; 1943 case 0x10: 1944 op = ASM_OP_LD1_BIAS, fmt = ASM_FMT_M3; 1945 break; 1946 case 0x11: 1947 op = ASM_OP_LD2_BIAS, fmt = ASM_FMT_M3; 1948 break; 1949 case 0x12: 1950 op = ASM_OP_LD4_BIAS, fmt = ASM_FMT_M3; 1951 break; 1952 case 0x13: 1953 op = ASM_OP_LD8_BIAS, fmt = ASM_FMT_M3; 1954 break; 1955 case 0x14: 1956 op = ASM_OP_LD1_ACQ, fmt = ASM_FMT_M3; 1957 break; 1958 case 0x15: 1959 op = ASM_OP_LD2_ACQ, fmt = ASM_FMT_M3; 1960 break; 1961 case 0x16: 1962 op = ASM_OP_LD4_ACQ, fmt = ASM_FMT_M3; 1963 break; 1964 case 0x17: 1965 op = ASM_OP_LD8_ACQ, fmt = ASM_FMT_M3; 1966 break; 1967 case 0x1B: 1968 op = ASM_OP_LD8_FILL, fmt = ASM_FMT_M3; 1969 break; 1970 case 0x20: 1971 op = ASM_OP_LD1_C_CLR, fmt = ASM_FMT_M3; 1972 break; 1973 case 0x21: 1974 op = ASM_OP_LD2_C_CLR, fmt = ASM_FMT_M3; 1975 break; 1976 case 0x22: 1977 op = ASM_OP_LD4_C_CLR, fmt = ASM_FMT_M3; 1978 break; 1979 case 0x23: 1980 op = ASM_OP_LD8_C_CLR, fmt = ASM_FMT_M3; 1981 break; 1982 case 0x24: 1983 op = ASM_OP_LD1_C_NC, fmt = ASM_FMT_M3; 1984 break; 1985 case 0x25: 1986 op = ASM_OP_LD2_C_NC, fmt = ASM_FMT_M3; 1987 break; 1988 case 0x26: 1989 op = ASM_OP_LD4_C_NC, fmt = ASM_FMT_M3; 1990 break; 1991 case 0x27: 1992 op = ASM_OP_LD8_C_NC, fmt = ASM_FMT_M3; 1993 break; 1994 case 0x28: 1995 op = ASM_OP_LD1_C_CLR_ACQ, fmt = ASM_FMT_M3; 1996 break; 1997 case 0x29: 1998 op = ASM_OP_LD2_C_CLR_ACQ, fmt = ASM_FMT_M3; 1999 break; 2000 case 0x2A: 2001 op = ASM_OP_LD4_C_CLR_ACQ, fmt = ASM_FMT_M3; 2002 break; 2003 case 0x2B: 2004 op = ASM_OP_LD8_C_CLR_ACQ, fmt = ASM_FMT_M3; 2005 break; 2006 case 0x30: 2007 op = ASM_OP_ST1_, fmt = ASM_FMT_M5; 2008 break; 2009 case 0x31: 2010 op = ASM_OP_ST2_, fmt = ASM_FMT_M5; 2011 break; 2012 case 0x32: 2013 op = ASM_OP_ST4_, fmt = ASM_FMT_M5; 2014 break; 2015 case 0x33: 2016 op = ASM_OP_ST8_, fmt = ASM_FMT_M5; 2017 break; 2018 case 0x34: 2019 op = ASM_OP_ST1_REL, fmt = ASM_FMT_M5; 2020 break; 2021 case 0x35: 2022 op = ASM_OP_ST2_REL, fmt = ASM_FMT_M5; 2023 break; 2024 case 0x36: 2025 op = ASM_OP_ST4_REL, fmt = ASM_FMT_M5; 2026 break; 2027 case 0x37: 2028 op = ASM_OP_ST8_REL, fmt = ASM_FMT_M5; 2029 break; 2030 case 0x3B: 2031 op = ASM_OP_ST8_SPILL, fmt = ASM_FMT_M5; 2032 break; 2033 } 2034 break; 2035 case 0x6: 2036 if (FIELD(bits, 27, 1) == 0) { /* x */ 2037 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 2038 case 0x0: 2039 op = ASM_OP_LDFE_, fmt = ASM_FMT_M6; 2040 break; 2041 case 0x1: 2042 op = ASM_OP_LDF8_, fmt = ASM_FMT_M6; 2043 break; 2044 case 0x2: 2045 op = ASM_OP_LDFS_, fmt = ASM_FMT_M6; 2046 break; 2047 case 0x3: 2048 op = ASM_OP_LDFD_, fmt = ASM_FMT_M6; 2049 break; 2050 case 0x4: 2051 op = ASM_OP_LDFE_S, fmt = ASM_FMT_M6; 2052 break; 2053 case 0x5: 2054 op = ASM_OP_LDF8_S, fmt = ASM_FMT_M6; 2055 break; 2056 case 0x6: 2057 op = ASM_OP_LDFS_S, fmt = ASM_FMT_M6; 2058 break; 2059 case 0x7: 2060 op = ASM_OP_LDFD_S, fmt = ASM_FMT_M6; 2061 break; 2062 case 0x8: 2063 op = ASM_OP_LDFE_A, fmt = ASM_FMT_M6; 2064 break; 2065 case 0x9: 2066 op = ASM_OP_LDF8_A, fmt = ASM_FMT_M6; 2067 break; 2068 case 0xA: 2069 op = ASM_OP_LDFS_A, fmt = ASM_FMT_M6; 2070 break; 2071 case 0xB: 2072 op = ASM_OP_LDFD_A, fmt = ASM_FMT_M6; 2073 break; 2074 case 0xC: 2075 op = ASM_OP_LDFE_SA, fmt = ASM_FMT_M6; 2076 break; 2077 case 0xD: 2078 op = ASM_OP_LDF8_SA, fmt = ASM_FMT_M6; 2079 break; 2080 case 0xE: 2081 op = ASM_OP_LDFS_SA, fmt = ASM_FMT_M6; 2082 break; 2083 case 0xF: 2084 op = ASM_OP_LDFD_SA, fmt = ASM_FMT_M6; 2085 break; 2086 case 0x1B: 2087 op = ASM_OP_LDF_FILL, fmt = ASM_FMT_M6; 2088 break; 2089 case 0x20: 2090 op = ASM_OP_LDFE_C_CLR, fmt = ASM_FMT_M6; 2091 break; 2092 case 0x21: 2093 op = ASM_OP_LDF8_C_CLR, fmt = ASM_FMT_M6; 2094 break; 2095 case 0x22: 2096 op = ASM_OP_LDFS_C_CLR, fmt = ASM_FMT_M6; 2097 break; 2098 case 0x23: 2099 op = ASM_OP_LDFD_C_CLR, fmt = ASM_FMT_M6; 2100 break; 2101 case 0x24: 2102 op = ASM_OP_LDFE_C_NC, fmt = ASM_FMT_M6; 2103 break; 2104 case 0x25: 2105 op = ASM_OP_LDF8_C_NC, fmt = ASM_FMT_M6; 2106 break; 2107 case 0x26: 2108 op = ASM_OP_LDFS_C_NC, fmt = ASM_FMT_M6; 2109 break; 2110 case 0x27: 2111 op = ASM_OP_LDFD_C_NC, fmt = ASM_FMT_M6; 2112 break; 2113 case 0x2C: 2114 op = ASM_OP_LFETCH_, fmt = ASM_FMT_M13; 2115 break; 2116 case 0x2D: 2117 op = ASM_OP_LFETCH_EXCL, fmt = ASM_FMT_M13; 2118 break; 2119 case 0x2E: 2120 op = ASM_OP_LFETCH_FAULT, fmt = ASM_FMT_M13; 2121 break; 2122 case 0x2F: 2123 op = ASM_OP_LFETCH_FAULT_EXCL, 2124 fmt = ASM_FMT_M13; 2125 break; 2126 case 0x30: 2127 op = ASM_OP_STFE, fmt = ASM_FMT_M9; 2128 break; 2129 case 0x31: 2130 op = ASM_OP_STF8, fmt = ASM_FMT_M9; 2131 break; 2132 case 0x32: 2133 op = ASM_OP_STFS, fmt = ASM_FMT_M9; 2134 break; 2135 case 0x33: 2136 op = ASM_OP_STFD, fmt = ASM_FMT_M9; 2137 break; 2138 case 0x3B: 2139 op = ASM_OP_STF_SPILL, fmt = ASM_FMT_M9; 2140 break; 2141 case 0x40: 2142 op = ASM_OP_LDFE_, fmt = ASM_FMT_M7; 2143 break; 2144 case 0x41: 2145 op = ASM_OP_LDF8_, fmt = ASM_FMT_M7; 2146 break; 2147 case 0x42: 2148 op = ASM_OP_LDFS_, fmt = ASM_FMT_M7; 2149 break; 2150 case 0x43: 2151 op = ASM_OP_LDFD_, fmt = ASM_FMT_M7; 2152 break; 2153 case 0x44: 2154 op = ASM_OP_LDFE_S, fmt = ASM_FMT_M7; 2155 break; 2156 case 0x45: 2157 op = ASM_OP_LDF8_S, fmt = ASM_FMT_M7; 2158 break; 2159 case 0x46: 2160 op = ASM_OP_LDFS_S, fmt = ASM_FMT_M7; 2161 break; 2162 case 0x47: 2163 op = ASM_OP_LDFD_S, fmt = ASM_FMT_M7; 2164 break; 2165 case 0x48: 2166 op = ASM_OP_LDFE_A, fmt = ASM_FMT_M7; 2167 break; 2168 case 0x49: 2169 op = ASM_OP_LDF8_A, fmt = ASM_FMT_M7; 2170 break; 2171 case 0x4A: 2172 op = ASM_OP_LDFS_A, fmt = ASM_FMT_M7; 2173 break; 2174 case 0x4B: 2175 op = ASM_OP_LDFD_A, fmt = ASM_FMT_M7; 2176 break; 2177 case 0x4C: 2178 op = ASM_OP_LDFE_SA, fmt = ASM_FMT_M7; 2179 break; 2180 case 0x4D: 2181 op = ASM_OP_LDF8_SA, fmt = ASM_FMT_M7; 2182 break; 2183 case 0x4E: 2184 op = ASM_OP_LDFS_SA, fmt = ASM_FMT_M7; 2185 break; 2186 case 0x4F: 2187 op = ASM_OP_LDFD_SA, fmt = ASM_FMT_M7; 2188 break; 2189 case 0x5B: 2190 op = ASM_OP_LDF_FILL, fmt = ASM_FMT_M7; 2191 break; 2192 case 0x60: 2193 op = ASM_OP_LDFE_C_CLR, fmt = ASM_FMT_M7; 2194 break; 2195 case 0x61: 2196 op = ASM_OP_LDF8_C_CLR, fmt = ASM_FMT_M7; 2197 break; 2198 case 0x62: 2199 op = ASM_OP_LDFS_C_CLR, fmt = ASM_FMT_M7; 2200 break; 2201 case 0x63: 2202 op = ASM_OP_LDFD_C_CLR, fmt = ASM_FMT_M7; 2203 break; 2204 case 0x64: 2205 op = ASM_OP_LDFE_C_NC, fmt = ASM_FMT_M7; 2206 break; 2207 case 0x65: 2208 op = ASM_OP_LDF8_C_NC, fmt = ASM_FMT_M7; 2209 break; 2210 case 0x66: 2211 op = ASM_OP_LDFS_C_NC, fmt = ASM_FMT_M7; 2212 break; 2213 case 0x67: 2214 op = ASM_OP_LDFD_C_NC, fmt = ASM_FMT_M7; 2215 break; 2216 case 0x6C: 2217 op = ASM_OP_LFETCH_, fmt = ASM_FMT_M14; 2218 break; 2219 case 0x6D: 2220 op = ASM_OP_LFETCH_EXCL, fmt = ASM_FMT_M14; 2221 break; 2222 case 0x6E: 2223 op = ASM_OP_LFETCH_FAULT, fmt = ASM_FMT_M14; 2224 break; 2225 case 0x6F: 2226 op = ASM_OP_LFETCH_FAULT_EXCL, 2227 fmt = ASM_FMT_M14; 2228 break; 2229 } 2230 } else { 2231 switch (FIELD(bits, 30, 7)) { /* x6 + m */ 2232 case 0x1: 2233 op = ASM_OP_LDFP8_, fmt = ASM_FMT_M11; 2234 break; 2235 case 0x2: 2236 op = ASM_OP_LDFPS_, fmt = ASM_FMT_M11; 2237 break; 2238 case 0x3: 2239 op = ASM_OP_LDFPD_, fmt = ASM_FMT_M11; 2240 break; 2241 case 0x5: 2242 op = ASM_OP_LDFP8_S, fmt = ASM_FMT_M11; 2243 break; 2244 case 0x6: 2245 op = ASM_OP_LDFPS_S, fmt = ASM_FMT_M11; 2246 break; 2247 case 0x7: 2248 op = ASM_OP_LDFPD_S, fmt = ASM_FMT_M11; 2249 break; 2250 case 0x9: 2251 op = ASM_OP_LDFP8_A, fmt = ASM_FMT_M11; 2252 break; 2253 case 0xA: 2254 op = ASM_OP_LDFPS_A, fmt = ASM_FMT_M11; 2255 break; 2256 case 0xB: 2257 op = ASM_OP_LDFPD_A, fmt = ASM_FMT_M11; 2258 break; 2259 case 0xD: 2260 op = ASM_OP_LDFP8_SA, fmt = ASM_FMT_M11; 2261 break; 2262 case 0xE: 2263 op = ASM_OP_LDFPS_SA, fmt = ASM_FMT_M11; 2264 break; 2265 case 0xF: 2266 op = ASM_OP_LDFPD_SA, fmt = ASM_FMT_M11; 2267 break; 2268 case 0x1C: 2269 op = ASM_OP_SETF_SIG, fmt = ASM_FMT_M18; 2270 break; 2271 case 0x1D: 2272 op = ASM_OP_SETF_EXP, fmt = ASM_FMT_M18; 2273 break; 2274 case 0x1E: 2275 op = ASM_OP_SETF_S, fmt = ASM_FMT_M18; 2276 break; 2277 case 0x1F: 2278 op = ASM_OP_SETF_D, fmt = ASM_FMT_M18; 2279 break; 2280 case 0x21: 2281 op = ASM_OP_LDFP8_C_CLR, fmt = ASM_FMT_M11; 2282 break; 2283 case 0x22: 2284 op = ASM_OP_LDFPS_C_CLR, fmt = ASM_FMT_M11; 2285 break; 2286 case 0x23: 2287 op = ASM_OP_LDFPD_C_CLR, fmt = ASM_FMT_M11; 2288 break; 2289 case 0x25: 2290 op = ASM_OP_LDFP8_C_NC, fmt = ASM_FMT_M11; 2291 break; 2292 case 0x26: 2293 op = ASM_OP_LDFPS_C_NC, fmt = ASM_FMT_M11; 2294 break; 2295 case 0x27: 2296 op = ASM_OP_LDFPD_C_NC, fmt = ASM_FMT_M11; 2297 break; 2298 case 0x41: 2299 op = ASM_OP_LDFP8_, fmt = ASM_FMT_M12; 2300 break; 2301 case 0x42: 2302 op = ASM_OP_LDFPS_, fmt = ASM_FMT_M12; 2303 break; 2304 case 0x43: 2305 op = ASM_OP_LDFPD_, fmt = ASM_FMT_M12; 2306 break; 2307 case 0x45: 2308 op = ASM_OP_LDFP8_S, fmt = ASM_FMT_M12; 2309 break; 2310 case 0x46: 2311 op = ASM_OP_LDFPS_S, fmt = ASM_FMT_M12; 2312 break; 2313 case 0x47: 2314 op = ASM_OP_LDFPD_S, fmt = ASM_FMT_M12; 2315 break; 2316 case 0x49: 2317 op = ASM_OP_LDFP8_A, fmt = ASM_FMT_M12; 2318 break; 2319 case 0x4A: 2320 op = ASM_OP_LDFPS_A, fmt = ASM_FMT_M12; 2321 break; 2322 case 0x4B: 2323 op = ASM_OP_LDFPD_A, fmt = ASM_FMT_M12; 2324 break; 2325 case 0x4D: 2326 op = ASM_OP_LDFP8_SA, fmt = ASM_FMT_M12; 2327 break; 2328 case 0x4E: 2329 op = ASM_OP_LDFPS_SA, fmt = ASM_FMT_M12; 2330 break; 2331 case 0x4F: 2332 op = ASM_OP_LDFPD_SA, fmt = ASM_FMT_M12; 2333 break; 2334 case 0x61: 2335 op = ASM_OP_LDFP8_C_CLR, fmt = ASM_FMT_M12; 2336 break; 2337 case 0x62: 2338 op = ASM_OP_LDFPS_C_CLR, fmt = ASM_FMT_M12; 2339 break; 2340 case 0x63: 2341 op = ASM_OP_LDFPD_C_CLR, fmt = ASM_FMT_M12; 2342 break; 2343 case 0x65: 2344 op = ASM_OP_LDFP8_C_NC, fmt = ASM_FMT_M12; 2345 break; 2346 case 0x66: 2347 op = ASM_OP_LDFPS_C_NC, fmt = ASM_FMT_M12; 2348 break; 2349 case 0x67: 2350 op = ASM_OP_LDFPD_C_NC, fmt = ASM_FMT_M12; 2351 break; 2352 } 2353 } 2354 break; 2355 case 0x7: 2356 switch (FIELD(bits, 30, 6)) { /* x6 */ 2357 case 0x0: 2358 op = ASM_OP_LDFE_, fmt = ASM_FMT_M8; 2359 break; 2360 case 0x1: 2361 op = ASM_OP_LDF8_, fmt = ASM_FMT_M8; 2362 break; 2363 case 0x2: 2364 op = ASM_OP_LDFS_, fmt = ASM_FMT_M8; 2365 break; 2366 case 0x3: 2367 op = ASM_OP_LDFD_, fmt = ASM_FMT_M8; 2368 break; 2369 case 0x4: 2370 op = ASM_OP_LDFE_S, fmt = ASM_FMT_M8; 2371 break; 2372 case 0x5: 2373 op = ASM_OP_LDF8_S, fmt = ASM_FMT_M8; 2374 break; 2375 case 0x6: 2376 op = ASM_OP_LDFS_S, fmt = ASM_FMT_M8; 2377 break; 2378 case 0x7: 2379 op = ASM_OP_LDFD_S, fmt = ASM_FMT_M8; 2380 break; 2381 case 0x8: 2382 op = ASM_OP_LDFE_A, fmt = ASM_FMT_M8; 2383 break; 2384 case 0x9: 2385 op = ASM_OP_LDF8_A, fmt = ASM_FMT_M8; 2386 break; 2387 case 0xA: 2388 op = ASM_OP_LDFS_A, fmt = ASM_FMT_M8; 2389 break; 2390 case 0xB: 2391 op = ASM_OP_LDFD_A, fmt = ASM_FMT_M8; 2392 break; 2393 case 0xC: 2394 op = ASM_OP_LDFE_SA, fmt = ASM_FMT_M8; 2395 break; 2396 case 0xD: 2397 op = ASM_OP_LDF8_SA, fmt = ASM_FMT_M8; 2398 break; 2399 case 0xE: 2400 op = ASM_OP_LDFS_SA, fmt = ASM_FMT_M8; 2401 break; 2402 case 0xF: 2403 op = ASM_OP_LDFD_SA, fmt = ASM_FMT_M8; 2404 break; 2405 case 0x1B: 2406 op = ASM_OP_LDF_FILL, fmt = ASM_FMT_M8; 2407 break; 2408 case 0x20: 2409 op = ASM_OP_LDFE_C_CLR, fmt = ASM_FMT_M8; 2410 break; 2411 case 0x21: 2412 op = ASM_OP_LDF8_C_CLR, fmt = ASM_FMT_M8; 2413 break; 2414 case 0x22: 2415 op = ASM_OP_LDFS_C_CLR, fmt = ASM_FMT_M8; 2416 break; 2417 case 0x23: 2418 op = ASM_OP_LDFD_C_CLR, fmt = ASM_FMT_M8; 2419 break; 2420 case 0x24: 2421 op = ASM_OP_LDFE_C_NC, fmt = ASM_FMT_M8; 2422 break; 2423 case 0x25: 2424 op = ASM_OP_LDF8_C_NC, fmt = ASM_FMT_M8; 2425 break; 2426 case 0x26: 2427 op = ASM_OP_LDFS_C_NC, fmt = ASM_FMT_M8; 2428 break; 2429 case 0x27: 2430 op = ASM_OP_LDFD_C_NC, fmt = ASM_FMT_M8; 2431 break; 2432 case 0x2C: 2433 op = ASM_OP_LFETCH_, fmt = ASM_FMT_M15; 2434 break; 2435 case 0x2D: 2436 op = ASM_OP_LFETCH_EXCL, fmt = ASM_FMT_M15; 2437 break; 2438 case 0x2E: 2439 op = ASM_OP_LFETCH_FAULT, fmt = ASM_FMT_M15; 2440 break; 2441 case 0x2F: 2442 op = ASM_OP_LFETCH_FAULT_EXCL, fmt = ASM_FMT_M15; 2443 break; 2444 case 0x30: 2445 op = ASM_OP_STFE, fmt = ASM_FMT_M10; 2446 break; 2447 case 0x31: 2448 op = ASM_OP_STF8, fmt = ASM_FMT_M10; 2449 break; 2450 case 0x32: 2451 op = ASM_OP_STFS, fmt = ASM_FMT_M10; 2452 break; 2453 case 0x33: 2454 op = ASM_OP_STFD, fmt = ASM_FMT_M10; 2455 break; 2456 case 0x3B: 2457 op = ASM_OP_STF_SPILL, fmt = ASM_FMT_M10; 2458 break; 2459 } 2460 break; 2461 } 2462 2463 if (op != ASM_OP_NONE) 2464 return (asm_extract(op, fmt, bits, b, slot)); 2465 return (0); 2466} 2467 2468/* 2469 * Decode X-unit instructions. 2470 */ 2471static int 2472asm_decodeX(uint64_t ip, struct asm_bundle *b, int slot) 2473{ 2474 uint64_t bits; 2475 enum asm_fmt fmt; 2476 enum asm_op op; 2477 2478 KASSERT(slot == 2, ("foo")); 2479 bits = SLOT(ip, slot); 2480 fmt = ASM_FMT_NONE, op = ASM_OP_NONE; 2481 /* Initialize slot 1 (slot - 1) */ 2482 b->b_inst[slot - 1].i_format = ASM_FMT_NONE; 2483 b->b_inst[slot - 1].i_bits = SLOT(ip, slot - 1); 2484 2485 switch((int)OPCODE(bits)) { 2486 case 0x0: 2487 if (FIELD(bits, 33, 3) == 0) { /* x3 */ 2488 switch (FIELD(bits, 27, 6)) { /* x6 */ 2489 case 0x0: 2490 op = ASM_OP_BREAK_X, fmt = ASM_FMT_X1; 2491 break; 2492 case 0x1: 2493 if (FIELD(bits, 26, 1) == 0) /* y */ 2494 op = ASM_OP_NOP_X, fmt = ASM_FMT_X5; 2495 else 2496 op = ASM_OP_HINT_X, fmt = ASM_FMT_X5; 2497 break; 2498 } 2499 } 2500 break; 2501 case 0x6: 2502 if (FIELD(bits, 20, 1) == 0) 2503 op = ASM_OP_MOVL, fmt = ASM_FMT_X2; 2504 break; 2505 case 0xC: 2506 if (FIELD(bits, 6, 3) == 0) /* btype */ 2507 op = ASM_OP_BRL_COND, fmt = ASM_FMT_X3; 2508 break; 2509 case 0xD: 2510 op = ASM_OP_BRL_CALL, fmt = ASM_FMT_X4; 2511 break; 2512 } 2513 2514 if (op != ASM_OP_NONE) 2515 return (asm_extract(op, fmt, bits, b, slot)); 2516 return (0); 2517} 2518 2519int 2520asm_decode(uint64_t ip, struct asm_bundle *b) 2521{ 2522 const char *tp; 2523 unsigned int slot; 2524 int ok; 2525 2526 memset(b, 0, sizeof(*b)); 2527 2528 b->b_templ = asm_templname[TMPL(ip)]; 2529 if (b->b_templ == 0) 2530 return (0); 2531 2532 slot = 0; 2533 tp = b->b_templ; 2534 2535 ok = 1; 2536 while (ok && *tp != 0) { 2537 switch (*tp++) { 2538 case 'B': 2539 ok = asm_decodeB(ip, b, slot++); 2540 break; 2541 case 'F': 2542 ok = asm_decodeF(ip, b, slot++); 2543 break; 2544 case 'I': 2545 ok = asm_decodeI(ip, b, slot++); 2546 break; 2547 case 'L': 2548 ok = (slot++ == 1) ? 1 : 0; 2549 break; 2550 case 'M': 2551 ok = asm_decodeM(ip, b, slot++); 2552 break; 2553 case 'X': 2554 ok = asm_decodeX(ip, b, slot++); 2555 break; 2556 case ';': 2557 ok = 1; 2558 break; 2559 default: 2560 ok = 0; 2561 break; 2562 } 2563 } 2564 return (ok); 2565} 2566