pci_pir.c revision 82026
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/i386/pci/pci_pir.c 82026 2001-08-21 03:10:55Z peter $ 29 * 30 */ 31 32#include <sys/param.h> /* XXX trim includes */ 33#include <sys/systm.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/malloc.h> 38#include <vm/vm.h> 39#include <vm/pmap.h> 40#include <machine/md_var.h> 41#include <pci/pcivar.h> 42#include <pci/pcireg.h> 43#include <isa/isavar.h> 44#include <machine/nexusvar.h> 45#include <machine/pci_cfgreg.h> 46#include <machine/segments.h> 47#include <machine/pc/bios.h> 48 49#ifdef APIC_IO 50#include <machine/smp.h> 51#endif /* APIC_IO */ 52 53#include "pcib_if.h" 54 55static int cfgmech; 56static int devmax; 57static int usebios; 58 59static int pci_cfgintr_unique(struct PIR_entry *pe, int pin); 60static int pci_cfgintr_linked(struct PIR_entry *pe, int pin); 61static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin); 62static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin); 63 64static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes); 65static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); 66static int pcibios_cfgopen(void); 67static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); 68static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); 69static int pcireg_cfgopen(void); 70 71static struct PIR_table *pci_route_table; 72static int pci_route_count; 73 74int 75pci_pcibios_active(void) 76{ 77 return usebios; 78} 79 80int 81pci_kill_pcibios(void) 82{ 83 usebios = 0; 84 return pcireg_cfgopen() != 0; 85} 86 87/* 88 * Initialise access to PCI configuration space 89 */ 90int 91pci_cfgregopen(void) 92{ 93 static int opened = 0; 94 u_long sigaddr; 95 static struct PIR_table *pt; 96 u_int8_t ck, *cv; 97 int i; 98 99 if (opened) 100 return(1); 101 102 if (pcibios_cfgopen() != 0) { 103 usebios = 1; 104 } else if (pcireg_cfgopen() != 0) { 105 usebios = 0; 106 } else { 107 return(0); 108 } 109 110 /* 111 * Look for the interrupt routing table. 112 */ 113 /* XXX use PCI BIOS if it's available */ 114 115 if ((pt == NULL) && ((sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0)) != 0)) { 116 pt = (struct PIR_table *)(uintptr_t)BIOS_PADDRTOVADDR(sigaddr); 117 for (cv = (u_int8_t *)pt, ck = 0, i = 0; i < (pt->pt_header.ph_length); i++) { 118 ck += cv[i]; 119 } 120 if (ck == 0) { 121 pci_route_table = pt; 122 pci_route_count = (pt->pt_header.ph_length - sizeof(struct PIR_header)) / sizeof(struct PIR_entry); 123 printf("Using $PIR table, %d entries at %p\n", pci_route_count, pci_route_table); 124 } 125 } 126 127 opened = 1; 128 return(1); 129} 130 131/* 132 * Read configuration space register 133 */ 134static u_int32_t 135pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes) 136{ 137 return(usebios ? 138 pcibios_cfgread(bus, slot, func, reg, bytes) : 139 pcireg_cfgread(bus, slot, func, reg, bytes)); 140} 141 142u_int32_t 143pci_cfgregread(int bus, int slot, int func, int reg, int bytes) 144{ 145#ifdef APIC_IO 146 /* 147 * If we are using the APIC, the contents of the intline register will probably 148 * be wrong (since they are set up for use with the PIC. 149 * Rather than rewrite these registers (maybe that would be smarter) we trap 150 * attempts to read them and translate to our private vector numbers. 151 */ 152 if ((reg == PCIR_INTLINE) && (bytes == 1)) { 153 int pin, line; 154 155 pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1); 156 line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1); 157 158 if (pin != 0) { 159 int airq; 160 161 airq = pci_apic_irq(bus, slot, pin); 162 if (airq >= 0) { 163 /* PCI specific entry found in MP table */ 164 if (airq != line) 165 undirect_pci_irq(line); 166 return(airq); 167 } else { 168 /* 169 * PCI interrupts might be redirected to the 170 * ISA bus according to some MP tables. Use the 171 * same methods as used by the ISA devices 172 * devices to find the proper IOAPIC int pin. 173 */ 174 airq = isa_apic_irq(line); 175 if ((airq >= 0) && (airq != line)) { 176 /* XXX: undirect_pci_irq() ? */ 177 undirect_isa_irq(line); 178 return(airq); 179 } 180 } 181 } 182 return(line); 183 } 184#endif /* APIC_IO */ 185 return(pci_do_cfgregread(bus, slot, func, reg, bytes)); 186} 187 188/* 189 * Write configuration space register 190 */ 191void 192pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) 193{ 194 return(usebios ? 195 pcibios_cfgwrite(bus, slot, func, reg, data, bytes) : 196 pcireg_cfgwrite(bus, slot, func, reg, data, bytes)); 197} 198 199/* 200 * Route a PCI interrupt 201 * 202 * XXX we don't do anything "right" with the function number in the PIR table 203 * (because the consumer isn't currently passing it in). We don't care 204 * anyway, due to the way PCI interrupts are assigned. 205 */ 206int 207pci_cfgintr(int bus, int device, int pin) 208{ 209 struct PIR_entry *pe; 210 int i, irq; 211 struct bios_regs args; 212 213 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) || 214 (pin < 1) || (pin > 4)) 215 return(255); 216 217 /* 218 * Scan the entry table for a contender 219 */ 220 for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count; i++, pe++) { 221 if ((bus != pe->pe_bus) || (device != pe->pe_device)) 222 continue; 223 224 irq = pci_cfgintr_unique(pe, pin); 225 if (irq == 255) 226 irq = pci_cfgintr_linked(pe, pin); 227 if (irq == 255) 228 irq = pci_cfgintr_virgin(pe, pin); 229 230 if (irq == 255) 231 break; 232 233 234 /* 235 * Ask the BIOS to route the interrupt 236 */ 237 args.eax = PCIBIOS_ROUTE_INTERRUPT; 238 args.ebx = (bus << 8) | (device << 3); 239 args.ecx = (irq << 8) | (0xa + pin - 1); /* pin value is 0xa - 0xd */ 240 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); 241 242 /* 243 * XXX if it fails, we should try to smack the router hardware directly 244 */ 245 246 printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", 247 bus, device, 'A' + pin - 1, irq); 248 return(irq); 249 } 250 251 printf("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus, device, 'A' + pin - 1); 252 return(255); 253} 254 255/* 256 * Look to see if the routing table claims this pin is uniquely routed. 257 */ 258static int 259pci_cfgintr_unique(struct PIR_entry *pe, int pin) 260{ 261 int irq; 262 263 if (powerof2(pe->pe_intpin[pin - 1].irqs)) { 264 irq = ffs(pe->pe_intpin[pin - 1].irqs) - 1; 265 printf("pci_cfgintr_unique: hard-routed to irq %d\n", irq); 266 return(irq); 267 } 268 return(255); 269} 270 271/* 272 * Look for another device which shares the same link byte and 273 * already has a unique IRQ, or which has had one routed already. 274 */ 275static int 276pci_cfgintr_linked(struct PIR_entry *pe, int pin) 277{ 278 struct PIR_entry *oe; 279 struct PIR_intpin *pi; 280 int i, j, irq; 281 282 /* 283 * Scan table slots. 284 */ 285 for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count; i++, oe++) { 286 287 /* scan interrupt pins */ 288 for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) { 289 290 /* don't look at the entry we're trying to match with */ 291 if ((pe == oe) && (i == (pin - 1))) 292 continue; 293 294 /* compare link bytes */ 295 if (pi->link != pe->pe_intpin[pin - 1].link) 296 continue; 297 298 /* link destination mapped to a unique interrupt? */ 299 if (powerof2(pi->irqs)) { 300 irq = ffs(pi->irqs) - 1; 301 printf("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n", 302 pi->link, irq); 303 return(irq); 304 } 305 306 /* look for the real PCI device that matches this table entry */ 307 if ((irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device, j, pin)) != 255) 308 return(irq); 309 } 310 } 311 return(255); 312} 313 314/* 315 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and 316 * see if it has already been assigned an interrupt. 317 */ 318static int 319pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin) 320{ 321 devclass_t pci_devclass; 322 device_t *pci_devices; 323 int pci_count; 324 device_t *pci_children; 325 int pci_childcount; 326 device_t *busp, *childp; 327 int i, j, irq; 328 329 /* 330 * Find all the PCI busses. 331 */ 332 pci_count = 0; 333 if ((pci_devclass = devclass_find("pci")) != NULL) 334 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 335 336 /* 337 * Scan all the PCI busses/devices looking for this one. 338 */ 339 irq = 255; 340 for (i = 0, busp = pci_devices; (i < pci_count) && (irq == 255); i++, busp++) { 341 pci_childcount = 0; 342 device_get_children(*busp, &pci_children, &pci_childcount); 343 344 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) { 345 if ((pci_get_bus(*childp) == bus) && 346 (pci_get_slot(*childp) == device) && 347 (pci_get_intpin(*childp) == matchpin) && 348 ((irq = pci_get_irq(*childp)) != 255)) { 349 printf("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n", 350 pe->pe_intpin[pin - 1].link, irq, 351 pci_get_bus(*childp), pci_get_slot(*childp), pci_get_function(*childp)); 352 break; 353 } 354 } 355 if (pci_children != NULL) 356 free(pci_children, M_TEMP); 357 } 358 if (pci_devices != NULL) 359 free(pci_devices, M_TEMP); 360 return(irq); 361} 362 363/* 364 * Pick a suitable IRQ from those listed as routable to this device. 365 */ 366static int 367pci_cfgintr_virgin(struct PIR_entry *pe, int pin) 368{ 369 int irq, ibit; 370 371 /* first scan the set of PCI-only interrupts and see if any of these are routable */ 372 for (irq = 0; irq < 16; irq++) { 373 ibit = (1 << irq); 374 375 /* can we use this interrupt? */ 376 if ((pci_route_table->pt_header.ph_pci_irqs & ibit) && 377 (pe->pe_intpin[pin - 1].irqs & ibit)) { 378 printf("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq); 379 return(irq); 380 } 381 } 382 383 /* life is tough, so just pick an interrupt */ 384 for (irq = 0; irq < 16; irq++) { 385 ibit = (1 << irq); 386 387 if (pe->pe_intpin[pin - 1].irqs & ibit) { 388 printf("pci_cfgintr_virgin: using routable interrupt %d\n", irq); 389 return(irq); 390 } 391 } 392 return(255); 393} 394 395 396/* 397 * Config space access using BIOS functions 398 */ 399static int 400pcibios_cfgread(int bus, int slot, int func, int reg, int bytes) 401{ 402 struct bios_regs args; 403 u_int mask; 404 405 switch(bytes) { 406 case 1: 407 args.eax = PCIBIOS_READ_CONFIG_BYTE; 408 mask = 0xff; 409 break; 410 case 2: 411 args.eax = PCIBIOS_READ_CONFIG_WORD; 412 mask = 0xffff; 413 break; 414 case 4: 415 args.eax = PCIBIOS_READ_CONFIG_DWORD; 416 mask = 0xffffffff; 417 break; 418 default: 419 return(-1); 420 } 421 args.ebx = (bus << 8) | (slot << 3) | func; 422 args.edi = reg; 423 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); 424 /* check call results? */ 425 return(args.ecx & mask); 426} 427 428static void 429pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) 430{ 431 struct bios_regs args; 432 433 switch(bytes) { 434 case 1: 435 args.eax = PCIBIOS_WRITE_CONFIG_BYTE; 436 break; 437 case 2: 438 args.eax = PCIBIOS_WRITE_CONFIG_WORD; 439 break; 440 case 4: 441 args.eax = PCIBIOS_WRITE_CONFIG_DWORD; 442 break; 443 default: 444 return; 445 } 446 args.ebx = (bus << 8) | (slot << 3) | func; 447 args.ecx = data; 448 args.edi = reg; 449 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); 450} 451 452/* 453 * Determine whether there is a PCI BIOS present 454 */ 455static int 456pcibios_cfgopen(void) 457{ 458 /* check for a found entrypoint */ 459 return(PCIbios.entry != 0); 460} 461 462/* 463 * Configuration space access using direct register operations 464 */ 465 466/* enable configuration space accesses and return data port address */ 467static int 468pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes) 469{ 470 int dataport = 0; 471 472 if (bus <= PCI_BUSMAX 473 && slot < devmax 474 && func <= PCI_FUNCMAX 475 && reg <= PCI_REGMAX 476 && bytes != 3 477 && (unsigned) bytes <= 4 478 && (reg & (bytes -1)) == 0) { 479 switch (cfgmech) { 480 case 1: 481 outl(CONF1_ADDR_PORT, (1 << 31) 482 | (bus << 16) | (slot << 11) 483 | (func << 8) | (reg & ~0x03)); 484 dataport = CONF1_DATA_PORT + (reg & 0x03); 485 break; 486 case 2: 487 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1)); 488 outb(CONF2_FORWARD_PORT, bus); 489 dataport = 0xc000 | (slot << 8) | reg; 490 break; 491 } 492 } 493 return (dataport); 494} 495 496/* disable configuration space accesses */ 497static void 498pci_cfgdisable(void) 499{ 500 switch (cfgmech) { 501 case 1: 502 outl(CONF1_ADDR_PORT, 0); 503 break; 504 case 2: 505 outb(CONF2_ENABLE_PORT, 0); 506 outb(CONF2_FORWARD_PORT, 0); 507 break; 508 } 509} 510 511static int 512pcireg_cfgread(int bus, int slot, int func, int reg, int bytes) 513{ 514 int data = -1; 515 int port; 516 517 port = pci_cfgenable(bus, slot, func, reg, bytes); 518 519 if (port != 0) { 520 switch (bytes) { 521 case 1: 522 data = inb(port); 523 break; 524 case 2: 525 data = inw(port); 526 break; 527 case 4: 528 data = inl(port); 529 break; 530 } 531 pci_cfgdisable(); 532 } 533 return (data); 534} 535 536static void 537pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) 538{ 539 int port; 540 541 port = pci_cfgenable(bus, slot, func, reg, bytes); 542 if (port != 0) { 543 switch (bytes) { 544 case 1: 545 outb(port, data); 546 break; 547 case 2: 548 outw(port, data); 549 break; 550 case 4: 551 outl(port, data); 552 break; 553 } 554 pci_cfgdisable(); 555 } 556} 557 558/* check whether the configuration mechanism has been correctly identified */ 559static int 560pci_cfgcheck(int maxdev) 561{ 562 u_char device; 563 564 if (bootverbose) 565 printf("pci_cfgcheck:\tdevice "); 566 567 for (device = 0; device < maxdev; device++) { 568 unsigned id, class, header; 569 if (bootverbose) 570 printf("%d ", device); 571 572 id = inl(pci_cfgenable(0, device, 0, 0, 4)); 573 if (id == 0 || id == -1) 574 continue; 575 576 class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8; 577 if (bootverbose) 578 printf("[class=%06x] ", class); 579 if (class == 0 || (class & 0xf870ff) != 0) 580 continue; 581 582 header = inb(pci_cfgenable(0, device, 0, 14, 1)); 583 if (bootverbose) 584 printf("[hdr=%02x] ", header); 585 if ((header & 0x7e) != 0) 586 continue; 587 588 if (bootverbose) 589 printf("is there (id=%08x)\n", id); 590 591 pci_cfgdisable(); 592 return (1); 593 } 594 if (bootverbose) 595 printf("-- nothing found\n"); 596 597 pci_cfgdisable(); 598 return (0); 599} 600 601static int 602pcireg_cfgopen(void) 603{ 604 unsigned long mode1res,oldval1; 605 unsigned char mode2res,oldval2; 606 607 oldval1 = inl(CONF1_ADDR_PORT); 608 609 if (bootverbose) { 610 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n", 611 oldval1); 612 } 613 614 if ((oldval1 & CONF1_ENABLE_MSK) == 0) { 615 616 cfgmech = 1; 617 devmax = 32; 618 619 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK); 620 outb(CONF1_ADDR_PORT +3, 0); 621 mode1res = inl(CONF1_ADDR_PORT); 622 outl(CONF1_ADDR_PORT, oldval1); 623 624 if (bootverbose) 625 printf("pci_open(1a):\tmode1res=0x%08lx (0x%08lx)\n", 626 mode1res, CONF1_ENABLE_CHK); 627 628 if (mode1res) { 629 if (pci_cfgcheck(32)) 630 return (cfgmech); 631 } 632 633 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1); 634 mode1res = inl(CONF1_ADDR_PORT); 635 outl(CONF1_ADDR_PORT, oldval1); 636 637 if (bootverbose) 638 printf("pci_open(1b):\tmode1res=0x%08lx (0x%08lx)\n", 639 mode1res, CONF1_ENABLE_CHK1); 640 641 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) { 642 if (pci_cfgcheck(32)) 643 return (cfgmech); 644 } 645 } 646 647 oldval2 = inb(CONF2_ENABLE_PORT); 648 649 if (bootverbose) { 650 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n", 651 oldval2); 652 } 653 654 if ((oldval2 & 0xf0) == 0) { 655 656 cfgmech = 2; 657 devmax = 16; 658 659 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK); 660 mode2res = inb(CONF2_ENABLE_PORT); 661 outb(CONF2_ENABLE_PORT, oldval2); 662 663 if (bootverbose) 664 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n", 665 mode2res, CONF2_ENABLE_CHK); 666 667 if (mode2res == CONF2_ENABLE_RES) { 668 if (bootverbose) 669 printf("pci_open(2a):\tnow trying mechanism 2\n"); 670 671 if (pci_cfgcheck(16)) 672 return (cfgmech); 673 } 674 } 675 676 cfgmech = 0; 677 devmax = 0; 678 return (cfgmech); 679} 680 681