pci_pir.c revision 103145
1/* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/i386/pci/pci_pir.c 103145 2002-09-09 18:24:35Z jhb $ 29 * 30 */ 31 32#include <sys/param.h> /* XXX trim includes */ 33#include <sys/systm.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/module.h> 37#include <sys/malloc.h> 38#include <vm/vm.h> 39#include <vm/pmap.h> 40#include <machine/md_var.h> 41#include <dev/pci/pcivar.h> 42#include <dev/pci/pcireg.h> 43#include <isa/isavar.h> 44#include <machine/nexusvar.h> 45#include <machine/pci_cfgreg.h> 46#include <machine/segments.h> 47#include <machine/pc/bios.h> 48 49#ifdef APIC_IO 50#include <machine/smp.h> 51#endif /* APIC_IO */ 52 53#include "pcib_if.h" 54 55#define PRVERB(a) printf a 56 57static int cfgmech; 58static int devmax; 59static int usebios; 60static int enable_pcibios = 0; 61 62TUNABLE_INT("hw.pci.enable_pcibios", &enable_pcibios); 63 64static int pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq); 65static int pci_cfgintr_unique(struct PIR_entry *pe, int pin); 66static int pci_cfgintr_linked(struct PIR_entry *pe, int pin); 67static int pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin); 68static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin); 69 70static void pci_print_irqmask(u_int16_t irqs); 71static void pci_print_route_table(struct PIR_table *prt, int size); 72static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes); 73static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); 74static int pcibios_cfgopen(void); 75static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); 76static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); 77static int pcireg_cfgopen(void); 78 79static struct PIR_table *pci_route_table; 80static int pci_route_count; 81 82/* 83 * Some BIOS writers seem to want to ignore the spec and put 84 * 0 in the intline rather than 255 to indicate none. Some use 85 * numbers in the range 128-254 to indicate something strange and 86 * apparently undocumented anywhere. Assume these are completely bogus 87 * and map them to 255, which means "none". 88 */ 89static __inline__ int 90pci_i386_map_intline(int line) 91{ 92 if (line == 0 || line >= 128) 93 return (PCI_INVALID_IRQ); 94 return (line); 95} 96 97int 98pci_pcibios_active(void) 99{ 100 return (usebios); 101} 102 103int 104pci_kill_pcibios(void) 105{ 106 usebios = 0; 107 return (pcireg_cfgopen() != 0); 108} 109 110static u_int16_t 111pcibios_get_version(void) 112{ 113 struct bios_regs args; 114 115 if (PCIbios.ventry == 0) { 116 PRVERB(("pcibios: No call entry point\n")); 117 return (0); 118 } 119 args.eax = PCIBIOS_BIOS_PRESENT; 120 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) { 121 PRVERB(("pcibios: BIOS_PRESENT call failed\n")); 122 return (0); 123 } 124 if (args.edx != 0x20494350) { 125 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n")); 126 return (0); 127 } 128 return (args.ebx & 0xffff); 129} 130 131/* 132 * Initialise access to PCI configuration space 133 */ 134int 135pci_cfgregopen(void) 136{ 137 static int opened = 0; 138 u_long sigaddr; 139 static struct PIR_table *pt; 140 u_int8_t ck, *cv; 141 int i; 142 143 if (opened) 144 return(1); 145 146 if (pcibios_cfgopen() != 0) 147 usebios = 1; 148 else if (pcireg_cfgopen() != 0) 149 usebios = 0; 150 else 151 return(0); 152 153 /* 154 * Look for the interrupt routing table. 155 * 156 * We use PCI BIOS's PIR table if it's available $PIR is the 157 * standard way to do this. Sadly, some machines are not 158 * standards conforming and have _PIR instead. We shrug and cope 159 * by looking for both. 160 */ 161 if (pcibios_get_version() >= 0x0210 && pt == NULL) { 162 sigaddr = bios_sigsearch(0, "$PIR", 4, 16, 0); 163 if (sigaddr == 0) 164 sigaddr = bios_sigsearch(0, "_PIR", 4, 16, 0); 165 if (sigaddr != 0) { 166 pt = (struct PIR_table *)(uintptr_t) 167 BIOS_PADDRTOVADDR(sigaddr); 168 for (cv = (u_int8_t *)pt, ck = 0, i = 0; 169 i < (pt->pt_header.ph_length); i++) { 170 ck += cv[i]; 171 } 172 if (ck == 0 && pt->pt_header.ph_length > 173 sizeof(struct PIR_header)) { 174 pci_route_table = pt; 175 pci_route_count = (pt->pt_header.ph_length - 176 sizeof(struct PIR_header)) / 177 sizeof(struct PIR_entry); 178 printf("Using $PIR table, %d entries at %p\n", 179 pci_route_count, pci_route_table); 180 if (bootverbose) 181 pci_print_route_table(pci_route_table, 182 pci_route_count); 183 } 184 } 185 } 186 opened = 1; 187 return(1); 188} 189 190/* 191 * Read configuration space register 192 */ 193static u_int32_t 194pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes) 195{ 196 return(usebios ? 197 pcibios_cfgread(bus, slot, func, reg, bytes) : 198 pcireg_cfgread(bus, slot, func, reg, bytes)); 199} 200 201u_int32_t 202pci_cfgregread(int bus, int slot, int func, int reg, int bytes) 203{ 204 uint32_t line; 205#ifdef APIC_IO 206 uint32_t pin; 207 208 /* 209 * If we are using the APIC, the contents of the intline 210 * register will probably be wrong (since they are set up for 211 * use with the PIC. Rather than rewrite these registers 212 * (maybe that would be smarter) we trap attempts to read them 213 * and translate to our private vector numbers. 214 */ 215 if ((reg == PCIR_INTLINE) && (bytes == 1)) { 216 217 pin = pci_do_cfgregread(bus, slot, func, PCIR_INTPIN, 1); 218 line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1); 219 220 if (pin != 0) { 221 int airq; 222 223 airq = pci_apic_irq(bus, slot, pin); 224 if (airq >= 0) { 225 /* PCI specific entry found in MP table */ 226 if (airq != line) 227 undirect_pci_irq(line); 228 return(airq); 229 } else { 230 /* 231 * PCI interrupts might be redirected 232 * to the ISA bus according to some MP 233 * tables. Use the same methods as 234 * used by the ISA devices devices to 235 * find the proper IOAPIC int pin. 236 */ 237 airq = isa_apic_irq(line); 238 if ((airq >= 0) && (airq != line)) { 239 /* XXX: undirect_pci_irq() ? */ 240 undirect_isa_irq(line); 241 return(airq); 242 } 243 } 244 } 245 return(line); 246 } 247#else 248 /* 249 * Some BIOS writers seem to want to ignore the spec and put 250 * 0 in the intline rather than 255 to indicate none. The rest of 251 * the code uses 255 as an invalid IRQ. 252 */ 253 if (reg == PCIR_INTLINE && bytes == 1) { 254 line = pci_do_cfgregread(bus, slot, func, PCIR_INTLINE, 1); 255 return pci_i386_map_intline(line); 256 } 257#endif /* APIC_IO */ 258 return(pci_do_cfgregread(bus, slot, func, reg, bytes)); 259} 260 261/* 262 * Write configuration space register 263 */ 264void 265pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) 266{ 267 return (usebios ? 268 pcibios_cfgwrite(bus, slot, func, reg, data, bytes) : 269 pcireg_cfgwrite(bus, slot, func, reg, data, bytes)); 270} 271 272/* 273 * Route a PCI interrupt 274 * 275 * XXX we don't do anything "right" with the function number in the PIR table 276 * (because the consumer isn't currently passing it in). We don't care 277 * anyway, due to the way PCI interrupts are assigned. 278 */ 279int 280pci_cfgintr(int bus, int device, int pin, int oldirq) 281{ 282 struct PIR_entry *pe; 283 int i, irq; 284 struct bios_regs args; 285 u_int16_t v; 286 int already = 0; 287 288 v = pcibios_get_version(); 289 if (v < 0x0210) { 290 PRVERB(( 291 "pci_cfgintr: BIOS %x.%02x doesn't support interrupt routing\n", 292 (v & 0xff00) >> 8, v & 0xff)); 293 return (PCI_INVALID_IRQ); 294 } 295 if ((bus < 0) || (bus > 255) || (device < 0) || (device > 255) || 296 (pin < 1) || (pin > 4)) 297 return(PCI_INVALID_IRQ); 298 299 /* 300 * Scan the entry table for a contender 301 */ 302 for (i = 0, pe = &pci_route_table->pt_entry[0]; i < pci_route_count; 303 i++, pe++) { 304 if ((bus != pe->pe_bus) || (device != pe->pe_device)) 305 continue; 306 /* 307 * A link of 0 means that this intpin is not connected to 308 * any other device's interrupt pins and is not connected to 309 * any of the Interrupt Router's interrupt pins, so we can't 310 * route it. 311 */ 312 if (pe->pe_intpin[pin - 1].link == 0) 313 continue; 314 315 if (pci_cfgintr_valid(pe, pin, oldirq)) { 316 printf("pci_cfgintr: %d:%d INT%c BIOS irq %d\n", bus, 317 device, 'A' + pin - 1, oldirq); 318 return (oldirq); 319 } 320 irq = pci_cfgintr_linked(pe, pin); 321 if (irq == PCI_INVALID_IRQ) 322 irq = pci_cfgintr_unique(pe, pin); 323 if (irq != PCI_INVALID_IRQ) 324 already = 1; 325 if (irq == PCI_INVALID_IRQ) 326 irq = pci_cfgintr_virgin(pe, pin); 327 if (irq == PCI_INVALID_IRQ) 328 break; 329 330 /* 331 * Ask the BIOS to route the interrupt 332 */ 333 args.eax = PCIBIOS_ROUTE_INTERRUPT; 334 args.ebx = (bus << 8) | (device << 3); 335 /* pin value is 0xa - 0xd */ 336 args.ecx = (irq << 8) | (0xa + pin - 1); 337 if (!already && 338 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) { 339 /* 340 * XXX if it fails, we should try to smack the router 341 * hardware directly. 342 * XXX Also, there may be other choices that we can 343 * try that will work. 344 */ 345 PRVERB(("pci_cfgintr: ROUTE_INTERRUPT failed.\n")); 346 return(PCI_INVALID_IRQ); 347 } 348 printf("pci_cfgintr: %d:%d INT%c routed to irq %d\n", bus, 349 device, 'A' + pin - 1, irq); 350 return(irq); 351 } 352 353 PRVERB(("pci_cfgintr: can't route an interrupt to %d:%d INT%c\n", bus, 354 device, 'A' + pin - 1)); 355 return(PCI_INVALID_IRQ); 356} 357 358/* 359 * Check to see if an existing IRQ setting is valid. 360 */ 361static int 362pci_cfgintr_valid(struct PIR_entry *pe, int pin, int irq) 363{ 364 uint32_t irqmask; 365 366 if (!PCI_INTERRUPT_VALID(irq)) 367 return (0); 368 irqmask = pe->pe_intpin[pin - 1].irqs; 369 if (irqmask & (1 << irq)) { 370 PRVERB(("pci_cfgintr_valid: BIOS irq %d is valid\n", irq)); 371 return (1); 372 } 373 return (0); 374} 375 376/* 377 * Look to see if the routing table claims this pin is uniquely routed. 378 */ 379static int 380pci_cfgintr_unique(struct PIR_entry *pe, int pin) 381{ 382 int irq; 383 uint32_t irqmask; 384 385 irqmask = pe->pe_intpin[pin - 1].irqs; 386 if (irqmask != 0 && powerof2(irqmask)) { 387 irq = ffs(irqmask) - 1; 388 PRVERB(("pci_cfgintr_unique: hard-routed to irq %d\n", irq)); 389 return(irq); 390 } 391 return(PCI_INVALID_IRQ); 392} 393 394/* 395 * Look for another device which shares the same link byte and 396 * already has a unique IRQ, or which has had one routed already. 397 */ 398static int 399pci_cfgintr_linked(struct PIR_entry *pe, int pin) 400{ 401 struct PIR_entry *oe; 402 struct PIR_intpin *pi; 403 int i, j, irq; 404 405 /* 406 * Scan table slots. 407 */ 408 for (i = 0, oe = &pci_route_table->pt_entry[0]; i < pci_route_count; 409 i++, oe++) { 410 /* scan interrupt pins */ 411 for (j = 0, pi = &oe->pe_intpin[0]; j < 4; j++, pi++) { 412 413 /* don't look at the entry we're trying to match */ 414 if ((pe == oe) && (i == (pin - 1))) 415 continue; 416 /* compare link bytes */ 417 if (pi->link != pe->pe_intpin[pin - 1].link) 418 continue; 419 /* link destination mapped to a unique interrupt? */ 420 if (pi->irqs != 0 && powerof2(pi->irqs)) { 421 irq = ffs(pi->irqs) - 1; 422 PRVERB(("pci_cfgintr_linked: linked (%x) to hard-routed irq %d\n", 423 pi->link, irq)); 424 return(irq); 425 } 426 427 /* 428 * look for the real PCI device that matches this 429 * table entry 430 */ 431 irq = pci_cfgintr_search(pe, oe->pe_bus, oe->pe_device, 432 j, pin); 433 if (irq != PCI_INVALID_IRQ) 434 return(irq); 435 } 436 } 437 return(PCI_INVALID_IRQ); 438} 439 440/* 441 * Scan for the real PCI device at (bus)/(device) using intpin (matchpin) and 442 * see if it has already been assigned an interrupt. 443 */ 444static int 445pci_cfgintr_search(struct PIR_entry *pe, int bus, int device, int matchpin, int pin) 446{ 447 devclass_t pci_devclass; 448 device_t *pci_devices; 449 int pci_count; 450 device_t *pci_children; 451 int pci_childcount; 452 device_t *busp, *childp; 453 int i, j, irq; 454 455 /* 456 * Find all the PCI busses. 457 */ 458 pci_count = 0; 459 if ((pci_devclass = devclass_find("pci")) != NULL) 460 devclass_get_devices(pci_devclass, &pci_devices, &pci_count); 461 462 /* 463 * Scan all the PCI busses/devices looking for this one. 464 */ 465 irq = PCI_INVALID_IRQ; 466 for (i = 0, busp = pci_devices; (i < pci_count) && (irq == PCI_INVALID_IRQ); 467 i++, busp++) { 468 pci_childcount = 0; 469 device_get_children(*busp, &pci_children, &pci_childcount); 470 471 for (j = 0, childp = pci_children; j < pci_childcount; j++, 472 childp++) { 473 if ((pci_get_bus(*childp) == bus) && 474 (pci_get_slot(*childp) == device) && 475 (pci_get_intpin(*childp) == matchpin)) { 476 irq = pci_i386_map_intline(pci_get_irq(*childp)); 477 if (irq != PCI_INVALID_IRQ) 478 PRVERB(("pci_cfgintr_search: linked (%x) to configured irq %d at %d:%d:%d\n", 479 pe->pe_intpin[pin - 1].link, irq, 480 pci_get_bus(*childp), 481 pci_get_slot(*childp), 482 pci_get_function(*childp))); 483 break; 484 } 485 } 486 if (pci_children != NULL) 487 free(pci_children, M_TEMP); 488 } 489 if (pci_devices != NULL) 490 free(pci_devices, M_TEMP); 491 return(irq); 492} 493 494/* 495 * Pick a suitable IRQ from those listed as routable to this device. 496 */ 497static int 498pci_cfgintr_virgin(struct PIR_entry *pe, int pin) 499{ 500 int irq, ibit; 501 502 /* 503 * first scan the set of PCI-only interrupts and see if any of these 504 * are routable 505 */ 506 for (irq = 0; irq < 16; irq++) { 507 ibit = (1 << irq); 508 509 /* can we use this interrupt? */ 510 if ((pci_route_table->pt_header.ph_pci_irqs & ibit) && 511 (pe->pe_intpin[pin - 1].irqs & ibit)) { 512 PRVERB(("pci_cfgintr_virgin: using routable PCI-only interrupt %d\n", irq)); 513 return(irq); 514 } 515 } 516 517 /* life is tough, so just pick an interrupt */ 518 for (irq = 0; irq < 16; irq++) { 519 ibit = (1 << irq); 520 if (pe->pe_intpin[pin - 1].irqs & ibit) { 521 PRVERB(("pci_cfgintr_virgin: using routable interrupt %d\n", irq)); 522 return(irq); 523 } 524 } 525 return(PCI_INVALID_IRQ); 526} 527 528static void 529pci_print_irqmask(u_int16_t irqs) 530{ 531 int i, first; 532 533 if (irqs == 0) { 534 printf("none"); 535 return; 536 } 537 first = 1; 538 for (i = 0; i < 16; i++, irqs >>= 1) 539 if (irqs & 1) { 540 if (!first) 541 printf(" "); 542 else 543 first = 0; 544 printf("%d", i); 545 } 546} 547 548/* 549 * Dump the contents of a PCI BIOS Interrupt Routing Table to the console. 550 */ 551static void 552pci_print_route_table(struct PIR_table *prt, int size) 553{ 554 struct PIR_entry *entry; 555 struct PIR_intpin *intpin; 556 int i, pin; 557 558 printf("PCI-Only Interrupts: "); 559 pci_print_irqmask(prt->pt_header.ph_pci_irqs); 560 printf("\nLocation Bus Device Pin Link IRQs\n"); 561 entry = &prt->pt_entry[0]; 562 for (i = 0; i < size; i++, entry++) { 563 intpin = &entry->pe_intpin[0]; 564 for (pin = 0; pin < 4; pin++, intpin++) 565 if (intpin->link != 0) { 566 if (entry->pe_slot == 0) 567 printf("embedded "); 568 else 569 printf("slot %-3d ", entry->pe_slot); 570 printf(" %3d %3d %c 0x%02x ", 571 entry->pe_bus, entry->pe_device, 572 'A' + pin, intpin->link); 573 pci_print_irqmask(intpin->irqs); 574 printf("\n"); 575 } 576 } 577} 578 579/* 580 * See if any interrupts for a given PCI bus are routed in the PIR. Don't 581 * even bother looking if the BIOS doesn't support routing anyways. 582 */ 583int 584pci_probe_route_table(int bus) 585{ 586 int i; 587 u_int16_t v; 588 589 v = pcibios_get_version(); 590 if (v < 0x0210) 591 return (0); 592 for (i = 0; i < pci_route_count; i++) 593 if (pci_route_table->pt_entry[i].pe_bus == bus) 594 return (1); 595 return (0); 596} 597 598/* 599 * Config space access using BIOS functions 600 */ 601static int 602pcibios_cfgread(int bus, int slot, int func, int reg, int bytes) 603{ 604 struct bios_regs args; 605 u_int mask; 606 607 switch(bytes) { 608 case 1: 609 args.eax = PCIBIOS_READ_CONFIG_BYTE; 610 mask = 0xff; 611 break; 612 case 2: 613 args.eax = PCIBIOS_READ_CONFIG_WORD; 614 mask = 0xffff; 615 break; 616 case 4: 617 args.eax = PCIBIOS_READ_CONFIG_DWORD; 618 mask = 0xffffffff; 619 break; 620 default: 621 return(-1); 622 } 623 args.ebx = (bus << 8) | (slot << 3) | func; 624 args.edi = reg; 625 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); 626 /* check call results? */ 627 return(args.ecx & mask); 628} 629 630static void 631pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) 632{ 633 struct bios_regs args; 634 635 switch(bytes) { 636 case 1: 637 args.eax = PCIBIOS_WRITE_CONFIG_BYTE; 638 break; 639 case 2: 640 args.eax = PCIBIOS_WRITE_CONFIG_WORD; 641 break; 642 case 4: 643 args.eax = PCIBIOS_WRITE_CONFIG_DWORD; 644 break; 645 default: 646 return; 647 } 648 args.ebx = (bus << 8) | (slot << 3) | func; 649 args.ecx = data; 650 args.edi = reg; 651 bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL)); 652} 653 654/* 655 * Determine whether there is a PCI BIOS present 656 */ 657static int 658pcibios_cfgopen(void) 659{ 660 u_int16_t v = 0; 661 662 if (PCIbios.ventry != 0 && enable_pcibios) { 663 v = pcibios_get_version(); 664 if (v > 0) 665 printf("pcibios: BIOS version %x.%02x\n", 666 (v & 0xff00) >> 8, v & 0xff); 667 } 668 return (v > 0); 669} 670 671/* 672 * Configuration space access using direct register operations 673 */ 674 675/* enable configuration space accesses and return data port address */ 676static int 677pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes) 678{ 679 int dataport = 0; 680 681 if (bus <= PCI_BUSMAX 682 && slot < devmax 683 && func <= PCI_FUNCMAX 684 && reg <= PCI_REGMAX 685 && bytes != 3 686 && (unsigned) bytes <= 4 687 && (reg & (bytes -1)) == 0) { 688 switch (cfgmech) { 689 case 1: 690 outl(CONF1_ADDR_PORT, (1 << 31) 691 | (bus << 16) | (slot << 11) 692 | (func << 8) | (reg & ~0x03)); 693 dataport = CONF1_DATA_PORT + (reg & 0x03); 694 break; 695 case 2: 696 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1)); 697 outb(CONF2_FORWARD_PORT, bus); 698 dataport = 0xc000 | (slot << 8) | reg; 699 break; 700 } 701 } 702 return (dataport); 703} 704 705/* disable configuration space accesses */ 706static void 707pci_cfgdisable(void) 708{ 709 switch (cfgmech) { 710 case 1: 711 outl(CONF1_ADDR_PORT, 0); 712 break; 713 case 2: 714 outb(CONF2_ENABLE_PORT, 0); 715 outb(CONF2_FORWARD_PORT, 0); 716 break; 717 } 718} 719 720static int 721pcireg_cfgread(int bus, int slot, int func, int reg, int bytes) 722{ 723 int data = -1; 724 int port; 725 726 port = pci_cfgenable(bus, slot, func, reg, bytes); 727 728 if (port != 0) { 729 switch (bytes) { 730 case 1: 731 data = inb(port); 732 break; 733 case 2: 734 data = inw(port); 735 break; 736 case 4: 737 data = inl(port); 738 break; 739 } 740 pci_cfgdisable(); 741 } 742 return (data); 743} 744 745static void 746pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) 747{ 748 int port; 749 750 port = pci_cfgenable(bus, slot, func, reg, bytes); 751 if (port != 0) { 752 switch (bytes) { 753 case 1: 754 outb(port, data); 755 break; 756 case 2: 757 outw(port, data); 758 break; 759 case 4: 760 outl(port, data); 761 break; 762 } 763 pci_cfgdisable(); 764 } 765} 766 767/* check whether the configuration mechanism has been correctly identified */ 768static int 769pci_cfgcheck(int maxdev) 770{ 771 u_char device; 772 773 if (bootverbose) 774 printf("pci_cfgcheck:\tdevice "); 775 776 for (device = 0; device < maxdev; device++) { 777 unsigned id, class, header; 778 if (bootverbose) 779 printf("%d ", device); 780 781 id = inl(pci_cfgenable(0, device, 0, 0, 4)); 782 if (id == 0 || id == -1) 783 continue; 784 785 class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8; 786 if (bootverbose) 787 printf("[class=%06x] ", class); 788 if (class == 0 || (class & 0xf870ff) != 0) 789 continue; 790 791 header = inb(pci_cfgenable(0, device, 0, 14, 1)); 792 if (bootverbose) 793 printf("[hdr=%02x] ", header); 794 if ((header & 0x7e) != 0) 795 continue; 796 797 if (bootverbose) 798 printf("is there (id=%08x)\n", id); 799 800 pci_cfgdisable(); 801 return (1); 802 } 803 if (bootverbose) 804 printf("-- nothing found\n"); 805 806 pci_cfgdisable(); 807 return (0); 808} 809 810static int 811pcireg_cfgopen(void) 812{ 813 unsigned long mode1res,oldval1; 814 unsigned char mode2res,oldval2; 815 816 oldval1 = inl(CONF1_ADDR_PORT); 817 818 if (bootverbose) { 819 printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n", 820 oldval1); 821 } 822 823 if ((oldval1 & CONF1_ENABLE_MSK) == 0) { 824 825 cfgmech = 1; 826 devmax = 32; 827 828 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK); 829 outb(CONF1_ADDR_PORT +3, 0); 830 mode1res = inl(CONF1_ADDR_PORT); 831 outl(CONF1_ADDR_PORT, oldval1); 832 833 if (bootverbose) 834 printf("pci_open(1a):\tmode1res=0x%08lx (0x%08lx)\n", 835 mode1res, CONF1_ENABLE_CHK); 836 837 if (mode1res) { 838 if (pci_cfgcheck(32)) 839 return (cfgmech); 840 } 841 842 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1); 843 mode1res = inl(CONF1_ADDR_PORT); 844 outl(CONF1_ADDR_PORT, oldval1); 845 846 if (bootverbose) 847 printf("pci_open(1b):\tmode1res=0x%08lx (0x%08lx)\n", 848 mode1res, CONF1_ENABLE_CHK1); 849 850 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) { 851 if (pci_cfgcheck(32)) 852 return (cfgmech); 853 } 854 } 855 856 oldval2 = inb(CONF2_ENABLE_PORT); 857 858 if (bootverbose) { 859 printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n", 860 oldval2); 861 } 862 863 if ((oldval2 & 0xf0) == 0) { 864 865 cfgmech = 2; 866 devmax = 16; 867 868 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK); 869 mode2res = inb(CONF2_ENABLE_PORT); 870 outb(CONF2_ENABLE_PORT, oldval2); 871 872 if (bootverbose) 873 printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n", 874 mode2res, CONF2_ENABLE_CHK); 875 876 if (mode2res == CONF2_ENABLE_RES) { 877 if (bootverbose) 878 printf("pci_open(2a):\tnow trying mechanism 2\n"); 879 880 if (pci_cfgcheck(16)) 881 return (cfgmech); 882 } 883 } 884 885 cfgmech = 0; 886 devmax = 0; 887 return (cfgmech); 888} 889 890