if_xlreg.h revision 51301
1139825Simp/* 254134Swpaul * Copyright (c) 1997, 1998 354134Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 454134Swpaul * 554134Swpaul * Redistribution and use in source and binary forms, with or without 654134Swpaul * modification, are permitted provided that the following conditions 754134Swpaul * are met: 854134Swpaul * 1. Redistributions of source code must retain the above copyright 954134Swpaul * notice, this list of conditions and the following disclaimer. 1054134Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1154134Swpaul * notice, this list of conditions and the following disclaimer in the 1254134Swpaul * documentation and/or other materials provided with the distribution. 1354134Swpaul * 3. All advertising materials mentioning features or use of this software 1454134Swpaul * must display the following acknowledgement: 1554134Swpaul * This product includes software developed by Bill Paul. 1654134Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1754134Swpaul * may be used to endorse or promote products derived from this software 1854134Swpaul * without specific prior written permission. 1954134Swpaul * 2054134Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2154134Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2254134Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2354134Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2454134Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2554134Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2654134Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2754134Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2854134Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2954134Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3054134Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3154134Swpaul * 3254134Swpaul * $FreeBSD: head/sys/pci/if_xlreg.h 51301 1999-09-15 07:19:34Z wpaul $ 3354134Swpaul */ 3454134Swpaul 3554134Swpaul#define XL_EE_READ 0x0080 /* read, 5 bit address */ 3654134Swpaul#define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 3754134Swpaul#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 3854134Swpaul#define XL_EE_EWEN 0x0030 /* erase, no data needed */ 3954134Swpaul#define XL_EE_BUSY 0x8000 4054134Swpaul 4154134Swpaul#define XL_EE_EADDR0 0x00 /* station address, first word */ 4254134Swpaul#define XL_EE_EADDR1 0x01 /* station address, next word, */ 4354134Swpaul#define XL_EE_EADDR2 0x02 /* station address, last word */ 4454134Swpaul#define XL_EE_PRODID 0x03 /* product ID code */ 4554134Swpaul#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 4654134Swpaul#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 4754134Swpaul#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 4854134Swpaul#define XL_EE_MFG_ID 0x07 4954134Swpaul#define XL_EE_PCI_PARM 0x08 5054134Swpaul#define XL_EE_ROM_ONFO 0x09 5154134Swpaul#define XL_EE_OEM_ADR0 0x0A 5254134Swpaul#define XL_EE_OEM_ADR1 0x0B 5354134Swpaul#define XL_EE_OEM_ADR2 0x0C 5454134Swpaul#define XL_EE_SOFTINFO1 0x0D 5567314Sjon#define XL_EE_COMPAT 0x0E 5654134Swpaul#define XL_EE_SOFTINFO2 0x0F 5754134Swpaul#define XL_EE_CAPS 0x10 /* capabilities word */ 5854134Swpaul#define XL_EE_RSVD0 0x11 5954134Swpaul#define XL_EE_ICFG_0 0x12 6054134Swpaul#define XL_EE_ICFG_1 0x13 6154134Swpaul#define XL_EE_RSVD1 0x14 6254134Swpaul#define XL_EE_SOFTINFO3 0x15 6354134Swpaul#define XL_EE_RSVD_2 0x16 6454134Swpaul 6554134Swpaul/* 6654134Swpaul * Bits in the capabilities word 6754134Swpaul */ 6854134Swpaul#define XL_CAPS_PNP 0x0001 6954134Swpaul#define XL_CAPS_FULL_DUPLEX 0x0002 7054134Swpaul#define XL_CAPS_LARGE_PKTS 0x0004 7154134Swpaul#define XL_CAPS_SLAVE_DMA 0x0008 7254134Swpaul#define XL_CAPS_SECOND_DMA 0x0010 7354134Swpaul#define XL_CAPS_FULL_BM 0x0020 7454134Swpaul#define XL_CAPS_FRAG_BM 0x0040 75201430Smbr#define XL_CAPS_CRC_PASSTHRU 0x0080 7654134Swpaul#define XL_CAPS_TXDONE 0x0100 7754134Swpaul#define XL_CAPS_NO_TXLENGTH 0x0200 7854134Swpaul#define XL_CAPS_RX_REPEAT 0x0400 7967314Sjon#define XL_CAPS_SNOOPING 0x0800 8082978Swpaul#define XL_CAPS_100MBPS 0x1000 8154134Swpaul#define XL_CAPS_PWRMGMT 0x2000 8254134Swpaul 8354134Swpaul#define XL_PACKET_SIZE 1536 8454134Swpaul 8554134Swpaul/* 8654134Swpaul * Register layouts. 8754134Swpaul */ 8854134Swpaul#define XL_COMMAND 0x0E 89201430Smbr#define XL_STATUS 0x0E 9054134Swpaul 9154134Swpaul#define XL_TX_STATUS 0x1B 9254134Swpaul#define XL_TX_FREE 0x1C 9354134Swpaul#define XL_DMACTL 0x20 94201430Smbr#define XL_DOWNLIST_PTR 0x24 9554134Swpaul#define XL_TX_FREETHRESH 0x2F 9654134Swpaul#define XL_UPLIST_PTR 0x38 9754134Swpaul#define XL_UPLIST_STATUS 0x30 9867314Sjon 9982978Swpaul#define XL_PKTSTAT_UP_STALLED 0x00002000 10054134Swpaul#define XL_PKTSTAT_UP_ERROR 0x00004000 10154134Swpaul#define XL_PKTSTAT_UP_CMPLT 0x00008000 10254134Swpaul 10354134Swpaul#define XL_DMACTL_DN_CMPLT_REQ 0x00000002 10466681Swpaul#define XL_DMACTL_DOWN_STALLED 0x00000004 10554134Swpaul#define XL_DMACTL_UP_CMPLT 0x00000008 10654134Swpaul#define XL_DMACTL_DOWN_CMPLT 0x00000010 10754134Swpaul#define XL_DMACTL_UP_RX_EARLY 0x00000020 10854134Swpaul#define XL_DMACTL_ARM_COUNTDOWN 0x00000040 10954134Swpaul#define XL_DMACTL_DOWN_INPROG 0x00000080 11054134Swpaul#define XL_DMACTL_COUNTER_SPEED 0x00000100 11154134Swpaul#define XL_DMACTL_DOWNDOWN_MODE 0x00000200 11254134Swpaul#define XL_DMACTL_TARGET_ABORT 0x40000000 11354134Swpaul#define XL_DMACTL_MASTER_ABORT 0x80000000 11454134Swpaul 11554134Swpaul/* 11654134Swpaul * Command codes. Some command codes require that we wait for 11754134Swpaul * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 11854134Swpaul */ 11954134Swpaul#define XL_CMD_RESET 0x0000 /* mustwait */ 12054134Swpaul#define XL_CMD_WINSEL 0x0800 12154134Swpaul#define XL_CMD_COAX_START 0x1000 12254134Swpaul#define XL_CMD_RX_DISABLE 0x1800 12354134Swpaul#define XL_CMD_RX_ENABLE 0x2000 12454134Swpaul#define XL_CMD_RX_RESET 0x2800 /* mustwait */ 12554134Swpaul#define XL_CMD_UP_STALL 0x3000 /* mustwait */ 12654134Swpaul#define XL_CMD_UP_UNSTALL 0x3001 12754134Swpaul#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 12854134Swpaul#define XL_CMD_DOWN_UNSTALL 0x3003 12954134Swpaul#define XL_CMD_RX_DISCARD 0x4000 13054134Swpaul#define XL_CMD_TX_ENABLE 0x4800 13154134Swpaul#define XL_CMD_TX_DISABLE 0x5000 13254134Swpaul#define XL_CMD_TX_RESET 0x5800 /* mustwait */ 13354134Swpaul#define XL_CMD_INTR_FAKE 0x6000 13454134Swpaul#define XL_CMD_INTR_ACK 0x6800 13554134Swpaul#define XL_CMD_INTR_ENB 0x7000 13654134Swpaul#define XL_CMD_STAT_ENB 0x7800 13754134Swpaul#define XL_CMD_RX_SET_FILT 0x8000 13854134Swpaul#define XL_CMD_RX_SET_THRESH 0x8800 13954134Swpaul#define XL_CMD_TX_SET_THRESH 0x9000 14054134Swpaul#define XL_CMD_TX_SET_START 0x9800 14154134Swpaul#define XL_CMD_DMA_UP 0xA000 14254134Swpaul#define XL_CMD_DMA_STOP 0xA001 14354134Swpaul#define XL_CMD_STATS_ENABLE 0xA800 14454134Swpaul#define XL_CMD_STATS_DISABLE 0xB000 14554134Swpaul#define XL_CMD_COAX_STOP 0xB800 14654134Swpaul 14754134Swpaul#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 14854134Swpaul#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 14954134Swpaul 15054134Swpaul#define XL_HASH_SET 0x0400 15154134Swpaul#define XL_HASHFILT_SIZE 256 15254134Swpaul 15354134Swpaul/* 15454134Swpaul * status codes 15554134Swpaul * Note that bits 15 to 13 indicate the currently visible register window 15654134Swpaul * which may be anything from 0 to 7. 15754134Swpaul */ 15854134Swpaul#define XL_STAT_INTLATCH 0x0001 /* 0 */ 15954134Swpaul#define XL_STAT_ADFAIL 0x0002 /* 1 */ 16054134Swpaul#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 16154134Swpaul#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 16254134Swpaul#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 16354134Swpaul#define XL_STAT_RX_EARLY 0x0020 /* 5 */ 16454134Swpaul#define XL_STAT_INTREQ 0x0040 /* 6 */ 16554134Swpaul#define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 16654134Swpaul#define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 16754134Swpaul#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 16854134Swpaul#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 16954134Swpaul#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 17054134Swpaul#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 17154134Swpaul#define XL_STAT_CMDBUSY 0x1000 /* 12 */ 17254134Swpaul 17354134Swpaul/* 17454134Swpaul * Interrupts we normally want enabled. 17554134Swpaul */ 17654134Swpaul#define XL_INTRS \ 17754134Swpaul (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \ 17854134Swpaul XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH) 17954134Swpaul 18054134Swpaul/* 18154134Swpaul * Window 0 registers 18254134Swpaul */ 18354134Swpaul#define XL_W0_EE_DATA 0x0C 18454134Swpaul#define XL_W0_EE_CMD 0x0A 185182461Smarius#define XL_W0_RSRC_CFG 0x08 186182461Smarius#define XL_W0_ADDR_CFG 0x06 187182461Smarius#define XL_W0_CFG_CTRL 0x04 188182461Smarius 18954134Swpaul#define XL_W0_PROD_ID 0x02 19054134Swpaul#define XL_W0_MFG_ID 0x00 19154134Swpaul 19254134Swpaul/* 19354134Swpaul * Window 1 19454134Swpaul */ 19554134Swpaul 19654134Swpaul#define XL_W1_TX_FIFO 0x10 19754134Swpaul 19854134Swpaul#define XL_W1_FREE_TX 0x0C 19954134Swpaul#define XL_W1_TX_STATUS 0x0B 20054134Swpaul#define XL_W1_TX_TIMER 0x0A 20154134Swpaul#define XL_W1_RX_STATUS 0x08 20254134Swpaul#define XL_W1_RX_FIFO 0x00 20354134Swpaul 20454134Swpaul/* 20554134Swpaul * RX status codes 20654134Swpaul */ 20754134Swpaul#define XL_RXSTATUS_OVERRUN 0x01 20854134Swpaul#define XL_RXSTATUS_RUNT 0x02 20954134Swpaul#define XL_RXSTATUS_ALIGN 0x04 21054134Swpaul#define XL_RXSTATUS_CRC 0x08 21154134Swpaul#define XL_RXSTATUS_OVERSIZE 0x10 21254134Swpaul#define XL_RXSTATUS_DRIBBLE 0x20 21354134Swpaul 21454134Swpaul/* 21554134Swpaul * TX status codes 21654134Swpaul */ 21754134Swpaul#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 21854134Swpaul#define XL_TXSTATUS_OVERFLOW 0x04 21954134Swpaul#define XL_TXSTATUS_MAXCOLS 0x08 22054134Swpaul#define XL_TXSTATUS_UNDERRUN 0x10 22154134Swpaul#define XL_TXSTATUS_JABBER 0x20 22254134Swpaul#define XL_TXSTATUS_INTREQ 0x40 22354134Swpaul#define XL_TXSTATUS_COMPLETE 0x80 22454134Swpaul 22554134Swpaul/* 22654134Swpaul * Window 2 22754134Swpaul */ 22854134Swpaul#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 22972915Swpaul#define XL_W2_STATION_MASK_HI 0x0A 23054134Swpaul#define XL_W2_STATION_MASK_MID 0x08 23154134Swpaul#define XL_W2_STATION_MASK_LO 0x06 23254134Swpaul#define XL_W2_STATION_ADDR_HI 0x04 23354134Swpaul#define XL_W2_STATION_ADDR_MID 0x02 23472915Swpaul#define XL_W2_STATION_ADDR_LO 0x00 23554134Swpaul 23672915Swpaul#define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 23772915Swpaul#define XL_RESETOPT_D3RESETDIS 0x0008 23872915Swpaul#define XL_RESETOPT_DISADVFD 0x0010 23954134Swpaul#define XL_RESETOPT_DISADV100 0x0020 24072915Swpaul#define XL_RESETOPT_DISAUTONEG 0x0040 24154134Swpaul#define XL_RESETOPT_DEBUGMODE 0x0080 24254134Swpaul#define XL_RESETOPT_FASTAUTO 0x0100 24354134Swpaul#define XL_RESETOPT_FASTEE 0x0200 24454134Swpaul#define XL_RESETOPT_FORCEDCONF 0x0400 24554134Swpaul#define XL_RESETOPT_TESTPDTPDR 0x0800 24654134Swpaul#define XL_RESETOPT_TEST100TX 0x1000 24754134Swpaul#define XL_RESETOPT_TEST100RX 0x2000 24854134Swpaul 24954134Swpaul/* 25054134Swpaul * Window 3 (fifo management) 25154134Swpaul */ 25254134Swpaul#define XL_W3_INTERNAL_CFG 0x00 25354134Swpaul#define XL_W3_RESET_OPT 0x08 25454134Swpaul#define XL_W3_FREE_TX 0x0C 25554134Swpaul#define XL_W3_FREE_RX 0x0A 25654134Swpaul#define XL_W3_MAC_CTRL 0x06 25754134Swpaul 25854134Swpaul#define XL_ICFG_CONNECTOR_MASK 0x00F00000 25954134Swpaul#define XL_ICFG_CONNECTOR_BITS 20 26054134Swpaul 26154134Swpaul#define XL_ICFG_RAMSIZE_MASK 0x00000007 26254134Swpaul#define XL_ICFG_RAMWIDTH 0x00000008 26354134Swpaul#define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 26454134Swpaul#define XL_ICFG_DISABLE_BASSD 0x00000100 26554134Swpaul#define XL_ICFG_RAMLOC 0x00000200 26654134Swpaul#define XL_ICFG_RAMPART (0x00010000|0x00020000) 26754134Swpaul#define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 26854134Swpaul#define XL_ICFG_AUTOSEL 0x01000000 26954134Swpaul 27054134Swpaul#define XL_XCVR_10BT 0x00 27154134Swpaul#define XL_XCVR_AUI 0x01 27254134Swpaul#define XL_XCVR_RSVD_0 0x02 27354134Swpaul#define XL_XCVR_COAX 0x03 27454134Swpaul#define XL_XCVR_100BTX 0x04 27554134Swpaul#define XL_XCVR_100BFX 0x05 27654134Swpaul#define XL_XCVR_MII 0x06 27754134Swpaul#define XL_XCVR_RSVD_1 0x07 27854134Swpaul#define XL_XCVR_AUTO 0x08 /* 3c905B only */ 27954134Swpaul 28054134Swpaul#define XL_MACCTRL_DEFER_EXT_END 0x0001 28154134Swpaul#define XL_MACCTRL_DEFER_0 0x0002 28254134Swpaul#define XL_MACCTRL_DEFER_1 0x0004 28354134Swpaul#define XL_MACCTRL_DEFER_2 0x0008 28454134Swpaul#define XL_MACCTRL_DEFER_3 0x0010 28554134Swpaul#define XL_MACCTRL_DUPLEX 0x0020 28654134Swpaul#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 28754134Swpaul#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 28854134Swpaul#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 28954134Swpaul#define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 29054134Swpaul 29154134Swpaul/* 29254134Swpaul * The 'reset options' register contains power-on reset values 29354134Swpaul * loaded from the EEPROM. This includes the supported media 29454134Swpaul * types on the card. It is also known as the media options register. 29554134Swpaul */ 29654134Swpaul#define XL_W3_MEDIA_OPT 0x08 29754134Swpaul 29854134Swpaul#define XL_MEDIAOPT_BT4 0x0001 /* MII */ 29954134Swpaul#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 30054134Swpaul#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 30154134Swpaul#define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 30254134Swpaul#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 30354134Swpaul#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 30454134Swpaul#define XL_MEDIAOPT_MII 0x0040 /* MII */ 30554134Swpaul#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 30654134Swpaul 30754134Swpaul#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 30854134Swpaul#define XL_MEDIAOPT_MASK 0x01FF 30954134Swpaul 31054134Swpaul/* 31154134Swpaul * Window 4 (diagnostics) 31254134Swpaul */ 31354134Swpaul#define XL_W4_UPPERBYTESOK 0x0D 31454134Swpaul#define XL_W4_BADSSD 0x0C 31554134Swpaul#define XL_W4_MEDIA_STATUS 0x0A 31654134Swpaul#define XL_W4_PHY_MGMT 0x08 31754134Swpaul#define XL_W4_NET_DIAG 0x06 31854134Swpaul#define XL_W4_FIFO_DIAG 0x04 31954134Swpaul#define XL_W4_VCO_DIAG 0x02 32054134Swpaul 32154134Swpaul#define XL_W4_CTRLR_STAT 0x08 32254134Swpaul#define XL_W4_TX_DIAG 0x00 32354134Swpaul 32454134Swpaul#define XL_MII_CLK 0x01 32554134Swpaul#define XL_MII_DATA 0x02 32654134Swpaul#define XL_MII_DIR 0x04 32754134Swpaul 32854134Swpaul#define XL_MEDIA_SQE 0x0008 32954134Swpaul#define XL_MEDIA_10TP 0x00C0 33054134Swpaul#define XL_MEDIA_LNK 0x0080 33154134Swpaul#define XL_MEDIA_LNKBEAT 0x0800 33254134Swpaul 33354134Swpaul#define XL_MEDIASTAT_CRCSTRIP 0x0004 33454134Swpaul#define XL_MEDIASTAT_SQEENB 0x0008 33554134Swpaul#define XL_MEDIASTAT_COLDET 0x0010 33654134Swpaul#define XL_MEDIASTAT_CARRIER 0x0020 33754134Swpaul#define XL_MEDIASTAT_JABGUARD 0x0040 33854134Swpaul#define XL_MEDIASTAT_LINKBEAT 0x0080 33954134Swpaul#define XL_MEDIASTAT_JABDETECT 0x0200 34054134Swpaul#define XL_MEDIASTAT_POLREVERS 0x0400 34154134Swpaul#define XL_MEDIASTAT_LINKDETECT 0x0800 34254134Swpaul#define XL_MEDIASTAT_TXINPROG 0x1000 34354134Swpaul#define XL_MEDIASTAT_DCENB 0x4000 34454134Swpaul#define XL_MEDIASTAT_AUIDIS 0x8000 34554134Swpaul 34654134Swpaul#define XL_NETDIAG_TEST_LOWVOLT 0x0001 34754134Swpaul#define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 34854134Swpaul#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 34954134Swpaul#define XL_NETDIAG_STATS_ENABLED 0x0080 35054134Swpaul#define XL_NETDIAG_TX_FATALERR 0x0100 35154134Swpaul#define XL_NETDIAG_TRANSMITTING 0x0200 35254134Swpaul#define XL_NETDIAG_RX_ENABLED 0x0400 35354134Swpaul#define XL_NETDIAG_TX_ENABLED 0x0800 35454134Swpaul#define XL_NETDIAG_FIFO_LOOPBACK 0x1000 35554134Swpaul#define XL_NETDIAG_MAC_LOOPBACK 0x2000 35654134Swpaul#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 35754134Swpaul#define XL_NETDIAG_EXTERNAL_LOOP 0x8000 35854134Swpaul 35954134Swpaul/* 36065350Swpaul * Window 5 36165350Swpaul */ 36265350Swpaul#define XL_W5_STAT_ENB 0x0C 36365350Swpaul#define XL_W5_INTR_ENB 0x0A 36464134Swpaul#define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */ 36554134Swpaul#define XL_W5_RX_FILTER 0x08 36654134Swpaul#define XL_W5_RX_EARLYTHRESH 0x06 36767314Sjon#define XL_W5_TX_AVAILTHRESH 0x02 36867314Sjon#define XL_W5_TX_STARTTHRESH 0x00 36967314Sjon 37067314Sjon/* 37167314Sjon * RX filter bits 37267314Sjon */ 37367314Sjon#define XL_RXFILTER_INDIVIDUAL 0x01 37467314Sjon#define XL_RXFILTER_ALLMULTI 0x02 37567314Sjon#define XL_RXFILTER_BROADCAST 0x04 37667314Sjon#define XL_RXFILTER_ALLFRAMES 0x08 37767314Sjon#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 37867314Sjon 37967314Sjon/* 38067314Sjon * Window 6 (stats) 38167314Sjon */ 38267314Sjon#define XL_W6_TX_BYTES_OK 0x0C 38367314Sjon#define XL_W6_RX_BYTES_OK 0x0A 38467314Sjon#define XL_W6_UPPER_FRAMES_OK 0x09 38567314Sjon#define XL_W6_DEFERRED 0x08 38654134Swpaul#define XL_W6_RX_OK 0x07 38754134Swpaul#define XL_W6_TX_OK 0x06 38854134Swpaul#define XL_W6_RX_OVERRUN 0x05 38954134Swpaul#define XL_W6_COL_LATE 0x04 39054134Swpaul#define XL_W6_COL_SINGLE 0x03 39154134Swpaul#define XL_W6_COL_MULTIPLE 0x02 39254134Swpaul#define XL_W6_SQE_ERRORS 0x01 39354134Swpaul#define XL_W6_CARRIER_LOST 0x00 39454134Swpaul 39554134Swpaul/* 39654134Swpaul * Window 7 (bus master control) 39754134Swpaul */ 39854134Swpaul#define XL_W7_BM_ADDR 0x00 39954134Swpaul#define XL_W7_BM_LEN 0x06 40054134Swpaul#define XL_W7_BM_STATUS 0x0B 40154134Swpaul#define XL_W7_BM_TIMEr 0x0A 40254134Swpaul 40354134Swpaul/* 40454134Swpaul * bus master control registers 40554134Swpaul */ 40654134Swpaul#define XL_BM_PKTSTAT 0x20 40789436Sambrisko#define XL_BM_DOWNLISTPTR 0x24 40854134Swpaul#define XL_BM_FRAGADDR 0x28 40954134Swpaul#define XL_BM_FRAGLEN 0x2C 41054134Swpaul#define XL_BM_TXFREETHRESH 0x2F 41154134Swpaul#define XL_BM_UPPKTSTAT 0x30 41254134Swpaul#define XL_BM_UPLISTPTR 0x38 41354134Swpaul 41454134Swpaul#define XL_LAST_FRAG 0x80000000 41554134Swpaul 41654134Swpaul/* 41789436Sambrisko * Boomerang/Cyclone TX/RX list structure. 41854134Swpaul * For the TX lists, bits 0 to 12 of the status word indicate 41954134Swpaul * length. 42054134Swpaul * This looks suspiciously like the ThunderLAN, doesn't it. 42154134Swpaul */ 42254134Swpaulstruct xl_frag { 42354134Swpaul u_int32_t xl_addr; /* 63 addr/len pairs */ 42454134Swpaul u_int32_t xl_len; 42554134Swpaul}; 42654134Swpaul 42754134Swpaulstruct xl_list { 42854134Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 42954134Swpaul u_int32_t xl_status; 43054134Swpaul struct xl_frag xl_frag[63]; 43154134Swpaul}; 43254134Swpaul 43354134Swpaulstruct xl_list_onefrag { 43454134Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 43554134Swpaul u_int32_t xl_status; 43654134Swpaul struct xl_frag xl_frag; 43754134Swpaul}; 43854134Swpaul 43954134Swpaul#define XL_MAXFRAGS 63 44054134Swpaul#define XL_RX_LIST_CNT 128 44154134Swpaul#define XL_TX_LIST_CNT 256 44254134Swpaul#define XL_MIN_FRAMELEN 60 44354134Swpaul 44454134Swpaulstruct xl_list_data { 44554134Swpaul struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT]; 44654134Swpaul struct xl_list xl_tx_list[XL_TX_LIST_CNT]; 44754134Swpaul unsigned char xl_pad[XL_MIN_FRAMELEN]; 44854134Swpaul}; 44954134Swpaul 45054134Swpaulstruct xl_chain { 45154134Swpaul struct xl_list *xl_ptr; 45254134Swpaul struct mbuf *xl_mbuf; 45354134Swpaul struct xl_chain *xl_next; 45454134Swpaul}; 45554134Swpaul 45654134Swpaulstruct xl_chain_onefrag { 45754134Swpaul struct xl_list_onefrag *xl_ptr; 45854134Swpaul struct mbuf *xl_mbuf; 45954134Swpaul struct xl_chain_onefrag *xl_next; 46054134Swpaul}; 46154134Swpaul 46287902Sluigistruct xl_chain_data { 46387902Sluigi struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 46487902Sluigi struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 46554134Swpaul 46687902Sluigi struct xl_chain_onefrag *xl_rx_head; 46754134Swpaul 468171729Smarius struct xl_chain *xl_tx_head; 46954134Swpaul struct xl_chain *xl_tx_tail; 47054134Swpaul struct xl_chain *xl_tx_free; 47154134Swpaul}; 472117295Smux 47354134Swpaul#define XL_RXSTAT_LENMASK 0x00001FFF 474117295Smux#define XL_RXSTAT_UP_ERROR 0x00004000 475117295Smux#define XL_RXSTAT_UP_CMPLT 0x00008000 476117295Smux#define XL_RXSTAT_UP_OVERRUN 0x00010000 477117295Smux#define XL_RXSTAT_RUNT 0x00020000 478117295Smux#define XL_RXSTAT_ALIGN 0x00040000 479117295Smux#define XL_RXSTAT_CRC 0x00080000 480117354Smux#define XL_RXSTAT_OVERSIZE 0x00100000 481153003Smarcel#define XL_RXSTAT_DRIBBLE 0x00800000 482117354Smux#define XL_RXSTAT_UP_OFLOW 0x01000000 483153003Smarcel#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 484117354Smux#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 485117354Smux#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 48654134Swpaul#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 48754134Swpaul#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 48854134Swpaul#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */ 48954134Swpaul#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 49054134Swpaul 49154134Swpaul#define XL_TXSTAT_LENMASK 0x00001FFF 49254134Swpaul#define XL_TXSTAT_CRCDIS 0x00002000 49354134Swpaul#define XL_TXSTAT_TX_INTR 0x00008000 494117295Smux#define XL_TXSTAT_DL_COMPLETE 0x00010000 495117295Smux#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 496117295Smux#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 49754134Swpaul#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 498117295Smux#define XL_TXSTAT_DL_INTR 0x80000000 49954134Swpaul 50054134Swpaul#define XL_CAPABILITY_BM 0x20 50154134Swpaul 50254134Swpaul 50354134Swpaulstruct xl_type { 50454134Swpaul u_int16_t xl_vid; 50566681Swpaul u_int16_t xl_did; 50666681Swpaul char *xl_name; 50766681Swpaul}; 50866681Swpaul 50966681Swpaulstruct xl_mii_frame { 51066681Swpaul u_int8_t mii_stdelim; 51166681Swpaul u_int8_t mii_opcode; 51266681Swpaul u_int8_t mii_phyaddr; 51366681Swpaul u_int8_t mii_regaddr; 51466681Swpaul u_int8_t mii_turnaround; 51554134Swpaul u_int16_t mii_data; 516159202Sjhb}; 517159202Sjhb 51854134Swpaul/* 51954134Swpaul * MII constants 52054134Swpaul */ 52154134Swpaul#define XL_MII_STARTDELIM 0x01 52254134Swpaul#define XL_MII_READOP 0x02 52354134Swpaul#define XL_MII_WRITEOP 0x01 52454134Swpaul#define XL_MII_TURNAROUND 0x02 52554134Swpaul 52654134Swpaul/* 52754134Swpaul * The 3C905B adapters implement a few features that we want to 52854134Swpaul * take advantage of, namely the multicast hash filter. With older 52954134Swpaul * chips, you only have the option of turning on reception of all 53054134Swpaul * multicast frames, which is kind of lame. 53154134Swpaul */ 53254134Swpaul#define XL_TYPE_905B 1 53354134Swpaul#define XL_TYPE_90X 2 53454134Swpaul 53554134Swpaulstruct xl_softc { 53654134Swpaul struct arpcom arpcom; /* interface info */ 53754134Swpaul struct ifmedia ifmedia; /* media info */ 53854134Swpaul bus_space_handle_t xl_bhandle; 53954134Swpaul bus_space_tag_t xl_btag; 54054134Swpaul void *xl_intrhand; 54154134Swpaul struct resource *xl_irq; 54254134Swpaul struct resource *xl_res; 54354134Swpaul device_t xl_miibus; 54454134Swpaul struct xl_type *xl_info; /* 3Com adapter info */ 54554134Swpaul u_int8_t xl_unit; /* interface number */ 546201430Smbr u_int8_t xl_type; 547201430Smbr u_int32_t xl_xcvr; 54854134Swpaul u_int16_t xl_media; 549103684Smbr u_int16_t xl_caps; 55054134Swpaul u_int8_t xl_stats_no_timeout; 55154134Swpaul u_int16_t xl_tx_thresh; 55254134Swpaul caddr_t xl_ldata_ptr; 55354134Swpaul struct xl_list_data *xl_ldata; 55454134Swpaul struct xl_chain_data xl_cdata; 55554134Swpaul struct callout_handle xl_stat_ch; 55654134Swpaul}; 55754134Swpaul 55854134Swpaul#define xl_rx_goodframes(x) \ 55954134Swpaul ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 56054134Swpaul 56154134Swpaul#define xl_tx_goodframes(x) \ 562103684Smbr ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 56354134Swpaul 56454134Swpaulstruct xl_stats { 56554134Swpaul u_int8_t xl_carrier_lost; 56654134Swpaul u_int8_t xl_sqe_errs; 56754134Swpaul u_int8_t xl_tx_multi_collision; 56854134Swpaul u_int8_t xl_tx_single_collision; 56954134Swpaul u_int8_t xl_tx_late_collision; 57054134Swpaul u_int8_t xl_rx_overrun; 57154134Swpaul u_int8_t xl_tx_frames_ok; 57254134Swpaul u_int8_t xl_rx_frames_ok; 57354134Swpaul u_int8_t xl_tx_deferred; 57454134Swpaul u_int8_t xl_upper_frames_ok; 57554134Swpaul u_int16_t xl_rx_bytes_ok; 57654134Swpaul u_int16_t xl_tx_bytes_ok; 57754134Swpaul u_int16_t status; 57854134Swpaul}; 57954134Swpaul 58054134Swpaul/* 58154134Swpaul * register space access macros 58254134Swpaul */ 58354134Swpaul#define CSR_WRITE_4(sc, reg, val) \ 58454134Swpaul bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val) 58554134Swpaul#define CSR_WRITE_2(sc, reg, val) \ 58654134Swpaul bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val) 58754134Swpaul#define CSR_WRITE_1(sc, reg, val) \ 58854134Swpaul bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val) 58954134Swpaul 59054134Swpaul#define CSR_READ_4(sc, reg) \ 59154134Swpaul bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg) 59254134Swpaul#define CSR_READ_2(sc, reg) \ 59354134Swpaul bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg) 59454134Swpaul#define CSR_READ_1(sc, reg) \ 59554134Swpaul bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg) 59654134Swpaul 59754134Swpaul#define XL_SEL_WIN(x) \ 59854134Swpaul CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 59954134Swpaul#define XL_TIMEOUT 1000 60054134Swpaul 60154134Swpaul/* 60254134Swpaul * General constants that are fun to know. 60354134Swpaul * 60454134Swpaul * 3Com PCI vendor ID 60554134Swpaul */ 60654134Swpaul#define TC_VENDORID 0x10B7 60754134Swpaul 60854134Swpaul/* 60954134Swpaul * 3Com chip device IDs. 61054134Swpaul */ 61154134Swpaul#define TC_DEVICEID_BOOMERANG_10BT 0x9000 61254134Swpaul#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 61354134Swpaul#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 61454134Swpaul#define TC_DEVICEID_BOOMERANG_100BT4 0x9051 61554134Swpaul#define TC_DEVICEID_KRAKATOA_10BT 0x9004 61654134Swpaul#define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005 61754134Swpaul#define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006 61854134Swpaul#define TC_DEVICEID_CYCLONE_10FL 0x900A 61954134Swpaul#define TC_DEVICEID_HURRICANE_10_100BT 0x9055 62054134Swpaul#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 62154134Swpaul#define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058 62254134Swpaul#define TC_DEVICEID_CYCLONE_10_100FX 0x905A 62354134Swpaul#define TC_DEVICEID_TORNADO_10_100BT 0x9200 62454134Swpaul#define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800 62554134Swpaul#define TC_DEVICEID_TORNADO_10_100BT_SERV 0x9805 62654134Swpaul#define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646 62754134Swpaul 62854134Swpaul/* 62954134Swpaul * PCI low memory base and low I/O base register, and 63054134Swpaul * other PCI registers. Note: some are only available on 63154134Swpaul * the 3c905B, in particular those that related to power management. 63254134Swpaul */ 63354134Swpaul 63454134Swpaul#define XL_PCI_VENDOR_ID 0x00 63554134Swpaul#define XL_PCI_DEVICE_ID 0x02 63654134Swpaul#define XL_PCI_COMMAND 0x04 63754134Swpaul#define XL_PCI_STATUS 0x06 63854134Swpaul#define XL_PCI_CLASSCODE 0x09 63954134Swpaul#define XL_PCI_LATENCY_TIMER 0x0D 64054134Swpaul#define XL_PCI_HEADER_TYPE 0x0E 64154134Swpaul#define XL_PCI_LOIO 0x10 64254134Swpaul#define XL_PCI_LOMEM 0x14 64354134Swpaul#define XL_PCI_BIOSROM 0x30 64454134Swpaul#define XL_PCI_INTLINE 0x3C 64554134Swpaul#define XL_PCI_INTPIN 0x3D 64654134Swpaul#define XL_PCI_MINGNT 0x3E 64754134Swpaul#define XL_PCI_MINLAT 0x0F 64854134Swpaul#define XL_PCI_RESETOPT 0x48 64954134Swpaul#define XL_PCI_EEPROM_DATA 0x4C 65054134Swpaul 65154134Swpaul/* 3c905B-only registers */ 65254134Swpaul#define XL_PCI_CAPID 0xDC /* 8 bits */ 65354134Swpaul#define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 65454134Swpaul#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 65554134Swpaul#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 65654134Swpaul 65754134Swpaul#define XL_PSTATE_MASK 0x0003 65854134Swpaul#define XL_PSTATE_D0 0x0000 65954134Swpaul#define XL_PSTATE_D1 0x0002 66054134Swpaul#define XL_PSTATE_D2 0x0002 66154134Swpaul#define XL_PSTATE_D3 0x0003 66254134Swpaul#define XL_PME_EN 0x0010 66354134Swpaul#define XL_PME_STATUS 0x8000 66454134Swpaul 66554134Swpaul#ifdef __alpha__ 66654134Swpaul#undef vtophys 66754134Swpaul#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 66854134Swpaul 66954134Swpaul#endif 67054134Swpaul 67154134Swpaul#ifndef IFM_10_FL 67254134Swpaul#define IFM_10_FL 13 /* 10baseFL - Fiber */ 67354134Swpaul#endif 67454134Swpaul