if_xlreg.h revision 112364
1136301Syongari/* 2136301Syongari * Copyright (c) 1997, 1998 3136301Syongari * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4136301Syongari * 5136301Syongari * Redistribution and use in source and binary forms, with or without 6136301Syongari * modification, are permitted provided that the following conditions 7136301Syongari * are met: 8136301Syongari * 1. Redistributions of source code must retain the above copyright 9136301Syongari * notice, this list of conditions and the following disclaimer. 10136301Syongari * 2. Redistributions in binary form must reproduce the above copyright 11136301Syongari * notice, this list of conditions and the following disclaimer in the 12136301Syongari * documentation and/or other materials provided with the distribution. 13136301Syongari * 3. All advertising materials mentioning features or use of this software 14136301Syongari * must display the following acknowledgement: 15136301Syongari * This product includes software developed by Bill Paul. 16136301Syongari * 4. Neither the name of the author nor the names of any co-contributors 17136301Syongari * may be used to endorse or promote products derived from this software 18136301Syongari * without specific prior written permission. 19136301Syongari * 20136301Syongari * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21136301Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22136301Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23136301Syongari * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24136301Syongari * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25136301Syongari * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26136301Syongari * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27136301Syongari * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28136301Syongari * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29136301Syongari * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30139749Simp * THE POSSIBILITY OF SUCH DAMAGE. 31136301Syongari * 32136301Syongari * $FreeBSD: head/sys/pci/if_xlreg.h 112364 2003-03-18 06:29:51Z silby $ 33136301Syongari */ 34136301Syongari 35136301Syongari#define XL_EE_READ 0x0080 /* read, 5 bit address */ 36136301Syongari#define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 37136301Syongari#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 38136301Syongari#define XL_EE_EWEN 0x0030 /* erase, no data needed */ 39136301Syongari#define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */ 40136301Syongari#define XL_EE_BUSY 0x8000 41136301Syongari 42136301Syongari#define XL_EE_EADDR0 0x00 /* station address, first word */ 43136301Syongari#define XL_EE_EADDR1 0x01 /* station address, next word, */ 44136301Syongari#define XL_EE_EADDR2 0x02 /* station address, last word */ 45136301Syongari#define XL_EE_PRODID 0x03 /* product ID code */ 46136301Syongari#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 47136301Syongari#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 48136301Syongari#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 49136301Syongari#define XL_EE_MFG_ID 0x07 50136301Syongari#define XL_EE_PCI_PARM 0x08 51136301Syongari#define XL_EE_ROM_ONFO 0x09 52136301Syongari#define XL_EE_OEM_ADR0 0x0A 53136301Syongari#define XL_EE_OEM_ADR1 0x0B 54136301Syongari#define XL_EE_OEM_ADR2 0x0C 55136301Syongari#define XL_EE_SOFTINFO1 0x0D 56136301Syongari#define XL_EE_COMPAT 0x0E 57136301Syongari#define XL_EE_SOFTINFO2 0x0F 58136301Syongari#define XL_EE_CAPS 0x10 /* capabilities word */ 59200815Smarius#define XL_EE_RSVD0 0x11 60136301Syongari#define XL_EE_ICFG_0 0x12 61136301Syongari#define XL_EE_ICFG_1 0x13 62136301Syongari#define XL_EE_RSVD1 0x14 63136301Syongari#define XL_EE_SOFTINFO3 0x15 64136301Syongari#define XL_EE_RSVD_2 0x16 65136301Syongari 66136301Syongari/* 67136301Syongari * Bits in the capabilities word 68136301Syongari */ 69136301Syongari#define XL_CAPS_PNP 0x0001 70136301Syongari#define XL_CAPS_FULL_DUPLEX 0x0002 71136301Syongari#define XL_CAPS_LARGE_PKTS 0x0004 72136301Syongari#define XL_CAPS_SLAVE_DMA 0x0008 73136301Syongari#define XL_CAPS_SECOND_DMA 0x0010 74136301Syongari#define XL_CAPS_FULL_BM 0x0020 75136301Syongari#define XL_CAPS_FRAG_BM 0x0040 76136301Syongari#define XL_CAPS_CRC_PASSTHRU 0x0080 77136301Syongari#define XL_CAPS_TXDONE 0x0100 78136301Syongari#define XL_CAPS_NO_TXLENGTH 0x0200 79136301Syongari#define XL_CAPS_RX_REPEAT 0x0400 80136301Syongari#define XL_CAPS_SNOOPING 0x0800 81136301Syongari#define XL_CAPS_100MBPS 0x1000 82136301Syongari#define XL_CAPS_PWRMGMT 0x2000 83136301Syongari 84136301Syongari#define XL_PACKET_SIZE 1540 85136301Syongari 86136301Syongari/* 87136301Syongari * Register layouts. 88200815Smarius */ 89200815Smarius#define XL_COMMAND 0x0E 90136301Syongari#define XL_STATUS 0x0E 91136301Syongari 92136301Syongari#define XL_TX_STATUS 0x1B 93136301Syongari#define XL_TX_FREE 0x1C 94136301Syongari#define XL_DMACTL 0x20 95136301Syongari#define XL_DOWNLIST_PTR 0x24 96136301Syongari#define XL_DOWN_POLL 0x2D /* 3c90xB only */ 97136301Syongari#define XL_TX_FREETHRESH 0x2F 98147877Smarius#define XL_UPLIST_PTR 0x38 99136301Syongari#define XL_UPLIST_STATUS 0x30 100136301Syongari#define XL_UP_POLL 0x3D /* 3c90xB only */ 101136301Syongari 102136301Syongari#define XL_PKTSTAT_UP_STALLED 0x00002000 103136301Syongari#define XL_PKTSTAT_UP_ERROR 0x00004000 104147877Smarius#define XL_PKTSTAT_UP_CMPLT 0x00008000 105147877Smarius 106147877Smarius#define XL_DMACTL_DN_CMPLT_REQ 0x00000002 107147877Smarius#define XL_DMACTL_DOWN_STALLED 0x00000004 108136301Syongari#define XL_DMACTL_UP_CMPLT 0x00000008 109136301Syongari#define XL_DMACTL_DOWN_CMPLT 0x00000010 110136301Syongari#define XL_DMACTL_UP_RX_EARLY 0x00000020 111136301Syongari#define XL_DMACTL_ARM_COUNTDOWN 0x00000040 112136301Syongari#define XL_DMACTL_DOWN_INPROG 0x00000080 113136301Syongari#define XL_DMACTL_COUNTER_SPEED 0x00000100 114136301Syongari#define XL_DMACTL_DOWNDOWN_MODE 0x00000200 115136301Syongari#define XL_DMACTL_TARGET_ABORT 0x40000000 116136301Syongari#define XL_DMACTL_MASTER_ABORT 0x80000000 117136301Syongari 118136301Syongari/* 119136301Syongari * Command codes. Some command codes require that we wait for 120146965Smarius * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 121136301Syongari */ 122136301Syongari#define XL_CMD_RESET 0x0000 /* mustwait */ 123136301Syongari#define XL_CMD_WINSEL 0x0800 124136301Syongari#define XL_CMD_COAX_START 0x1000 125136301Syongari#define XL_CMD_RX_DISABLE 0x1800 126136301Syongari#define XL_CMD_RX_ENABLE 0x2000 127136301Syongari#define XL_CMD_RX_RESET 0x2800 /* mustwait */ 128136301Syongari#define XL_CMD_UP_STALL 0x3000 /* mustwait */ 129136301Syongari#define XL_CMD_UP_UNSTALL 0x3001 130136301Syongari#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 131136301Syongari#define XL_CMD_DOWN_UNSTALL 0x3003 132136301Syongari#define XL_CMD_RX_DISCARD 0x4000 133136301Syongari#define XL_CMD_TX_ENABLE 0x4800 134246128Ssbz#define XL_CMD_TX_DISABLE 0x5000 135246128Ssbz#define XL_CMD_TX_RESET 0x5800 /* mustwait */ 136136301Syongari#define XL_CMD_INTR_FAKE 0x6000 137136301Syongari#define XL_CMD_INTR_ACK 0x6800 138136301Syongari#define XL_CMD_INTR_ENB 0x7000 139136301Syongari#define XL_CMD_STAT_ENB 0x7800 140136301Syongari#define XL_CMD_RX_SET_FILT 0x8000 141136301Syongari#define XL_CMD_RX_SET_THRESH 0x8800 142136301Syongari#define XL_CMD_TX_SET_THRESH 0x9000 143136301Syongari#define XL_CMD_TX_SET_START 0x9800 144136301Syongari#define XL_CMD_DMA_UP 0xA000 145200874Smarius#define XL_CMD_DMA_STOP 0xA001 146200874Smarius#define XL_CMD_STATS_ENABLE 0xA800 147200874Smarius#define XL_CMD_STATS_DISABLE 0xB000 148200815Smarius#define XL_CMD_COAX_STOP 0xB800 149136301Syongari 150136301Syongari#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 151136301Syongari#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 152136301Syongari 153136301Syongari#define XL_HASH_SET 0x0400 154136301Syongari#define XL_HASHFILT_SIZE 256 155246128Ssbz 156246128Ssbz/* 157136301Syongari * status codes 158136301Syongari * Note that bits 15 to 13 indicate the currently visible register window 159136301Syongari * which may be anything from 0 to 7. 160136301Syongari */ 161136301Syongari#define XL_STAT_INTLATCH 0x0001 /* 0 */ 162136301Syongari#define XL_STAT_ADFAIL 0x0002 /* 1 */ 163136301Syongari#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 164136301Syongari#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 165200874Smarius#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 166200874Smarius#define XL_STAT_RX_EARLY 0x0020 /* 5 */ 167200815Smarius#define XL_STAT_INTREQ 0x0040 /* 6 */ 168136301Syongari#define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 169136301Syongari#define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 170136301Syongari#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 171136301Syongari#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 172136301Syongari#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 173136301Syongari#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 174136301Syongari#define XL_STAT_CMDBUSY 0x1000 /* 12 */ 175136301Syongari 176136301Syongari/* 177136301Syongari * Interrupts we normally want enabled. 178136301Syongari */ 179136301Syongari#define XL_INTRS \ 180136301Syongari (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \ 181136301Syongari XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH) 182136301Syongari 183136301Syongari/* 184136301Syongari * Window 0 registers 185136301Syongari */ 186136301Syongari#define XL_W0_EE_DATA 0x0C 187136301Syongari#define XL_W0_EE_CMD 0x0A 188136301Syongari#define XL_W0_RSRC_CFG 0x08 189136301Syongari#define XL_W0_ADDR_CFG 0x06 190136301Syongari#define XL_W0_CFG_CTRL 0x04 191136301Syongari 192136301Syongari#define XL_W0_PROD_ID 0x02 193136301Syongari#define XL_W0_MFG_ID 0x00 194136301Syongari 195136301Syongari/* 196136301Syongari * Window 1 197136301Syongari */ 198136301Syongari 199136301Syongari#define XL_W1_TX_FIFO 0x10 200136301Syongari 201136301Syongari#define XL_W1_FREE_TX 0x0C 202136301Syongari#define XL_W1_TX_STATUS 0x0B 203136301Syongari#define XL_W1_TX_TIMER 0x0A 204136301Syongari#define XL_W1_RX_STATUS 0x08 205136301Syongari#define XL_W1_RX_FIFO 0x00 206136301Syongari 207136301Syongari/* 208136301Syongari * RX status codes 209136301Syongari */ 210136301Syongari#define XL_RXSTATUS_OVERRUN 0x01 211154864Smarius#define XL_RXSTATUS_RUNT 0x02 212154864Smarius#define XL_RXSTATUS_ALIGN 0x04 213154864Smarius#define XL_RXSTATUS_CRC 0x08 214154864Smarius#define XL_RXSTATUS_OVERSIZE 0x10 215154864Smarius#define XL_RXSTATUS_DRIBBLE 0x20 216154864Smarius 217154864Smarius/* 218154864Smarius * TX status codes 219136301Syongari */ 220136301Syongari#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 221136301Syongari#define XL_TXSTATUS_OVERFLOW 0x04 222136301Syongari#define XL_TXSTATUS_MAXCOLS 0x08 223136301Syongari#define XL_TXSTATUS_UNDERRUN 0x10 224136301Syongari#define XL_TXSTATUS_JABBER 0x20 225136301Syongari#define XL_TXSTATUS_INTREQ 0x40 226136301Syongari#define XL_TXSTATUS_COMPLETE 0x80 227136301Syongari 228136301Syongari/* 229136301Syongari * Window 2 230136301Syongari */ 231136301Syongari#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 232136301Syongari#define XL_W2_STATION_MASK_HI 0x0A 233136301Syongari#define XL_W2_STATION_MASK_MID 0x08 234136301Syongari#define XL_W2_STATION_MASK_LO 0x06 235136301Syongari#define XL_W2_STATION_ADDR_HI 0x04 236136301Syongari#define XL_W2_STATION_ADDR_MID 0x02 237136301Syongari#define XL_W2_STATION_ADDR_LO 0x00 238136301Syongari 239136301Syongari#define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 240136301Syongari#define XL_RESETOPT_D3RESETDIS 0x0008 241136301Syongari#define XL_RESETOPT_DISADVFD 0x0010 242136301Syongari#define XL_RESETOPT_DISADV100 0x0020 243136301Syongari#define XL_RESETOPT_DISAUTONEG 0x0040 244136301Syongari#define XL_RESETOPT_DEBUGMODE 0x0080 245136301Syongari#define XL_RESETOPT_FASTAUTO 0x0100 246147877Smarius#define XL_RESETOPT_FASTEE 0x0200 247146965Smarius#define XL_RESETOPT_FORCEDCONF 0x0400 248146965Smarius#define XL_RESETOPT_TESTPDTPDR 0x0800 249146965Smarius#define XL_RESETOPT_TEST100TX 0x1000 250146965Smarius#define XL_RESETOPT_TEST100RX 0x2000 251146965Smarius 252146965Smarius#define XL_RESETOPT_INVERT_LED 0x0010 253146965Smarius#define XL_RESETOPT_INVERT_MII 0x4000 254146965Smarius 255146965Smarius/* 256146965Smarius * Window 3 (fifo management) 257146965Smarius */ 258146965Smarius#define XL_W3_INTERNAL_CFG 0x00 259146965Smarius#define XL_W3_MAXPKTSIZE 0x04 /* 3c905B only */ 260146965Smarius#define XL_W3_RESET_OPT 0x08 261136301Syongari#define XL_W3_FREE_TX 0x0C 262136301Syongari#define XL_W3_FREE_RX 0x0A 263136301Syongari#define XL_W3_MAC_CTRL 0x06 264136301Syongari 265136301Syongari#define XL_ICFG_CONNECTOR_MASK 0x00F00000 266136301Syongari#define XL_ICFG_CONNECTOR_BITS 20 267136301Syongari 268136301Syongari#define XL_ICFG_RAMSIZE_MASK 0x00000007 269136301Syongari#define XL_ICFG_RAMWIDTH 0x00000008 270136301Syongari#define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 271136301Syongari#define XL_ICFG_DISABLE_BASSD 0x00000100 272154864Smarius#define XL_ICFG_RAMLOC 0x00000200 273146965Smarius#define XL_ICFG_RAMPART (0x00010000|0x00020000) 274146965Smarius#define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 275146965Smarius#define XL_ICFG_AUTOSEL 0x01000000 276146965Smarius 277136301Syongari#define XL_XCVR_10BT 0x00 278136301Syongari#define XL_XCVR_AUI 0x01 279136301Syongari#define XL_XCVR_RSVD_0 0x02 280136301Syongari#define XL_XCVR_COAX 0x03 281136301Syongari#define XL_XCVR_100BTX 0x04 282136301Syongari#define XL_XCVR_100BFX 0x05 283136301Syongari#define XL_XCVR_MII 0x06 284136301Syongari#define XL_XCVR_RSVD_1 0x07 285136301Syongari#define XL_XCVR_AUTO 0x08 /* 3c905B only */ 286136301Syongari 287136301Syongari#define XL_MACCTRL_DEFER_EXT_END 0x0001 288136301Syongari#define XL_MACCTRL_DEFER_0 0x0002 289136301Syongari#define XL_MACCTRL_DEFER_1 0x0004 290136301Syongari#define XL_MACCTRL_DEFER_2 0x0008 291136301Syongari#define XL_MACCTRL_DEFER_3 0x0010 292136301Syongari#define XL_MACCTRL_DUPLEX 0x0020 293136301Syongari#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 294136301Syongari#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 295136301Syongari#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 296136301Syongari#define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 297136301Syongari 298136301Syongari/* 299136301Syongari * The 'reset options' register contains power-on reset values 300136301Syongari * loaded from the EEPROM. This includes the supported media 301146965Smarius * types on the card. It is also known as the media options register. 302136301Syongari */ 303146965Smarius#define XL_W3_MEDIA_OPT 0x08 304136301Syongari 305146965Smarius#define XL_MEDIAOPT_BT4 0x0001 /* MII */ 306146965Smarius#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 307136301Syongari#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 308136301Syongari#define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 309136301Syongari#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 310136301Syongari#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 311136301Syongari#define XL_MEDIAOPT_MII 0x0040 /* MII */ 312136301Syongari#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 313136301Syongari 314136301Syongari#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 315136301Syongari#define XL_MEDIAOPT_MASK 0x01FF 316136301Syongari 317136301Syongari/* 318136301Syongari * Window 4 (diagnostics) 319136301Syongari */ 320136301Syongari#define XL_W4_UPPERBYTESOK 0x0D 321136301Syongari#define XL_W4_BADSSD 0x0C 322146965Smarius#define XL_W4_MEDIA_STATUS 0x0A 323136301Syongari#define XL_W4_PHY_MGMT 0x08 324#define XL_W4_NET_DIAG 0x06 325#define XL_W4_FIFO_DIAG 0x04 326#define XL_W4_VCO_DIAG 0x02 327 328#define XL_W4_CTRLR_STAT 0x08 329#define XL_W4_TX_DIAG 0x00 330 331#define XL_MII_CLK 0x01 332#define XL_MII_DATA 0x02 333#define XL_MII_DIR 0x04 334 335#define XL_MEDIA_SQE 0x0008 336#define XL_MEDIA_10TP 0x00C0 337#define XL_MEDIA_LNK 0x0080 338#define XL_MEDIA_LNKBEAT 0x0800 339 340#define XL_MEDIASTAT_CRCSTRIP 0x0004 341#define XL_MEDIASTAT_SQEENB 0x0008 342#define XL_MEDIASTAT_COLDET 0x0010 343#define XL_MEDIASTAT_CARRIER 0x0020 344#define XL_MEDIASTAT_JABGUARD 0x0040 345#define XL_MEDIASTAT_LINKBEAT 0x0080 346#define XL_MEDIASTAT_JABDETECT 0x0200 347#define XL_MEDIASTAT_POLREVERS 0x0400 348#define XL_MEDIASTAT_LINKDETECT 0x0800 349#define XL_MEDIASTAT_TXINPROG 0x1000 350#define XL_MEDIASTAT_DCENB 0x4000 351#define XL_MEDIASTAT_AUIDIS 0x8000 352 353#define XL_NETDIAG_TEST_LOWVOLT 0x0001 354#define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 355#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 356#define XL_NETDIAG_STATS_ENABLED 0x0080 357#define XL_NETDIAG_TX_FATALERR 0x0100 358#define XL_NETDIAG_TRANSMITTING 0x0200 359#define XL_NETDIAG_RX_ENABLED 0x0400 360#define XL_NETDIAG_TX_ENABLED 0x0800 361#define XL_NETDIAG_FIFO_LOOPBACK 0x1000 362#define XL_NETDIAG_MAC_LOOPBACK 0x2000 363#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 364#define XL_NETDIAG_EXTERNAL_LOOP 0x8000 365 366/* 367 * Window 5 368 */ 369#define XL_W5_STAT_ENB 0x0C 370#define XL_W5_INTR_ENB 0x0A 371#define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */ 372#define XL_W5_RX_FILTER 0x08 373#define XL_W5_RX_EARLYTHRESH 0x06 374#define XL_W5_TX_AVAILTHRESH 0x02 375#define XL_W5_TX_STARTTHRESH 0x00 376 377/* 378 * RX filter bits 379 */ 380#define XL_RXFILTER_INDIVIDUAL 0x01 381#define XL_RXFILTER_ALLMULTI 0x02 382#define XL_RXFILTER_BROADCAST 0x04 383#define XL_RXFILTER_ALLFRAMES 0x08 384#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 385 386/* 387 * Window 6 (stats) 388 */ 389#define XL_W6_TX_BYTES_OK 0x0C 390#define XL_W6_RX_BYTES_OK 0x0A 391#define XL_W6_UPPER_FRAMES_OK 0x09 392#define XL_W6_DEFERRED 0x08 393#define XL_W6_RX_OK 0x07 394#define XL_W6_TX_OK 0x06 395#define XL_W6_RX_OVERRUN 0x05 396#define XL_W6_COL_LATE 0x04 397#define XL_W6_COL_SINGLE 0x03 398#define XL_W6_COL_MULTIPLE 0x02 399#define XL_W6_SQE_ERRORS 0x01 400#define XL_W6_CARRIER_LOST 0x00 401 402/* 403 * Window 7 (bus master control) 404 */ 405#define XL_W7_BM_ADDR 0x00 406#define XL_W7_BM_LEN 0x06 407#define XL_W7_BM_STATUS 0x0B 408#define XL_W7_BM_TIMEr 0x0A 409 410/* 411 * bus master control registers 412 */ 413#define XL_BM_PKTSTAT 0x20 414#define XL_BM_DOWNLISTPTR 0x24 415#define XL_BM_FRAGADDR 0x28 416#define XL_BM_FRAGLEN 0x2C 417#define XL_BM_TXFREETHRESH 0x2F 418#define XL_BM_UPPKTSTAT 0x30 419#define XL_BM_UPLISTPTR 0x38 420 421#define XL_LAST_FRAG 0x80000000 422 423#define XL_MAXFRAGS 63 424#define XL_RX_LIST_CNT 128 425#define XL_TX_LIST_CNT 256 426#define XL_RX_LIST_SZ XL_RX_LIST_CNT * sizeof(struct xl_list_onefrag) 427#define XL_TX_LIST_SZ XL_TX_LIST_CNT * sizeof(struct xl_list) 428#define XL_MIN_FRAMELEN 60 429#define ETHER_ALIGN 2 430#define XL_INC(x, y) (x) = (x + 1) % y 431 432/* 433 * Boomerang/Cyclone TX/RX list structure. 434 * For the TX lists, bits 0 to 12 of the status word indicate 435 * length. 436 * This looks suspiciously like the ThunderLAN, doesn't it. 437 */ 438struct xl_frag { 439 u_int32_t xl_addr; /* 63 addr/len pairs */ 440 u_int32_t xl_len; 441}; 442 443struct xl_list { 444 u_int32_t xl_next; /* final entry has 0 nextptr */ 445 u_int32_t xl_status; 446 struct xl_frag xl_frag[XL_MAXFRAGS]; 447}; 448 449struct xl_list_onefrag { 450 u_int32_t xl_next; /* final entry has 0 nextptr */ 451 u_int32_t xl_status; 452 struct xl_frag xl_frag; 453}; 454 455struct xl_list_data { 456 struct xl_list_onefrag *xl_rx_list; 457 struct xl_list *xl_tx_list; 458 u_int32_t xl_rx_dmaaddr; 459 bus_dma_tag_t xl_rx_tag; 460 bus_dmamap_t xl_rx_dmamap; 461 u_int32_t xl_tx_dmaaddr; 462 bus_dma_tag_t xl_tx_tag; 463 bus_dmamap_t xl_tx_dmamap; 464}; 465 466struct xl_chain { 467 struct xl_list *xl_ptr; 468 struct mbuf *xl_mbuf; 469 struct xl_chain *xl_next; 470 struct xl_chain *xl_prev; 471 u_int32_t xl_phys; 472 bus_dmamap_t xl_map; 473}; 474 475struct xl_chain_onefrag { 476 struct xl_list_onefrag *xl_ptr; 477 struct mbuf *xl_mbuf; 478 struct xl_chain_onefrag *xl_next; 479 bus_dmamap_t xl_map; 480}; 481 482struct xl_chain_data { 483 struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 484 struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 485 486 struct xl_chain_onefrag *xl_rx_head; 487 488 /* 3c90x "boomerang" queuing stuff */ 489 struct xl_chain *xl_tx_head; 490 struct xl_chain *xl_tx_tail; 491 struct xl_chain *xl_tx_free; 492 493 /* 3c90xB "cyclone/hurricane/tornado" stuff */ 494 int xl_tx_prod; 495 int xl_tx_cons; 496 int xl_tx_cnt; 497}; 498 499#define XL_RXSTAT_LENMASK 0x00001FFF 500#define XL_RXSTAT_UP_ERROR 0x00004000 501#define XL_RXSTAT_UP_CMPLT 0x00008000 502#define XL_RXSTAT_UP_OVERRUN 0x00010000 503#define XL_RXSTAT_RUNT 0x00020000 504#define XL_RXSTAT_ALIGN 0x00040000 505#define XL_RXSTAT_CRC 0x00080000 506#define XL_RXSTAT_OVERSIZE 0x00100000 507#define XL_RXSTAT_DRIBBLE 0x00800000 508#define XL_RXSTAT_UP_OFLOW 0x01000000 509#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 510#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 511#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 512#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 513#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 514#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */ 515#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 516 517#define XL_TXSTAT_LENMASK 0x00001FFF 518#define XL_TXSTAT_CRCDIS 0x00002000 519#define XL_TXSTAT_TX_INTR 0x00008000 520#define XL_TXSTAT_DL_COMPLETE 0x00010000 521#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 522#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 523#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 524#define XL_TXSTAT_RND_DEFEAT 0x10000000 /* 3c905B only */ 525#define XL_TXSTAT_EMPTY 0x20000000 /* 3c905B only */ 526#define XL_TXSTAT_DL_INTR 0x80000000 527 528#define XL_CAPABILITY_BM 0x20 529 530struct xl_type { 531 u_int16_t xl_vid; 532 u_int16_t xl_did; 533 char *xl_name; 534}; 535 536struct xl_mii_frame { 537 u_int8_t mii_stdelim; 538 u_int8_t mii_opcode; 539 u_int8_t mii_phyaddr; 540 u_int8_t mii_regaddr; 541 u_int8_t mii_turnaround; 542 u_int16_t mii_data; 543}; 544 545/* 546 * MII constants 547 */ 548#define XL_MII_STARTDELIM 0x01 549#define XL_MII_READOP 0x02 550#define XL_MII_WRITEOP 0x01 551#define XL_MII_TURNAROUND 0x02 552 553/* 554 * The 3C905B adapters implement a few features that we want to 555 * take advantage of, namely the multicast hash filter. With older 556 * chips, you only have the option of turning on reception of all 557 * multicast frames, which is kind of lame. 558 * 559 * We also use this to decide on a transmit strategy. For the 3c90xB 560 * cards, we can use polled descriptor mode, which reduces CPU overhead. 561 */ 562#define XL_TYPE_905B 1 563#define XL_TYPE_90X 2 564 565#define XL_FLAG_FUNCREG 0x0001 566#define XL_FLAG_PHYOK 0x0002 567#define XL_FLAG_EEPROM_OFFSET_30 0x0004 568#define XL_FLAG_WEIRDRESET 0x0008 569#define XL_FLAG_8BITROM 0x0010 570#define XL_FLAG_INVERT_LED_PWR 0x0020 571#define XL_FLAG_INVERT_MII_PWR 0x0040 572#define XL_FLAG_NO_XCVR_PWR 0x0080 573#define XL_FLAG_USE_MMIO 0x0100 574 575#define XL_NO_XCVR_PWR_MAGICBITS 0x0900 576 577struct xl_softc { 578 struct arpcom arpcom; /* interface info */ 579 struct ifmedia ifmedia; /* media info */ 580 bus_space_handle_t xl_bhandle; 581 bus_space_tag_t xl_btag; 582 void *xl_intrhand; 583 struct resource *xl_irq; 584 struct resource *xl_res; 585 device_t xl_miibus; 586 struct xl_type *xl_info; /* 3Com adapter info */ 587 bus_dma_tag_t xl_mtag; 588 bus_dmamap_t xl_tmpmap; /* spare DMA map */ 589 u_int8_t xl_unit; /* interface number */ 590 u_int8_t xl_type; 591 u_int32_t xl_xcvr; 592 u_int16_t xl_media; 593 u_int16_t xl_caps; 594 u_int8_t xl_stats_no_timeout; 595 u_int16_t xl_tx_thresh; 596 int xl_if_flags; 597 struct xl_list_data xl_ldata; 598 struct xl_chain_data xl_cdata; 599 struct callout_handle xl_stat_ch; 600 int xl_flags; 601 struct resource *xl_fres; 602 bus_space_handle_t xl_fhandle; 603 bus_space_tag_t xl_ftag; 604 struct mtx xl_mtx; 605}; 606 607#if 0 608/* These are a bit premature. The driver still tries to sleep with locks. */ 609#define XL_LOCK(_sc) mtx_lock(&(_sc)->xl_mtx) 610#define XL_UNLOCK(_sc) mtx_unlock(&(_sc)->xl_mtx) 611#else 612#define XL_LOCK(x) do { } while (0) 613#define XL_UNLOCK(x) do { } while (0) 614#endif 615 616#define xl_rx_goodframes(x) \ 617 ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 618 619#define xl_tx_goodframes(x) \ 620 ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 621 622struct xl_stats { 623 u_int8_t xl_carrier_lost; 624 u_int8_t xl_sqe_errs; 625 u_int8_t xl_tx_multi_collision; 626 u_int8_t xl_tx_single_collision; 627 u_int8_t xl_tx_late_collision; 628 u_int8_t xl_rx_overrun; 629 u_int8_t xl_tx_frames_ok; 630 u_int8_t xl_rx_frames_ok; 631 u_int8_t xl_tx_deferred; 632 u_int8_t xl_upper_frames_ok; 633 u_int16_t xl_rx_bytes_ok; 634 u_int16_t xl_tx_bytes_ok; 635 u_int16_t status; 636}; 637 638/* 639 * register space access macros 640 */ 641#define CSR_WRITE_4(sc, reg, val) \ 642 bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val) 643#define CSR_WRITE_2(sc, reg, val) \ 644 bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val) 645#define CSR_WRITE_1(sc, reg, val) \ 646 bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val) 647 648#define CSR_READ_4(sc, reg) \ 649 bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg) 650#define CSR_READ_2(sc, reg) \ 651 bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg) 652#define CSR_READ_1(sc, reg) \ 653 bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg) 654 655#define XL_SEL_WIN(x) \ 656 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 657#define XL_TIMEOUT 1000 658 659/* 660 * General constants that are fun to know. 661 * 662 * 3Com PCI vendor ID 663 */ 664#define TC_VENDORID 0x10B7 665 666/* 667 * 3Com chip device IDs. 668 */ 669#define TC_DEVICEID_BOOMERANG_10BT 0x9000 670#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 671#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 672#define TC_DEVICEID_BOOMERANG_100BT4 0x9051 673#define TC_DEVICEID_KRAKATOA_10BT 0x9004 674#define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005 675#define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006 676#define TC_DEVICEID_CYCLONE_10FL 0x900A 677#define TC_DEVICEID_HURRICANE_10_100BT 0x9055 678#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 679#define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058 680#define TC_DEVICEID_CYCLONE_10_100FX 0x905A 681#define TC_DEVICEID_TORNADO_10_100BT 0x9200 682#define TC_DEVICEID_TORNADO_10_100BT_920B 0x9201 683#define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800 684#define TC_DEVICEID_TORNADO_10_100BT_SERV 0x9805 685#define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646 686#define TC_DEVICEID_TORNADO_HOMECONNECT 0x4500 687#define TC_DEVICEID_HURRICANE_555 0x5055 688#define TC_DEVICEID_HURRICANE_556 0x6055 689#define TC_DEVICEID_HURRICANE_556B 0x6056 690#define TC_DEVICEID_HURRICANE_575A 0x5057 691#define TC_DEVICEID_HURRICANE_575B 0x5157 692#define TC_DEVICEID_HURRICANE_575C 0x5257 693#define TC_DEVICEID_HURRICANE_656 0x6560 694#define TC_DEVICEID_HURRICANE_656B 0x6562 695#define TC_DEVICEID_TORNADO_656C 0x6564 696 697/* 698 * PCI low memory base and low I/O base register, and 699 * other PCI registers. Note: some are only available on 700 * the 3c905B, in particular those that related to power management. 701 */ 702 703#define XL_PCI_VENDOR_ID 0x00 704#define XL_PCI_DEVICE_ID 0x02 705#define XL_PCI_COMMAND 0x04 706#define XL_PCI_STATUS 0x06 707#define XL_PCI_CLASSCODE 0x09 708#define XL_PCI_LATENCY_TIMER 0x0D 709#define XL_PCI_HEADER_TYPE 0x0E 710#define XL_PCI_LOIO 0x10 711#define XL_PCI_LOMEM 0x14 712#define XL_PCI_FUNCMEM 0x18 713#define XL_PCI_BIOSROM 0x30 714#define XL_PCI_INTLINE 0x3C 715#define XL_PCI_INTPIN 0x3D 716#define XL_PCI_MINGNT 0x3E 717#define XL_PCI_MINLAT 0x0F 718#define XL_PCI_RESETOPT 0x48 719#define XL_PCI_EEPROM_DATA 0x4C 720 721/* 3c905B-only registers */ 722#define XL_PCI_CAPID 0xDC /* 8 bits */ 723#define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 724#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 725#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 726 727#define XL_PSTATE_MASK 0x0003 728#define XL_PSTATE_D0 0x0000 729#define XL_PSTATE_D1 0x0002 730#define XL_PSTATE_D2 0x0002 731#define XL_PSTATE_D3 0x0003 732#define XL_PME_EN 0x0010 733#define XL_PME_STATUS 0x8000 734 735#ifndef IFM_10_FL 736#define IFM_10_FL 13 /* 10baseFL - Fiber */ 737#endif 738