1221167Sgnn/*-
2221167Sgnn * Copyright(c) 2002-2011 Exar Corp.
3221167Sgnn * All rights reserved.
4221167Sgnn *
5221167Sgnn * Redistribution and use in source and binary forms, with or without
6221167Sgnn * modification are permitted provided the following conditions are met:
7221167Sgnn *
8221167Sgnn *    1. Redistributions of source code must retain the above copyright notice,
9221167Sgnn *       this list of conditions and the following disclaimer.
10221167Sgnn *
11221167Sgnn *    2. Redistributions in binary form must reproduce the above copyright
12221167Sgnn *       notice, this list of conditions and the following disclaimer in the
13221167Sgnn *       documentation and/or other materials provided with the distribution.
14221167Sgnn *
15221167Sgnn *    3. Neither the name of the Exar Corporation nor the names of its
16221167Sgnn *       contributors may be used to endorse or promote products derived from
17221167Sgnn *       this software without specific prior written permission.
18221167Sgnn *
19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29221167Sgnn * POSSIBILITY OF SUCH DAMAGE.
30221167Sgnn */
31221167Sgnn/*$FreeBSD$*/
32221167Sgnn
33221167Sgnn#ifndef	VXGE_HAL_MRPCIM_H
34221167Sgnn#define	VXGE_HAL_MRPCIM_H
35221167Sgnn
36221167Sgnn__EXTERN_BEGIN_DECLS
37221167Sgnn
38221167Sgnn/*
39221167Sgnn * __hal_mrpcim_t
40221167Sgnn *
41221167Sgnn * HAL mrpcim object. Represents privileged mode device.
42221167Sgnn */
43221167Sgnntypedef struct __hal_mrpcim_t {
44221167Sgnn	u32	mdio_phy_prtad0;
45221167Sgnn	u32	mdio_phy_prtad1;
46221167Sgnn	u32	mdio_dte_prtad0;
47221167Sgnn	u32	mdio_dte_prtad1;
48221167Sgnn	vxge_hal_vpd_data_t vpd_data;
49221167Sgnn	__hal_blockpool_entry_t *mrpcim_stats_block;
50221167Sgnn	vxge_hal_mrpcim_stats_hw_info_t *mrpcim_stats;
51221167Sgnn	vxge_hal_mrpcim_stats_hw_info_t mrpcim_stats_sav;
52221167Sgnn	vxge_hal_mrpcim_xpak_stats_t xpak_stats[VXGE_HAL_MAC_MAX_WIRE_PORTS];
53221167Sgnn} __hal_mrpcim_t;
54221167Sgnn
55221167Sgnn#define	VXGE_HAL_MRPCIM_STATS_PIO_READ(loc, offset) {			\
56221167Sgnn	status = vxge_hal_mrpcim_stats_access(devh,			\
57221167Sgnn				VXGE_HAL_STATS_OP_READ,			\
58221167Sgnn				loc,					\
59221167Sgnn				offset,					\
60221167Sgnn				&val64);				\
61221167Sgnn									\
62221167Sgnn	if (status != VXGE_HAL_OK) {					\
63221167Sgnn		vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d",	\
64221167Sgnn				__FILE__, __func__, __LINE__, status);	\
65221167Sgnn		return (status);					\
66221167Sgnn	}								\
67221167Sgnn}
68221167Sgnn
69221167Sgnn#define	VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(reg)				\
70221167Sgnn	vxge_os_pio_mem_write64(					\
71221167Sgnn		hldev->header.pdev,					\
72221167Sgnn		hldev->header.regh0,					\
73221167Sgnn		VXGE_HAL_INTR_MASK_ALL,					\
74221167Sgnn		(reg));
75221167Sgnn
76221167Sgnn#define	VXGE_HAL_MRPCIM_ERROR_REG_MASK(reg)				\
77221167Sgnn	vxge_os_pio_mem_write64(					\
78221167Sgnn		hldev->header.pdev,					\
79221167Sgnn		hldev->header.regh0,					\
80221167Sgnn		VXGE_HAL_INTR_MASK_ALL,					\
81221167Sgnn		(reg));
82221167Sgnn
83221167Sgnn#define	VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(mask, reg)			\
84221167Sgnn	vxge_os_pio_mem_write64(					\
85221167Sgnn		hldev->header.pdev,					\
86221167Sgnn		hldev->header.regh0,					\
87221167Sgnn		~mask,							\
88221167Sgnn		(reg));
89221167Sgnn
90221167Sgnnvxge_hal_status_e
91221167Sgnn__hal_mrpcim_mdio_access(
92221167Sgnn    vxge_hal_device_h devh,
93221167Sgnn    u32 port,
94221167Sgnn    u32 operation,
95221167Sgnn    u32 device,
96221167Sgnn    u16 addr,
97221167Sgnn    u16 *data);
98221167Sgnn
99221167Sgnnvxge_hal_status_e
100221167Sgnn__hal_mrpcim_rts_table_access(
101221167Sgnn    vxge_hal_device_h devh,
102221167Sgnn    u32 action,
103221167Sgnn    u32 rts_table,
104221167Sgnn    u32 offset,
105221167Sgnn    u64 *data1,
106221167Sgnn    u64 *data2,
107221167Sgnn    u64 *vpath_vector);
108221167Sgnn
109221167Sgnnvxge_hal_status_e
110221167Sgnn__hal_mrpcim_initialize(__hal_device_t *hldev);
111221167Sgnn
112221167Sgnnvxge_hal_status_e
113221167Sgnn__hal_mrpcim_terminate(__hal_device_t *hldev);
114221167Sgnn
115221167Sgnnvoid
116221167Sgnn__hal_mrpcim_get_vpd_data(__hal_device_t *hldev);
117221167Sgnn
118221167Sgnnvoid
119221167Sgnn__hal_mrpcim_xpak_counter_check(__hal_device_t *hldev,
120221167Sgnn    u32 port, u32 type, u32 value);
121221167Sgnn
122221167Sgnnvxge_hal_status_e
123221167Sgnn__hal_mrpcim_stats_get(
124221167Sgnn    __hal_device_t *hldev,
125221167Sgnn    vxge_hal_mrpcim_stats_hw_info_t *mrpcim_stats);
126221167Sgnn
127221167Sgnnvxge_hal_status_e
128221167Sgnn__hal_mrpcim_mac_configure(__hal_device_t *hldev);
129221167Sgnn
130221167Sgnnvxge_hal_status_e
131221167Sgnn__hal_mrpcim_lag_configure(__hal_device_t *hldev);
132221167Sgnn
133221167Sgnn__EXTERN_END_DECLS
134221167Sgnn
135221167Sgnn#endif	/* VXGE_HAL_MRPCIM_H */
136