1139825Simp/*- 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD$"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * VIA Rhine fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various network adapters based on the VIA Rhine 4041502Swpaul * and Rhine II PCI controllers, including the D-Link DFE530TX. 4141502Swpaul * Datasheets are available at http://www.via.com.tw. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 47131503Sbms 4841502Swpaul/* 4941502Swpaul * The VIA Rhine controllers are similar in some respects to the 5041502Swpaul * the DEC tulip chips, except less complicated. The controller 5141502Swpaul * uses an MII bus and an external physical layer interface. The 5241502Swpaul * receiver has a one entry perfect filter and a 64-bit hash table 5341502Swpaul * multicast filter. Transmit and receive descriptors are similar 5441502Swpaul * to the tulip. 5541502Swpaul * 56168953Sphk * Some Rhine chips has a serious flaw in its transmit DMA mechanism: 5741502Swpaul * transmit buffers must be longword aligned. Unfortunately, 5841502Swpaul * FreeBSD doesn't guarantee that mbufs will be filled in starting 5941502Swpaul * at longword boundaries, so we have to do a buffer copy before 6041502Swpaul * transmission. 6141502Swpaul */ 6241502Swpaul 63150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 64150968Sglebius#include "opt_device_polling.h" 65150968Sglebius#endif 66150968Sglebius 6741502Swpaul#include <sys/param.h> 6841502Swpaul#include <sys/systm.h> 69177050Syongari#include <sys/bus.h> 70177050Syongari#include <sys/endian.h> 71177050Syongari#include <sys/kernel.h> 72177050Syongari#include <sys/malloc.h> 7341502Swpaul#include <sys/mbuf.h> 74129878Sphk#include <sys/module.h> 75177050Syongari#include <sys/rman.h> 7641502Swpaul#include <sys/socket.h> 77177050Syongari#include <sys/sockio.h> 78177050Syongari#include <sys/sysctl.h> 79177050Syongari#include <sys/taskqueue.h> 8041502Swpaul 81177050Syongari#include <net/bpf.h> 8241502Swpaul#include <net/if.h> 8341502Swpaul#include <net/ethernet.h> 8441502Swpaul#include <net/if_dl.h> 8541502Swpaul#include <net/if_media.h> 86147256Sbrooks#include <net/if_types.h> 87177050Syongari#include <net/if_vlan_var.h> 8841502Swpaul 89177050Syongari#include <dev/mii/mii.h> 9051432Swpaul#include <dev/mii/miivar.h> 9151432Swpaul 92172555Syongari#include <dev/pci/pcireg.h> 93119288Simp#include <dev/pci/pcivar.h> 9441502Swpaul 95177050Syongari#include <machine/bus.h> 9641502Swpaul 97177047Syongari#include <dev/vr/if_vrreg.h> 9841502Swpaul 99177050Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 100177050Syongari#include "miibus_if.h" 101177050Syongari 102113506SmdoddMODULE_DEPEND(vr, pci, 1, 1, 1); 103113506SmdoddMODULE_DEPEND(vr, ether, 1, 1, 1); 10459758SpeterMODULE_DEPEND(vr, miibus, 1, 1, 1); 10559758Speter 106177050Syongari/* Define to show Rx/Tx error status. */ 107177050Syongari#undef VR_SHOW_ERRORS 108177050Syongari#define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 10951432Swpaul 11041502Swpaul/* 111177050Syongari * Various supported device vendors/types, their names & quirks. 11241502Swpaul */ 113168952Sphk#define VR_Q_NEEDALIGN (1<<0) 114168952Sphk#define VR_Q_CSUM (1<<1) 115177050Syongari#define VR_Q_CAM (1<<2) 116168952Sphk 117226171Smariusstatic const struct vr_type { 118168952Sphk u_int16_t vr_vid; 119168952Sphk u_int16_t vr_did; 120168952Sphk int vr_quirks; 121226171Smarius const char *vr_name; 122242625Sdim} vr_devs[] = { 123168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE, 124168827Sphk VR_Q_NEEDALIGN, 125168827Sphk "VIA VT3043 Rhine I 10/100BaseTX" }, 126168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 127168827Sphk VR_Q_NEEDALIGN, 128168827Sphk "VIA VT86C100A Rhine II 10/100BaseTX" }, 129168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 130168827Sphk 0, 131168827Sphk "VIA VT6102 Rhine II 10/100BaseTX" }, 132168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 133168827Sphk 0, 134168827Sphk "VIA VT6105 Rhine III 10/100BaseTX" }, 135168827Sphk { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 136185962Syongari VR_Q_CSUM, 137168827Sphk "VIA VT6105M Rhine III 10/100BaseTX" }, 138168827Sphk { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 139168827Sphk VR_Q_NEEDALIGN, 140168827Sphk "Delta Electronics Rhine II 10/100BaseTX" }, 141168827Sphk { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 142168827Sphk VR_Q_NEEDALIGN, 143168827Sphk "Addtron Technology Rhine II 10/100BaseTX" }, 144168813Sphk { 0, 0, 0, NULL } 14541502Swpaul}; 14641502Swpaul 147142407Simpstatic int vr_probe(device_t); 148142407Simpstatic int vr_attach(device_t); 149142407Simpstatic int vr_detach(device_t); 150177050Syongaristatic int vr_shutdown(device_t); 151177050Syongaristatic int vr_suspend(device_t); 152177050Syongaristatic int vr_resume(device_t); 15341502Swpaul 154177050Syongaristatic void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int); 155177050Syongaristatic int vr_dma_alloc(struct vr_softc *); 156177050Syongaristatic void vr_dma_free(struct vr_softc *); 157177050Syongaristatic __inline void vr_discard_rxbuf(struct vr_rxdesc *); 158177050Syongaristatic int vr_newbuf(struct vr_softc *, int); 15941502Swpaul 160177050Syongari#ifndef __NO_STRICT_ALIGNMENT 161177050Syongaristatic __inline void vr_fixup_rx(struct mbuf *); 162177050Syongari#endif 163193096Sattiliostatic int vr_rxeof(struct vr_softc *); 164142407Simpstatic void vr_txeof(struct vr_softc *); 165142407Simpstatic void vr_tick(void *); 166177050Syongaristatic int vr_error(struct vr_softc *, uint16_t); 167177050Syongaristatic void vr_tx_underrun(struct vr_softc *); 168235334Srpaulostatic int vr_intr(void *); 169235334Srpaulostatic void vr_int_task(void *, int); 170142407Simpstatic void vr_start(struct ifnet *); 171142407Simpstatic void vr_start_locked(struct ifnet *); 172177050Syongaristatic int vr_encap(struct vr_softc *, struct mbuf **); 173142407Simpstatic int vr_ioctl(struct ifnet *, u_long, caddr_t); 174142407Simpstatic void vr_init(void *); 175142407Simpstatic void vr_init_locked(struct vr_softc *); 176177050Syongaristatic void vr_tx_start(struct vr_softc *); 177177050Syongaristatic void vr_rx_start(struct vr_softc *); 178177050Syongaristatic int vr_tx_stop(struct vr_softc *); 179177050Syongaristatic int vr_rx_stop(struct vr_softc *); 180142407Simpstatic void vr_stop(struct vr_softc *); 181177050Syongaristatic void vr_watchdog(struct vr_softc *); 182142407Simpstatic int vr_ifmedia_upd(struct ifnet *); 183142407Simpstatic void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 18441502Swpaul 185177050Syongaristatic int vr_miibus_readreg(device_t, int, int); 186177050Syongaristatic int vr_miibus_writereg(device_t, int, int, int); 187142407Simpstatic void vr_miibus_statchg(device_t); 18841502Swpaul 189180552Syongaristatic void vr_cam_mask(struct vr_softc *, uint32_t, int); 190180552Syongaristatic int vr_cam_data(struct vr_softc *, int, int, uint8_t *); 191177050Syongaristatic void vr_set_filter(struct vr_softc *); 192168946Sphkstatic void vr_reset(const struct vr_softc *); 193177050Syongaristatic int vr_tx_ring_init(struct vr_softc *); 194177050Syongaristatic int vr_rx_ring_init(struct vr_softc *); 195177050Syongaristatic void vr_setwol(struct vr_softc *); 196177050Syongaristatic void vr_clrwol(struct vr_softc *); 197177050Syongaristatic int vr_sysctl_stats(SYSCTL_HANDLER_ARGS); 19841502Swpaul 199226171Smariusstatic const struct vr_tx_threshold_table { 200177050Syongari int tx_cfg; 201177050Syongari int bcr_cfg; 202177050Syongari int value; 203242625Sdim} vr_tx_threshold_tables[] = { 204177050Syongari { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 }, 205177050Syongari { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 }, 206177050Syongari { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 }, 207177050Syongari { VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 }, 208177050Syongari { VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 }, 209177050Syongari { VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 } 210177050Syongari}; 21149610Swpaul 21249610Swpaulstatic device_method_t vr_methods[] = { 21349610Swpaul /* Device interface */ 21449610Swpaul DEVMETHOD(device_probe, vr_probe), 21549610Swpaul DEVMETHOD(device_attach, vr_attach), 21649610Swpaul DEVMETHOD(device_detach, vr_detach), 21749610Swpaul DEVMETHOD(device_shutdown, vr_shutdown), 218177050Syongari DEVMETHOD(device_suspend, vr_suspend), 219177050Syongari DEVMETHOD(device_resume, vr_resume), 22051432Swpaul 22151432Swpaul /* MII interface */ 22251432Swpaul DEVMETHOD(miibus_readreg, vr_miibus_readreg), 22351432Swpaul DEVMETHOD(miibus_writereg, vr_miibus_writereg), 22451432Swpaul DEVMETHOD(miibus_statchg, vr_miibus_statchg), 22551432Swpaul 226227843Smarius DEVMETHOD_END 22749610Swpaul}; 22849610Swpaul 22949610Swpaulstatic driver_t vr_driver = { 23051455Swpaul "vr", 23149610Swpaul vr_methods, 23249610Swpaul sizeof(struct vr_softc) 23349610Swpaul}; 23449610Swpaul 23549610Swpaulstatic devclass_t vr_devclass; 23649610Swpaul 237113506SmdoddDRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 23851473SwpaulDRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 23949610Swpaul 240102336Salfredstatic int 241177050Syongarivr_miibus_readreg(device_t dev, int phy, int reg) 24241502Swpaul{ 243177050Syongari struct vr_softc *sc; 244177050Syongari int i; 24541502Swpaul 246177050Syongari sc = device_get_softc(dev); 247110168Ssilby 248131503Sbms /* Set the register address. */ 249177050Syongari CSR_WRITE_1(sc, VR_MIIADDR, reg); 250110168Ssilby VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 251131503Sbms 252177050Syongari for (i = 0; i < VR_MII_TIMEOUT; i++) { 253177050Syongari DELAY(1); 254110168Ssilby if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 255110168Ssilby break; 256110168Ssilby } 257177050Syongari if (i == VR_MII_TIMEOUT) 258177050Syongari device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg); 259110168Ssilby 260177050Syongari return (CSR_READ_2(sc, VR_MIIDATA)); 261110168Ssilby} 262110168Ssilby 263102336Salfredstatic int 264177050Syongarivr_miibus_writereg(device_t dev, int phy, int reg, int data) 26541502Swpaul{ 266177050Syongari struct vr_softc *sc; 267177050Syongari int i; 26841502Swpaul 269177050Syongari sc = device_get_softc(dev); 270110168Ssilby 271131503Sbms /* Set the register address and data to write. */ 272177050Syongari CSR_WRITE_1(sc, VR_MIIADDR, reg); 273177050Syongari CSR_WRITE_2(sc, VR_MIIDATA, data); 274110168Ssilby VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 275110168Ssilby 276177050Syongari for (i = 0; i < VR_MII_TIMEOUT; i++) { 277177050Syongari DELAY(1); 278110168Ssilby if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 279110168Ssilby break; 280110168Ssilby } 281177050Syongari if (i == VR_MII_TIMEOUT) 282177050Syongari device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy, 283177050Syongari reg); 284110168Ssilby 285131503Sbms return (0); 286110168Ssilby} 287110168Ssilby 288177050Syongari/* 289177050Syongari * In order to fiddle with the 290177050Syongari * 'full-duplex' and '100Mbps' bits in the netconfig register, we 291177050Syongari * first have to put the transmit and/or receive logic in the idle state. 292177050Syongari */ 293177050Syongaristatic void 294223405Syongarivr_miibus_statchg(device_t dev) 29551432Swpaul{ 296177050Syongari struct vr_softc *sc; 297177050Syongari struct mii_data *mii; 298177050Syongari struct ifnet *ifp; 299177050Syongari int lfdx, mfdx; 300177050Syongari uint8_t cr0, cr1, fc; 30141502Swpaul 302223405Syongari sc = device_get_softc(dev); 303177050Syongari mii = device_get_softc(sc->vr_miibus); 304177050Syongari ifp = sc->vr_ifp; 305177050Syongari if (mii == NULL || ifp == NULL || 306223405Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 307177050Syongari return; 30841502Swpaul 309228086Syongari sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE); 310223405Syongari if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 311223405Syongari (IFM_ACTIVE | IFM_AVALID)) { 312223405Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 313223405Syongari case IFM_10_T: 314223405Syongari case IFM_100_TX: 315228084Syongari sc->vr_flags |= VR_F_LINK; 316223405Syongari break; 317223405Syongari default: 318223405Syongari break; 319223405Syongari } 320223405Syongari } 321177050Syongari 322228084Syongari if ((sc->vr_flags & VR_F_LINK) != 0) { 323177050Syongari cr0 = CSR_READ_1(sc, VR_CR0); 324177050Syongari cr1 = CSR_READ_1(sc, VR_CR1); 325177050Syongari mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0; 326177050Syongari lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0; 327177050Syongari if (mfdx != lfdx) { 328177050Syongari if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) { 329177050Syongari if (vr_tx_stop(sc) != 0 || 330177050Syongari vr_rx_stop(sc) != 0) { 331177050Syongari device_printf(sc->vr_dev, 332177050Syongari "%s: Tx/Rx shutdown error -- " 333177050Syongari "resetting\n", __func__); 334177050Syongari sc->vr_flags |= VR_F_RESTART; 335177050Syongari VR_UNLOCK(sc); 336177050Syongari return; 337177050Syongari } 338177050Syongari } 339177050Syongari if (lfdx) 340177050Syongari cr1 |= VR_CR1_FULLDUPLEX; 341177050Syongari else 342177050Syongari cr1 &= ~VR_CR1_FULLDUPLEX; 343177050Syongari CSR_WRITE_1(sc, VR_CR1, cr1); 344177050Syongari } 345177050Syongari fc = 0; 346177050Syongari /* Configure flow-control. */ 347177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) { 348177050Syongari fc = CSR_READ_1(sc, VR_FLOWCR1); 349177050Syongari fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE); 350177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 351177050Syongari IFM_ETH_RXPAUSE) != 0) 352177050Syongari fc |= VR_FLOWCR1_RXPAUSE; 353177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 354228086Syongari IFM_ETH_TXPAUSE) != 0) { 355177050Syongari fc |= VR_FLOWCR1_TXPAUSE; 356228086Syongari sc->vr_flags |= VR_F_TXPAUSE; 357228086Syongari } 358177050Syongari CSR_WRITE_1(sc, VR_FLOWCR1, fc); 359177050Syongari } else if (sc->vr_revid >= REV_ID_VT6102_A) { 360177050Syongari /* No Tx puase capability available for Rhine II. */ 361177050Syongari fc = CSR_READ_1(sc, VR_MISC_CR0); 362177050Syongari fc &= ~VR_MISCCR0_RXPAUSE; 363177050Syongari if ((IFM_OPTIONS(mii->mii_media_active) & 364177050Syongari IFM_ETH_RXPAUSE) != 0) 365177050Syongari fc |= VR_MISCCR0_RXPAUSE; 366177050Syongari CSR_WRITE_1(sc, VR_MISC_CR0, fc); 367177050Syongari } 368177050Syongari vr_rx_start(sc); 369177050Syongari vr_tx_start(sc); 370177050Syongari } else { 371177050Syongari if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) { 372177050Syongari device_printf(sc->vr_dev, 373177050Syongari "%s: Tx/Rx shutdown error -- resetting\n", 374177050Syongari __func__); 375177050Syongari sc->vr_flags |= VR_F_RESTART; 376177050Syongari } 377177050Syongari } 37851432Swpaul} 37951432Swpaul 380180552Syongari 381180552Syongaristatic void 382180552Syongarivr_cam_mask(struct vr_softc *sc, uint32_t mask, int type) 383180552Syongari{ 384180552Syongari 385180552Syongari if (type == VR_MCAST_CAM) 386180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 387180552Syongari else 388180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 389180552Syongari CSR_WRITE_4(sc, VR_CAMMASK, mask); 390180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, 0); 391180552Syongari} 392180552Syongari 393177050Syongaristatic int 394180552Syongarivr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac) 39551432Swpaul{ 396177050Syongari int i; 39751432Swpaul 398180552Syongari if (type == VR_MCAST_CAM) { 399180552Syongari if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL) 400180552Syongari return (EINVAL); 401180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 402180552Syongari } else 403180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 404177050Syongari 405177050Syongari /* Set CAM entry address. */ 406177050Syongari CSR_WRITE_1(sc, VR_CAMADDR, idx); 407177050Syongari /* Set CAM entry data. */ 408180552Syongari if (type == VR_MCAST_CAM) { 409180552Syongari for (i = 0; i < ETHER_ADDR_LEN; i++) 410180552Syongari CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]); 411180552Syongari } else { 412180552Syongari CSR_WRITE_1(sc, VR_VCAM0, mac[0]); 413180552Syongari CSR_WRITE_1(sc, VR_VCAM1, mac[1]); 414180552Syongari } 415180552Syongari DELAY(10); 416177050Syongari /* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */ 417180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE); 418177050Syongari for (i = 0; i < VR_TIMEOUT; i++) { 419177050Syongari DELAY(1); 420177050Syongari if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0) 421177050Syongari break; 422177050Syongari } 423177050Syongari 424177050Syongari if (i == VR_TIMEOUT) 425177050Syongari device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n", 426177050Syongari __func__); 427180552Syongari CSR_WRITE_1(sc, VR_CAMCTL, 0); 428177050Syongari 429177050Syongari return (i == VR_TIMEOUT ? ETIMEDOUT : 0); 43041502Swpaul} 43141502Swpaul 43241502Swpaul/* 43341502Swpaul * Program the 64-bit multicast hash filter. 43441502Swpaul */ 435102336Salfredstatic void 436177050Syongarivr_set_filter(struct vr_softc *sc) 43741502Swpaul{ 438177050Syongari struct ifnet *ifp; 439177050Syongari int h; 440131503Sbms uint32_t hashes[2] = { 0, 0 }; 44141502Swpaul struct ifmultiaddr *ifma; 442131503Sbms uint8_t rxfilt; 443177050Syongari int error, mcnt; 444177050Syongari uint32_t cam_mask; 44541502Swpaul 446131518Sbms VR_LOCK_ASSERT(sc); 44741502Swpaul 448177050Syongari ifp = sc->vr_ifp; 44941502Swpaul rxfilt = CSR_READ_1(sc, VR_RXCFG); 450185014Syongari rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD | 451185014Syongari VR_RXCFG_RX_MULTI); 452177050Syongari if (ifp->if_flags & IFF_BROADCAST) 453177050Syongari rxfilt |= VR_RXCFG_RX_BROAD; 45441502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 45541502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 456177050Syongari if (ifp->if_flags & IFF_PROMISC) 457177050Syongari rxfilt |= VR_RXCFG_RX_PROMISC; 45841502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 45941502Swpaul CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 46041502Swpaul CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 46141502Swpaul return; 46241502Swpaul } 46341502Swpaul 464131503Sbms /* Now program new ones. */ 465177050Syongari error = 0; 466180552Syongari mcnt = 0; 467195049Srwatson if_maddr_rlock(ifp); 468177050Syongari if ((sc->vr_quirks & VR_Q_CAM) != 0) { 469177050Syongari /* 470177050Syongari * For hardwares that have CAM capability, use 471177050Syongari * 32 entries multicast perfect filter. 472177050Syongari */ 473177050Syongari cam_mask = 0; 474177050Syongari TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 475177050Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 476177050Syongari continue; 477180552Syongari error = vr_cam_data(sc, VR_MCAST_CAM, mcnt, 478177050Syongari LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 479177050Syongari if (error != 0) { 480177050Syongari cam_mask = 0; 481177050Syongari break; 482177050Syongari } 483177050Syongari cam_mask |= 1 << mcnt; 484177050Syongari mcnt++; 485177050Syongari } 486180552Syongari vr_cam_mask(sc, VR_MCAST_CAM, cam_mask); 48741502Swpaul } 488177050Syongari 489177050Syongari if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) { 490177050Syongari /* 491177050Syongari * If there are too many multicast addresses or 492177050Syongari * setting multicast CAM filter failed, use hash 493177050Syongari * table based filtering. 494177050Syongari */ 495180552Syongari mcnt = 0; 496177050Syongari TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 497177050Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 498177050Syongari continue; 499177050Syongari h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 500177050Syongari ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 501177050Syongari if (h < 32) 502177050Syongari hashes[0] |= (1 << h); 503177050Syongari else 504177050Syongari hashes[1] |= (1 << (h - 32)); 505177050Syongari mcnt++; 506177050Syongari } 507177050Syongari } 508195049Srwatson if_maddr_runlock(ifp); 50941502Swpaul 510177050Syongari if (mcnt > 0) 51141502Swpaul rxfilt |= VR_RXCFG_RX_MULTI; 51241502Swpaul 51341502Swpaul CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 51441502Swpaul CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 51541502Swpaul CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 51641502Swpaul} 51741502Swpaul 518102336Salfredstatic void 519168946Sphkvr_reset(const struct vr_softc *sc) 52041502Swpaul{ 521177050Syongari int i; 52241502Swpaul 523151773Sjhb /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 524131518Sbms 525177050Syongari CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET); 526177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) { 527177050Syongari /* VT86C100A needs more delay after reset. */ 528177050Syongari DELAY(100); 529177050Syongari } 53041502Swpaul for (i = 0; i < VR_TIMEOUT; i++) { 53141502Swpaul DELAY(10); 532177050Syongari if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET)) 53341502Swpaul break; 53441502Swpaul } 535107220Ssilby if (i == VR_TIMEOUT) { 536177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) 537162315Sglebius device_printf(sc->vr_dev, "reset never completed!\n"); 538107220Ssilby else { 539177050Syongari /* Use newer force reset command. */ 540177050Syongari device_printf(sc->vr_dev, 541177050Syongari "Using force reset command.\n"); 542107220Ssilby VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 543177050Syongari /* 544177050Syongari * Wait a little while for the chip to get its brains 545177050Syongari * in order. 546177050Syongari */ 547177050Syongari DELAY(2000); 548107220Ssilby } 549107220Ssilby } 55041502Swpaul 55141502Swpaul} 55241502Swpaul 55341502Swpaul/* 55441502Swpaul * Probe for a VIA Rhine chip. Check the PCI vendor and device 555168813Sphk * IDs against our list and return a match or NULL 556168813Sphk */ 557226171Smariusstatic const struct vr_type * 558168813Sphkvr_match(device_t dev) 559168813Sphk{ 560226171Smarius const struct vr_type *t = vr_devs; 561168813Sphk 562168813Sphk for (t = vr_devs; t->vr_name != NULL; t++) 563168813Sphk if ((pci_get_vendor(dev) == t->vr_vid) && 564168813Sphk (pci_get_device(dev) == t->vr_did)) 565168813Sphk return (t); 566168813Sphk return (NULL); 567168813Sphk} 568168813Sphk 569168813Sphk/* 570168813Sphk * Probe for a VIA Rhine chip. Check the PCI vendor and device 57141502Swpaul * IDs against our list and return a device name if we find a match. 57241502Swpaul */ 573102336Salfredstatic int 574131503Sbmsvr_probe(device_t dev) 57541502Swpaul{ 576226171Smarius const struct vr_type *t; 57741502Swpaul 578168813Sphk t = vr_match(dev); 579168813Sphk if (t != NULL) { 580168813Sphk device_set_desc(dev, t->vr_name); 581168813Sphk return (BUS_PROBE_DEFAULT); 58241502Swpaul } 583131503Sbms return (ENXIO); 58441502Swpaul} 58541502Swpaul 58641502Swpaul/* 58741502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 58841502Swpaul * setup and ethernet/BPF attach. 58941502Swpaul */ 590102336Salfredstatic int 591168946Sphkvr_attach(device_t dev) 59241502Swpaul{ 59341502Swpaul struct vr_softc *sc; 59441502Swpaul struct ifnet *ifp; 595226171Smarius const struct vr_type *t; 596177050Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 597177050Syongari int error, rid; 598213893Smarius int i, phy, pmc; 59941502Swpaul 60049610Swpaul sc = device_get_softc(dev); 601162315Sglebius sc->vr_dev = dev; 602168813Sphk t = vr_match(dev); 603168813Sphk KASSERT(t != NULL, ("Lost if_vr device match")); 604168813Sphk sc->vr_quirks = t->vr_quirks; 605168813Sphk device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks); 60641502Swpaul 60793818Sjhb mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 608131518Sbms MTX_DEF); 609151911Sjhb callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0); 610177050Syongari SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 611177050Syongari SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 612177050Syongari OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 613177050Syongari vr_sysctl_stats, "I", "Statistics"); 614151911Sjhb 615177050Syongari error = 0; 616177050Syongari 61741502Swpaul /* 61841502Swpaul * Map control/status registers. 61941502Swpaul */ 62072813Swpaul pci_enable_busmaster(dev); 621177050Syongari sc->vr_revid = pci_get_revid(dev); 622177050Syongari device_printf(dev, "Revision: 0x%x\n", sc->vr_revid); 62341502Swpaul 624177050Syongari sc->vr_res_id = PCIR_BAR(0); 625177050Syongari sc->vr_res_type = SYS_RES_IOPORT; 626177050Syongari sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type, 627177050Syongari &sc->vr_res_id, RF_ACTIVE); 62849610Swpaul if (sc->vr_res == NULL) { 629177050Syongari device_printf(dev, "couldn't map ports\n"); 63049610Swpaul error = ENXIO; 63141502Swpaul goto fail; 63241502Swpaul } 63341502Swpaul 634177050Syongari /* Allocate interrupt. */ 63549610Swpaul rid = 0; 636127135Snjl sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 63749610Swpaul RF_SHAREABLE | RF_ACTIVE); 63849610Swpaul 63949610Swpaul if (sc->vr_irq == NULL) { 640151773Sjhb device_printf(dev, "couldn't map interrupt\n"); 64149610Swpaul error = ENXIO; 64241502Swpaul goto fail; 64341502Swpaul } 64441502Swpaul 645151773Sjhb /* Allocate ifnet structure. */ 646151773Sjhb ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 647151773Sjhb if (ifp == NULL) { 648177050Syongari device_printf(dev, "couldn't allocate ifnet structure\n"); 649151773Sjhb error = ENOSPC; 650151773Sjhb goto fail; 651151773Sjhb } 652151773Sjhb ifp->if_softc = sc; 653151773Sjhb if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 654151773Sjhb ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 655151773Sjhb ifp->if_ioctl = vr_ioctl; 656151773Sjhb ifp->if_start = vr_start; 657151773Sjhb ifp->if_init = vr_init; 658177050Syongari IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1); 659177050Syongari ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1; 660151773Sjhb IFQ_SET_READY(&ifp->if_snd); 661168827Sphk 662235334Srpaulo TASK_INIT(&sc->vr_inttask, 0, vr_int_task, sc); 663235334Srpaulo 664177050Syongari /* Configure Tx FIFO threshold. */ 665177050Syongari sc->vr_txthresh = VR_TXTHRESH_MIN; 666177050Syongari if (sc->vr_revid < REV_ID_VT6105_A0) { 667177050Syongari /* 668177050Syongari * Use store and forward mode for Rhine I/II. 669177050Syongari * Otherwise they produce a lot of Tx underruns and 670177050Syongari * it would take a while to get working FIFO threshold 671177050Syongari * value. 672177050Syongari */ 673177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 674177050Syongari } 675177050Syongari if ((sc->vr_quirks & VR_Q_CSUM) != 0) { 676177050Syongari ifp->if_hwassist = VR_CSUM_FEATURES; 677168827Sphk ifp->if_capabilities |= IFCAP_HWCSUM; 678177050Syongari /* 679177050Syongari * To update checksum field the hardware may need to 680177050Syongari * store entire frames into FIFO before transmitting. 681177050Syongari */ 682177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 683168827Sphk } 684168827Sphk 685177050Syongari if (sc->vr_revid >= REV_ID_VT6102_A && 686219902Sjhb pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 687177050Syongari ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC; 688177050Syongari 689177050Syongari /* Rhine supports oversized VLAN frame. */ 690168973Sphk ifp->if_capabilities |= IFCAP_VLAN_MTU; 691151773Sjhb ifp->if_capenable = ifp->if_capabilities; 692151773Sjhb#ifdef DEVICE_POLLING 693151773Sjhb ifp->if_capabilities |= IFCAP_POLLING; 694151773Sjhb#endif 695151773Sjhb 69676586Swpaul /* 69776586Swpaul * Windows may put the chip in suspend mode when it 69876586Swpaul * shuts down. Be sure to kick it in the head to wake it 69976586Swpaul * up again. 70076586Swpaul */ 701219902Sjhb if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 702172555Syongari VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 70376586Swpaul 704131503Sbms /* 70541502Swpaul * Get station address. The way the Rhine chips work, 70641502Swpaul * you're not allowed to directly access the EEPROM once 70741502Swpaul * they've been programmed a special way. Consequently, 70841502Swpaul * we need to read the node address from the PAR0 and PAR1 70941502Swpaul * registers. 710177050Syongari * Reloading EEPROM also overwrites VR_CFGA, VR_CFGB, 711177050Syongari * VR_CFGC and VR_CFGD such that memory mapped IO configured 712177050Syongari * by driver is reset to default state. 71341502Swpaul */ 71441502Swpaul VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 715177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 716177050Syongari DELAY(1); 717177050Syongari if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0) 718177050Syongari break; 719177050Syongari } 720177050Syongari if (i == 0) 721177050Syongari device_printf(dev, "Reloading EEPROM timeout!\n"); 72241502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 72341502Swpaul eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 72441502Swpaul 725177050Syongari /* Reset the adapter. */ 726177050Syongari vr_reset(sc); 727177050Syongari /* Ack intr & disable further interrupts. */ 728177050Syongari CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 729177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 730177050Syongari if (sc->vr_revid >= REV_ID_VT6102_A) 731177050Syongari CSR_WRITE_2(sc, VR_MII_IMR, 0); 73251432Swpaul 733177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) { 734177050Syongari pci_write_config(dev, VR_PCI_MODE2, 735177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 736177050Syongari VR_MODE2_MODE10T, 1); 737177050Syongari } else { 738177050Syongari /* Report error instead of retrying forever. */ 739177050Syongari pci_write_config(dev, VR_PCI_MODE2, 740177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 741177050Syongari VR_MODE2_PCEROPT, 1); 742177050Syongari /* Detect MII coding error. */ 743177050Syongari pci_write_config(dev, VR_PCI_MODE3, 744177050Syongari pci_read_config(dev, VR_PCI_MODE3, 1) | 745177050Syongari VR_MODE3_MIION, 1); 746177050Syongari if (sc->vr_revid >= REV_ID_VT6105_LOM && 747177050Syongari sc->vr_revid < REV_ID_VT6105M_A0) 748177050Syongari pci_write_config(dev, VR_PCI_MODE2, 749177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 750177050Syongari VR_MODE2_MODE10T, 1); 751177050Syongari /* Enable Memory-Read-Multiple. */ 752177050Syongari if (sc->vr_revid >= REV_ID_VT6107_A1 && 753177050Syongari sc->vr_revid < REV_ID_VT6105M_A0) 754177050Syongari pci_write_config(dev, VR_PCI_MODE2, 755177050Syongari pci_read_config(dev, VR_PCI_MODE2, 1) | 756177050Syongari VR_MODE2_MRDPL, 1); 757177050Syongari } 758177050Syongari /* Disable MII AUTOPOLL. */ 759177050Syongari VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 760177050Syongari 761177050Syongari if (vr_dma_alloc(sc) != 0) { 76249610Swpaul error = ENXIO; 76349610Swpaul goto fail; 76441502Swpaul } 76541502Swpaul 766213893Smarius /* Do MII setup. */ 767177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) 768213893Smarius phy = 1; 769177050Syongari else 770213893Smarius phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK; 771213893Smarius error = mii_attach(dev, &sc->vr_miibus, ifp, vr_ifmedia_upd, 772228086Syongari vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 773228086Syongari sc->vr_revid >= REV_ID_VT6102_A ? MIIF_DOPAUSE : 0); 774213893Smarius if (error != 0) { 775213893Smarius device_printf(dev, "attaching PHYs failed\n"); 77641502Swpaul goto fail; 77741502Swpaul } 77841502Swpaul 779131503Sbms /* Call MI attach routine. */ 780106936Ssam ether_ifattach(ifp, eaddr); 781177050Syongari /* 782177050Syongari * Tell the upper layer(s) we support long frames. 783177050Syongari * Must appear after the call to ether_ifattach() because 784177050Syongari * ether_ifattach() sets ifi_hdrlen to the default value. 785177050Syongari */ 786177050Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 78741502Swpaul 788177050Syongari /* Hook interrupt last to avoid having to lock softc. */ 789131518Sbms error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 790235334Srpaulo vr_intr, NULL, sc, &sc->vr_intrhand); 791112872Snjl 792112872Snjl if (error) { 793151773Sjhb device_printf(dev, "couldn't set up irq\n"); 794113609Snjl ether_ifdetach(ifp); 795112872Snjl goto fail; 796112872Snjl } 797112872Snjl 79841502Swpaulfail: 799112872Snjl if (error) 800112872Snjl vr_detach(dev); 80167087Swpaul 802131503Sbms return (error); 80341502Swpaul} 80441502Swpaul 805113609Snjl/* 806113609Snjl * Shutdown hardware and free up resources. This can be called any 807113609Snjl * time after the mutex has been initialized. It is called in both 808113609Snjl * the error case in attach and the normal detach case so it needs 809113609Snjl * to be careful about only freeing resources that have actually been 810113609Snjl * allocated. 811113609Snjl */ 812102336Salfredstatic int 813131503Sbmsvr_detach(device_t dev) 81449610Swpaul{ 815131503Sbms struct vr_softc *sc = device_get_softc(dev); 816147256Sbrooks struct ifnet *ifp = sc->vr_ifp; 81749610Swpaul 818112880Sjhb KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 819131518Sbms 820150789Sglebius#ifdef DEVICE_POLLING 821177050Syongari if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 822150789Sglebius ether_poll_deregister(ifp); 823150789Sglebius#endif 824150789Sglebius 825177050Syongari /* These should only be active if attach succeeded. */ 826113812Simp if (device_is_attached(dev)) { 827151911Sjhb VR_LOCK(sc); 828228084Syongari sc->vr_flags |= VR_F_DETACHED; 829113609Snjl vr_stop(sc); 830151911Sjhb VR_UNLOCK(sc); 831151911Sjhb callout_drain(&sc->vr_stat_callout); 832235334Srpaulo taskqueue_drain(taskqueue_fast, &sc->vr_inttask); 833112872Snjl ether_ifdetach(ifp); 834113609Snjl } 835113609Snjl if (sc->vr_miibus) 836112872Snjl device_delete_child(dev, sc->vr_miibus); 837113609Snjl bus_generic_detach(dev); 83849610Swpaul 839112872Snjl if (sc->vr_intrhand) 840112872Snjl bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 841112872Snjl if (sc->vr_irq) 842112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 843112872Snjl if (sc->vr_res) 844177050Syongari bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id, 845177050Syongari sc->vr_res); 84651432Swpaul 847151297Sru if (ifp) 848151297Sru if_free(ifp); 849151297Sru 850177050Syongari vr_dma_free(sc); 85149610Swpaul 85267087Swpaul mtx_destroy(&sc->vr_mtx); 85349610Swpaul 854131503Sbms return (0); 85549610Swpaul} 85649610Swpaul 857177050Syongaristruct vr_dmamap_arg { 858177050Syongari bus_addr_t vr_busaddr; 859177050Syongari}; 860177050Syongari 861177050Syongaristatic void 862177050Syongarivr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 863177050Syongari{ 864177050Syongari struct vr_dmamap_arg *ctx; 865177050Syongari 866177050Syongari if (error != 0) 867177050Syongari return; 868177050Syongari ctx = arg; 869177050Syongari ctx->vr_busaddr = segs[0].ds_addr; 870177050Syongari} 871177050Syongari 872177050Syongaristatic int 873177050Syongarivr_dma_alloc(struct vr_softc *sc) 874177050Syongari{ 875177050Syongari struct vr_dmamap_arg ctx; 876177050Syongari struct vr_txdesc *txd; 877177050Syongari struct vr_rxdesc *rxd; 878177050Syongari bus_size_t tx_alignment; 879177050Syongari int error, i; 880177050Syongari 881177050Syongari /* Create parent DMA tag. */ 882177050Syongari error = bus_dma_tag_create( 883177050Syongari bus_get_dma_tag(sc->vr_dev), /* parent */ 884177050Syongari 1, 0, /* alignment, boundary */ 885177050Syongari BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 886177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 887177050Syongari NULL, NULL, /* filter, filterarg */ 888177050Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 889177050Syongari 0, /* nsegments */ 890177050Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 891177050Syongari 0, /* flags */ 892177050Syongari NULL, NULL, /* lockfunc, lockarg */ 893177050Syongari &sc->vr_cdata.vr_parent_tag); 894177050Syongari if (error != 0) { 895177050Syongari device_printf(sc->vr_dev, "failed to create parent DMA tag\n"); 896177050Syongari goto fail; 897177050Syongari } 898177050Syongari /* Create tag for Tx ring. */ 899177050Syongari error = bus_dma_tag_create( 900177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 901177050Syongari VR_RING_ALIGN, 0, /* alignment, boundary */ 902177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 903177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 904177050Syongari NULL, NULL, /* filter, filterarg */ 905177050Syongari VR_TX_RING_SIZE, /* maxsize */ 906177050Syongari 1, /* nsegments */ 907177050Syongari VR_TX_RING_SIZE, /* maxsegsize */ 908177050Syongari 0, /* flags */ 909177050Syongari NULL, NULL, /* lockfunc, lockarg */ 910177050Syongari &sc->vr_cdata.vr_tx_ring_tag); 911177050Syongari if (error != 0) { 912177050Syongari device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n"); 913177050Syongari goto fail; 914177050Syongari } 915177050Syongari 916177050Syongari /* Create tag for Rx ring. */ 917177050Syongari error = bus_dma_tag_create( 918177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 919177050Syongari VR_RING_ALIGN, 0, /* alignment, boundary */ 920177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 921177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 922177050Syongari NULL, NULL, /* filter, filterarg */ 923177050Syongari VR_RX_RING_SIZE, /* maxsize */ 924177050Syongari 1, /* nsegments */ 925177050Syongari VR_RX_RING_SIZE, /* maxsegsize */ 926177050Syongari 0, /* flags */ 927177050Syongari NULL, NULL, /* lockfunc, lockarg */ 928177050Syongari &sc->vr_cdata.vr_rx_ring_tag); 929177050Syongari if (error != 0) { 930177050Syongari device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n"); 931177050Syongari goto fail; 932177050Syongari } 933177050Syongari 934177050Syongari if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) 935177050Syongari tx_alignment = sizeof(uint32_t); 936177050Syongari else 937177050Syongari tx_alignment = 1; 938177050Syongari /* Create tag for Tx buffers. */ 939177050Syongari error = bus_dma_tag_create( 940177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 941177050Syongari tx_alignment, 0, /* alignment, boundary */ 942177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 943177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 944177050Syongari NULL, NULL, /* filter, filterarg */ 945177050Syongari MCLBYTES * VR_MAXFRAGS, /* maxsize */ 946177050Syongari VR_MAXFRAGS, /* nsegments */ 947177050Syongari MCLBYTES, /* maxsegsize */ 948177050Syongari 0, /* flags */ 949177050Syongari NULL, NULL, /* lockfunc, lockarg */ 950177050Syongari &sc->vr_cdata.vr_tx_tag); 951177050Syongari if (error != 0) { 952177050Syongari device_printf(sc->vr_dev, "failed to create Tx DMA tag\n"); 953177050Syongari goto fail; 954177050Syongari } 955177050Syongari 956177050Syongari /* Create tag for Rx buffers. */ 957177050Syongari error = bus_dma_tag_create( 958177050Syongari sc->vr_cdata.vr_parent_tag, /* parent */ 959177050Syongari VR_RX_ALIGN, 0, /* alignment, boundary */ 960177050Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 961177050Syongari BUS_SPACE_MAXADDR, /* highaddr */ 962177050Syongari NULL, NULL, /* filter, filterarg */ 963177050Syongari MCLBYTES, /* maxsize */ 964177050Syongari 1, /* nsegments */ 965177050Syongari MCLBYTES, /* maxsegsize */ 966177050Syongari 0, /* flags */ 967177050Syongari NULL, NULL, /* lockfunc, lockarg */ 968177050Syongari &sc->vr_cdata.vr_rx_tag); 969177050Syongari if (error != 0) { 970177050Syongari device_printf(sc->vr_dev, "failed to create Rx DMA tag\n"); 971177050Syongari goto fail; 972177050Syongari } 973177050Syongari 974177050Syongari /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 975177050Syongari error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag, 976177050Syongari (void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK | 977177050Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map); 978177050Syongari if (error != 0) { 979177050Syongari device_printf(sc->vr_dev, 980177050Syongari "failed to allocate DMA'able memory for Tx ring\n"); 981177050Syongari goto fail; 982177050Syongari } 983177050Syongari 984177050Syongari ctx.vr_busaddr = 0; 985177050Syongari error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag, 986177050Syongari sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring, 987177050Syongari VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 988177050Syongari if (error != 0 || ctx.vr_busaddr == 0) { 989177050Syongari device_printf(sc->vr_dev, 990177050Syongari "failed to load DMA'able memory for Tx ring\n"); 991177050Syongari goto fail; 992177050Syongari } 993177050Syongari sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr; 994177050Syongari 995177050Syongari /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 996177050Syongari error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag, 997177050Syongari (void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK | 998177050Syongari BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map); 999177050Syongari if (error != 0) { 1000177050Syongari device_printf(sc->vr_dev, 1001177050Syongari "failed to allocate DMA'able memory for Rx ring\n"); 1002177050Syongari goto fail; 1003177050Syongari } 1004177050Syongari 1005177050Syongari ctx.vr_busaddr = 0; 1006177050Syongari error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag, 1007177050Syongari sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring, 1008177050Syongari VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 1009177050Syongari if (error != 0 || ctx.vr_busaddr == 0) { 1010177050Syongari device_printf(sc->vr_dev, 1011177050Syongari "failed to load DMA'able memory for Rx ring\n"); 1012177050Syongari goto fail; 1013177050Syongari } 1014177050Syongari sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr; 1015177050Syongari 1016177050Syongari /* Create DMA maps for Tx buffers. */ 1017177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1018177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1019177050Syongari txd->tx_m = NULL; 1020177050Syongari txd->tx_dmamap = NULL; 1021177050Syongari error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0, 1022177050Syongari &txd->tx_dmamap); 1023177050Syongari if (error != 0) { 1024177050Syongari device_printf(sc->vr_dev, 1025177050Syongari "failed to create Tx dmamap\n"); 1026177050Syongari goto fail; 1027177050Syongari } 1028177050Syongari } 1029177050Syongari /* Create DMA maps for Rx buffers. */ 1030177050Syongari if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1031177050Syongari &sc->vr_cdata.vr_rx_sparemap)) != 0) { 1032177050Syongari device_printf(sc->vr_dev, 1033177050Syongari "failed to create spare Rx dmamap\n"); 1034177050Syongari goto fail; 1035177050Syongari } 1036177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1037177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1038177050Syongari rxd->rx_m = NULL; 1039177050Syongari rxd->rx_dmamap = NULL; 1040177050Syongari error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1041177050Syongari &rxd->rx_dmamap); 1042177050Syongari if (error != 0) { 1043177050Syongari device_printf(sc->vr_dev, 1044177050Syongari "failed to create Rx dmamap\n"); 1045177050Syongari goto fail; 1046177050Syongari } 1047177050Syongari } 1048177050Syongari 1049177050Syongarifail: 1050177050Syongari return (error); 1051177050Syongari} 1052177050Syongari 1053177050Syongaristatic void 1054177050Syongarivr_dma_free(struct vr_softc *sc) 1055177050Syongari{ 1056177050Syongari struct vr_txdesc *txd; 1057177050Syongari struct vr_rxdesc *rxd; 1058177050Syongari int i; 1059177050Syongari 1060177050Syongari /* Tx ring. */ 1061177050Syongari if (sc->vr_cdata.vr_tx_ring_tag) { 1062177050Syongari if (sc->vr_cdata.vr_tx_ring_map) 1063177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag, 1064177050Syongari sc->vr_cdata.vr_tx_ring_map); 1065177050Syongari if (sc->vr_cdata.vr_tx_ring_map && 1066177050Syongari sc->vr_rdata.vr_tx_ring) 1067177050Syongari bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag, 1068177050Syongari sc->vr_rdata.vr_tx_ring, 1069177050Syongari sc->vr_cdata.vr_tx_ring_map); 1070177050Syongari sc->vr_rdata.vr_tx_ring = NULL; 1071177050Syongari sc->vr_cdata.vr_tx_ring_map = NULL; 1072177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag); 1073177050Syongari sc->vr_cdata.vr_tx_ring_tag = NULL; 1074177050Syongari } 1075177050Syongari /* Rx ring. */ 1076177050Syongari if (sc->vr_cdata.vr_rx_ring_tag) { 1077177050Syongari if (sc->vr_cdata.vr_rx_ring_map) 1078177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag, 1079177050Syongari sc->vr_cdata.vr_rx_ring_map); 1080177050Syongari if (sc->vr_cdata.vr_rx_ring_map && 1081177050Syongari sc->vr_rdata.vr_rx_ring) 1082177050Syongari bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag, 1083177050Syongari sc->vr_rdata.vr_rx_ring, 1084177050Syongari sc->vr_cdata.vr_rx_ring_map); 1085177050Syongari sc->vr_rdata.vr_rx_ring = NULL; 1086177050Syongari sc->vr_cdata.vr_rx_ring_map = NULL; 1087177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag); 1088177050Syongari sc->vr_cdata.vr_rx_ring_tag = NULL; 1089177050Syongari } 1090177050Syongari /* Tx buffers. */ 1091177050Syongari if (sc->vr_cdata.vr_tx_tag) { 1092177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1093177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1094177050Syongari if (txd->tx_dmamap) { 1095177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag, 1096177050Syongari txd->tx_dmamap); 1097177050Syongari txd->tx_dmamap = NULL; 1098177050Syongari } 1099177050Syongari } 1100177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag); 1101177050Syongari sc->vr_cdata.vr_tx_tag = NULL; 1102177050Syongari } 1103177050Syongari /* Rx buffers. */ 1104177050Syongari if (sc->vr_cdata.vr_rx_tag) { 1105177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1106177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1107177050Syongari if (rxd->rx_dmamap) { 1108177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1109177050Syongari rxd->rx_dmamap); 1110177050Syongari rxd->rx_dmamap = NULL; 1111177050Syongari } 1112177050Syongari } 1113177050Syongari if (sc->vr_cdata.vr_rx_sparemap) { 1114177050Syongari bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1115177050Syongari sc->vr_cdata.vr_rx_sparemap); 1116177050Syongari sc->vr_cdata.vr_rx_sparemap = 0; 1117177050Syongari } 1118177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag); 1119177050Syongari sc->vr_cdata.vr_rx_tag = NULL; 1120177050Syongari } 1121177050Syongari 1122177050Syongari if (sc->vr_cdata.vr_parent_tag) { 1123177050Syongari bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag); 1124177050Syongari sc->vr_cdata.vr_parent_tag = NULL; 1125177050Syongari } 1126177050Syongari} 1127177050Syongari 112841502Swpaul/* 112941502Swpaul * Initialize the transmit descriptors. 113041502Swpaul */ 1131102336Salfredstatic int 1132177050Syongarivr_tx_ring_init(struct vr_softc *sc) 113341502Swpaul{ 1134177050Syongari struct vr_ring_data *rd; 1135177050Syongari struct vr_txdesc *txd; 1136177050Syongari bus_addr_t addr; 113741502Swpaul int i; 113841502Swpaul 1139177050Syongari sc->vr_cdata.vr_tx_prod = 0; 1140177050Syongari sc->vr_cdata.vr_tx_cons = 0; 1141177050Syongari sc->vr_cdata.vr_tx_cnt = 0; 1142177050Syongari sc->vr_cdata.vr_tx_pkts = 0; 1143177050Syongari 1144177050Syongari rd = &sc->vr_rdata; 1145177050Syongari bzero(rd->vr_tx_ring, VR_TX_RING_SIZE); 1146177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 1147177050Syongari if (i == VR_TX_RING_CNT - 1) 1148177050Syongari addr = VR_TX_RING_ADDR(sc, 0); 1149177050Syongari else 1150177050Syongari addr = VR_TX_RING_ADDR(sc, i + 1); 1151177050Syongari rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1152177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 1153177050Syongari txd->tx_m = NULL; 115441502Swpaul } 115541502Swpaul 1156177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1157177050Syongari sc->vr_cdata.vr_tx_ring_map, 1158177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1159177050Syongari 1160131503Sbms return (0); 116141502Swpaul} 116241502Swpaul 116341502Swpaul/* 116441502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 116541502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 116641502Swpaul * points back to the first. 116741502Swpaul */ 1168102336Salfredstatic int 1169177050Syongarivr_rx_ring_init(struct vr_softc *sc) 117041502Swpaul{ 1171177050Syongari struct vr_ring_data *rd; 1172177050Syongari struct vr_rxdesc *rxd; 1173177050Syongari bus_addr_t addr; 117441502Swpaul int i; 117541502Swpaul 1176177050Syongari sc->vr_cdata.vr_rx_cons = 0; 1177131518Sbms 1178177050Syongari rd = &sc->vr_rdata; 1179177050Syongari bzero(rd->vr_rx_ring, VR_RX_RING_SIZE); 1180177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 1181177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 1182177050Syongari rxd->rx_m = NULL; 1183177050Syongari rxd->desc = &rd->vr_rx_ring[i]; 1184177050Syongari if (i == VR_RX_RING_CNT - 1) 1185177050Syongari addr = VR_RX_RING_ADDR(sc, 0); 1186177050Syongari else 1187177050Syongari addr = VR_RX_RING_ADDR(sc, i + 1); 1188177050Syongari rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1189177050Syongari if (vr_newbuf(sc, i) != 0) 1190131503Sbms return (ENOBUFS); 119141502Swpaul } 119241502Swpaul 1193177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1194177050Syongari sc->vr_cdata.vr_rx_ring_map, 1195177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 119641502Swpaul 1197131503Sbms return (0); 119841502Swpaul} 119941502Swpaul 1200177050Syongaristatic __inline void 1201177050Syongarivr_discard_rxbuf(struct vr_rxdesc *rxd) 1202177050Syongari{ 1203177050Syongari struct vr_desc *desc; 1204177050Syongari 1205177050Syongari desc = rxd->desc; 1206177050Syongari desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t))); 1207177050Syongari desc->vr_status = htole32(VR_RXSTAT_OWN); 1208177050Syongari} 1209177050Syongari 121041502Swpaul/* 121141502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 121241502Swpaul * Note: the length fields are only 11 bits wide, which means the 121341502Swpaul * largest size we can specify is 2047. This is important because 121441502Swpaul * MCLBYTES is 2048, so we have to subtract one otherwise we'll 121541502Swpaul * overflow the field and make a mess. 121641502Swpaul */ 1217102336Salfredstatic int 1218177050Syongarivr_newbuf(struct vr_softc *sc, int idx) 121941502Swpaul{ 1220177050Syongari struct vr_desc *desc; 1221177050Syongari struct vr_rxdesc *rxd; 1222177050Syongari struct mbuf *m; 1223177050Syongari bus_dma_segment_t segs[1]; 1224177050Syongari bus_dmamap_t map; 1225177050Syongari int nsegs; 122641502Swpaul 1227243857Sglebius m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1228177050Syongari if (m == NULL) 1229177050Syongari return (ENOBUFS); 1230177050Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 1231177050Syongari m_adj(m, sizeof(uint64_t)); 1232177050Syongari 1233177050Syongari if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag, 1234177050Syongari sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1235177050Syongari m_freem(m); 1236177050Syongari return (ENOBUFS); 123741502Swpaul } 1238177050Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 123941502Swpaul 1240177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[idx]; 1241177050Syongari if (rxd->rx_m != NULL) { 1242177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1243177050Syongari BUS_DMASYNC_POSTREAD); 1244177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap); 1245177050Syongari } 1246177050Syongari map = rxd->rx_dmamap; 1247177050Syongari rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap; 1248177050Syongari sc->vr_cdata.vr_rx_sparemap = map; 1249177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1250177050Syongari BUS_DMASYNC_PREREAD); 1251177050Syongari rxd->rx_m = m; 1252177050Syongari desc = rxd->desc; 1253177050Syongari desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr)); 1254177050Syongari desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len); 1255177050Syongari desc->vr_status = htole32(VR_RXSTAT_OWN); 125649610Swpaul 1257131503Sbms return (0); 125841502Swpaul} 125941502Swpaul 1260177050Syongari#ifndef __NO_STRICT_ALIGNMENT 1261177050Syongaristatic __inline void 1262177050Syongarivr_fixup_rx(struct mbuf *m) 1263177050Syongari{ 1264177050Syongari uint16_t *src, *dst; 1265177050Syongari int i; 1266177050Syongari 1267177050Syongari src = mtod(m, uint16_t *); 1268177050Syongari dst = src - 1; 1269177050Syongari 1270177050Syongari for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1271177050Syongari *dst++ = *src++; 1272177050Syongari 1273177050Syongari m->m_data -= ETHER_ALIGN; 1274177050Syongari} 1275177050Syongari#endif 1276177050Syongari 127741502Swpaul/* 127841502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 127941502Swpaul * the higher level protocols. 128041502Swpaul */ 1281193096Sattiliostatic int 1282131503Sbmsvr_rxeof(struct vr_softc *sc) 128341502Swpaul{ 1284177050Syongari struct vr_rxdesc *rxd; 1285177050Syongari struct mbuf *m; 1286131503Sbms struct ifnet *ifp; 1287168952Sphk struct vr_desc *cur_rx; 1288193096Sattilio int cons, prog, total_len, rx_npkts; 1289168827Sphk uint32_t rxstat, rxctl; 129041502Swpaul 1291122689Ssam VR_LOCK_ASSERT(sc); 1292147256Sbrooks ifp = sc->vr_ifp; 1293177050Syongari cons = sc->vr_cdata.vr_rx_cons; 1294193096Sattilio rx_npkts = 0; 129541502Swpaul 1296177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1297177050Syongari sc->vr_cdata.vr_rx_ring_map, 1298177050Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1299177050Syongari 1300177050Syongari for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) { 1301127901Sru#ifdef DEVICE_POLLING 1302150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1303127901Sru if (sc->rxcycles <= 0) 1304127901Sru break; 1305127901Sru sc->rxcycles--; 1306127901Sru } 1307150789Sglebius#endif 1308177050Syongari cur_rx = &sc->vr_rdata.vr_rx_ring[cons]; 1309177050Syongari rxstat = le32toh(cur_rx->vr_status); 1310177050Syongari rxctl = le32toh(cur_rx->vr_ctl); 1311177050Syongari if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN) 1312177050Syongari break; 131341502Swpaul 1314177050Syongari prog++; 1315177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[cons]; 1316177050Syongari m = rxd->rx_m; 1317177050Syongari 131841502Swpaul /* 131941502Swpaul * If an error occurs, update stats, clear the 132041502Swpaul * status word and leave the mbuf cluster in place: 132141502Swpaul * it should simply get re-used next time this descriptor 1322131503Sbms * comes up in the ring. 1323177050Syongari * We don't support SG in Rx path yet, so discard 1324177050Syongari * partial frame. 132541502Swpaul */ 1326180551Syongari if ((rxstat & VR_RXSTAT_RX_OK) == 0 || 1327180551Syongari (rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) != 1328177050Syongari (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) { 132941502Swpaul ifp->if_ierrors++; 1330177050Syongari sc->vr_stat.rx_errors++; 1331110131Ssilby if (rxstat & VR_RXSTAT_CRCERR) 1332177050Syongari sc->vr_stat.rx_crc_errors++; 1333110131Ssilby if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1334177050Syongari sc->vr_stat.rx_alignment++; 1335110131Ssilby if (rxstat & VR_RXSTAT_FIFOOFLOW) 1336177050Syongari sc->vr_stat.rx_fifo_overflows++; 1337110131Ssilby if (rxstat & VR_RXSTAT_GIANT) 1338177050Syongari sc->vr_stat.rx_giants++; 1339110131Ssilby if (rxstat & VR_RXSTAT_RUNT) 1340177050Syongari sc->vr_stat.rx_runts++; 1341110131Ssilby if (rxstat & VR_RXSTAT_BUFFERR) 1342177050Syongari sc->vr_stat.rx_no_buffers++; 1343177050Syongari#ifdef VR_SHOW_ERRORS 1344177050Syongari device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1345177050Syongari __func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS); 1346177050Syongari#endif 1347177050Syongari vr_discard_rxbuf(rxd); 134841502Swpaul continue; 134941502Swpaul } 135041502Swpaul 1351177050Syongari if (vr_newbuf(sc, cons) != 0) { 1352177050Syongari ifp->if_iqdrops++; 1353177050Syongari sc->vr_stat.rx_errors++; 1354177050Syongari sc->vr_stat.rx_no_mbufs++; 1355177050Syongari vr_discard_rxbuf(rxd); 1356177050Syongari continue; 1357168827Sphk } 135841502Swpaul 135941502Swpaul /* 136042048Swpaul * XXX The VIA Rhine chip includes the CRC with every 136142048Swpaul * received frame, and there's no way to turn this 136242048Swpaul * behavior off (at least, I can't find anything in 1363131503Sbms * the manual that explains how to do it) so we have 136442048Swpaul * to trim off the CRC manually. 136542048Swpaul */ 1366177050Syongari total_len = VR_RXBYTES(rxstat); 136742048Swpaul total_len -= ETHER_CRC_LEN; 1368177050Syongari m->m_pkthdr.len = m->m_len = total_len; 1369177050Syongari#ifndef __NO_STRICT_ALIGNMENT 1370177050Syongari /* 1371177050Syongari * RX buffers must be 32-bit aligned. 1372177050Syongari * Ignore the alignment problems on the non-strict alignment 1373177050Syongari * platform. The performance hit incurred due to unaligned 1374177050Syongari * accesses is much smaller than the hit produced by forcing 1375177050Syongari * buffer copies all the time. 1376177050Syongari */ 1377177050Syongari vr_fixup_rx(m); 1378177050Syongari#endif 1379177050Syongari m->m_pkthdr.rcvif = ifp; 1380177050Syongari ifp->if_ipackets++; 1381177050Syongari sc->vr_stat.rx_ok++; 1382177050Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1383177050Syongari (rxstat & VR_RXSTAT_FRAG) == 0 && 1384177050Syongari (rxctl & VR_RXCTL_IP) != 0) { 1385177050Syongari /* Checksum is valid for non-fragmented IP packets. */ 1386177050Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1387177050Syongari if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) { 1388177050Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1389177050Syongari if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) { 1390177050Syongari m->m_pkthdr.csum_flags |= 1391177050Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1392177050Syongari if ((rxctl & VR_RXCTL_TCPUDPOK) != 0) 1393177050Syongari m->m_pkthdr.csum_data = 0xffff; 1394177050Syongari } 1395177050Syongari } 139641502Swpaul } 1397122689Ssam VR_UNLOCK(sc); 1398106936Ssam (*ifp->if_input)(ifp, m); 1399122689Ssam VR_LOCK(sc); 1400193096Sattilio rx_npkts++; 140141502Swpaul } 140241502Swpaul 1403177050Syongari if (prog > 0) { 1404228086Syongari /* 1405228086Syongari * Let controller know how many number of RX buffers 1406228086Syongari * are posted but avoid expensive register access if 1407228086Syongari * TX pause capability was not negotiated with link 1408228086Syongari * partner. 1409228086Syongari */ 1410228086Syongari if ((sc->vr_flags & VR_F_TXPAUSE) != 0) { 1411228086Syongari if (prog >= VR_RX_RING_CNT) 1412228086Syongari prog = VR_RX_RING_CNT - 1; 1413228086Syongari CSR_WRITE_1(sc, VR_FLOWCR0, prog); 1414228086Syongari } 1415177050Syongari sc->vr_cdata.vr_rx_cons = cons; 1416177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1417177050Syongari sc->vr_cdata.vr_rx_ring_map, 1418177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1419131503Sbms } 1420193096Sattilio return (rx_npkts); 142141502Swpaul} 142241502Swpaul 142341502Swpaul/* 142441502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 142541502Swpaul * the list buffers. 142641502Swpaul */ 1427102336Salfredstatic void 1428131503Sbmsvr_txeof(struct vr_softc *sc) 142941502Swpaul{ 1430177050Syongari struct vr_txdesc *txd; 1431168952Sphk struct vr_desc *cur_tx; 1432177050Syongari struct ifnet *ifp; 1433177050Syongari uint32_t txctl, txstat; 1434177050Syongari int cons, prod; 143541502Swpaul 1436131518Sbms VR_LOCK_ASSERT(sc); 143741502Swpaul 1438177050Syongari cons = sc->vr_cdata.vr_tx_cons; 1439177050Syongari prod = sc->vr_cdata.vr_tx_prod; 1440177050Syongari if (cons == prod) 1441177050Syongari return; 1442177050Syongari 1443177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1444177050Syongari sc->vr_cdata.vr_tx_ring_map, 1445177050Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1446177050Syongari 1447177050Syongari ifp = sc->vr_ifp; 144841502Swpaul /* 144941502Swpaul * Go through our tx list and free mbufs for those 145041502Swpaul * frames that have been transmitted. 145141502Swpaul */ 1452177050Syongari for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) { 1453177050Syongari cur_tx = &sc->vr_rdata.vr_tx_ring[cons]; 1454177050Syongari txctl = le32toh(cur_tx->vr_ctl); 1455177050Syongari txstat = le32toh(cur_tx->vr_status); 1456177050Syongari if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN) 1457177050Syongari break; 145841502Swpaul 1459177050Syongari sc->vr_cdata.vr_tx_cnt--; 1460177050Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1461177050Syongari /* Only the first descriptor in the chain is valid. */ 1462177050Syongari if ((txctl & VR_TXCTL_FIRSTFRAG) == 0) 1463177050Syongari continue; 146441502Swpaul 1465177050Syongari txd = &sc->vr_cdata.vr_txdesc[cons]; 1466177050Syongari KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n", 1467177050Syongari __func__)); 1468177050Syongari 1469177050Syongari if ((txstat & VR_TXSTAT_ERRSUM) != 0) { 1470177050Syongari ifp->if_oerrors++; 1471177050Syongari sc->vr_stat.tx_errors++; 1472177050Syongari if ((txstat & VR_TXSTAT_ABRT) != 0) { 1473177050Syongari /* Give up and restart Tx. */ 1474177050Syongari sc->vr_stat.tx_abort++; 1475177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 1476177050Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1477177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 1478177050Syongari txd->tx_dmamap); 1479177050Syongari m_freem(txd->tx_m); 1480177050Syongari txd->tx_m = NULL; 1481177050Syongari VR_INC(cons, VR_TX_RING_CNT); 1482177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1483177050Syongari if (vr_tx_stop(sc) != 0) { 1484177050Syongari device_printf(sc->vr_dev, 1485177050Syongari "%s: Tx shutdown error -- " 1486177050Syongari "resetting\n", __func__); 1487177050Syongari sc->vr_flags |= VR_F_RESTART; 1488177050Syongari return; 1489177050Syongari } 1490177050Syongari vr_tx_start(sc); 1491110131Ssilby break; 1492110131Ssilby } 1493177050Syongari if ((sc->vr_revid < REV_ID_VT3071_A && 1494177050Syongari (txstat & VR_TXSTAT_UNDERRUN)) || 1495177050Syongari (txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) { 1496177050Syongari sc->vr_stat.tx_underrun++; 1497177050Syongari /* Retry and restart Tx. */ 1498177050Syongari sc->vr_cdata.vr_tx_cnt++; 1499177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1500177050Syongari cur_tx->vr_status = htole32(VR_TXSTAT_OWN); 1501177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1502177050Syongari sc->vr_cdata.vr_tx_ring_map, 1503177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1504177050Syongari vr_tx_underrun(sc); 1505177050Syongari return; 1506177050Syongari } 1507177050Syongari if ((txstat & VR_TXSTAT_DEFER) != 0) { 150841502Swpaul ifp->if_collisions++; 1509177050Syongari sc->vr_stat.tx_collisions++; 1510177050Syongari } 1511177050Syongari if ((txstat & VR_TXSTAT_LATECOLL) != 0) { 151241502Swpaul ifp->if_collisions++; 1513177050Syongari sc->vr_stat.tx_late_collisions++; 1514177050Syongari } 1515177050Syongari } else { 1516177050Syongari sc->vr_stat.tx_ok++; 1517177050Syongari ifp->if_opackets++; 151841502Swpaul } 151941502Swpaul 1520177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1521177050Syongari BUS_DMASYNC_POSTWRITE); 1522177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1523177050Syongari if (sc->vr_revid < REV_ID_VT3071_A) { 1524177050Syongari ifp->if_collisions += 1525177050Syongari (txstat & VR_TXSTAT_COLLCNT) >> 3; 1526177050Syongari sc->vr_stat.tx_collisions += 1527177050Syongari (txstat & VR_TXSTAT_COLLCNT) >> 3; 1528177050Syongari } else { 1529177050Syongari ifp->if_collisions += (txstat & 0x0f); 1530177050Syongari sc->vr_stat.tx_collisions += (txstat & 0x0f); 1531177050Syongari } 1532177050Syongari m_freem(txd->tx_m); 1533177050Syongari txd->tx_m = NULL; 1534177050Syongari } 153541502Swpaul 1536177050Syongari sc->vr_cdata.vr_tx_cons = cons; 1537177050Syongari if (sc->vr_cdata.vr_tx_cnt == 0) 1538177050Syongari sc->vr_watchdog_timer = 0; 153941502Swpaul} 154041502Swpaul 1541102336Salfredstatic void 1542131503Sbmsvr_tick(void *xsc) 154351432Swpaul{ 1544177050Syongari struct vr_softc *sc; 154551432Swpaul struct mii_data *mii; 154651432Swpaul 1547177050Syongari sc = (struct vr_softc *)xsc; 1548177050Syongari 1549151911Sjhb VR_LOCK_ASSERT(sc); 1550131517Sbms 1551177050Syongari if ((sc->vr_flags & VR_F_RESTART) != 0) { 1552162315Sglebius device_printf(sc->vr_dev, "restarting\n"); 1553177050Syongari sc->vr_stat.num_restart++; 1554211765Syongari sc->vr_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1555131844Sbms vr_init_locked(sc); 1556110131Ssilby sc->vr_flags &= ~VR_F_RESTART; 1557110131Ssilby } 1558110131Ssilby 155951432Swpaul mii = device_get_softc(sc->vr_miibus); 156051432Swpaul mii_tick(mii); 1561228084Syongari if ((sc->vr_flags & VR_F_LINK) == 0) 1562223405Syongari vr_miibus_statchg(sc->vr_dev); 1563177050Syongari vr_watchdog(sc); 1564151911Sjhb callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 156551432Swpaul} 156651432Swpaul 1567127901Sru#ifdef DEVICE_POLLING 1568127901Srustatic poll_handler_t vr_poll; 1569131844Sbmsstatic poll_handler_t vr_poll_locked; 1570127901Sru 1571193096Sattiliostatic int 1572127901Sruvr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1573127901Sru{ 1574177050Syongari struct vr_softc *sc; 1575193096Sattilio int rx_npkts; 1576127901Sru 1577177050Syongari sc = ifp->if_softc; 1578193096Sattilio rx_npkts = 0; 1579177050Syongari 1580127901Sru VR_LOCK(sc); 1581177050Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1582193096Sattilio rx_npkts = vr_poll_locked(ifp, cmd, count); 1583131844Sbms VR_UNLOCK(sc); 1584193096Sattilio return (rx_npkts); 1585131844Sbms} 1586131517Sbms 1587193096Sattiliostatic int 1588131844Sbmsvr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1589131844Sbms{ 1590177050Syongari struct vr_softc *sc; 1591193096Sattilio int rx_npkts; 1592131844Sbms 1593177050Syongari sc = ifp->if_softc; 1594177050Syongari 1595131844Sbms VR_LOCK_ASSERT(sc); 1596131844Sbms 1597127901Sru sc->rxcycles = count; 1598193096Sattilio rx_npkts = vr_rxeof(sc); 1599127901Sru vr_txeof(sc); 1600133006Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1601131844Sbms vr_start_locked(ifp); 1602127901Sru 1603131503Sbms if (cmd == POLL_AND_CHECK_STATUS) { 1604131503Sbms uint16_t status; 1605127901Sru 1606131503Sbms /* Also check status register. */ 1607127901Sru status = CSR_READ_2(sc, VR_ISR); 1608127901Sru if (status) 1609127901Sru CSR_WRITE_2(sc, VR_ISR, status); 1610127901Sru 1611127901Sru if ((status & VR_INTRS) == 0) 1612193096Sattilio return (rx_npkts); 1613127901Sru 1614177050Syongari if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1615177050Syongari VR_ISR_STATSOFLOW)) != 0) { 1616177050Syongari if (vr_error(sc, status) != 0) 1617193096Sattilio return (rx_npkts); 1618127901Sru } 1619177050Syongari if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1620177050Syongari#ifdef VR_SHOW_ERRORS 1621177050Syongari device_printf(sc->vr_dev, "%s: receive error : 0x%b\n", 1622177050Syongari __func__, status, VR_ISR_ERR_BITS); 1623177050Syongari#endif 1624177050Syongari vr_rx_start(sc); 1625127901Sru } 1626177050Syongari } 1627193096Sattilio return (rx_npkts); 1628177050Syongari} 1629177050Syongari#endif /* DEVICE_POLLING */ 1630127901Sru 1631177050Syongari/* Back off the transmit threshold. */ 1632177050Syongaristatic void 1633177050Syongarivr_tx_underrun(struct vr_softc *sc) 1634177050Syongari{ 1635177050Syongari int thresh; 1636127901Sru 1637177050Syongari device_printf(sc->vr_dev, "Tx underrun -- "); 1638177050Syongari if (sc->vr_txthresh < VR_TXTHRESH_MAX) { 1639177050Syongari thresh = sc->vr_txthresh; 1640177050Syongari sc->vr_txthresh++; 1641177050Syongari if (sc->vr_txthresh >= VR_TXTHRESH_MAX) { 1642177050Syongari sc->vr_txthresh = VR_TXTHRESH_MAX; 1643177050Syongari printf("using store and forward mode\n"); 1644177050Syongari } else 1645177050Syongari printf("increasing Tx threshold(%d -> %d)\n", 1646177050Syongari vr_tx_threshold_tables[thresh].value, 1647177050Syongari vr_tx_threshold_tables[thresh + 1].value); 1648177050Syongari } else 1649177050Syongari printf("\n"); 1650177050Syongari sc->vr_stat.tx_underrun++; 1651177050Syongari if (vr_tx_stop(sc) != 0) { 1652177050Syongari device_printf(sc->vr_dev, "%s: Tx shutdown error -- " 1653177050Syongari "resetting\n", __func__); 1654177050Syongari sc->vr_flags |= VR_F_RESTART; 1655177050Syongari return; 1656127901Sru } 1657177050Syongari vr_tx_start(sc); 1658127901Sru} 1659127901Sru 1660235334Srpaulostatic int 1661131503Sbmsvr_intr(void *arg) 166241502Swpaul{ 1663177050Syongari struct vr_softc *sc; 1664235334Srpaulo uint16_t status; 1665235334Srpaulo 1666235334Srpaulo sc = (struct vr_softc *)arg; 1667235334Srpaulo 1668235334Srpaulo status = CSR_READ_2(sc, VR_ISR); 1669235334Srpaulo if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0) 1670235334Srpaulo return (FILTER_STRAY); 1671235334Srpaulo 1672235334Srpaulo /* Disable interrupts. */ 1673235334Srpaulo CSR_WRITE_2(sc, VR_IMR, 0x0000); 1674235334Srpaulo 1675235334Srpaulo taskqueue_enqueue_fast(taskqueue_fast, &sc->vr_inttask); 1676235334Srpaulo 1677235334Srpaulo return (FILTER_HANDLED); 1678235334Srpaulo} 1679235334Srpaulo 1680235334Srpaulostatic void 1681235334Srpaulovr_int_task(void *arg, int npending) 1682235334Srpaulo{ 1683235334Srpaulo struct vr_softc *sc; 1684177050Syongari struct ifnet *ifp; 1685131503Sbms uint16_t status; 168641502Swpaul 1687177050Syongari sc = (struct vr_softc *)arg; 1688177050Syongari 168967087Swpaul VR_LOCK(sc); 1690131844Sbms 1691228084Syongari if ((sc->vr_flags & VR_F_SUSPENDED) != 0) 1692131844Sbms goto done_locked; 1693131844Sbms 1694177050Syongari status = CSR_READ_2(sc, VR_ISR); 1695177050Syongari ifp = sc->vr_ifp; 1696127901Sru#ifdef DEVICE_POLLING 1697177050Syongari if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1698131844Sbms goto done_locked; 1699150789Sglebius#endif 1700131844Sbms 1701131844Sbms /* Suppress unwanted interrupts. */ 1702177050Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1703177050Syongari (sc->vr_flags & VR_F_RESTART) != 0) { 1704177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 1705177050Syongari CSR_WRITE_2(sc, VR_ISR, status); 1706131844Sbms goto done_locked; 170741502Swpaul } 170841502Swpaul 1709177050Syongari for (; (status & VR_INTRS) != 0;) { 1710177050Syongari CSR_WRITE_2(sc, VR_ISR, status); 1711177050Syongari if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1712177050Syongari VR_ISR_STATSOFLOW)) != 0) { 1713177050Syongari if (vr_error(sc, status) != 0) { 1714177050Syongari VR_UNLOCK(sc); 1715177050Syongari return; 1716177050Syongari } 1717177050Syongari } 1718177050Syongari vr_rxeof(sc); 1719177050Syongari if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1720177050Syongari#ifdef VR_SHOW_ERRORS 1721177050Syongari device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1722177050Syongari __func__, status, VR_ISR_ERR_BITS); 1723177050Syongari#endif 1724177050Syongari /* Restart Rx if RxDMA SM was stopped. */ 1725177050Syongari vr_rx_start(sc); 1726177050Syongari } 1727177050Syongari vr_txeof(sc); 1728235334Srpaulo 1729235334Srpaulo if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1730235334Srpaulo vr_start_locked(ifp); 1731235334Srpaulo 173241502Swpaul status = CSR_READ_2(sc, VR_ISR); 1733177050Syongari } 1734168813Sphk 1735177050Syongari /* Re-enable interrupts. */ 1736177050Syongari CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 173741502Swpaul 1738177050Syongaridone_locked: 1739177050Syongari VR_UNLOCK(sc); 1740177050Syongari} 174141502Swpaul 1742177050Syongaristatic int 1743177050Syongarivr_error(struct vr_softc *sc, uint16_t status) 1744177050Syongari{ 1745177050Syongari uint16_t pcis; 1746110131Ssilby 1747177050Syongari status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW; 1748177050Syongari if ((status & VR_ISR_BUSERR) != 0) { 1749177050Syongari status &= ~VR_ISR_BUSERR; 1750177050Syongari sc->vr_stat.bus_errors++; 1751177050Syongari /* Disable further interrupts. */ 1752177050Syongari CSR_WRITE_2(sc, VR_IMR, 0); 1753177050Syongari pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2); 1754177050Syongari device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- " 1755177050Syongari "resetting\n", pcis); 1756177050Syongari pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2); 1757177050Syongari sc->vr_flags |= VR_F_RESTART; 1758177050Syongari return (EAGAIN); 1759177050Syongari } 1760177050Syongari if ((status & VR_ISR_LINKSTAT2) != 0) { 1761177050Syongari /* Link state change, duplex changes etc. */ 1762177050Syongari status &= ~VR_ISR_LINKSTAT2; 1763177050Syongari } 1764177050Syongari if ((status & VR_ISR_STATSOFLOW) != 0) { 1765177050Syongari status &= ~VR_ISR_STATSOFLOW; 1766177050Syongari if (sc->vr_revid >= REV_ID_VT6105M_A0) { 1767177050Syongari /* Update MIB counters. */ 176841502Swpaul } 1769177050Syongari } 177041502Swpaul 1771177050Syongari if (status != 0) 1772177050Syongari device_printf(sc->vr_dev, 1773177050Syongari "unhandled interrupt, status = 0x%04x\n", status); 1774177050Syongari return (0); 1775177050Syongari} 1776177050Syongari 1777177050Syongari/* 1778177050Syongari * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1779177050Syongari * pointers to the fragment pointers. 1780177050Syongari */ 1781177050Syongaristatic int 1782177050Syongarivr_encap(struct vr_softc *sc, struct mbuf **m_head) 1783177050Syongari{ 1784177050Syongari struct vr_txdesc *txd; 1785177050Syongari struct vr_desc *desc; 1786177050Syongari struct mbuf *m; 1787177050Syongari bus_dma_segment_t txsegs[VR_MAXFRAGS]; 1788177050Syongari uint32_t csum_flags, txctl; 1789177050Syongari int error, i, nsegs, prod, si; 1790177050Syongari int padlen; 1791177050Syongari 1792177050Syongari VR_LOCK_ASSERT(sc); 1793177050Syongari 1794177050Syongari M_ASSERTPKTHDR((*m_head)); 1795177050Syongari 1796177050Syongari /* 1797177050Syongari * Some VIA Rhine wants packet buffers to be longword 1798177050Syongari * aligned, but very often our mbufs aren't. Rather than 1799177050Syongari * waste time trying to decide when to copy and when not 1800177050Syongari * to copy, just do it all the time. 1801177050Syongari */ 1802177050Syongari if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) { 1803243857Sglebius m = m_defrag(*m_head, M_NOWAIT); 1804177050Syongari if (m == NULL) { 1805177050Syongari m_freem(*m_head); 1806177050Syongari *m_head = NULL; 1807177050Syongari return (ENOBUFS); 180841502Swpaul } 1809177050Syongari *m_head = m; 1810177050Syongari } 181141502Swpaul 1812177050Syongari /* 1813177050Syongari * The Rhine chip doesn't auto-pad, so we have to make 1814177050Syongari * sure to pad short frames out to the minimum frame length 1815177050Syongari * ourselves. 1816177050Syongari */ 1817177050Syongari if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) { 1818177050Syongari m = *m_head; 1819177050Syongari padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len; 1820177050Syongari if (M_WRITABLE(m) == 0) { 1821177050Syongari /* Get a writable copy. */ 1822243857Sglebius m = m_dup(*m_head, M_NOWAIT); 1823177050Syongari m_freem(*m_head); 1824177050Syongari if (m == NULL) { 1825177050Syongari *m_head = NULL; 1826177050Syongari return (ENOBUFS); 1827127901Sru } 1828177050Syongari *m_head = m; 182941502Swpaul } 1830177050Syongari if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1831243857Sglebius m = m_defrag(m, M_NOWAIT); 1832177050Syongari if (m == NULL) { 1833177050Syongari m_freem(*m_head); 1834177050Syongari *m_head = NULL; 1835177050Syongari return (ENOBUFS); 1836177050Syongari } 1837177050Syongari } 1838177050Syongari /* 1839177050Syongari * Manually pad short frames, and zero the pad space 1840177050Syongari * to avoid leaking data. 1841177050Syongari */ 1842177050Syongari bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1843177050Syongari m->m_pkthdr.len += padlen; 1844177050Syongari m->m_len = m->m_pkthdr.len; 1845177050Syongari *m_head = m; 184641502Swpaul } 184741502Swpaul 1848177050Syongari prod = sc->vr_cdata.vr_tx_prod; 1849177050Syongari txd = &sc->vr_cdata.vr_txdesc[prod]; 1850177050Syongari error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1851177050Syongari *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1852177050Syongari if (error == EFBIG) { 1853243857Sglebius m = m_collapse(*m_head, M_NOWAIT, VR_MAXFRAGS); 1854177050Syongari if (m == NULL) { 1855177050Syongari m_freem(*m_head); 1856177050Syongari *m_head = NULL; 1857177050Syongari return (ENOBUFS); 1858177050Syongari } 1859177050Syongari *m_head = m; 1860177050Syongari error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, 1861177050Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1862177050Syongari if (error != 0) { 1863177050Syongari m_freem(*m_head); 1864177050Syongari *m_head = NULL; 1865177050Syongari return (error); 1866177050Syongari } 1867177050Syongari } else if (error != 0) 1868177050Syongari return (error); 1869177050Syongari if (nsegs == 0) { 1870177050Syongari m_freem(*m_head); 1871177050Syongari *m_head = NULL; 1872177050Syongari return (EIO); 1873177050Syongari } 187441502Swpaul 1875177050Syongari /* Check number of available descriptors. */ 1876177050Syongari if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) { 1877177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1878177050Syongari return (ENOBUFS); 1879177050Syongari } 1880131844Sbms 1881177050Syongari txd->tx_m = *m_head; 1882177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1883177050Syongari BUS_DMASYNC_PREWRITE); 1884177050Syongari 1885177050Syongari /* Set checksum offload. */ 1886177050Syongari csum_flags = 0; 1887177050Syongari if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) { 1888177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1889177050Syongari csum_flags |= VR_TXCTL_IPCSUM; 1890177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1891177050Syongari csum_flags |= VR_TXCTL_TCPCSUM; 1892177050Syongari if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1893177050Syongari csum_flags |= VR_TXCTL_UDPCSUM; 1894177050Syongari } 1895177050Syongari 1896177050Syongari /* 1897177050Syongari * Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit 1898177050Syongari * is required for all descriptors regardless of single or 1899177050Syongari * multiple buffers. Also VR_TXSTAT_OWN bit is valid only for 1900177050Syongari * the first descriptor for a multi-fragmented frames. Without 1901177050Syongari * that VIA Rhine chip generates Tx underrun interrupts and can't 1902177050Syongari * send any frames. 1903177050Syongari */ 1904177050Syongari si = prod; 1905177050Syongari for (i = 0; i < nsegs; i++) { 1906177050Syongari desc = &sc->vr_rdata.vr_tx_ring[prod]; 1907177050Syongari desc->vr_status = 0; 1908177050Syongari txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags; 1909177050Syongari if (i == 0) 1910177050Syongari txctl |= VR_TXCTL_FIRSTFRAG; 1911177050Syongari desc->vr_ctl = htole32(txctl); 1912177050Syongari desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr)); 1913177050Syongari sc->vr_cdata.vr_tx_cnt++; 1914177050Syongari VR_INC(prod, VR_TX_RING_CNT); 1915177050Syongari } 1916177050Syongari /* Update producer index. */ 1917177050Syongari sc->vr_cdata.vr_tx_prod = prod; 1918177050Syongari 1919177050Syongari prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT; 1920177050Syongari desc = &sc->vr_rdata.vr_tx_ring[prod]; 1921177050Syongari 1922177050Syongari /* 1923177050Syongari * Set EOP on the last desciptor and reuqest Tx completion 1924177050Syongari * interrupt for every VR_TX_INTR_THRESH-th frames. 1925177050Syongari */ 1926177050Syongari VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH); 1927177050Syongari if (sc->vr_cdata.vr_tx_pkts == 0) 1928177050Syongari desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT); 1929177050Syongari else 1930177050Syongari desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG); 1931177050Syongari 1932177050Syongari /* Lastly turn the first descriptor ownership to hardware. */ 1933177050Syongari desc = &sc->vr_rdata.vr_tx_ring[si]; 1934177050Syongari desc->vr_status |= htole32(VR_TXSTAT_OWN); 1935177050Syongari 1936177050Syongari /* Sync descriptors. */ 1937177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1938177050Syongari sc->vr_cdata.vr_tx_ring_map, 1939177050Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1940177050Syongari 1941177050Syongari return (0); 194241502Swpaul} 194341502Swpaul 1944102336Salfredstatic void 1945131503Sbmsvr_start(struct ifnet *ifp) 194641502Swpaul{ 1947177050Syongari struct vr_softc *sc; 1948131844Sbms 1949177050Syongari sc = ifp->if_softc; 1950131844Sbms VR_LOCK(sc); 1951131844Sbms vr_start_locked(ifp); 1952131844Sbms VR_UNLOCK(sc); 1953131844Sbms} 1954131844Sbms 1955131844Sbmsstatic void 1956131844Sbmsvr_start_locked(struct ifnet *ifp) 1957131844Sbms{ 1958177050Syongari struct vr_softc *sc; 1959177050Syongari struct mbuf *m_head; 1960177050Syongari int enq; 196141502Swpaul 1962177050Syongari sc = ifp->if_softc; 1963177050Syongari 1964177050Syongari VR_LOCK_ASSERT(sc); 1965177050Syongari 1966177050Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1967228084Syongari IFF_DRV_RUNNING || (sc->vr_flags & VR_F_LINK) == 0) 1968127901Sru return; 1969127901Sru 1970177050Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1971177050Syongari sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) { 1972177050Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 197341502Swpaul if (m_head == NULL) 197441502Swpaul break; 1975168813Sphk /* 1976177050Syongari * Pack the data into the transmit ring. If we 1977177050Syongari * don't have room, set the OACTIVE flag and wait 1978177050Syongari * for the NIC to drain the ring. 1979168813Sphk */ 1980177050Syongari if (vr_encap(sc, &m_head)) { 1981177050Syongari if (m_head == NULL) 1982168813Sphk break; 1983177050Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1984177050Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1985177050Syongari break; 1986168813Sphk } 198751583Swpaul 1988177050Syongari enq++; 1989168813Sphk /* 1990168813Sphk * If there's a BPF listener, bounce a copy of this frame 1991168813Sphk * to him. 1992168813Sphk */ 1993177050Syongari ETHER_BPF_MTAP(ifp, m_head); 1994127901Sru } 1995177050Syongari 1996177050Syongari if (enq > 0) { 1997177050Syongari /* Tell the chip to start transmitting. */ 1998177050Syongari VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 1999177050Syongari /* Set a timeout in case the chip goes out to lunch. */ 2000177050Syongari sc->vr_watchdog_timer = 5; 2001177050Syongari } 2002131844Sbms} 200341502Swpaul 2004131844Sbmsstatic void 2005131844Sbmsvr_init(void *xsc) 2006131844Sbms{ 2007177050Syongari struct vr_softc *sc; 2008131844Sbms 2009177050Syongari sc = (struct vr_softc *)xsc; 2010131844Sbms VR_LOCK(sc); 2011131844Sbms vr_init_locked(sc); 201267087Swpaul VR_UNLOCK(sc); 201341502Swpaul} 201441502Swpaul 2015102336Salfredstatic void 2016131844Sbmsvr_init_locked(struct vr_softc *sc) 201741502Swpaul{ 2018177050Syongari struct ifnet *ifp; 201951432Swpaul struct mii_data *mii; 2020177050Syongari bus_addr_t addr; 202173963Swpaul int i; 202241502Swpaul 2023131844Sbms VR_LOCK_ASSERT(sc); 202441502Swpaul 2025177050Syongari ifp = sc->vr_ifp; 202651432Swpaul mii = device_get_softc(sc->vr_miibus); 202741502Swpaul 2028211765Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2029211765Syongari return; 2030211765Syongari 2031131503Sbms /* Cancel pending I/O and free all RX/TX buffers. */ 203241502Swpaul vr_stop(sc); 203341502Swpaul vr_reset(sc); 203441502Swpaul 2035131503Sbms /* Set our station address. */ 203673963Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 2037152315Sru CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]); 2038131503Sbms 2039131503Sbms /* Set DMA size. */ 2040101375Ssilby VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 2041101375Ssilby VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 204273963Swpaul 2043131503Sbms /* 2044101375Ssilby * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 2045101108Ssilby * so we must set both. 2046101108Ssilby */ 2047101108Ssilby VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 2048110131Ssilby VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 2049101108Ssilby 2050101108Ssilby VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 2051177050Syongari VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg); 2052101108Ssilby 205341502Swpaul VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 2054110131Ssilby VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 205541502Swpaul 205641502Swpaul VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 2057177050Syongari VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg); 205841502Swpaul 205941502Swpaul /* Init circular RX list. */ 2060177050Syongari if (vr_rx_ring_init(sc) != 0) { 2061162315Sglebius device_printf(sc->vr_dev, 2062151773Sjhb "initialization failed: no memory for rx buffers\n"); 206341502Swpaul vr_stop(sc); 206441502Swpaul return; 206541502Swpaul } 206641502Swpaul 2067131503Sbms /* Init tx descriptors. */ 2068177050Syongari vr_tx_ring_init(sc); 206941502Swpaul 2070177050Syongari if ((sc->vr_quirks & VR_Q_CAM) != 0) { 2071180552Syongari uint8_t vcam[2] = { 0, 0 }; 2072180552Syongari 2073180552Syongari /* Disable VLAN hardware tag insertion/stripping. */ 2074180552Syongari VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL); 2075180552Syongari /* Disable VLAN hardware filtering. */ 2076180552Syongari VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB); 2077180552Syongari /* Disable all CAM entries. */ 2078180552Syongari vr_cam_mask(sc, VR_MCAST_CAM, 0); 2079180552Syongari vr_cam_mask(sc, VR_VLAN_CAM, 0); 2080180552Syongari /* Enable the first VLAN CAM. */ 2081180552Syongari vr_cam_data(sc, VR_VLAN_CAM, 0, vcam); 2082180552Syongari vr_cam_mask(sc, VR_VLAN_CAM, 1); 2083177050Syongari } 208441502Swpaul 208541502Swpaul /* 2086177050Syongari * Set up receive filter. 208741502Swpaul */ 2088177050Syongari vr_set_filter(sc); 208941502Swpaul 209041502Swpaul /* 2091177050Syongari * Load the address of the RX ring. 209241502Swpaul */ 2093177050Syongari addr = VR_RX_RING_ADDR(sc, 0); 2094177050Syongari CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2095177050Syongari /* 2096177050Syongari * Load the address of the TX ring. 2097177050Syongari */ 2098177050Syongari addr = VR_TX_RING_ADDR(sc, 0); 2099177050Syongari CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2100177050Syongari /* Default : full-duplex, no Tx poll. */ 2101177050Syongari CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL); 210241502Swpaul 2103177050Syongari /* Set flow-control parameters for Rhine III. */ 2104177050Syongari if (sc->vr_revid >= REV_ID_VT6105_A0) { 2105177050Syongari /* 2106228086Syongari * Configure Rx buffer count available for incoming 2107228086Syongari * packet. 2108228086Syongari * Even though data sheet says almost nothing about 2109228086Syongari * this register, this register should be updated 2110228086Syongari * whenever driver adds new RX buffers to controller. 2111228086Syongari * Otherwise, XON frame is not sent to link partner 2112228086Syongari * even if controller has enough RX buffers and you 2113228086Syongari * would be isolated from network. 2114228086Syongari * The controller is not smart enough to know number 2115228086Syongari * of available RX buffers so driver have to let 2116228086Syongari * controller know how many RX buffers are posted. 2117228086Syongari * In other words, this register works like a residue 2118228086Syongari * counter for RX buffers and should be initialized 2119228086Syongari * to the number of total RX buffers - 1 before 2120228086Syongari * enabling RX MAC. Note, this register is 8bits so 2121228086Syongari * it effectively limits the maximum number of RX 2122228086Syongari * buffer to be configured by controller is 255. 2123177050Syongari */ 2124228086Syongari CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT - 1); 2125228086Syongari /* 2126228086Syongari * Tx pause low threshold : 8 free receive buffers 2127228086Syongari * Tx pause XON high threshold : 24 free receive buffers 2128228086Syongari */ 2129177050Syongari CSR_WRITE_1(sc, VR_FLOWCR1, 2130228086Syongari VR_FLOWCR1_TXLO8 | VR_FLOWCR1_TXHI24 | VR_FLOWCR1_XONXOFF); 2131177050Syongari /* Set Tx pause timer. */ 2132177050Syongari CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff); 2133177050Syongari } 2134177050Syongari 213541502Swpaul /* Enable receiver and transmitter. */ 2136177050Syongari CSR_WRITE_1(sc, VR_CR0, 2137177050Syongari VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO); 213841502Swpaul 2139127901Sru CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 2140127901Sru#ifdef DEVICE_POLLING 214141502Swpaul /* 2142127901Sru * Disable interrupts if we are polling. 2143127901Sru */ 2144150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 2145127901Sru CSR_WRITE_2(sc, VR_IMR, 0); 2146131503Sbms else 2147150789Sglebius#endif 2148127901Sru /* 2149177050Syongari * Enable interrupts and disable MII intrs. 215041502Swpaul */ 215141502Swpaul CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2152177050Syongari if (sc->vr_revid > REV_ID_VT6102_A) 2153177050Syongari CSR_WRITE_2(sc, VR_MII_IMR, 0); 215441502Swpaul 2155148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2156148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 215741502Swpaul 2158228086Syongari sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE); 2159228084Syongari mii_mediachg(mii); 2160228084Syongari 2161151911Sjhb callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 216241502Swpaul} 216341502Swpaul 216441502Swpaul/* 216541502Swpaul * Set media options. 216641502Swpaul */ 2167102336Salfredstatic int 2168131503Sbmsvr_ifmedia_upd(struct ifnet *ifp) 216941502Swpaul{ 2170177050Syongari struct vr_softc *sc; 2171177050Syongari struct mii_data *mii; 2172177050Syongari struct mii_softc *miisc; 2173177050Syongari int error; 217441502Swpaul 2175177050Syongari sc = ifp->if_softc; 2176177050Syongari VR_LOCK(sc); 2177177050Syongari mii = device_get_softc(sc->vr_miibus); 2178221407Smarius LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2179221407Smarius PHY_RESET(miisc); 2180228086Syongari sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE); 2181177050Syongari error = mii_mediachg(mii); 2182177050Syongari VR_UNLOCK(sc); 218341502Swpaul 2184177050Syongari return (error); 218541502Swpaul} 218641502Swpaul 218741502Swpaul/* 218841502Swpaul * Report current media status. 218941502Swpaul */ 2190102336Salfredstatic void 2191131503Sbmsvr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 219241502Swpaul{ 2193177050Syongari struct vr_softc *sc; 219451432Swpaul struct mii_data *mii; 219541502Swpaul 2196177050Syongari sc = ifp->if_softc; 219751432Swpaul mii = device_get_softc(sc->vr_miibus); 2198133468Sscottl VR_LOCK(sc); 2199223405Syongari if ((ifp->if_flags & IFF_UP) == 0) { 2200223405Syongari VR_UNLOCK(sc); 2201223405Syongari return; 2202223405Syongari } 220351432Swpaul mii_pollstat(mii); 220451432Swpaul ifmr->ifm_active = mii->mii_media_active; 220551432Swpaul ifmr->ifm_status = mii->mii_media_status; 2206226478Syongari VR_UNLOCK(sc); 220741502Swpaul} 220841502Swpaul 2209102336Salfredstatic int 2210131503Sbmsvr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 221141502Swpaul{ 2212177050Syongari struct vr_softc *sc; 2213177050Syongari struct ifreq *ifr; 221451432Swpaul struct mii_data *mii; 2215177050Syongari int error, mask; 221641502Swpaul 2217177050Syongari sc = ifp->if_softc; 2218177050Syongari ifr = (struct ifreq *)data; 2219177050Syongari error = 0; 2220177050Syongari 2221131503Sbms switch (command) { 222241502Swpaul case SIOCSIFFLAGS: 2223131844Sbms VR_LOCK(sc); 222441502Swpaul if (ifp->if_flags & IFF_UP) { 2225177050Syongari if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2226177050Syongari if ((ifp->if_flags ^ sc->vr_if_flags) & 2227177050Syongari (IFF_PROMISC | IFF_ALLMULTI)) 2228177050Syongari vr_set_filter(sc); 2229177050Syongari } else { 2230228084Syongari if ((sc->vr_flags & VR_F_DETACHED) == 0) 2231177050Syongari vr_init_locked(sc); 2232177050Syongari } 223341502Swpaul } else { 2234148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 223541502Swpaul vr_stop(sc); 223641502Swpaul } 2237177050Syongari sc->vr_if_flags = ifp->if_flags; 2238131844Sbms VR_UNLOCK(sc); 223941502Swpaul break; 224041502Swpaul case SIOCADDMULTI: 224141502Swpaul case SIOCDELMULTI: 2242131518Sbms VR_LOCK(sc); 2243177050Syongari vr_set_filter(sc); 2244131518Sbms VR_UNLOCK(sc); 224541502Swpaul break; 224641502Swpaul case SIOCGIFMEDIA: 224741502Swpaul case SIOCSIFMEDIA: 224851432Swpaul mii = device_get_softc(sc->vr_miibus); 224951432Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 225041502Swpaul break; 2251128118Sru case SIOCSIFCAP: 2252177050Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2253150789Sglebius#ifdef DEVICE_POLLING 2254177050Syongari if (mask & IFCAP_POLLING) { 2255177050Syongari if (ifr->ifr_reqcap & IFCAP_POLLING) { 2256177050Syongari error = ether_poll_register(vr_poll, ifp); 2257177050Syongari if (error != 0) 2258177050Syongari break; 2259177050Syongari VR_LOCK(sc); 2260177050Syongari /* Disable interrupts. */ 2261177050Syongari CSR_WRITE_2(sc, VR_IMR, 0x0000); 2262177050Syongari ifp->if_capenable |= IFCAP_POLLING; 2263177050Syongari VR_UNLOCK(sc); 2264177050Syongari } else { 2265177050Syongari error = ether_poll_deregister(ifp); 2266177050Syongari /* Enable interrupts. */ 2267177050Syongari VR_LOCK(sc); 2268177050Syongari CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2269177050Syongari ifp->if_capenable &= ~IFCAP_POLLING; 2270177050Syongari VR_UNLOCK(sc); 2271177050Syongari } 2272150789Sglebius } 2273177050Syongari#endif /* DEVICE_POLLING */ 2274177050Syongari if ((mask & IFCAP_TXCSUM) != 0 && 2275177050Syongari (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2276177050Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 2277177050Syongari if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2278177050Syongari ifp->if_hwassist |= VR_CSUM_FEATURES; 2279177050Syongari else 2280177050Syongari ifp->if_hwassist &= ~VR_CSUM_FEATURES; 2281150789Sglebius } 2282177050Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2283177050Syongari (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 2284177050Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2285177050Syongari if ((mask & IFCAP_WOL_UCAST) != 0 && 2286177050Syongari (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0) 2287177050Syongari ifp->if_capenable ^= IFCAP_WOL_UCAST; 2288177050Syongari if ((mask & IFCAP_WOL_MAGIC) != 0 && 2289177050Syongari (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2290177050Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2291128118Sru break; 229241502Swpaul default: 2293106936Ssam error = ether_ioctl(ifp, command, data); 229441502Swpaul break; 229541502Swpaul } 229641502Swpaul 2297131503Sbms return (error); 229841502Swpaul} 229941502Swpaul 2300102336Salfredstatic void 2301177050Syongarivr_watchdog(struct vr_softc *sc) 230241502Swpaul{ 2303177050Syongari struct ifnet *ifp; 230441502Swpaul 2305177050Syongari VR_LOCK_ASSERT(sc); 2306131844Sbms 2307177050Syongari if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer) 2308177050Syongari return; 2309177050Syongari 2310177050Syongari ifp = sc->vr_ifp; 2311177050Syongari /* 2312177050Syongari * Reclaim first as we don't request interrupt for every packets. 2313177050Syongari */ 2314177050Syongari vr_txeof(sc); 2315177050Syongari if (sc->vr_cdata.vr_tx_cnt == 0) 2316177050Syongari return; 2317177050Syongari 2318228084Syongari if ((sc->vr_flags & VR_F_LINK) == 0) { 2319177050Syongari if (bootverbose) 2320177050Syongari if_printf(sc->vr_ifp, "watchdog timeout " 2321177050Syongari "(missed link)\n"); 2322177050Syongari ifp->if_oerrors++; 2323211765Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2324177050Syongari vr_init_locked(sc); 2325177050Syongari return; 2326177050Syongari } 2327177050Syongari 232841502Swpaul ifp->if_oerrors++; 2329151773Sjhb if_printf(ifp, "watchdog timeout\n"); 233041502Swpaul 2331211765Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2332131844Sbms vr_init_locked(sc); 2333131518Sbms 2334132986Smlaier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2335131844Sbms vr_start_locked(ifp); 2336177050Syongari} 2337131844Sbms 2338177050Syongaristatic void 2339177050Syongarivr_tx_start(struct vr_softc *sc) 2340177050Syongari{ 2341177050Syongari bus_addr_t addr; 2342177050Syongari uint8_t cmd; 2343177050Syongari 2344177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2345177050Syongari if ((cmd & VR_CR0_TX_ON) == 0) { 2346177050Syongari addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons); 2347177050Syongari CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2348177050Syongari cmd |= VR_CR0_TX_ON; 2349177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2350177050Syongari } 2351177050Syongari if (sc->vr_cdata.vr_tx_cnt != 0) { 2352177050Syongari sc->vr_watchdog_timer = 5; 2353177050Syongari VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 2354177050Syongari } 235541502Swpaul} 235641502Swpaul 2357177050Syongaristatic void 2358177050Syongarivr_rx_start(struct vr_softc *sc) 2359177050Syongari{ 2360177050Syongari bus_addr_t addr; 2361177050Syongari uint8_t cmd; 2362177050Syongari 2363177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2364177050Syongari if ((cmd & VR_CR0_RX_ON) == 0) { 2365177050Syongari addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons); 2366177050Syongari CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2367177050Syongari cmd |= VR_CR0_RX_ON; 2368177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2369177050Syongari } 2370177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO); 2371177050Syongari} 2372177050Syongari 2373177050Syongaristatic int 2374177050Syongarivr_tx_stop(struct vr_softc *sc) 2375177050Syongari{ 2376177050Syongari int i; 2377177050Syongari uint8_t cmd; 2378177050Syongari 2379177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2380177050Syongari if ((cmd & VR_CR0_TX_ON) != 0) { 2381177050Syongari cmd &= ~VR_CR0_TX_ON; 2382177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2383177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 2384177050Syongari DELAY(5); 2385177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2386177050Syongari if ((cmd & VR_CR0_TX_ON) == 0) 2387177050Syongari break; 2388177050Syongari } 2389177050Syongari if (i == 0) 2390177050Syongari return (ETIMEDOUT); 2391177050Syongari } 2392177050Syongari return (0); 2393177050Syongari} 2394177050Syongari 2395177050Syongaristatic int 2396177050Syongarivr_rx_stop(struct vr_softc *sc) 2397177050Syongari{ 2398177050Syongari int i; 2399177050Syongari uint8_t cmd; 2400177050Syongari 2401177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2402177050Syongari if ((cmd & VR_CR0_RX_ON) != 0) { 2403177050Syongari cmd &= ~VR_CR0_RX_ON; 2404177050Syongari CSR_WRITE_1(sc, VR_CR0, cmd); 2405177050Syongari for (i = VR_TIMEOUT; i > 0; i--) { 2406177050Syongari DELAY(5); 2407177050Syongari cmd = CSR_READ_1(sc, VR_CR0); 2408177050Syongari if ((cmd & VR_CR0_RX_ON) == 0) 2409177050Syongari break; 2410177050Syongari } 2411177050Syongari if (i == 0) 2412177050Syongari return (ETIMEDOUT); 2413177050Syongari } 2414177050Syongari return (0); 2415177050Syongari} 2416177050Syongari 241741502Swpaul/* 241841502Swpaul * Stop the adapter and free any mbufs allocated to the 241941502Swpaul * RX and TX lists. 242041502Swpaul */ 2421102336Salfredstatic void 2422131503Sbmsvr_stop(struct vr_softc *sc) 242341502Swpaul{ 2424177050Syongari struct vr_txdesc *txd; 2425177050Syongari struct vr_rxdesc *rxd; 2426177050Syongari struct ifnet *ifp; 2427177050Syongari int i; 242841502Swpaul 2429131518Sbms VR_LOCK_ASSERT(sc); 243067087Swpaul 2431147256Sbrooks ifp = sc->vr_ifp; 2432177050Syongari sc->vr_watchdog_timer = 0; 243341502Swpaul 2434151911Sjhb callout_stop(&sc->vr_stat_callout); 2435148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 243651432Swpaul 2437177050Syongari CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP); 2438177050Syongari if (vr_rx_stop(sc) != 0) 2439177050Syongari device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__); 2440177050Syongari if (vr_tx_stop(sc) != 0) 2441177050Syongari device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__); 2442177050Syongari /* Clear pending interrupts. */ 2443177050Syongari CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 244441502Swpaul CSR_WRITE_2(sc, VR_IMR, 0x0000); 244541502Swpaul CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 244641502Swpaul CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 244741502Swpaul 244841502Swpaul /* 2449177050Syongari * Free RX and TX mbufs still in the queues. 245041502Swpaul */ 2451177050Syongari for (i = 0; i < VR_RX_RING_CNT; i++) { 2452177050Syongari rxd = &sc->vr_cdata.vr_rxdesc[i]; 2453177050Syongari if (rxd->rx_m != NULL) { 2454177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, 2455177050Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2456177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, 2457177050Syongari rxd->rx_dmamap); 2458177050Syongari m_freem(rxd->rx_m); 2459177050Syongari rxd->rx_m = NULL; 2460177050Syongari } 2461177050Syongari } 2462177050Syongari for (i = 0; i < VR_TX_RING_CNT; i++) { 2463177050Syongari txd = &sc->vr_cdata.vr_txdesc[i]; 2464177050Syongari if (txd->tx_m != NULL) { 2465177050Syongari bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 2466177050Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2467177050Syongari bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 2468177050Syongari txd->tx_dmamap); 2469177050Syongari m_freem(txd->tx_m); 2470177050Syongari txd->tx_m = NULL; 2471177050Syongari } 2472177050Syongari } 247341502Swpaul} 247441502Swpaul 247541502Swpaul/* 247641502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 247741502Swpaul * get confused by errant DMAs when rebooting. 247841502Swpaul */ 2479173839Syongaristatic int 2480131503Sbmsvr_shutdown(device_t dev) 248141502Swpaul{ 248241502Swpaul 2483177050Syongari return (vr_suspend(dev)); 2484177050Syongari} 2485173839Syongari 2486177050Syongaristatic int 2487177050Syongarivr_suspend(device_t dev) 2488177050Syongari{ 2489177050Syongari struct vr_softc *sc; 2490177050Syongari 2491177050Syongari sc = device_get_softc(dev); 2492177050Syongari 2493177050Syongari VR_LOCK(sc); 2494177050Syongari vr_stop(sc); 2495177050Syongari vr_setwol(sc); 2496228084Syongari sc->vr_flags |= VR_F_SUSPENDED; 2497177050Syongari VR_UNLOCK(sc); 2498177050Syongari 2499173839Syongari return (0); 250041502Swpaul} 2501177050Syongari 2502177050Syongaristatic int 2503177050Syongarivr_resume(device_t dev) 2504177050Syongari{ 2505177050Syongari struct vr_softc *sc; 2506177050Syongari struct ifnet *ifp; 2507177050Syongari 2508177050Syongari sc = device_get_softc(dev); 2509177050Syongari 2510177050Syongari VR_LOCK(sc); 2511177050Syongari ifp = sc->vr_ifp; 2512177050Syongari vr_clrwol(sc); 2513177050Syongari vr_reset(sc); 2514177050Syongari if (ifp->if_flags & IFF_UP) 2515177050Syongari vr_init_locked(sc); 2516177050Syongari 2517228084Syongari sc->vr_flags &= ~VR_F_SUSPENDED; 2518177050Syongari VR_UNLOCK(sc); 2519177050Syongari 2520177050Syongari return (0); 2521177050Syongari} 2522177050Syongari 2523177050Syongaristatic void 2524177050Syongarivr_setwol(struct vr_softc *sc) 2525177050Syongari{ 2526177050Syongari struct ifnet *ifp; 2527177050Syongari int pmc; 2528177050Syongari uint16_t pmstat; 2529177050Syongari uint8_t v; 2530177050Syongari 2531177050Syongari VR_LOCK_ASSERT(sc); 2532177050Syongari 2533177050Syongari if (sc->vr_revid < REV_ID_VT6102_A || 2534219902Sjhb pci_find_cap(sc->vr_dev, PCIY_PMG, &pmc) != 0) 2535177050Syongari return; 2536177050Syongari 2537177050Syongari ifp = sc->vr_ifp; 2538177050Syongari 2539177050Syongari /* Clear WOL configuration. */ 2540177050Syongari CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2541177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2542177050Syongari CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2543177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2544177050Syongari if (sc->vr_revid > REV_ID_VT6105_B0) { 2545177050Syongari /* Newer Rhine III supports two additional patterns. */ 2546177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2547177050Syongari CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2548177050Syongari CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2549177050Syongari } 2550177050Syongari if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2551177050Syongari CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST); 2552177050Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2553177050Syongari CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC); 2554177050Syongari /* 2555177050Syongari * It seems that multicast wakeup frames require programming pattern 2556177050Syongari * registers and valid CRC as well as pattern mask for each pattern. 2557177050Syongari * While it's possible to setup such a pattern it would complicate 2558177050Syongari * WOL configuration so ignore multicast wakeup frames. 2559177050Syongari */ 2560177050Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2561177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2562177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2563177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB); 2564177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN); 2565177050Syongari } 2566177050Syongari 2567177050Syongari /* Put hardware into sleep. */ 2568177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2569177050Syongari v |= VR_STICKHW_DS0 | VR_STICKHW_DS1; 2570177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v); 2571177050Syongari 2572177050Syongari /* Request PME if WOL is requested. */ 2573177050Syongari pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2); 2574177050Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2575177050Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 2576177050Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2577177050Syongari pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2578177050Syongari} 2579177050Syongari 2580177050Syongaristatic void 2581177050Syongarivr_clrwol(struct vr_softc *sc) 2582177050Syongari{ 2583177050Syongari uint8_t v; 2584177050Syongari 2585177050Syongari VR_LOCK_ASSERT(sc); 2586177050Syongari 2587177050Syongari if (sc->vr_revid < REV_ID_VT6102_A) 2588177050Syongari return; 2589177050Syongari 2590177050Syongari /* Take hardware out of sleep. */ 2591177050Syongari v = CSR_READ_1(sc, VR_STICKHW); 2592177050Syongari v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB); 2593177050Syongari CSR_WRITE_1(sc, VR_STICKHW, v); 2594177050Syongari 2595177050Syongari /* Clear WOL configuration as WOL may interfere normal operation. */ 2596177050Syongari CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2597177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, 2598177050Syongari VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR); 2599177050Syongari CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2600177050Syongari CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2601177050Syongari if (sc->vr_revid > REV_ID_VT6105_B0) { 2602177050Syongari /* Newer Rhine III supports two additional patterns. */ 2603177050Syongari CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2604177050Syongari CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2605177050Syongari CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2606177050Syongari } 2607177050Syongari} 2608177050Syongari 2609177050Syongaristatic int 2610177050Syongarivr_sysctl_stats(SYSCTL_HANDLER_ARGS) 2611177050Syongari{ 2612177050Syongari struct vr_softc *sc; 2613177050Syongari struct vr_statistics *stat; 2614177050Syongari int error; 2615177050Syongari int result; 2616177050Syongari 2617177050Syongari result = -1; 2618177050Syongari error = sysctl_handle_int(oidp, &result, 0, req); 2619177050Syongari 2620177050Syongari if (error != 0 || req->newptr == NULL) 2621177050Syongari return (error); 2622177050Syongari 2623177050Syongari if (result == 1) { 2624177050Syongari sc = (struct vr_softc *)arg1; 2625177050Syongari stat = &sc->vr_stat; 2626177050Syongari 2627177050Syongari printf("%s statistics:\n", device_get_nameunit(sc->vr_dev)); 2628177050Syongari printf("Outbound good frames : %ju\n", 2629177050Syongari (uintmax_t)stat->tx_ok); 2630177050Syongari printf("Inbound good frames : %ju\n", 2631177050Syongari (uintmax_t)stat->rx_ok); 2632177050Syongari printf("Outbound errors : %u\n", stat->tx_errors); 2633177050Syongari printf("Inbound errors : %u\n", stat->rx_errors); 2634177050Syongari printf("Inbound no buffers : %u\n", stat->rx_no_buffers); 2635177050Syongari printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs); 2636177050Syongari printf("Inbound FIFO overflows : %d\n", 2637177050Syongari stat->rx_fifo_overflows); 2638177050Syongari printf("Inbound CRC errors : %u\n", stat->rx_crc_errors); 2639177050Syongari printf("Inbound frame alignment errors : %u\n", 2640177050Syongari stat->rx_alignment); 2641177050Syongari printf("Inbound giant frames : %u\n", stat->rx_giants); 2642177050Syongari printf("Inbound runt frames : %u\n", stat->rx_runts); 2643177050Syongari printf("Outbound aborted with excessive collisions : %u\n", 2644177050Syongari stat->tx_abort); 2645177050Syongari printf("Outbound collisions : %u\n", stat->tx_collisions); 2646177050Syongari printf("Outbound late collisions : %u\n", 2647177050Syongari stat->tx_late_collisions); 2648177050Syongari printf("Outbound underrun : %u\n", stat->tx_underrun); 2649177050Syongari printf("PCI bus errors : %u\n", stat->bus_errors); 2650177050Syongari printf("driver restarted due to Rx/Tx shutdown failure : %u\n", 2651177050Syongari stat->num_restart); 2652177050Syongari } 2653177050Syongari 2654177050Syongari return (error); 2655177050Syongari} 2656