if_vgevar.h revision 200541
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/vge/if_vgevar.h 200541 2009-12-14 20:49:50Z yongari $ 33 */ 34 35#define VGE_JUMBO_MTU 9000 36 37#define VGE_IFQ_MAXLEN 64 38 39#define VGE_TX_DESC_CNT 256 40#define VGE_RX_DESC_CNT 252 /* Must be a multiple of 4!! */ 41#define VGE_TX_RING_ALIGN 64 42#define VGE_RX_RING_ALIGN 64 43#define VGE_MAXTXSEGS 6 44#define VGE_RX_BUF_ALIGN sizeof(uint32_t) 45 46/* 47 * VIA Velocity allows 64bit DMA addressing but high 16bits 48 * of the DMA address should be the same for Tx/Rx buffers. 49 * Because this condition can't be guaranteed vge(4) limit 50 * DMA address space to 48bits. 51 */ 52#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 53#define VGE_BUF_DMA_MAXADDR BUS_SPACE_MAXADDR 54#else 55#define VGE_BUF_DMA_MAXADDR 0xFFFFFFFFFFFF 56#endif 57 58#define VGE_RX_LIST_SZ (VGE_RX_DESC_CNT * sizeof(struct vge_rx_desc)) 59#define VGE_TX_LIST_SZ (VGE_TX_DESC_CNT * sizeof(struct vge_tx_desc)) 60#define VGE_TX_DESC_INC(x) ((x) = ((x) + 1) % VGE_TX_DESC_CNT) 61#define VGE_TX_DESC_DEC(x) \ 62 ((x) = (((x) + VGE_TX_DESC_CNT - 1) % VGE_TX_DESC_CNT)) 63#define VGE_RX_DESC_INC(x) ((x) = ((x) + 1) % VGE_RX_DESC_CNT) 64#define VGE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 65#define VGE_ADDR_HI(y) ((uint64_t) (y) >> 32) 66#define VGE_BUFLEN(y) ((y) & 0x3FFF) 67#define VGE_RXBYTES(x) (((x) & VGE_RDSTS_BUFSIZ) >> 16) 68#define VGE_MIN_FRAMELEN 60 69 70#ifdef VGE_FIXUP_RX 71#define VGE_ETHER_ALIGN sizeof(uint32_t) 72#else 73#define VGE_ETHER_ALIGN 0 74#endif 75 76struct vge_type { 77 uint16_t vge_vid; 78 uint16_t vge_did; 79 char *vge_name; 80}; 81 82struct vge_txdesc { 83 struct mbuf *tx_m; 84 bus_dmamap_t tx_dmamap; 85 struct vge_tx_desc *tx_desc; 86 struct vge_txdesc *txd_prev; 87}; 88 89struct vge_rxdesc { 90 struct mbuf *rx_m; 91 bus_dmamap_t rx_dmamap; 92 struct vge_rx_desc *rx_desc; 93 struct vge_rxdesc *rxd_prev; 94}; 95 96struct vge_chain_data{ 97 bus_dma_tag_t vge_ring_tag; 98 bus_dma_tag_t vge_buffer_tag; 99 bus_dma_tag_t vge_tx_tag; 100 struct vge_txdesc vge_txdesc[VGE_TX_DESC_CNT]; 101 bus_dma_tag_t vge_rx_tag; 102 struct vge_rxdesc vge_rxdesc[VGE_RX_DESC_CNT]; 103 bus_dma_tag_t vge_tx_ring_tag; 104 bus_dmamap_t vge_tx_ring_map; 105 bus_dma_tag_t vge_rx_ring_tag; 106 bus_dmamap_t vge_rx_ring_map; 107 bus_dmamap_t vge_rx_sparemap; 108 109 int vge_tx_prodidx; 110 int vge_tx_considx; 111 int vge_tx_cnt; 112 int vge_rx_prodidx; 113 int vge_rx_commit; 114 115 struct mbuf *vge_head; 116 struct mbuf *vge_tail; 117}; 118 119#define VGE_CHAIN_RESET(_sc) \ 120do { \ 121 if ((_sc)->vge_cdata.vge_head != NULL) { \ 122 m_freem((_sc)->vge_cdata.vge_head); \ 123 (_sc)->vge_cdata.vge_head = NULL; \ 124 (_sc)->vge_cdata.vge_tail = NULL; \ 125 } \ 126} while (0); 127 128struct vge_ring_data { 129 struct vge_tx_desc *vge_tx_ring; 130 bus_addr_t vge_tx_ring_paddr; 131 struct vge_rx_desc *vge_rx_ring; 132 bus_addr_t vge_rx_ring_paddr; 133}; 134 135struct vge_softc { 136 struct ifnet *vge_ifp; /* interface info */ 137 device_t vge_dev; 138 struct resource *vge_res; 139 struct resource *vge_irq; 140 void *vge_intrhand; 141 device_t vge_miibus; 142 uint8_t vge_type; 143 int vge_if_flags; 144 int vge_phyaddr; 145 int vge_flags; 146#define VGE_FLAG_PCIE 0x0001 147#define VGE_FLAG_MSI 0x0002 148#define VGE_FLAG_LINK 0x8000 149 int vge_expcap; 150 int vge_camidx; 151 struct mtx vge_mtx; 152 struct callout vge_watchdog; 153 int vge_timer; 154 155 struct vge_chain_data vge_cdata; 156 struct vge_ring_data vge_rdata; 157 158 int suspended; /* 0 = normal 1 = suspended */ 159}; 160 161#define VGE_LOCK(_sc) mtx_lock(&(_sc)->vge_mtx) 162#define VGE_UNLOCK(_sc) mtx_unlock(&(_sc)->vge_mtx) 163#define VGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vge_mtx, MA_OWNED) 164 165/* 166 * register space access macros 167 */ 168#define CSR_WRITE_STREAM_4(sc, reg, val) \ 169 bus_write_stream_4(sc->vge_res, reg, val) 170#define CSR_WRITE_4(sc, reg, val) \ 171 bus_write_4(sc->vge_res, reg, val) 172#define CSR_WRITE_2(sc, reg, val) \ 173 bus_write_2(sc->vge_res, reg, val) 174#define CSR_WRITE_1(sc, reg, val) \ 175 bus_write_1(sc->vge_res, reg, val) 176 177#define CSR_READ_4(sc, reg) \ 178 bus_read_4(sc->vge_res, reg) 179#define CSR_READ_2(sc, reg) \ 180 bus_read_2(sc->vge_res, reg) 181#define CSR_READ_1(sc, reg) \ 182 bus_read_1(sc->vge_res, reg) 183 184#define CSR_SETBIT_1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 186#define CSR_SETBIT_2(sc, reg, x) \ 187 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 188#define CSR_SETBIT_4(sc, reg, x) \ 189 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 190 191#define CSR_CLRBIT_1(sc, reg, x) \ 192 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 193#define CSR_CLRBIT_2(sc, reg, x) \ 194 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 195#define CSR_CLRBIT_4(sc, reg, x) \ 196 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 197 198#define VGE_RXCHUNK 4 199#define VGE_TIMEOUT 10000 200 201