if_vgereg.h revision 200527
1168404Spjd/*- 2168404Spjd * Copyright (c) 2004 3168404Spjd * Bill Paul <wpaul@windriver.com>. All rights reserved. 4168404Spjd * 5168404Spjd * Redistribution and use in source and binary forms, with or without 6168404Spjd * modification, are permitted provided that the following conditions 7168404Spjd * are met: 8168404Spjd * 1. Redistributions of source code must retain the above copyright 9168404Spjd * notice, this list of conditions and the following disclaimer. 10168404Spjd * 2. Redistributions in binary form must reproduce the above copyright 11168404Spjd * notice, this list of conditions and the following disclaimer in the 12168404Spjd * documentation and/or other materials provided with the distribution. 13168404Spjd * 3. All advertising materials mentioning features or use of this software 14168404Spjd * must display the following acknowledgement: 15168404Spjd * This product includes software developed by Bill Paul. 16168404Spjd * 4. Neither the name of the author nor the names of any co-contributors 17168404Spjd * may be used to endorse or promote products derived from this software 18168404Spjd * without specific prior written permission. 19168404Spjd * 20168404Spjd * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21168404Spjd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22168404Spjd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23168404Spjd * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24168404Spjd * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25168404Spjd * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26168404Spjd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27168404Spjd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28168404Spjd * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29168404Spjd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30169303Spjd * THE POSSIBILITY OF SUCH DAMAGE. 31168404Spjd * 32168404Spjd * $FreeBSD: head/sys/dev/vge/if_vgereg.h 200527 2009-12-14 18:50:26Z yongari $ 33168404Spjd */ 34168404Spjd 35168404Spjd/* 36169303Spjd * Register definitions for the VIA VT6122 gigabit ethernet controller. 37168404Spjd * Definitions for the built-in copper PHY can be found in vgphy.h. 38168404Spjd * 39168404Spjd * The VT612x controllers have 256 bytes of register space. The 40168404Spjd * manual seems to imply that the registers should all be accessed 41168404Spjd * using 32-bit I/O cycles, but some of them are less than 32 bits 42168404Spjd * wide. Go figure. 43168404Spjd */ 44168404Spjd 45168404Spjd#ifndef _IF_VGEREG_H_ 46168404Spjd#define _IF_VGEREG_H_ 47168404Spjd 48168404Spjd#define VIA_VENDORID 0x1106 49168404Spjd#define VIA_DEVICEID_61XX 0x3119 50168404Spjd 51168404Spjd#define VGE_PAR0 0x00 /* physical address register */ 52168404Spjd#define VGE_PAR1 0x02 53168404Spjd#define VGE_PAR2 0x04 54168404Spjd#define VGE_RXCTL 0x06 /* RX control register */ 55168404Spjd#define VGE_TXCTL 0x07 /* TX control register */ 56168404Spjd#define VGE_CRS0 0x08 /* Global cmd register 0 (w to set) */ 57168404Spjd#define VGE_CRS1 0x09 /* Global cmd register 1 (w to set) */ 58168404Spjd#define VGE_CRS2 0x0A /* Global cmd register 2 (w to set) */ 59168404Spjd#define VGE_CRS3 0x0B /* Global cmd register 3 (w to set) */ 60168404Spjd#define VGE_CRC0 0x0C /* Global cmd register 0 (w to clr) */ 61168404Spjd#define VGE_CRC1 0x0D /* Global cmd register 1 (w to clr) */ 62168404Spjd#define VGE_CRC2 0x0E /* Global cmd register 2 (w to clr) */ 63168404Spjd#define VGE_CRC3 0x0F /* Global cmd register 3 (w to clr) */ 64168404Spjd#define VGE_MAR0 0x10 /* Mcast hash/CAM register 0 */ 65168404Spjd#define VGE_MAR1 0x14 /* Mcast hash/CAM register 1 */ 66168404Spjd#define VGE_CAM0 0x10 67168404Spjd#define VGE_CAM1 0x11 68168404Spjd#define VGE_CAM2 0x12 69168404Spjd#define VGE_CAM3 0x13 70168404Spjd#define VGE_CAM4 0x14 71168404Spjd#define VGE_CAM5 0x15 72168404Spjd#define VGE_CAM6 0x16 73168404Spjd#define VGE_CAM7 0x17 74168404Spjd#define VGE_TXDESC_HIADDR 0x18 /* Hi part of 64bit txdesc base addr */ 75168404Spjd#define VGE_DATABUF_HIADDR 0x1D /* Hi part of 64bit data buffer addr */ 76168404Spjd#define VGE_INTCTL0 0x20 /* interrupt control register */ 77168404Spjd#define VGE_RXSUPPTHR 0x20 78168404Spjd#define VGE_TXSUPPTHR 0x20 79168404Spjd#define VGE_INTHOLDOFF 0x20 80168404Spjd#define VGE_INTCTL1 0x21 /* interrupt control register */ 81168404Spjd#define VGE_TXHOSTERR 0x22 /* TX host error status */ 82168404Spjd#define VGE_RXHOSTERR 0x23 /* RX host error status */ 83168404Spjd#define VGE_ISR 0x24 /* Interrupt status register */ 84168404Spjd#define VGE_IMR 0x28 /* Interrupt mask register */ 85168404Spjd#define VGE_TXSTS_PORT 0x2C /* Transmit status port (???) */ 86168404Spjd#define VGE_TXQCSRS 0x30 /* TX queue ctl/status set */ 87168404Spjd#define VGE_RXQCSRS 0x32 /* RX queue ctl/status set */ 88169303Spjd#define VGE_TXQCSRC 0x34 /* TX queue ctl/status clear */ 89169303Spjd#define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */ 90169087Spjd#define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */ 91168404Spjd#define VGE_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */ 92168404Spjd#define VGE_RXQTIMER 0x3E /* RX queue timer pend register */ 93168404Spjd#define VGE_TXQTIMER 0x3F /* TX queue timer pend register */ 94168404Spjd#define VGE_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */ 95168404Spjd#define VGE_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */ 96169087Spjd#define VGE_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */ 97168404Spjd#define VGE_TXDESC_ADDR_LO3 0x4C /* TX desc3 base addr (lo 32 bits) */ 98168404Spjd#define VGE_RXDESCNUM 0x50 /* Size of RX desc ring */ 99185029Spjd#define VGE_TXDESCNUM 0x52 /* Size of TX desc ring */ 100185029Spjd#define VGE_TXDESC_CONSIDX0 0x54 /* Current TX descriptor index */ 101185029Spjd#define VGE_TXDESC_CONSIDX1 0x56 /* Current TX descriptor index */ 102168404Spjd#define VGE_TXDESC_CONSIDX2 0x58 /* Current TX descriptor index */ 103168404Spjd#define VGE_TXDESC_CONSIDX3 0x5A /* Current TX descriptor index */ 104168404Spjd#define VGE_TX_PAUSE_TIMER 0x5C /* TX pause frame timer */ 105168404Spjd#define VGE_RXDESC_RESIDUECNT 0x5E /* RX descriptor residue count */ 106168404Spjd#define VGE_FIFOTEST0 0x60 /* FIFO test register */ 107168404Spjd#define VGE_FIFOTEST1 0x64 /* FIFO test register */ 108168404Spjd#define VGE_CAMADDR 0x68 /* CAM address register */ 109168404Spjd#define VGE_CAMCTL 0x69 /* CAM control register */ 110168404Spjd#define VGE_GFTEST 0x6A 111168404Spjd#define VGE_FTSCMD 0x6B 112168404Spjd#define VGE_MIICFG 0x6C /* MII port config register */ 113168404Spjd#define VGE_MIISTS 0x6D /* MII port status register */ 114168404Spjd#define VGE_PHYSTS0 0x6E /* PHY status register */ 115169303Spjd#define VGE_PHYSTS1 0x6F /* PHY status register */ 116169303Spjd#define VGE_MIICMD 0x70 /* MII command register */ 117169303Spjd#define VGE_MIIADDR 0x71 /* MII address register */ 118169303Spjd#define VGE_MIIDATA 0x72 /* MII data register */ 119169303Spjd#define VGE_SSTIMER 0x74 /* single-shot timer */ 120168404Spjd#define VGE_PTIMER 0x76 /* periodic timer */ 121168404Spjd#define VGE_CHIPCFG0 0x78 /* chip config A */ 122168404Spjd#define VGE_CHIPCFG1 0x79 /* chip config B */ 123168404Spjd#define VGE_CHIPCFG2 0x7A /* chip config C */ 124168404Spjd#define VGE_CHIPCFG3 0x7B /* chip config D */ 125168404Spjd#define VGE_DMACFG0 0x7C /* DMA config 0 */ 126168404Spjd#define VGE_DMACFG1 0x7D /* DMA config 1 */ 127168404Spjd#define VGE_RXCFG 0x7E /* MAC RX config */ 128168404Spjd#define VGE_TXCFG 0x7F /* MAC TX config */ 129168404Spjd#define VGE_PWRMGMT 0x82 /* power management shadow register */ 130168404Spjd#define VGE_PWRSTAT 0x83 /* power state shadow register */ 131168404Spjd#define VGE_MIBCSR 0x84 /* MIB control/status register */ 132168404Spjd#define VGE_SWEEDATA 0x85 /* EEPROM software loaded data */ 133168404Spjd#define VGE_MIBDATA 0x88 /* MIB data register */ 134168404Spjd#define VGE_EEWRDAT 0x8C /* EEPROM embedded write */ 135168404Spjd#define VGE_EECSUM 0x92 /* EEPROM checksum */ 136168404Spjd#define VGE_EECSR 0x93 /* EEPROM control/status */ 137168404Spjd#define VGE_EERDDAT 0x94 /* EEPROM embedded read */ 138168404Spjd#define VGE_EEADDR 0x96 /* EEPROM address */ 139168404Spjd#define VGE_EECMD 0x97 /* EEPROM embedded command */ 140168404Spjd#define VGE_CHIPSTRAP 0x99 /* Chip jumper strapping status */ 141168404Spjd#define VGE_MEDIASTRAP 0x9B /* Media jumper strapping */ 142168404Spjd#define VGE_DIAGSTS 0x9C /* Chip diagnostic status */ 143168404Spjd#define VGE_DBGCTL 0x9E /* Chip debug control */ 144168404Spjd#define VGE_DIAGCTL 0x9F /* Chip diagnostic control */ 145168404Spjd#define VGE_WOLCR0S 0xA0 /* WOL0 event set */ 146168404Spjd#define VGE_WOLCR1S 0xA1 /* WOL1 event set */ 147168404Spjd#define VGE_PWRCFGS 0xA2 /* Power management config set */ 148168404Spjd#define VGE_WOLCFGS 0xA3 /* WOL config set */ 149168404Spjd#define VGE_WOLCR0C 0xA4 /* WOL0 event clear */ 150168404Spjd#define VGE_WOLCR1C 0xA5 /* WOL1 event clear */ 151168404Spjd#define VGE_PWRCFGC 0xA6 /* Power management config clear */ 152168404Spjd#define VGE_WOLCFGC 0xA7 /* WOL config clear */ 153168404Spjd#define VGE_WOLSR0S 0xA8 /* WOL status set */ 154168404Spjd#define VGE_WOLSR1S 0xA9 /* WOL status set */ 155168404Spjd#define VGE_WOLSR0C 0xAC /* WOL status clear */ 156168404Spjd#define VGE_WOLSR1C 0xAD /* WOL status clear */ 157168404Spjd#define VGE_WAKEPAT_CRC0 0xB0 158168404Spjd#define VGE_WAKEPAT_CRC1 0xB2 159168404Spjd#define VGE_WAKEPAT_CRC2 0xB4 160168404Spjd#define VGE_WAKEPAT_CRC3 0xB6 161168404Spjd#define VGE_WAKEPAT_CRC4 0xB8 162168404Spjd#define VGE_WAKEPAT_CRC5 0xBA 163168404Spjd#define VGE_WAKEPAT_CRC6 0xBC 164168404Spjd#define VGE_WAKEPAT_CRC7 0xBE 165168404Spjd#define VGE_WAKEPAT_MSK0_0 0xC0 166168404Spjd#define VGE_WAKEPAT_MSK0_1 0xC4 167168404Spjd#define VGE_WAKEPAT_MSK0_2 0xC8 168168404Spjd#define VGE_WAKEPAT_MSK0_3 0xCC 169168404Spjd#define VGE_WAKEPAT_MSK1_0 0xD0 170168404Spjd#define VGE_WAKEPAT_MSK1_1 0xD4 171168404Spjd#define VGE_WAKEPAT_MSK1_2 0xD8 172168404Spjd#define VGE_WAKEPAT_MSK1_3 0xDC 173168404Spjd#define VGE_WAKEPAT_MSK2_0 0xE0 174168404Spjd#define VGE_WAKEPAT_MSK2_1 0xE4 175168404Spjd#define VGE_WAKEPAT_MSK2_2 0xE8 176168404Spjd#define VGE_WAKEPAT_MSK2_3 0xEC 177168404Spjd#define VGE_WAKEPAT_MSK3_0 0xF0 178168404Spjd#define VGE_WAKEPAT_MSK3_1 0xF4 179168404Spjd#define VGE_WAKEPAT_MSK3_2 0xF8 180168404Spjd#define VGE_WAKEPAT_MSK3_3 0xFC 181168404Spjd 182168404Spjd/* Receive control register */ 183168404Spjd 184168404Spjd#define VGE_RXCTL_RX_BADFRAMES 0x01 /* accept CRC error frames */ 185168404Spjd#define VGE_RXCTL_RX_RUNT 0x02 /* accept runts */ 186168404Spjd#define VGE_RXCTL_RX_MCAST 0x04 /* accept multicasts */ 187168404Spjd#define VGE_RXCTL_RX_BCAST 0x08 /* accept broadcasts */ 188168404Spjd#define VGE_RXCTL_RX_PROMISC 0x10 /* promisc mode */ 189168404Spjd#define VGE_RXCTL_RX_GIANT 0x20 /* accept VLAN tagged frames */ 190168404Spjd#define VGE_RXCTL_RX_UCAST 0x40 /* use perfect filtering */ 191168404Spjd#define VGE_RXCTL_RX_SYMERR 0x80 /* accept symbol err packet */ 192168404Spjd 193168404Spjd/* Transmit control register */ 194168404Spjd 195168404Spjd#define VGE_TXCTL_LOOPCTL 0x03 /* loopback control */ 196168404Spjd#define VGE_TXCTL_COLLCTL 0x0C /* collision retry control */ 197168404Spjd 198168404Spjd#define VGE_TXLOOPCTL_OFF 0x00 199168404Spjd#define VGE_TXLOOPCTL_MAC_INTERNAL 0x01 200168404Spjd#define VGE_TXLOOPCTL_EXTERNAL 0x02 201168404Spjd 202168404Spjd#define VGE_TXCOLLS_NORMAL 0x00 /* one set of 16 retries */ 203168404Spjd#define VGE_TXCOLLS_32 0x04 /* two sets of 16 retries */ 204168404Spjd#define VGE_TXCOLLS_48 0x08 /* three sets of 16 retries */ 205168404Spjd#define VGE_TXCOLLS_INFINITE 0x0C /* retry forever */ 206172836Sjulian 207168404Spjd/* Global command register 0 */ 208168404Spjd 209168404Spjd#define VGE_CR0_START 0x01 /* start NIC */ 210168404Spjd#define VGE_CR0_STOP 0x02 /* stop NIC */ 211168404Spjd#define VGE_CR0_RX_ENABLE 0x04 /* turn on RX engine */ 212168404Spjd#define VGE_CR0_TX_ENABLE 0x08 /* turn on TX engine */ 213168404Spjd 214168404Spjd/* Global command register 1 */ 215168404Spjd 216168404Spjd#define VGE_CR1_NOUCAST 0x01 /* disable unicast reception */ 217168404Spjd#define VGE_CR1_NOPOLL 0x08 /* disable RX/TX desc polling */ 218168404Spjd#define VGE_CR1_TIMER0_ENABLE 0x20 /* enable single shot timer */ 219168404Spjd#define VGE_CR1_TIMER1_ENABLE 0x40 /* enable periodic timer */ 220168404Spjd#define VGE_CR1_SOFTRESET 0x80 /* software reset */ 221168404Spjd 222168404Spjd/* Global command register 2 */ 223168404Spjd 224168404Spjd#define VGE_CR2_TXPAUSE_THRESH_LO 0x03 /* TX pause frame lo threshold */ 225168404Spjd#define VGE_CR2_TXPAUSE_THRESH_HI 0x0C /* TX pause frame hi threshold */ 226168404Spjd#define VGE_CR2_HDX_FLOWCTL_ENABLE 0x10 /* half duplex flow control */ 227168404Spjd#define VGE_CR2_FDX_RXFLOWCTL_ENABLE 0x20 /* full duplex RX flow control */ 228185029Spjd#define VGE_CR2_FDX_TXFLOWCTL_ENABLE 0x40 /* full duplex TX flow control */ 229168404Spjd#define VGE_CR2_XON_ENABLE 0x80 /* 802.3x XON/XOFF flow control */ 230168404Spjd 231168404Spjd/* Global command register 3 */ 232169303Spjd 233169303Spjd#define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */ 234169303Spjd#define VGE_CR3_INT_GMSK 0x02 /* mask off all interrupts */ 235169303Spjd#define VGE_CR3_INT_HOLDOFF 0x04 /* enable int hold off timer */ 236169303Spjd#define VGE_CR3_DIAG 0x10 /* diagnostic enabled */ 237169303Spjd#define VGE_CR3_PHYRST 0x20 /* assert PHYRSTZ */ 238169303Spjd#define VGE_CR3_STOP_FORCE 0x40 /* force NIC to stopped state */ 239169303Spjd 240169303Spjd/* Interrupt control register */ 241169303Spjd 242169303Spjd#define VGE_INTCTL_SC_RELOAD 0x01 /* reload hold timer */ 243169303Spjd#define VGE_INTCTL_HC_RELOAD 0x02 /* enable hold timer reload */ 244169303Spjd#define VGE_INTCTL_STATUS 0x04 /* interrupt pending status */ 245169303Spjd#define VGE_INTCTL_MASK 0x18 /* multilayer int mask */ 246169303Spjd#define VGE_INTCTL_RXINTSUP_DISABLE 0x20 /* disable RX int supression */ 247169303Spjd#define VGE_INTCTL_TXINTSUP_DISABLE 0x40 /* disable TX int supression */ 248185029Spjd#define VGE_INTCTL_SOFTINT 0x80 /* request soft interrupt */ 249185029Spjd 250185029Spjd#define VGE_INTMASK_LAYER0 0x00 251185029Spjd#define VGE_INTMASK_LAYER1 0x08 252185029Spjd#define VGE_INTMASK_ALL 0x10 253185029Spjd#define VGE_INTMASK_ALL2 0x18 254185029Spjd 255185029Spjd/* Transmit host error status register */ 256185029Spjd 257185029Spjd#define VGE_TXHOSTERR_TDSTRUCT 0x01 /* bad TX desc structure */ 258185029Spjd#define VGE_TXHOSTERR_TDFETCH_BUSERR 0x02 /* bus error on desc fetch */ 259185029Spjd#define VGE_TXHOSTERR_TDWBACK_BUSERR 0x04 /* bus error on desc writeback */ 260185029Spjd#define VGE_TXHOSTERR_FIFOERR 0x08 /* TX FIFO DMA bus error */ 261185029Spjd 262185029Spjd/* Receive host error status register */ 263185029Spjd 264185029Spjd#define VGE_RXHOSTERR_RDSTRUCT 0x01 /* bad RX desc structure */ 265185029Spjd#define VGE_RXHOSTERR_RDFETCH_BUSERR 0x02 /* bus error on desc fetch */ 266185029Spjd#define VGE_RXHOSTERR_RDWBACK_BUSERR 0x04 /* bus error on desc writeback */ 267185029Spjd#define VGE_RXHOSTERR_FIFOERR 0x08 /* RX FIFO DMA bus error */ 268185029Spjd 269185029Spjd/* Interrupt status register */ 270185029Spjd 271185029Spjd#define VGE_ISR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ 272185029Spjd#define VGE_ISR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ 273185029Spjd#define VGE_ISR_RXOK 0x00000004 /* normal RX done */ 274185029Spjd#define VGE_ISR_TXOK 0x00000008 /* combo results for next 4 bits */ 275185029Spjd#define VGE_ISR_TXOK0 0x00000010 /* TX complete on queue 0 */ 276185029Spjd#define VGE_ISR_TXOK1 0x00000020 /* TX complete on queue 1 */ 277185029Spjd#define VGE_ISR_TXOK2 0x00000040 /* TX complete on queue 2 */ 278185029Spjd#define VGE_ISR_TXOK3 0x00000080 /* TX complete on queue 3 */ 279185029Spjd#define VGE_ISR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ 280185029Spjd#define VGE_ISR_RXPAUSE 0x00000800 /* pause frame RX'ed */ 281185029Spjd#define VGE_ISR_RXOFLOW 0x00001000 /* RX FIFO overflow */ 282185029Spjd#define VGE_ISR_RXNODESC 0x00002000 /* ran out of RX descriptors */ 283185029Spjd#define VGE_ISR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ 284185029Spjd#define VGE_ISR_LINKSTS 0x00008000 /* link status change */ 285185029Spjd#define VGE_ISR_TIMER0 0x00010000 /* one shot timer expired */ 286185029Spjd#define VGE_ISR_TIMER1 0x00020000 /* periodic timer expired */ 287185029Spjd#define VGE_ISR_PWR 0x00040000 /* wake up power event */ 288185029Spjd#define VGE_ISR_PHYINT 0x00080000 /* PHY interrupt */ 289185029Spjd#define VGE_ISR_STOPPED 0x00100000 /* software shutdown complete */ 290185029Spjd#define VGE_ISR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ 291185029Spjd#define VGE_ISR_SOFTINT 0x00400000 /* software interrupt */ 292185029Spjd#define VGE_ISR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ 293185029Spjd#define VGE_ISR_RXDMA_STALL 0x01000000 /* RX DMA stall */ 294185029Spjd#define VGE_ISR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ 295185029Spjd#define VGE_ISR_ISRC0 0x10000000 /* interrupt source indication */ 296185029Spjd#define VGE_ISR_ISRC1 0x20000000 /* interrupt source indication */ 297185029Spjd#define VGE_ISR_ISRC2 0x40000000 /* interrupt source indication */ 298185029Spjd#define VGE_ISR_ISRC3 0x80000000 /* interrupt source indication */ 299185029Spjd 300185029Spjd#define VGE_INTRS (VGE_ISR_TXOK0|VGE_ISR_RXOK|VGE_ISR_STOPPED| \ 301185029Spjd VGE_ISR_RXOFLOW|VGE_ISR_PHYINT| \ 302185029Spjd VGE_ISR_LINKSTS|VGE_ISR_RXNODESC| \ 303185029Spjd VGE_ISR_RXDMA_STALL|VGE_ISR_TXDMA_STALL| \ 304185029Spjd VGE_ISR_MIBOFLOW|VGE_ISR_TIMER0) 305185029Spjd 306185029Spjd/* Interrupt mask register */ 307185029Spjd 308185029Spjd#define VGE_IMR_RXOK_HIPRIO 0x00000001 /* hi prio RX int */ 309185029Spjd#define VGE_IMR_TXOK_HIPRIO 0x00000002 /* hi prio TX int */ 310185029Spjd#define VGE_IMR_RXOK 0x00000004 /* normal RX done */ 311185029Spjd#define VGE_IMR_TXOK 0x00000008 /* combo results for next 4 bits */ 312185029Spjd#define VGE_IMR_TXOK0 0x00000010 /* TX complete on queue 0 */ 313185029Spjd#define VGE_IMR_TXOK1 0x00000020 /* TX complete on queue 1 */ 314185029Spjd#define VGE_IMR_TXOK2 0x00000040 /* TX complete on queue 2 */ 315185029Spjd#define VGE_IMR_TXOK3 0x00000080 /* TX complete on queue 3 */ 316185029Spjd#define VGE_IMR_RXCNTOFLOW 0x00000400 /* RX packet count overflow */ 317185029Spjd#define VGE_IMR_RXPAUSE 0x00000800 /* pause frame RX'ed */ 318185029Spjd#define VGE_IMR_RXOFLOW 0x00001000 /* RX FIFO overflow */ 319185029Spjd#define VGE_IMR_RXNODESC 0x00002000 /* ran out of RX descriptors */ 320185029Spjd#define VGE_IMR_RXNODESC_WARN 0x00004000 /* running out of RX descs */ 321185029Spjd#define VGE_IMR_LINKSTS 0x00008000 /* link status change */ 322185029Spjd#define VGE_IMR_TIMER0 0x00010000 /* one shot timer expired */ 323185029Spjd#define VGE_IMR_TIMER1 0x00020000 /* periodic timer expired */ 324185029Spjd#define VGE_IMR_PWR 0x00040000 /* wake up power event */ 325185029Spjd#define VGE_IMR_PHYINT 0x00080000 /* PHY interrupt */ 326185029Spjd#define VGE_IMR_STOPPED 0x00100000 /* software shutdown complete */ 327185029Spjd#define VGE_IMR_MIBOFLOW 0x00200000 /* MIB counter overflow warning */ 328185029Spjd#define VGE_IMR_SOFTINT 0x00400000 /* software interrupt */ 329185029Spjd#define VGE_IMR_HOLDOFF_RELOAD 0x00800000 /* reload hold timer */ 330185029Spjd#define VGE_IMR_RXDMA_STALL 0x01000000 /* RX DMA stall */ 331185029Spjd#define VGE_IMR_TXDMA_STALL 0x02000000 /* TX DMA STALL */ 332185029Spjd#define VGE_IMR_ISRC0 0x10000000 /* interrupt source indication */ 333185029Spjd#define VGE_IMR_ISRC1 0x20000000 /* interrupt source indication */ 334185029Spjd#define VGE_IMR_ISRC2 0x40000000 /* interrupt source indication */ 335185029Spjd#define VGE_IMR_ISRC3 0x80000000 /* interrupt source indication */ 336185029Spjd 337185029Spjd/* TX descriptor queue control/status register */ 338185029Spjd 339185029Spjd#define VGE_TXQCSR_RUN0 0x0001 /* Enable TX queue 0 */ 340185029Spjd#define VGE_TXQCSR_ACT0 0x0002 /* queue 0 active indicator */ 341185029Spjd#define VGE_TXQCSR_WAK0 0x0004 /* Wake up (poll) queue 0 */ 342185029Spjd#define VGE_TXQCSR_DEAD0 0x0008 /* queue 0 dead indicator */ 343185029Spjd#define VGE_TXQCSR_RUN1 0x0010 /* Enable TX queue 1 */ 344185029Spjd#define VGE_TXQCSR_ACT1 0x0020 /* queue 1 active indicator */ 345185029Spjd#define VGE_TXQCSR_WAK1 0x0040 /* Wake up (poll) queue 1 */ 346185029Spjd#define VGE_TXQCSR_DEAD1 0x0080 /* queue 1 dead indicator */ 347185029Spjd#define VGE_TXQCSR_RUN2 0x0100 /* Enable TX queue 2 */ 348185029Spjd#define VGE_TXQCSR_ACT2 0x0200 /* queue 2 active indicator */ 349185029Spjd#define VGE_TXQCSR_WAK2 0x0400 /* Wake up (poll) queue 2 */ 350185029Spjd#define VGE_TXQCSR_DEAD2 0x0800 /* queue 2 dead indicator */ 351185029Spjd#define VGE_TXQCSR_RUN3 0x1000 /* Enable TX queue 3 */ 352185029Spjd#define VGE_TXQCSR_ACT3 0x2000 /* queue 3 active indicator */ 353185029Spjd#define VGE_TXQCSR_WAK3 0x4000 /* Wake up (poll) queue 3 */ 354185029Spjd#define VGE_TXQCSR_DEAD3 0x8000 /* queue 3 dead indicator */ 355185029Spjd 356185029Spjd/* RX descriptor queue control/status register */ 357185029Spjd 358185029Spjd#define VGE_RXQCSR_RUN 0x0001 /* Enable RX queue */ 359185029Spjd#define VGE_RXQCSR_ACT 0x0002 /* queue active indicator */ 360185029Spjd#define VGE_RXQCSR_WAK 0x0004 /* Wake up (poll) queue */ 361185029Spjd#define VGE_RXQCSR_DEAD 0x0008 /* queue dead indicator */ 362185029Spjd 363185029Spjd/* RX/TX queue empty interrupt delay timer register */ 364185029Spjd 365185029Spjd#define VGE_QTIMER_PENDCNT 0x3F 366185029Spjd#define VGE_QTIMER_RESOLUTION 0xC0 367185029Spjd 368185029Spjd#define VGE_QTIMER_RES_1US 0x00 369185029Spjd#define VGE_QTIMER_RES_4US 0x40 370185029Spjd#define VGE_QTIMER_RES_16US 0x80 371185029Spjd#define VGE_QTIMER_RES_64US 0xC0 372185029Spjd 373185029Spjd/* CAM address register */ 374185029Spjd 375185029Spjd#define VGE_CAMADDR_ADDR 0x3F /* CAM address to program */ 376185029Spjd#define VGE_CAMADDR_AVSEL 0x40 /* 0 = address cam, 1 = VLAN cam */ 377185029Spjd#define VGE_CAMADDR_ENABLE 0x80 /* enable CAM read/write */ 378185029Spjd 379185029Spjd#define VGE_CAM_MAXADDRS 64 380185029Spjd 381185029Spjd/* 382185029Spjd * CAM command register 383185029Spjd * Note that the page select bits in this register affect three 384185029Spjd * different things: 385185029Spjd * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the 386185029Spjd * page select bits control whether the MAR0/MAR1 registers affect 387185029Spjd * the multicast hash filter or the CAM table) 388185029Spjd * - The behavior of the interrupt holdoff timer register at offset 389185029Spjd * 0x20 (the page select bits allow you to set the interrupt 390185029Spjd * holdoff timer, the TX interrupt supression count or the 391185029Spjd * RX interrupt supression count) 392185029Spjd * - The behavior the WOL pattern programming registers at offset 393185029Spjd * 0xC0 (controls which pattern is set) 394185029Spjd */ 395185029Spjd 396185029Spjd 397185029Spjd#define VGE_CAMCTL_WRITE 0x04 /* CAM write command */ 398185029Spjd#define VGE_CAMCTL_READ 0x08 /* CAM read command */ 399185029Spjd#define VGE_CAMCTL_INTPKT_SIZ 0x10 /* select interesting pkt CAM size */ 400185029Spjd#define VGE_CAMCTL_INTPKT_ENB 0x20 /* enable interesting packet mode */ 401185029Spjd#define VGE_CAMCTL_PAGESEL 0xC0 /* page select */ 402185029Spjd 403185029Spjd#define VGE_PAGESEL_MAR 0x00 404185029Spjd#define VGE_PAGESEL_CAMMASK 0x40 405185029Spjd#define VGE_PAGESEL_CAMDATA 0x80 406185029Spjd 407185029Spjd#define VGE_PAGESEL_INTHLDOFF 0x00 408185029Spjd#define VGE_PAGESEL_TXSUPPTHR 0x40 409185029Spjd#define VGE_PAGESEL_RXSUPPTHR 0x80 410185029Spjd 411185029Spjd#define VGE_PAGESEL_WOLPAT0 0x00 412185029Spjd#define VGE_PAGESEL_WOLPAT1 0x40 413185029Spjd 414185029Spjd/* MII port config register */ 415185029Spjd 416185029Spjd#define VGE_MIICFG_PHYADDR 0x1F /* PHY address (internal PHY is 1) */ 417185029Spjd#define VGE_MIICFG_MDCSPEED 0x20 /* MDC accelerate x 4 */ 418185029Spjd#define VGE_MIICFG_POLLINT 0xC0 /* polling interval */ 419185029Spjd 420185029Spjd#define VGE_MIIPOLLINT_1024 0x00 421185029Spjd#define VGE_MIIPOLLINT_512 0x40 422185029Spjd#define VGE_MIIPOLLINT_128 0x80 423185029Spjd#define VGE_MIIPOLLINT_64 0xC0 424185029Spjd 425185029Spjd/* MII port status register */ 426185029Spjd 427185029Spjd#define VGE_MIISTS_IIDL 0x80 /* not at sofrware/timer poll cycle */ 428185029Spjd 429185029Spjd/* PHY status register */ 430185029Spjd 431185029Spjd#define VGE_PHYSTS_TXFLOWCAP 0x01 /* resolved TX flow control cap */ 432185029Spjd#define VGE_PHYSTS_RXFLOWCAP 0x02 /* resolved RX flow control cap */ 433185029Spjd#define VGE_PHYSTS_SPEED10 0x04 /* PHY in 10Mbps mode */ 434185029Spjd#define VGE_PHYSTS_SPEED1000 0x08 /* PHY in giga mode */ 435185029Spjd#define VGE_PHYSTS_FDX 0x10 /* PHY in full duplex mode */ 436169303Spjd#define VGE_PHYSTS_LINK 0x40 /* link status */ 437169303Spjd#define VGE_PHYSTS_RESETSTS 0x80 /* reset status */ 438169303Spjd 439169303Spjd/* MII management command register */ 440169303Spjd 441169303Spjd#define VGE_MIICMD_MDC 0x01 /* clock pin */ 442169303Spjd#define VGE_MIICMD_MDI 0x02 /* data in pin */ 443169303Spjd#define VGE_MIICMD_MDO 0x04 /* data out pin */ 444169303Spjd#define VGE_MIICMD_MOUT 0x08 /* data out pin enable */ 445169303Spjd#define VGE_MIICMD_MDP 0x10 /* enable direct programming mode */ 446169303Spjd#define VGE_MIICMD_WCMD 0x20 /* embedded mode write */ 447169303Spjd#define VGE_MIICMD_RCMD 0x40 /* embadded mode read */ 448169303Spjd#define VGE_MIICMD_MAUTO 0x80 /* enable autopolling */ 449169303Spjd 450169303Spjd/* MII address register */ 451169303Spjd 452169303Spjd#define VGE_MIIADDR_SWMPL 0x80 /* initiate priority resolution */ 453169303Spjd 454169303Spjd/* Chip config register A */ 455169303Spjd 456169303Spjd#define VGE_CHIPCFG0_PACPI 0x01 /* pre-ACPI wakeup function */ 457169303Spjd#define VGE_CHIPCFG0_ABSHDN 0x02 /* abnormal shutdown function */ 458169303Spjd#define VGE_CHIPCFG0_GPIO1PD 0x04 /* GPIO pin enable */ 459169303Spjd#define VGE_CHIPCFG0_SKIPTAG 0x08 /* omit 802.1p tag from CRC calc */ 460169303Spjd#define VGE_CHIPCFG0_PHLED 0x30 /* phy LED select */ 461169303Spjd 462169303Spjd/* Chip config register B */ 463169303Spjd/* Note: some of these bits are not documented in the manual! */ 464169303Spjd 465169303Spjd#define VGE_CHIPCFG1_BAKOPT 0x01 466169303Spjd#define VGE_CHIPCFG1_MBA 0x02 467169303Spjd#define VGE_CHIPCFG1_CAP 0x04 468169303Spjd#define VGE_CHIPCFG1_CRANDOM 0x08 469169303Spjd#define VGE_CHIPCFG1_OFSET 0x10 470169303Spjd#define VGE_CHIPCFG1_SLOTTIME 0x20 /* slot time 512/500 in giga mode */ 471169303Spjd#define VGE_CHIPCFG1_MIIOPT 0x40 472169303Spjd#define VGE_CHIPCFG1_GTCKOPT 0x80 473169303Spjd 474169303Spjd/* Chip config register C */ 475169303Spjd 476169303Spjd#define VGE_CHIPCFG2_EELOAD 0x80 /* enable EEPROM programming */ 477185029Spjd 478169303Spjd/* Chip config register D */ 479169303Spjd 480169303Spjd#define VGE_CHIPCFG3_64BIT_DAC 0x20 /* enable 64bit via DAC */ 481169303Spjd#define VGE_CHIPCFG3_IODISABLE 0x80 /* disable I/O access mode */ 482169303Spjd 483169303Spjd/* DMA config register 0 */ 484169303Spjd 485169303Spjd#define VGE_DMACFG0_BURSTLEN 0x07 /* RX/TX DMA burst (in dwords) */ 486169303Spjd 487169303Spjd#define VGE_DMABURST_8 0x00 488169303Spjd#define VGE_DMABURST_16 0x01 489169303Spjd#define VGE_DMABURST_32 0x02 490169303Spjd#define VGE_DMABURST_64 0x03 491169303Spjd#define VGE_DMABURST_128 0x04 492169303Spjd#define VGE_DMABURST_256 0x05 493169303Spjd#define VGE_DMABURST_STRFWD 0x07 494169303Spjd 495169303Spjd/* DMA config register 1 */ 496169303Spjd 497169303Spjd#define VGE_DMACFG1_LATENB 0x01 /* Latency timer enable */ 498169303Spjd#define VGE_DMACFG1_MWWAIT 0x02 /* insert wait on master write */ 499169303Spjd#define VGE_DMACFG1_MRWAIT 0x04 /* insert wait on master read */ 500169303Spjd#define VGE_DMACFG1_MRM 0x08 /* use memory read multiple */ 501169303Spjd#define VGE_DMACFG1_PERR_DIS 0x10 /* disable parity error checking */ 502169303Spjd#define VGE_DMACFG1_XMRL 0x20 /* disable memory read line support */ 503169303Spjd 504169303Spjd/* RX MAC config register */ 505169303Spjd 506169303Spjd#define VGE_RXCFG_VLANFILT 0x01 /* filter VLAN ID mismatches */ 507169303Spjd#define VGE_RXCFG_VTAGOPT 0x06 /* VLAN tag handling */ 508169303Spjd#define VGE_RXCFG_FIFO_LOWAT 0x08 /* RX FIFO low watermark (7QW/15QW) */ 509169303Spjd#define VGE_RXCFG_FIFO_THR 0x30 /* RX FIFO threshold */ 510169303Spjd#define VGE_RXCFG_ARB_PRIO 0x80 /* arbitration priority */ 511169303Spjd 512185029Spjd#define VGE_VTAG_OPT0 0x00 /* TX: no tag insertion 513185029Spjd RX: rx all, no tag extraction */ 514185029Spjd 515185029Spjd#define VGE_VTAG_OPT1 0x02 /* TX: no tag insertion 516185029Spjd RX: rx only tagged pkts, no 517185029Spjd extraction */ 518185029Spjd 519185029Spjd#define VGE_VTAG_OPT2 0x04 /* TX: perform tag insertion, 520185029Spjd RX: rx all, extract tags */ 521185029Spjd 522185029Spjd#define VGE_VTAG_OPT3 0x06 /* TX: perform tag insertion, 523185029Spjd RX: rx only tagged pkts, 524185029Spjd with extraction */ 525185029Spjd 526185029Spjd#define VGE_RXFIFOTHR_128BYTES 0x00 527185029Spjd#define VGE_RXFIFOTHR_512BYTES 0x10 528185029Spjd#define VGE_RXFIFOTHR_1024BYTES 0x20 529185029Spjd#define VGE_RXFIFOTHR_STRNFWD 0x30 530185029Spjd 531185029Spjd/* TX MAC config register */ 532185029Spjd 533185029Spjd#define VGE_TXCFG_SNAPOPT 0x01 /* 1 == insert VLAN tag at 534185029Spjd 13th byte 535185029Spjd 0 == insert VLANM tag after 536185029Spjd SNAP header (21st byte) */ 537185029Spjd#define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */ 538185029Spjd#define VGE_TXCFG_NONBLK_THR 0x0C /* non-blocking threshold */ 539185029Spjd#define VGE_TXCFG_ARB_PRIO 0x80 /* arbitration priority */ 540185029Spjd 541185029Spjd#define VGE_TXBLOCK_64PKTS 0x00 542185029Spjd#define VGE_TXBLOCK_32PKTS 0x04 543185029Spjd#define VGE_TXBLOCK_128PKTS 0x08 544185029Spjd#define VGE_TXBLOCK_8PKTS 0x0C 545185029Spjd 546185029Spjd/* EEPROM control/status register */ 547169303Spjd 548169303Spjd#define VGE_EECSR_EDO 0x01 /* data out pin */ 549169303Spjd#define VGE_EECSR_EDI 0x02 /* data in pin */ 550169303Spjd#define VGE_EECSR_ECK 0x04 /* clock pin */ 551169303Spjd#define VGE_EECSR_ECS 0x08 /* chip select pin */ 552169303Spjd#define VGE_EECSR_DPM 0x10 /* direct program mode enable */ 553169303Spjd#define VGE_EECSR_RELOAD 0x20 /* trigger reload from EEPROM */ 554169303Spjd#define VGE_EECSR_EMBP 0x40 /* embedded program mode enable */ 555169303Spjd 556169303Spjd/* EEPROM embedded command register */ 557169303Spjd 558169303Spjd#define VGE_EECMD_ERD 0x01 /* EEPROM read command */ 559169303Spjd#define VGE_EECMD_EWR 0x02 /* EEPROM write command */ 560169303Spjd#define VGE_EECMD_EWEN 0x04 /* EEPROM write enable */ 561169303Spjd#define VGE_EECMD_EWDIS 0x08 /* EEPROM write disable */ 562169303Spjd#define VGE_EECMD_EDONE 0x80 /* read/write done */ 563169303Spjd 564169303Spjd/* Chip operation and diagnostic control register */ 565169303Spjd 566169303Spjd#define VGE_DIAGCTL_PHYINT_ENB 0x01 /* Enable PHY interrupts */ 567169303Spjd#define VGE_DIAGCTL_TIMER0_RES 0x02 /* timer0 uSec resolution */ 568185029Spjd#define VGE_DIAGCTL_TIMER1_RES 0x04 /* timer1 uSec resolution */ 569185029Spjd#define VGE_DIAGCTL_LPSEL_DIS 0x08 /* disable LPSEL field */ 570168404Spjd#define VGE_DIAGCTL_MACFORCE 0x10 /* MAC side force mode */ 571168404Spjd#define VGE_DIAGCTL_FCRSVD 0x20 /* reserved for future fiber use */ 572168404Spjd#define VGE_DIAGCTL_FDXFORCE 0x40 /* force full duplex mode */ 573185029Spjd#define VGE_DIAGCTL_GMII 0x80 /* force GMII mode, otherwise MII */ 574168404Spjd 575169303Spjd/* Location of station address in EEPROM */ 576168404Spjd#define VGE_EE_EADDR 0 577168404Spjd 578169303Spjd/* DMA descriptor structures */ 579169303Spjd 580169303Spjd/* 581169303Spjd * Each TX DMA descriptor has a control and status word, and 7 582169303Spjd * fragment address/length words. If a transmitted packet spans 583169303Spjd * more than 7 fragments, it has to be coalesced. 584169303Spjd */ 585169303Spjd 586169303Spjd#define VGE_TX_FRAGS 7 587169303Spjd 588169303Spjdstruct vge_tx_frag { 589169303Spjd uint32_t vge_addrlo; 590169303Spjd uint32_t vge_addrhi; 591185029Spjd}; 592185029Spjd 593185029Spjd/* 594185029Spjd * The high bit in the buflen field of fragment #0 has special meaning. 595169303Spjd * Normally, the chip requires the driver to issue a TX poll command 596168404Spjd * for every packet that gets put in the TX DMA queue. Sometimes though, 597168404Spjd * the driver might want to queue up several packets at once and just 598169303Spjd * issue one transmit command to have all of them processed. In order 599185029Spjd * to obtain this behavior, the special 'queue' bit must be set. 600185029Spjd */ 601169303Spjd 602185029Spjd#define VGE_TXDESC_Q 0x80000000 603185029Spjd 604185029Spjdstruct vge_tx_desc { 605185029Spjd uint32_t vge_sts; 606185029Spjd uint32_t vge_ctl; 607185029Spjd struct vge_tx_frag vge_frag[VGE_TX_FRAGS]; 608185029Spjd}; 609185029Spjd 610185029Spjd#define VGE_TDSTS_COLLCNT 0x0000000F /* TX collision count */ 611185029Spjd#define VGE_TDSTS_COLL 0x00000010 /* collision seen */ 612185029Spjd#define VGE_TDSTS_OWINCOLL 0x00000020 /* out of window collision */ 613185029Spjd#define VGE_TDSTS_OWT 0x00000040 /* jumbo frame tx abort */ 614185029Spjd#define VGE_TDSTS_EXCESSCOLL 0x00000080 /* TX aborted, excess colls */ 615185029Spjd#define VGE_TDSTS_HBEATFAIL 0x00000100 /* heartbeat detect failed */ 616185029Spjd#define VGE_TDSTS_CARRLOSS 0x00000200 /* carrier sense lost */ 617185029Spjd#define VGE_TDSTS_SHUTDOWN 0x00000400 /* shutdown during TX */ 618185029Spjd#define VGE_TDSTS_LINKFAIL 0x00001000 /* link fail during TX */ 619185029Spjd#define VGE_TDSTS_GMII 0x00002000 /* GMII transmission */ 620185029Spjd#define VGE_TDSTS_FDX 0x00004000 /* full duplex transmit */ 621185029Spjd#define VGE_TDSTS_TXERR 0x00008000 /* error occurred */ 622185029Spjd#define VGE_TDSTS_SEGSIZE 0x3FFF0000 /* TCP large send size */ 623185029Spjd#define VGE_TDSTS_OWN 0x80000000 /* own bit */ 624185029Spjd 625185029Spjd#define VGE_TDCTL_VLANID 0x00000FFF /* VLAN ID */ 626185029Spjd#define VGE_TDCTL_CFI 0x00001000 /* VLAN CFI bit */ 627185029Spjd#define VGE_TDCTL_PRIO 0x0000E000 /* VLAN prio bits */ 628185029Spjd#define VGE_TDCTL_NOCRC 0x00010000 /* disable CRC generation */ 629185029Spjd#define VGE_TDCTL_JUMBO 0x00020000 /* jumbo frame */ 630185029Spjd#define VGE_TDCTL_TCPCSUM 0x00040000 /* do TCP hw checksum */ 631185029Spjd#define VGE_TDCTL_UDPCSUM 0x00080000 /* do UDP hw checksum */ 632185029Spjd#define VGE_TDCTL_IPCSUM 0x00100000 /* do IP hw checksum */ 633185029Spjd#define VGE_TDCTL_VTAG 0x00200000 /* insert VLAN tag */ 634185029Spjd#define VGE_TDCTL_PRIO_INT 0x00400000 /* priority int request */ 635185029Spjd#define VGE_TDCTL_TIC 0x00800000 /* transfer int request */ 636185029Spjd#define VGE_TDCTL_TCPLSCTL 0x03000000 /* TCP large send ctl */ 637185029Spjd#define VGE_TDCTL_FRAGCNT 0xF0000000 /* number of frags used */ 638185029Spjd 639185029Spjd#define VGE_TD_LS_MOF 0x00000000 /* middle of large send */ 640185029Spjd#define VGE_TD_LS_SOF 0x01000000 /* start of large send */ 641185029Spjd#define VGE_TD_LS_EOF 0x02000000 /* end of large send */ 642185029Spjd#define VGE_TD_LS_NORM 0x03000000 /* normal frame */ 643185029Spjd 644185029Spjd/* Receive DMA descriptors have a single fragment pointer. */ 645185029Spjd 646185029Spjdstruct vge_rx_desc { 647185029Spjd uint32_t vge_sts; 648185029Spjd uint32_t vge_ctl; 649185029Spjd uint32_t vge_addrlo; 650185029Spjd uint32_t vge_addrhi; 651185029Spjd}; 652185029Spjd 653185029Spjd/* 654185029Spjd * Like the TX descriptor, the high bit in the buflen field in the 655185029Spjd * RX descriptor has special meaning. This bit controls whether or 656185029Spjd * not interrupts are generated for this descriptor. 657185029Spjd */ 658185029Spjd 659185029Spjd#define VGE_RXDESC_I 0x80000000 660185029Spjd 661185029Spjd#define VGE_RDSTS_VIDM 0x00000001 /* VLAN tag filter miss */ 662185029Spjd#define VGE_RDSTS_CRCERR 0x00000002 /* bad CRC error */ 663185029Spjd#define VGE_RDSTS_FAERR 0x00000004 /* frame alignment error */ 664185029Spjd#define VGE_RDSTS_CSUMERR 0x00000008 /* bad TCP/IP checksum */ 665185029Spjd#define VGE_RDSTS_RLERR 0x00000010 /* RX length error */ 666185029Spjd#define VGE_RDSTS_SYMERR 0x00000020 /* PCS symbol error */ 667169303Spjd#define VGE_RDSTS_SNTAG 0x00000040 /* RX'ed tagged SNAP pkt */ 668169303Spjd#define VGE_RDSTS_DETAG 0x00000080 /* VLAN tag extracted */ 669168404Spjd#define VGE_RDSTS_BOUNDARY 0x00000300 /* frame boundary bits */ 670168404Spjd#define VGE_RDSTS_VTAG 0x00000400 /* VLAN tag indicator */ 671185029Spjd#define VGE_RDSTS_UCAST 0x00000800 /* unicast frame */ 672185029Spjd#define VGE_RDSTS_BCAST 0x00001000 /* broadcast frame */ 673185029Spjd#define VGE_RDSTS_MCAST 0x00002000 /* multicast frame */ 674185029Spjd#define VGE_RDSTS_PFT 0x00004000 /* perfect filter hit */ 675185029Spjd#define VGE_RDSTS_RXOK 0x00008000 /* frame is good. */ 676185029Spjd#define VGE_RDSTS_BUFSIZ 0x3FFF0000 /* received frame len */ 677185029Spjd#define VGE_RDSTS_SHUTDOWN 0x40000000 /* shutdown during RX */ 678185029Spjd#define VGE_RDSTS_OWN 0x80000000 /* own bit. */ 679185029Spjd 680185029Spjd#define VGE_RXPKT_ONEFRAG 0x00000000 /* only one fragment */ 681169303Spjd#define VGE_RXPKT_EOF 0x00000100 /* first frag in frame */ 682168404Spjd#define VGE_RXPKT_SOF 0x00000200 /* last frag in frame */ 683185029Spjd#define VGE_RXPKT_MOF 0x00000300 /* intermediate frag */ 684185029Spjd 685185029Spjd#define VGE_RDCTL_VLANID 0x0000FFFF /* VLAN ID info */ 686168404Spjd#define VGE_RDCTL_UDPPKT 0x00010000 /* UDP packet received */ 687168404Spjd#define VGE_RDCTL_TCPPKT 0x00020000 /* TCP packet received */ 688168404Spjd#define VGE_RDCTL_IPPKT 0x00040000 /* IP packet received */ 689168404Spjd#define VGE_RDCTL_UDPZERO 0x00080000 /* pkt with UDP CSUM of 0 */ 690168404Spjd#define VGE_RDCTL_FRAG 0x00100000 /* received IP frag */ 691168404Spjd#define VGE_RDCTL_PROTOCSUMOK 0x00200000 /* TCP/UDP checksum ok */ 692168404Spjd#define VGE_RDCTL_IPCSUMOK 0x00400000 /* IP checksum ok */ 693168404Spjd#define VGE_RDCTL_FILTIDX 0x3C000000 /* interesting filter idx */ 694168404Spjd 695168404Spjd#endif /* _IF_VGEREG_H_ */ 696168404Spjd