1239275Sgonzo/*- 2239275Sgonzo * Copyright (c) 2012 3239275Sgonzo * Ben Gray <bgray@freebsd.org>. 4239275Sgonzo * All rights reserved. 5239275Sgonzo * 6239275Sgonzo * Redistribution and use in source and binary forms, with or without 7239275Sgonzo * modification, are permitted provided that the following conditions 8239275Sgonzo * are met: 9239275Sgonzo * 1. Redistributions of source code must retain the above copyright 10239275Sgonzo * notice, this list of conditions and the following disclaimer. 11239275Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12239275Sgonzo * notice, this list of conditions and the following disclaimer in the 13239275Sgonzo * documentation and/or other materials provided with the distribution. 14239275Sgonzo * 15239275Sgonzo * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16239275Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17239275Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18239275Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19239275Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20239275Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21239275Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22239275Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23239275Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24239275Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25239275Sgonzo * SUCH DAMAGE. 26239275Sgonzo * 27239275Sgonzo * $FreeBSD$ 28239275Sgonzo */ 29239275Sgonzo#ifndef _IF_SMSCREG_H_ 30239275Sgonzo#define _IF_SMSCREG_H_ 31239275Sgonzo 32239275Sgonzo/* 33239275Sgonzo * Definitions for the SMSC LAN9514 and LAN9514 USB to ethernet controllers. 34239275Sgonzo * 35239275Sgonzo * This information was gleaned from the SMSC driver in the linux kernel, where 36239275Sgonzo * it is Copyrighted (C) 2007-2008 SMSC. 37239275Sgonzo * 38239275Sgonzo */ 39239275Sgonzo 40239275Sgonzo/** 41239275Sgonzo * TRANSMIT FRAMES 42239275Sgonzo * --------------- 43239275Sgonzo * Tx frames are prefixed with an 8-byte header which describes the frame 44239275Sgonzo * 45239275Sgonzo * 4 bytes 4 bytes variable 46239275Sgonzo * +------------+------------+--- . . . . . . . . . . . . ---+ 47239275Sgonzo * | TX_CTRL_0 | TX_CTRL_1 | Ethernet frame data | 48239275Sgonzo * +------------+------------+--- . . . . . . . . . . . . ---+ 49239275Sgonzo * 50239275Sgonzo * Where the headers have the following fields: 51239275Sgonzo * 52239275Sgonzo * TX_CTRL_0 <20:16> Data offset 53239275Sgonzo * TX_CTRL_0 <13> First segment of frame indicator 54239275Sgonzo * TX_CTRL_0 <12> Last segment of frame indicator 55239275Sgonzo * TX_CTRL_0 <10:0> Buffer size (?) 56239275Sgonzo * 57239275Sgonzo * TX_CTRL_1 <14> Perform H/W checksuming on IP packets 58239275Sgonzo * TX_CTRL_1 <13> Disable automatic ethernet CRC generation 59239275Sgonzo * TX_CTRL_1 <12> Disable padding (?) 60239275Sgonzo * TX_CTRL_1 <10:0> Packet byte length 61239275Sgonzo * 62239275Sgonzo */ 63239275Sgonzo#define SMSC_TX_CTRL_0_OFFSET(x) (((x) & 0x1FUL) << 16) 64239275Sgonzo#define SMSC_TX_CTRL_0_FIRST_SEG (0x1UL << 13) 65239275Sgonzo#define SMSC_TX_CTRL_0_LAST_SEG (0x1UL << 12) 66239275Sgonzo#define SMSC_TX_CTRL_0_BUF_SIZE(x) ((x) & 0x000007FFUL) 67239275Sgonzo 68239275Sgonzo#define SMSC_TX_CTRL_1_CSUM_ENABLE (0x1UL << 14) 69239275Sgonzo#define SMSC_TX_CTRL_1_CRC_DISABLE (0x1UL << 13) 70239275Sgonzo#define SMSC_TX_CTRL_1_PADDING_DISABLE (0x1UL << 12) 71239275Sgonzo#define SMSC_TX_CTRL_1_PKT_LENGTH(x) ((x) & 0x000007FFUL) 72239275Sgonzo 73239275Sgonzo/** 74239275Sgonzo * RECEIVE FRAMES 75239275Sgonzo * -------------- 76239275Sgonzo * Rx frames are prefixed with an 4-byte status header which describes any 77239275Sgonzo * errors with the frame as well as things like the length 78239275Sgonzo * 79239275Sgonzo * 4 bytes variable 80239275Sgonzo * +------------+--- . . . . . . . . . . . . ---+ 81239275Sgonzo * | RX_STAT | Ethernet frame data | 82239275Sgonzo * +------------+--- . . . . . . . . . . . . ---+ 83239275Sgonzo * 84239275Sgonzo * Where the status header has the following fields: 85239275Sgonzo * 86239275Sgonzo * RX_STAT <30> Filter Fail 87239275Sgonzo * RX_STAT <29:16> Frame Length 88239275Sgonzo * RX_STAT <15> Error Summary 89239275Sgonzo * RX_STAT <13> Broadcast Frame 90239275Sgonzo * RX_STAT <12> Length Error 91239275Sgonzo * RX_STAT <11> Runt Frame 92239275Sgonzo * RX_STAT <10> Multicast Frame 93239275Sgonzo * RX_STAT <7> Frame too long 94239275Sgonzo * RX_STAT <6> Collision Seen 95239275Sgonzo * RX_STAT <5> Frame Type 96239275Sgonzo * RX_STAT <4> Receive Watchdog 97239275Sgonzo * RX_STAT <3> Mii Error 98239275Sgonzo * RX_STAT <2> Dribbling 99239275Sgonzo * RX_STAT <1> CRC Error 100239275Sgonzo * 101239275Sgonzo */ 102239275Sgonzo#define SMSC_RX_STAT_FILTER_FAIL (0x1UL << 30) 103239275Sgonzo#define SMSC_RX_STAT_FRM_LENGTH(x) (((x) >> 16) & 0x3FFFUL) 104239275Sgonzo#define SMSC_RX_STAT_ERROR (0x1UL << 15) 105239275Sgonzo#define SMSC_RX_STAT_BROADCAST (0x1UL << 13) 106239275Sgonzo#define SMSC_RX_STAT_LENGTH_ERROR (0x1UL << 12) 107239275Sgonzo#define SMSC_RX_STAT_RUNT (0x1UL << 11) 108239275Sgonzo#define SMSC_RX_STAT_MULTICAST (0x1UL << 10) 109239275Sgonzo#define SMSC_RX_STAT_FRM_TO_LONG (0x1UL << 7) 110239275Sgonzo#define SMSC_RX_STAT_COLLISION (0x1UL << 6) 111239275Sgonzo#define SMSC_RX_STAT_FRM_TYPE (0x1UL << 5) 112239275Sgonzo#define SMSC_RX_STAT_WATCHDOG (0x1UL << 4) 113239275Sgonzo#define SMSC_RX_STAT_MII_ERROR (0x1UL << 3) 114239275Sgonzo#define SMSC_RX_STAT_DRIBBLING (0x1UL << 2) 115239275Sgonzo#define SMSC_RX_STAT_CRC_ERROR (0x1UL << 1) 116239275Sgonzo 117239275Sgonzo/** 118239275Sgonzo * REGISTERS 119239275Sgonzo * 120239275Sgonzo */ 121239275Sgonzo#define SMSC_ID_REV 0x000 122239275Sgonzo#define SMSC_INTR_STATUS 0x008 123239275Sgonzo#define SMSC_RX_CFG 0x00C 124239275Sgonzo#define SMSC_TX_CFG 0x010 125239275Sgonzo#define SMSC_HW_CFG 0x014 126239275Sgonzo#define SMSC_PM_CTRL 0x020 127239275Sgonzo#define SMSC_LED_GPIO_CFG 0x024 128239275Sgonzo#define SMSC_GPIO_CFG 0x028 129239275Sgonzo#define SMSC_AFC_CFG 0x02C 130239275Sgonzo#define SMSC_EEPROM_CMD 0x030 131239275Sgonzo#define SMSC_EEPROM_DATA 0x034 132239275Sgonzo#define SMSC_BURST_CAP 0x038 133239275Sgonzo#define SMSC_GPIO_WAKE 0x064 134239275Sgonzo#define SMSC_INTR_CFG 0x068 135239275Sgonzo#define SMSC_BULK_IN_DLY 0x06C 136239275Sgonzo#define SMSC_MAC_CSR 0x100 137239275Sgonzo#define SMSC_MAC_ADDRH 0x104 138239275Sgonzo#define SMSC_MAC_ADDRL 0x108 139239275Sgonzo#define SMSC_HASHH 0x10C 140239275Sgonzo#define SMSC_HASHL 0x110 141239275Sgonzo#define SMSC_MII_ADDR 0x114 142239275Sgonzo#define SMSC_MII_DATA 0x118 143239275Sgonzo#define SMSC_FLOW 0x11C 144239275Sgonzo#define SMSC_VLAN1 0x120 145239275Sgonzo#define SMSC_VLAN2 0x124 146239275Sgonzo#define SMSC_WUFF 0x128 147239275Sgonzo#define SMSC_WUCSR 0x12C 148239275Sgonzo#define SMSC_COE_CTRL 0x130 149239275Sgonzo 150239275Sgonzo/* ID / Revision register */ 151239275Sgonzo#define SMSC_ID_REV_CHIP_ID_MASK 0xFFFF0000UL 152239275Sgonzo#define SMSC_ID_REV_CHIP_REV_MASK 0x0000FFFFUL 153239275Sgonzo 154239275Sgonzo#define SMSC_RX_FIFO_FLUSH (0x1UL << 0) 155239275Sgonzo 156239275Sgonzo#define SMSC_TX_CFG_ON (0x1UL << 2) 157239275Sgonzo#define SMSC_TX_CFG_STOP (0x1UL << 1) 158239275Sgonzo#define SMSC_TX_CFG_FIFO_FLUSH (0x1UL << 0) 159239275Sgonzo 160239275Sgonzo#define SMSC_HW_CFG_BIR (0x1UL << 12) 161239275Sgonzo#define SMSC_HW_CFG_LEDB (0x1UL << 11) 162239275Sgonzo#define SMSC_HW_CFG_RXDOFF (0x3UL << 9) /* RX pkt alignment */ 163239275Sgonzo#define SMSC_HW_CFG_DRP (0x1UL << 6) 164239275Sgonzo#define SMSC_HW_CFG_MEF (0x1UL << 5) 165239275Sgonzo#define SMSC_HW_CFG_LRST (0x1UL << 3) /* Lite reset */ 166239275Sgonzo#define SMSC_HW_CFG_PSEL (0x1UL << 2) 167239275Sgonzo#define SMSC_HW_CFG_BCE (0x1UL << 1) 168239275Sgonzo#define SMSC_HW_CFG_SRST (0x1UL << 0) 169239275Sgonzo 170239275Sgonzo#define SMSC_PM_CTRL_PHY_RST (0x1UL << 4) /* PHY reset */ 171239275Sgonzo 172239275Sgonzo#define SMSC_LED_GPIO_CFG_SPD_LED (0x1UL << 24) 173239275Sgonzo#define SMSC_LED_GPIO_CFG_LNK_LED (0x1UL << 20) 174239275Sgonzo#define SMSC_LED_GPIO_CFG_FDX_LED (0x1UL << 16) 175239275Sgonzo 176239275Sgonzo/* Hi watermark = 15.5Kb (~10 mtu pkts) */ 177239275Sgonzo/* low watermark = 3k (~2 mtu pkts) */ 178239275Sgonzo/* backpressure duration = ~ 350us */ 179239275Sgonzo/* Apply FC on any frame. */ 180239275Sgonzo#define AFC_CFG_DEFAULT (0x00F830A1) 181239275Sgonzo 182239275Sgonzo#define SMSC_EEPROM_CMD_BUSY (0x1UL << 31) 183239275Sgonzo#define SMSC_EEPROM_CMD_MASK (0x7UL << 28) 184239275Sgonzo#define SMSC_EEPROM_CMD_READ (0x0UL << 28) 185239275Sgonzo#define SMSC_EEPROM_CMD_WRITE (0x3UL << 28) 186239275Sgonzo#define SMSC_EEPROM_CMD_ERASE (0x5UL << 28) 187239275Sgonzo#define SMSC_EEPROM_CMD_RELOAD (0x7UL << 28) 188239275Sgonzo#define SMSC_EEPROM_CMD_TIMEOUT (0x1UL << 10) 189239275Sgonzo#define SMSC_EEPROM_CMD_ADDR_MASK 0x000001FFUL 190239275Sgonzo 191239275Sgonzo/* MAC Control and Status Register */ 192239275Sgonzo#define SMSC_MAC_CSR_RCVOWN (0x1UL << 23) /* Half duplex */ 193239275Sgonzo#define SMSC_MAC_CSR_LOOPBK (0x1UL << 21) /* Loopback */ 194239275Sgonzo#define SMSC_MAC_CSR_FDPX (0x1UL << 20) /* Full duplex */ 195239275Sgonzo#define SMSC_MAC_CSR_MCPAS (0x1UL << 19) /* Multicast mode */ 196239275Sgonzo#define SMSC_MAC_CSR_PRMS (0x1UL << 18) /* Promiscuous mode */ 197239275Sgonzo#define SMSC_MAC_CSR_INVFILT (0x1UL << 17) /* Inverse filtering */ 198239275Sgonzo#define SMSC_MAC_CSR_PASSBAD (0x1UL << 16) /* Pass on bad frames */ 199239275Sgonzo#define SMSC_MAC_CSR_HPFILT (0x1UL << 13) /* Hash filtering */ 200239275Sgonzo#define SMSC_MAC_CSR_BCAST (0x1UL << 11) /* Broadcast */ 201239275Sgonzo#define SMSC_MAC_CSR_TXEN (0x1UL << 3) /* TX enable */ 202239275Sgonzo#define SMSC_MAC_CSR_RXEN (0x1UL << 2) /* RX enable */ 203239275Sgonzo 204239275Sgonzo/* Interrupt control register */ 205239275Sgonzo#define SMSC_INTR_NTEP (0x1UL << 31) 206239275Sgonzo#define SMSC_INTR_MACRTO (0x1UL << 19) 207239275Sgonzo#define SMSC_INTR_TX_STOP (0x1UL << 17) 208239275Sgonzo#define SMSC_INTR_RX_STOP (0x1UL << 16) 209239275Sgonzo#define SMSC_INTR_PHY_INT (0x1UL << 15) 210239275Sgonzo#define SMSC_INTR_TXE (0x1UL << 14) 211239275Sgonzo#define SMSC_INTR_TDFU (0x1UL << 13) 212239275Sgonzo#define SMSC_INTR_TDFO (0x1UL << 12) 213239275Sgonzo#define SMSC_INTR_RXDF (0x1UL << 11) 214239275Sgonzo#define SMSC_INTR_GPIOS 0x000007FFUL 215239275Sgonzo 216239275Sgonzo/* Phy MII interface register */ 217239275Sgonzo#define SMSC_MII_WRITE (0x1UL << 1) 218239275Sgonzo#define SMSC_MII_READ (0x0UL << 1) 219239275Sgonzo#define SMSC_MII_BUSY (0x1UL << 0) 220239275Sgonzo 221239275Sgonzo/* H/W checksum register */ 222239275Sgonzo#define SMSC_COE_CTRL_TX_EN (0x1UL << 16) /* Tx H/W csum enable */ 223239275Sgonzo#define SMSC_COE_CTRL_RX_MODE (0x1UL << 1) 224239275Sgonzo#define SMSC_COE_CTRL_RX_EN (0x1UL << 0) /* Rx H/W csum enable */ 225239275Sgonzo 226239275Sgonzo/* Registers on the phy, accessed via MII/MDIO */ 227239275Sgonzo#define SMSC_PHY_INTR_STAT (29) 228239275Sgonzo#define SMSC_PHY_INTR_MASK (30) 229239275Sgonzo 230239275Sgonzo#define SMSC_PHY_INTR_ENERGY_ON (0x1U << 7) 231239275Sgonzo#define SMSC_PHY_INTR_ANEG_COMP (0x1U << 6) 232239275Sgonzo#define SMSC_PHY_INTR_REMOTE_FAULT (0x1U << 5) 233239275Sgonzo#define SMSC_PHY_INTR_LINK_DOWN (0x1U << 4) 234239275Sgonzo 235239275Sgonzo/* USB Vendor Requests */ 236239275Sgonzo#define SMSC_UR_WRITE_REG 0xA0 237239275Sgonzo#define SMSC_UR_READ_REG 0xA1 238239275Sgonzo#define SMSC_UR_GET_STATS 0xA2 239239275Sgonzo 240239275Sgonzo#define SMSC_CONFIG_INDEX 0 /* config number 1 */ 241239275Sgonzo#define SMSC_IFACE_IDX 0 242239275Sgonzo 243239275Sgonzo/* 244239275Sgonzo * USB endpoints. 245239275Sgonzo */ 246239275Sgonzoenum { 247239275Sgonzo SMSC_BULK_DT_RD, 248239275Sgonzo SMSC_BULK_DT_WR, 249239275Sgonzo /* the LAN9514 device does support interrupt endpoints, however I couldn't 250239275Sgonzo * get then to work reliably and since they are unneeded (poll the mii 251239275Sgonzo * status) they are unused. 252239275Sgonzo * SMSC_INTR_DT_WR, 253239275Sgonzo * SMSC_INTR_DT_RD, 254239275Sgonzo */ 255239275Sgonzo SMSC_N_TRANSFER, 256239275Sgonzo}; 257239275Sgonzo 258239275Sgonzostruct smsc_softc { 259239275Sgonzo struct usb_ether sc_ue; 260239275Sgonzo struct mtx sc_mtx; 261239275Sgonzo struct usb_xfer *sc_xfer[SMSC_N_TRANSFER]; 262239275Sgonzo int sc_phyno; 263239275Sgonzo 264239275Sgonzo /* The following stores the settings in the mac control (MAC_CSR) register */ 265239275Sgonzo uint32_t sc_mac_csr; 266239275Sgonzo uint32_t sc_rev_id; 267239275Sgonzo 268239275Sgonzo uint32_t sc_flags; 269239275Sgonzo#define SMSC_FLAG_LINK 0x0001 270239275Sgonzo#define SMSC_FLAG_LAN9514 0x1000 /* LAN9514 */ 271239275Sgonzo}; 272239275Sgonzo 273239275Sgonzo#define SMSC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 274239275Sgonzo#define SMSC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 275239275Sgonzo#define SMSC_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 276239275Sgonzo 277239275Sgonzo#endif /* _IF_SMSCREG_H_ */ 278