if_auereg.h revision 187378
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/usb2/ethernet/if_auereg.h 187378 2009-01-18 05:35:58Z thompsa $ 33 */ 34 35/* 36 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet 37 * chip. The Pegasus uses a total of four USB endpoints: the control 38 * endpoint (0), a bulk read endpoint for receiving packets (1), 39 * a bulk write endpoint for sending packets (2) and an interrupt 40 * endpoint for passing RX and TX status (3). Endpoint 0 is used 41 * to read and write the ethernet module's registers. All registers 42 * are 8 bits wide. 43 * 44 * Packet transfer is done in 64 byte chunks. The last chunk in a 45 * transfer is denoted by having a length less that 64 bytes. For 46 * the RX case, the data includes an optional RX status word. 47 */ 48 49#define AUE_UR_READREG 0xF0 50#define AUE_UR_WRITEREG 0xF1 51 52#define AUE_CONFIG_INDEX 0 /* config number 1 */ 53#define AUE_IFACE_IDX 0 54 55/* 56 * Note that while the ADMtek technically has four endpoints, the control 57 * endpoint (endpoint 0) is regarded as special by the USB code and drivers 58 * don't have direct access to it (we access it using usb2_do_request() 59 * when reading/writing registers. Consequently, our endpoint indexes 60 * don't match those in the ADMtek Pegasus manual: we consider the RX data 61 * endpoint to be index 0 and work up from there. 62 */ 63enum { 64 AUE_BULK_DT_WR, 65 AUE_BULK_DT_RD, 66 AUE_BULK_CS_WR, 67 AUE_BULK_CS_RD, 68 AUE_INTR_DT_RD, 69 AUE_INTR_CS_RD, 70 AUE_N_TRANSFER = 6, 71}; 72 73#define AUE_INTR_PKTLEN 0x8 74 75#define AUE_CTL0 0x00 76#define AUE_CTL1 0x01 77#define AUE_CTL2 0x02 78#define AUE_MAR0 0x08 79#define AUE_MAR1 0x09 80#define AUE_MAR2 0x0A 81#define AUE_MAR3 0x0B 82#define AUE_MAR4 0x0C 83#define AUE_MAR5 0x0D 84#define AUE_MAR6 0x0E 85#define AUE_MAR7 0x0F 86#define AUE_MAR AUE_MAR0 87#define AUE_PAR0 0x10 88#define AUE_PAR1 0x11 89#define AUE_PAR2 0x12 90#define AUE_PAR3 0x13 91#define AUE_PAR4 0x14 92#define AUE_PAR5 0x15 93#define AUE_PAR AUE_PAR0 94#define AUE_PAUSE0 0x18 95#define AUE_PAUSE1 0x19 96#define AUE_PAUSE AUE_PAUSE0 97#define AUE_RX_FLOWCTL_CNT 0x1A 98#define AUE_RX_FLOWCTL_FIFO 0x1B 99#define AUE_REG_1D 0x1D 100#define AUE_EE_REG 0x20 101#define AUE_EE_DATA0 0x21 102#define AUE_EE_DATA1 0x22 103#define AUE_EE_DATA AUE_EE_DATA0 104#define AUE_EE_CTL 0x23 105#define AUE_PHY_ADDR 0x25 106#define AUE_PHY_DATA0 0x26 107#define AUE_PHY_DATA1 0x27 108#define AUE_PHY_DATA AUE_PHY_DATA0 109#define AUE_PHY_CTL 0x28 110#define AUE_USB_STS 0x2A 111#define AUE_TXSTAT0 0x2B 112#define AUE_TXSTAT1 0x2C 113#define AUE_TXSTAT AUE_TXSTAT0 114#define AUE_RXSTAT 0x2D 115#define AUE_PKTLOST0 0x2E 116#define AUE_PKTLOST1 0x2F 117#define AUE_PKTLOST AUE_PKTLOST0 118 119#define AUE_REG_7B 0x7B 120#define AUE_GPIO0 0x7E 121#define AUE_GPIO1 0x7F 122#define AUE_REG_81 0x81 123 124#define AUE_CTL0_INCLUDE_RXCRC 0x01 125#define AUE_CTL0_ALLMULTI 0x02 126#define AUE_CTL0_STOP_BACKOFF 0x04 127#define AUE_CTL0_RXSTAT_APPEND 0x08 128#define AUE_CTL0_WAKEON_ENB 0x10 129#define AUE_CTL0_RXPAUSE_ENB 0x20 130#define AUE_CTL0_RX_ENB 0x40 131#define AUE_CTL0_TX_ENB 0x80 132 133#define AUE_CTL1_HOMELAN 0x04 134#define AUE_CTL1_RESETMAC 0x08 135#define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */ 136#define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */ 137#define AUE_CTL1_DELAYHOME 0x40 138 139#define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */ 140#define AUE_CTL2_RX_BADFRAMES 0x02 141#define AUE_CTL2_RX_PROMISC 0x04 142#define AUE_CTL2_LOOPBACK 0x08 143#define AUE_CTL2_EEPROMWR_ENB 0x10 144#define AUE_CTL2_EEPROM_LOAD 0x20 145 146#define AUE_EECTL_WRITE 0x01 147#define AUE_EECTL_READ 0x02 148#define AUE_EECTL_DONE 0x04 149 150#define AUE_PHYCTL_PHYREG 0x1F 151#define AUE_PHYCTL_WRITE 0x20 152#define AUE_PHYCTL_READ 0x40 153#define AUE_PHYCTL_DONE 0x80 154 155#define AUE_USBSTS_SUSPEND 0x01 156#define AUE_USBSTS_RESUME 0x02 157 158#define AUE_TXSTAT0_JABTIMO 0x04 159#define AUE_TXSTAT0_CARLOSS 0x08 160#define AUE_TXSTAT0_NOCARRIER 0x10 161#define AUE_TXSTAT0_LATECOLL 0x20 162#define AUE_TXSTAT0_EXCESSCOLL 0x40 163#define AUE_TXSTAT0_UNDERRUN 0x80 164 165#define AUE_TXSTAT1_PKTCNT 0x0F 166#define AUE_TXSTAT1_FIFO_EMPTY 0x40 167#define AUE_TXSTAT1_FIFO_FULL 0x80 168 169#define AUE_RXSTAT_OVERRUN 0x01 170#define AUE_RXSTAT_PAUSE 0x02 171 172#define AUE_GPIO_IN0 0x01 173#define AUE_GPIO_OUT0 0x02 174#define AUE_GPIO_SEL0 0x04 175#define AUE_GPIO_IN1 0x08 176#define AUE_GPIO_OUT1 0x10 177#define AUE_GPIO_SEL1 0x20 178 179#define AUE_TIMEOUT 100 /* 10*ms */ 180#define AUE_MIN_FRAMELEN 60 181 182#define AUE_RXSTAT_MCAST 0x01 183#define AUE_RXSTAT_GIANT 0x02 184#define AUE_RXSTAT_RUNT 0x04 185#define AUE_RXSTAT_CRCERR 0x08 186#define AUE_RXSTAT_DRIBBLE 0x10 187#define AUE_RXSTAT_MASK 0x1E 188 189#define GET_MII(sc) ((sc)->sc_miibus ? \ 190 device_get_softc((sc)->sc_miibus) : NULL) 191 192struct aue_intrpkt { 193 uint8_t aue_txstat0; 194 uint8_t aue_txstat1; 195 uint8_t aue_rxstat; 196 uint8_t aue_rxlostpkt0; 197 uint8_t aue_rxlostpkt1; 198 uint8_t aue_wakeupstat; 199 uint8_t aue_rsvd; 200} __packed; 201 202struct aue_rxpkt { 203 uint16_t aue_pktlen; 204 uint8_t aue_rxstat; 205} __packed; 206 207struct aue_softc { 208 struct ifnet *sc_ifp; 209 210 struct usb2_config_td sc_config_td; 211 struct usb2_callout sc_watchdog; 212 struct mtx sc_mtx; 213 struct aue_rxpkt sc_rxpkt; 214 215 struct usb2_device *sc_udev; 216 struct usb2_xfer *sc_xfer[AUE_N_TRANSFER]; 217 device_t sc_miibus; 218 device_t sc_dev; 219 220 uint32_t sc_unit; 221 uint32_t sc_media_active; 222 uint32_t sc_media_status; 223 224 uint16_t sc_flags; 225#define AUE_FLAG_LSYS 0x0001 /* use Linksys reset */ 226#define AUE_FLAG_PNA 0x0002 /* has Home PNA */ 227#define AUE_FLAG_PII 0x0004 /* Pegasus II chip */ 228#define AUE_FLAG_WAIT_LINK 0x0008 /* wait for link to come up */ 229#define AUE_FLAG_READ_STALL 0x0010 /* wait for clearing of stall */ 230#define AUE_FLAG_WRITE_STALL 0x0020 /* wait for clearing of stall */ 231#define AUE_FLAG_LL_READY 0x0040 /* Lower Layer Ready */ 232#define AUE_FLAG_HL_READY 0x0080 /* Higher Layer Ready */ 233#define AUE_FLAG_INTR_STALL 0x0100 /* wait for clearing of stall */ 234#define AUE_FLAG_VER_2 0x0200 /* chip is version 2 */ 235#define AUE_FLAG_DUAL_PHY 0x0400 /* chip has two transcivers */ 236 237 uint8_t sc_name[16]; 238}; 239