ohci.c revision 198500
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/usb/controller/ohci.c 198500 2009-10-26 20:23:15Z thompsa $"); 30 31/* 32 * USB Open Host Controller driver. 33 * 34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 */ 37 38#include <sys/stdint.h> 39#include <sys/stddef.h> 40#include <sys/param.h> 41#include <sys/queue.h> 42#include <sys/types.h> 43#include <sys/systm.h> 44#include <sys/kernel.h> 45#include <sys/bus.h> 46#include <sys/linker_set.h> 47#include <sys/module.h> 48#include <sys/lock.h> 49#include <sys/mutex.h> 50#include <sys/condvar.h> 51#include <sys/sysctl.h> 52#include <sys/sx.h> 53#include <sys/unistd.h> 54#include <sys/callout.h> 55#include <sys/malloc.h> 56#include <sys/priv.h> 57 58#include <dev/usb/usb.h> 59#include <dev/usb/usbdi.h> 60 61#define USB_DEBUG_VAR ohcidebug 62 63#include <dev/usb/usb_core.h> 64#include <dev/usb/usb_debug.h> 65#include <dev/usb/usb_busdma.h> 66#include <dev/usb/usb_process.h> 67#include <dev/usb/usb_transfer.h> 68#include <dev/usb/usb_device.h> 69#include <dev/usb/usb_hub.h> 70#include <dev/usb/usb_util.h> 71 72#include <dev/usb/usb_controller.h> 73#include <dev/usb/usb_bus.h> 74#include <dev/usb/controller/ohci.h> 75#include <dev/usb/controller/ohcireg.h> 76 77#define OHCI_BUS2SC(bus) \ 78 ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 79 ((uint8_t *)&(((ohci_softc_t *)0)->sc_bus)))) 80 81#ifdef USB_DEBUG 82static int ohcidebug = 0; 83 84SYSCTL_NODE(_hw_usb, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 85SYSCTL_INT(_hw_usb_ohci, OID_AUTO, debug, CTLFLAG_RW, 86 &ohcidebug, 0, "ohci debug level"); 87static void ohci_dumpregs(ohci_softc_t *); 88static void ohci_dump_tds(ohci_td_t *); 89static uint8_t ohci_dump_td(ohci_td_t *); 90static void ohci_dump_ed(ohci_ed_t *); 91static uint8_t ohci_dump_itd(ohci_itd_t *); 92static void ohci_dump_itds(ohci_itd_t *); 93 94#endif 95 96#define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 97 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 98#define OWRITE1(sc, r, x) \ 99 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 100#define OWRITE2(sc, r, x) \ 101 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 102#define OWRITE4(sc, r, x) \ 103 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 104#define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 105#define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 106#define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 107 108#define OHCI_INTR_ENDPT 1 109 110extern struct usb_bus_methods ohci_bus_methods; 111extern struct usb_pipe_methods ohci_device_bulk_methods; 112extern struct usb_pipe_methods ohci_device_ctrl_methods; 113extern struct usb_pipe_methods ohci_device_intr_methods; 114extern struct usb_pipe_methods ohci_device_isoc_methods; 115 116static void ohci_do_poll(struct usb_bus *bus); 117static void ohci_device_done(struct usb_xfer *xfer, usb_error_t error); 118static void ohci_timeout(void *arg); 119static uint8_t ohci_check_transfer(struct usb_xfer *xfer); 120static void ohci_root_intr(ohci_softc_t *sc); 121 122struct ohci_std_temp { 123 struct usb_page_cache *pc; 124 ohci_td_t *td; 125 ohci_td_t *td_next; 126 uint32_t average; 127 uint32_t td_flags; 128 uint32_t len; 129 uint16_t max_frame_size; 130 uint8_t shortpkt; 131 uint8_t setup_alt_next; 132 uint8_t last_frame; 133}; 134 135static struct ohci_hcca * 136ohci_get_hcca(ohci_softc_t *sc) 137{ 138 usb_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 139 return (sc->sc_hcca_p); 140} 141 142void 143ohci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 144{ 145 struct ohci_softc *sc = OHCI_BUS2SC(bus); 146 uint32_t i; 147 148 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 149 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 150 151 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 152 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 153 154 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 155 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 156 157 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 158 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 159 160 for (i = 0; i != OHCI_NO_EDS; i++) { 161 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 162 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 163 } 164} 165 166static usb_error_t 167ohci_controller_init(ohci_softc_t *sc) 168{ 169 struct usb_page_search buf_res; 170 uint32_t i; 171 uint32_t ctl; 172 uint32_t ival; 173 uint32_t hcr; 174 uint32_t fm; 175 uint32_t per; 176 uint32_t desca; 177 178 /* 179 * This reset should not be necessary according to the OHCI spec, but 180 * without it some controllers do not start. 181 */ 182 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 183 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 184 185 usb_pause_mtx(NULL, 186 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 187 188 /* we now own the host controller and the bus has been reset */ 189 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 190 191 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 192 /* nominal time for a reset is 10 us */ 193 for (i = 0; i < 10; i++) { 194 DELAY(10); 195 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 196 if (!hcr) { 197 break; 198 } 199 } 200 if (hcr) { 201 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 202 return (USB_ERR_IOERROR); 203 } 204#ifdef USB_DEBUG 205 if (ohcidebug > 15) { 206 ohci_dumpregs(sc); 207 } 208#endif 209 210 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 211 212 /* set up HC registers */ 213 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 214 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 215 216 usbd_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 217 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 218 219 usbd_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 220 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 221 222 /* disable all interrupts and then switch on all desired interrupts */ 223 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 224 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 225 /* switch on desired functional features */ 226 ctl = OREAD4(sc, OHCI_CONTROL); 227 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 228 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 229 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 230 /* And finally start it! */ 231 OWRITE4(sc, OHCI_CONTROL, ctl); 232 233 /* 234 * The controller is now OPERATIONAL. Set a some final 235 * registers that should be set earlier, but that the 236 * controller ignores when in the SUSPEND state. 237 */ 238 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 239 fm |= OHCI_FSMPS(ival) | ival; 240 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 241 per = OHCI_PERIODIC(ival); /* 90% periodic */ 242 OWRITE4(sc, OHCI_PERIODIC_START, per); 243 244 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 245 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 246 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 247 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 248 usb_pause_mtx(NULL, 249 USB_MS_TO_TICKS(OHCI_ENABLE_POWER_DELAY)); 250 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 251 252 /* 253 * The AMD756 requires a delay before re-reading the register, 254 * otherwise it will occasionally report 0 ports. 255 */ 256 sc->sc_noport = 0; 257 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 258 usb_pause_mtx(NULL, 259 USB_MS_TO_TICKS(OHCI_READ_DESC_DELAY)); 260 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 261 } 262 263#ifdef USB_DEBUG 264 if (ohcidebug > 5) { 265 ohci_dumpregs(sc); 266 } 267#endif 268 return (USB_ERR_NORMAL_COMPLETION); 269} 270 271static struct ohci_ed * 272ohci_init_ed(struct usb_page_cache *pc) 273{ 274 struct usb_page_search buf_res; 275 struct ohci_ed *ed; 276 277 usbd_get_page(pc, 0, &buf_res); 278 279 ed = buf_res.buffer; 280 281 ed->ed_self = htole32(buf_res.physaddr); 282 ed->ed_flags = htole32(OHCI_ED_SKIP); 283 ed->page_cache = pc; 284 285 return (ed); 286} 287 288usb_error_t 289ohci_init(ohci_softc_t *sc) 290{ 291 struct usb_page_search buf_res; 292 uint16_t i; 293 uint16_t bit; 294 uint16_t x; 295 uint16_t y; 296 297 DPRINTF("start\n"); 298 299 sc->sc_eintrs = OHCI_NORMAL_INTRS; 300 301 /* 302 * Setup all ED's 303 */ 304 305 sc->sc_ctrl_p_last = 306 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 307 308 sc->sc_bulk_p_last = 309 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 310 311 sc->sc_isoc_p_last = 312 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 313 314 for (i = 0; i != OHCI_NO_EDS; i++) { 315 sc->sc_intr_p_last[i] = 316 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 317 } 318 319 /* 320 * the QHs are arranged to give poll intervals that are 321 * powers of 2 times 1ms 322 */ 323 bit = OHCI_NO_EDS / 2; 324 while (bit) { 325 x = bit; 326 while (x & bit) { 327 ohci_ed_t *ed_x; 328 ohci_ed_t *ed_y; 329 330 y = (x ^ bit) | (bit / 2); 331 332 /* 333 * the next QH has half the poll interval 334 */ 335 ed_x = sc->sc_intr_p_last[x]; 336 ed_y = sc->sc_intr_p_last[y]; 337 338 ed_x->next = NULL; 339 ed_x->ed_next = ed_y->ed_self; 340 341 x++; 342 } 343 bit >>= 1; 344 } 345 346 if (1) { 347 348 ohci_ed_t *ed_int; 349 ohci_ed_t *ed_isc; 350 351 ed_int = sc->sc_intr_p_last[0]; 352 ed_isc = sc->sc_isoc_p_last; 353 354 /* the last (1ms) QH */ 355 ed_int->next = ed_isc; 356 ed_int->ed_next = ed_isc->ed_self; 357 } 358 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 359 360 sc->sc_hcca_p = buf_res.buffer; 361 362 /* 363 * Fill HCCA interrupt table. The bit reversal is to get 364 * the tree set up properly to spread the interrupts. 365 */ 366 for (i = 0; i != OHCI_NO_INTRS; i++) { 367 sc->sc_hcca_p->hcca_interrupt_table[i] = 368 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 369 } 370 /* flush all cache into memory */ 371 372 usb_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 373 374 /* set up the bus struct */ 375 sc->sc_bus.methods = &ohci_bus_methods; 376 377 usb_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 378 379#ifdef USB_DEBUG 380 if (ohcidebug > 15) { 381 for (i = 0; i != OHCI_NO_EDS; i++) { 382 printf("ed#%d ", i); 383 ohci_dump_ed(sc->sc_intr_p_last[i]); 384 } 385 printf("iso "); 386 ohci_dump_ed(sc->sc_isoc_p_last); 387 } 388#endif 389 390 sc->sc_bus.usbrev = USB_REV_1_0; 391 392 if (ohci_controller_init(sc)) { 393 return (USB_ERR_INVAL); 394 } else { 395 /* catch any lost interrupts */ 396 ohci_do_poll(&sc->sc_bus); 397 return (USB_ERR_NORMAL_COMPLETION); 398 } 399} 400 401/* 402 * shut down the controller when the system is going down 403 */ 404void 405ohci_detach(struct ohci_softc *sc) 406{ 407 USB_BUS_LOCK(&sc->sc_bus); 408 409 usb_callout_stop(&sc->sc_tmo_rhsc); 410 411 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 412 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 413 414 USB_BUS_UNLOCK(&sc->sc_bus); 415 416 /* XXX let stray task complete */ 417 usb_pause_mtx(NULL, hz / 20); 418 419 usb_callout_drain(&sc->sc_tmo_rhsc); 420} 421 422/* NOTE: suspend/resume is called from 423 * interrupt context and cannot sleep! 424 */ 425void 426ohci_suspend(ohci_softc_t *sc) 427{ 428 uint32_t ctl; 429 430 USB_BUS_LOCK(&sc->sc_bus); 431 432#ifdef USB_DEBUG 433 DPRINTF("\n"); 434 if (ohcidebug > 2) { 435 ohci_dumpregs(sc); 436 } 437#endif 438 439 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 440 if (sc->sc_control == 0) { 441 /* 442 * Preserve register values, in case that APM BIOS 443 * does not recover them. 444 */ 445 sc->sc_control = ctl; 446 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 447 } 448 ctl |= OHCI_HCFS_SUSPEND; 449 OWRITE4(sc, OHCI_CONTROL, ctl); 450 451 usb_pause_mtx(&sc->sc_bus.bus_mtx, 452 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 453 454 USB_BUS_UNLOCK(&sc->sc_bus); 455} 456 457void 458ohci_resume(ohci_softc_t *sc) 459{ 460 uint32_t ctl; 461 462#ifdef USB_DEBUG 463 DPRINTF("\n"); 464 if (ohcidebug > 2) { 465 ohci_dumpregs(sc); 466 } 467#endif 468 /* some broken BIOSes never initialize the Controller chip */ 469 ohci_controller_init(sc); 470 471 USB_BUS_LOCK(&sc->sc_bus); 472 if (sc->sc_intre) { 473 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 474 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 475 } 476 if (sc->sc_control) 477 ctl = sc->sc_control; 478 else 479 ctl = OREAD4(sc, OHCI_CONTROL); 480 ctl |= OHCI_HCFS_RESUME; 481 OWRITE4(sc, OHCI_CONTROL, ctl); 482 usb_pause_mtx(&sc->sc_bus.bus_mtx, 483 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 484 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 485 OWRITE4(sc, OHCI_CONTROL, ctl); 486 usb_pause_mtx(&sc->sc_bus.bus_mtx, 487 USB_MS_TO_TICKS(USB_RESUME_RECOVERY)); 488 sc->sc_control = sc->sc_intre = 0; 489 490 USB_BUS_UNLOCK(&sc->sc_bus); 491 492 /* catch any lost interrupts */ 493 ohci_do_poll(&sc->sc_bus); 494} 495 496#ifdef USB_DEBUG 497static void 498ohci_dumpregs(ohci_softc_t *sc) 499{ 500 struct ohci_hcca *hcca; 501 502 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 503 OREAD4(sc, OHCI_REVISION), 504 OREAD4(sc, OHCI_CONTROL), 505 OREAD4(sc, OHCI_COMMAND_STATUS)); 506 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 507 OREAD4(sc, OHCI_INTERRUPT_STATUS), 508 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 509 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 510 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 511 OREAD4(sc, OHCI_HCCA), 512 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 513 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 514 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 515 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 516 OREAD4(sc, OHCI_BULK_HEAD_ED), 517 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 518 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 519 OREAD4(sc, OHCI_DONE_HEAD), 520 OREAD4(sc, OHCI_FM_INTERVAL), 521 OREAD4(sc, OHCI_FM_REMAINING)); 522 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 523 OREAD4(sc, OHCI_FM_NUMBER), 524 OREAD4(sc, OHCI_PERIODIC_START), 525 OREAD4(sc, OHCI_LS_THRESHOLD)); 526 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 527 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 528 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 529 OREAD4(sc, OHCI_RH_STATUS)); 530 DPRINTF(" port1=0x%08x port2=0x%08x\n", 531 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 532 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 533 534 hcca = ohci_get_hcca(sc); 535 536 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 537 le32toh(hcca->hcca_frame_number), 538 le32toh(hcca->hcca_done_head)); 539} 540static void 541ohci_dump_tds(ohci_td_t *std) 542{ 543 for (; std; std = std->obj_next) { 544 if (ohci_dump_td(std)) { 545 break; 546 } 547 } 548} 549 550static uint8_t 551ohci_dump_td(ohci_td_t *std) 552{ 553 uint32_t td_flags; 554 uint8_t temp; 555 556 usb_pc_cpu_invalidate(std->page_cache); 557 558 td_flags = le32toh(std->td_flags); 559 temp = (std->td_next == 0); 560 561 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 562 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 563 std, le32toh(std->td_self), 564 (td_flags & OHCI_TD_R) ? "-R" : "", 565 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 566 (td_flags & OHCI_TD_IN) ? "-IN" : "", 567 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 568 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 569 OHCI_TD_GET_DI(td_flags), 570 OHCI_TD_GET_EC(td_flags), 571 OHCI_TD_GET_CC(td_flags), 572 le32toh(std->td_cbp), 573 le32toh(std->td_next), 574 le32toh(std->td_be)); 575 576 return (temp); 577} 578 579static uint8_t 580ohci_dump_itd(ohci_itd_t *sitd) 581{ 582 uint32_t itd_flags; 583 uint16_t i; 584 uint8_t temp; 585 586 usb_pc_cpu_invalidate(sitd->page_cache); 587 588 itd_flags = le32toh(sitd->itd_flags); 589 temp = (sitd->itd_next == 0); 590 591 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 592 "bp0=0x%08x next=0x%08x be=0x%08x\n", 593 sitd, le32toh(sitd->itd_self), 594 OHCI_ITD_GET_SF(itd_flags), 595 OHCI_ITD_GET_DI(itd_flags), 596 OHCI_ITD_GET_FC(itd_flags), 597 OHCI_ITD_GET_CC(itd_flags), 598 le32toh(sitd->itd_bp0), 599 le32toh(sitd->itd_next), 600 le32toh(sitd->itd_be)); 601 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 602 printf("offs[%d]=0x%04x ", i, 603 (uint32_t)le16toh(sitd->itd_offset[i])); 604 } 605 printf("\n"); 606 607 return (temp); 608} 609 610static void 611ohci_dump_itds(ohci_itd_t *sitd) 612{ 613 for (; sitd; sitd = sitd->obj_next) { 614 if (ohci_dump_itd(sitd)) { 615 break; 616 } 617 } 618} 619 620static void 621ohci_dump_ed(ohci_ed_t *sed) 622{ 623 uint32_t ed_flags; 624 uint32_t ed_headp; 625 626 usb_pc_cpu_invalidate(sed->page_cache); 627 628 ed_flags = le32toh(sed->ed_flags); 629 ed_headp = le32toh(sed->ed_headp); 630 631 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 632 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 633 sed, le32toh(sed->ed_self), 634 OHCI_ED_GET_FA(ed_flags), 635 OHCI_ED_GET_EN(ed_flags), 636 OHCI_ED_GET_MAXP(ed_flags), 637 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 638 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 639 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 640 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 641 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 642 le32toh(sed->ed_tailp), 643 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 644 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 645 le32toh(sed->ed_headp), 646 le32toh(sed->ed_next)); 647} 648 649#endif 650 651static void 652ohci_transfer_intr_enqueue(struct usb_xfer *xfer) 653{ 654 /* check for early completion */ 655 if (ohci_check_transfer(xfer)) { 656 return; 657 } 658 /* put transfer on interrupt queue */ 659 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 660 661 /* start timeout, if any */ 662 if (xfer->timeout != 0) { 663 usbd_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 664 } 665} 666 667#define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 668static ohci_ed_t * 669_ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 670{ 671 DPRINTFN(11, "%p to %p\n", sed, last); 672 673 if (sed->prev != NULL) { 674 /* should not happen */ 675 DPRINTFN(0, "ED already linked!\n"); 676 return (last); 677 } 678 /* (sc->sc_bus.bus_mtx) must be locked */ 679 680 sed->next = last->next; 681 sed->ed_next = last->ed_next; 682 sed->ed_tailp = 0; 683 684 sed->prev = last; 685 686 usb_pc_cpu_flush(sed->page_cache); 687 688 /* 689 * the last->next->prev is never followed: sed->next->prev = sed; 690 */ 691 692 last->next = sed; 693 last->ed_next = sed->ed_self; 694 695 usb_pc_cpu_flush(last->page_cache); 696 697 return (sed); 698} 699 700#define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 701static ohci_ed_t * 702_ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 703{ 704 DPRINTFN(11, "%p from %p\n", sed, last); 705 706 /* (sc->sc_bus.bus_mtx) must be locked */ 707 708 /* only remove if not removed from a queue */ 709 if (sed->prev) { 710 711 sed->prev->next = sed->next; 712 sed->prev->ed_next = sed->ed_next; 713 714 usb_pc_cpu_flush(sed->prev->page_cache); 715 716 if (sed->next) { 717 sed->next->prev = sed->prev; 718 usb_pc_cpu_flush(sed->next->page_cache); 719 } 720 last = ((last == sed) ? sed->prev : last); 721 722 sed->prev = 0; 723 724 usb_pc_cpu_flush(sed->page_cache); 725 } 726 return (last); 727} 728 729static void 730ohci_isoc_done(struct usb_xfer *xfer) 731{ 732 uint8_t nframes; 733 uint32_t *plen = xfer->frlengths; 734 volatile uint16_t *olen; 735 uint16_t len = 0; 736 ohci_itd_t *td = xfer->td_transfer_first; 737 738 while (1) { 739 if (td == NULL) { 740 panic("%s:%d: out of TD's\n", 741 __FUNCTION__, __LINE__); 742 } 743#ifdef USB_DEBUG 744 if (ohcidebug > 5) { 745 DPRINTF("isoc TD\n"); 746 ohci_dump_itd(td); 747 } 748#endif 749 usb_pc_cpu_invalidate(td->page_cache); 750 751 nframes = td->frames; 752 olen = &td->itd_offset[0]; 753 754 if (nframes > 8) { 755 nframes = 8; 756 } 757 while (nframes--) { 758 len = le16toh(*olen); 759 760 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 761 len = 0; 762 } else { 763 len &= ((1 << 12) - 1); 764 } 765 766 if (len > *plen) { 767 len = 0;/* invalid length */ 768 } 769 *plen = len; 770 plen++; 771 olen++; 772 } 773 774 if (((void *)td) == xfer->td_transfer_last) { 775 break; 776 } 777 td = td->obj_next; 778 } 779 780 xfer->aframes = xfer->nframes; 781 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 782} 783 784#ifdef USB_DEBUG 785static const char *const 786 ohci_cc_strs[] = 787{ 788 "NO_ERROR", 789 "CRC", 790 "BIT_STUFFING", 791 "DATA_TOGGLE_MISMATCH", 792 793 "STALL", 794 "DEVICE_NOT_RESPONDING", 795 "PID_CHECK_FAILURE", 796 "UNEXPECTED_PID", 797 798 "DATA_OVERRUN", 799 "DATA_UNDERRUN", 800 "BUFFER_OVERRUN", 801 "BUFFER_UNDERRUN", 802 803 "reserved", 804 "reserved", 805 "NOT_ACCESSED", 806 "NOT_ACCESSED" 807}; 808 809#endif 810 811static usb_error_t 812ohci_non_isoc_done_sub(struct usb_xfer *xfer) 813{ 814 ohci_td_t *td; 815 ohci_td_t *td_alt_next; 816 uint32_t temp; 817 uint32_t phy_start; 818 uint32_t phy_end; 819 uint32_t td_flags; 820 uint16_t cc; 821 822 td = xfer->td_transfer_cache; 823 td_alt_next = td->alt_next; 824 td_flags = 0; 825 826 if (xfer->aframes != xfer->nframes) { 827 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 828 } 829 while (1) { 830 831 usb_pc_cpu_invalidate(td->page_cache); 832 phy_start = le32toh(td->td_cbp); 833 td_flags = le32toh(td->td_flags); 834 cc = OHCI_TD_GET_CC(td_flags); 835 836 if (phy_start) { 837 /* 838 * short transfer - compute the number of remaining 839 * bytes in the hardware buffer: 840 */ 841 phy_end = le32toh(td->td_be); 842 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 843 (OHCI_PAGE_SIZE + 1) : 0x0001); 844 temp += OHCI_PAGE_OFFSET(phy_end); 845 temp -= OHCI_PAGE_OFFSET(phy_start); 846 847 if (temp > td->len) { 848 /* guard against corruption */ 849 cc = OHCI_CC_STALL; 850 } else if (xfer->aframes != xfer->nframes) { 851 /* 852 * Sum up total transfer length 853 * in "frlengths[]": 854 */ 855 xfer->frlengths[xfer->aframes] += td->len - temp; 856 } 857 } else { 858 if (xfer->aframes != xfer->nframes) { 859 /* transfer was complete */ 860 xfer->frlengths[xfer->aframes] += td->len; 861 } 862 } 863 /* Check for last transfer */ 864 if (((void *)td) == xfer->td_transfer_last) { 865 td = NULL; 866 break; 867 } 868 /* Check transfer status */ 869 if (cc) { 870 /* the transfer is finished */ 871 td = NULL; 872 break; 873 } 874 /* Check for short transfer */ 875 if (phy_start) { 876 if (xfer->flags_int.short_frames_ok) { 877 /* follow alt next */ 878 td = td->alt_next; 879 } else { 880 /* the transfer is finished */ 881 td = NULL; 882 } 883 break; 884 } 885 td = td->obj_next; 886 887 if (td->alt_next != td_alt_next) { 888 /* this USB frame is complete */ 889 break; 890 } 891 } 892 893 /* update transfer cache */ 894 895 xfer->td_transfer_cache = td; 896 897 DPRINTFN(16, "error cc=%d (%s)\n", 898 cc, ohci_cc_strs[cc]); 899 900 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 901 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 902} 903 904static void 905ohci_non_isoc_done(struct usb_xfer *xfer) 906{ 907 usb_error_t err = 0; 908 909 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 910 xfer, xfer->endpoint); 911 912#ifdef USB_DEBUG 913 if (ohcidebug > 10) { 914 ohci_dump_tds(xfer->td_transfer_first); 915 } 916#endif 917 918 /* reset scanner */ 919 920 xfer->td_transfer_cache = xfer->td_transfer_first; 921 922 if (xfer->flags_int.control_xfr) { 923 924 if (xfer->flags_int.control_hdr) { 925 926 err = ohci_non_isoc_done_sub(xfer); 927 } 928 xfer->aframes = 1; 929 930 if (xfer->td_transfer_cache == NULL) { 931 goto done; 932 } 933 } 934 while (xfer->aframes != xfer->nframes) { 935 936 err = ohci_non_isoc_done_sub(xfer); 937 xfer->aframes++; 938 939 if (xfer->td_transfer_cache == NULL) { 940 goto done; 941 } 942 } 943 944 if (xfer->flags_int.control_xfr && 945 !xfer->flags_int.control_act) { 946 947 err = ohci_non_isoc_done_sub(xfer); 948 } 949done: 950 ohci_device_done(xfer, err); 951} 952 953/*------------------------------------------------------------------------* 954 * ohci_check_transfer_sub 955 *------------------------------------------------------------------------*/ 956static void 957ohci_check_transfer_sub(struct usb_xfer *xfer) 958{ 959 ohci_td_t *td; 960 ohci_ed_t *ed; 961 uint32_t phy_start; 962 uint32_t td_flags; 963 uint32_t td_next; 964 uint16_t cc; 965 966 td = xfer->td_transfer_cache; 967 968 while (1) { 969 970 usb_pc_cpu_invalidate(td->page_cache); 971 phy_start = le32toh(td->td_cbp); 972 td_flags = le32toh(td->td_flags); 973 td_next = le32toh(td->td_next); 974 975 /* Check for last transfer */ 976 if (((void *)td) == xfer->td_transfer_last) { 977 /* the transfer is finished */ 978 td = NULL; 979 break; 980 } 981 /* Check transfer status */ 982 cc = OHCI_TD_GET_CC(td_flags); 983 if (cc) { 984 /* the transfer is finished */ 985 td = NULL; 986 break; 987 } 988 /* 989 * Check if we reached the last packet 990 * or if there is a short packet: 991 */ 992 993 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 994 /* follow alt next */ 995 td = td->alt_next; 996 break; 997 } 998 td = td->obj_next; 999 } 1000 1001 /* update transfer cache */ 1002 1003 xfer->td_transfer_cache = td; 1004 1005 if (td) { 1006 1007 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1008 1009 ed->ed_headp = td->td_self; 1010 usb_pc_cpu_flush(ed->page_cache); 1011 1012 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1013 1014 /* 1015 * Make sure that the OHCI re-scans the schedule by 1016 * writing the BLF and CLF bits: 1017 */ 1018 1019 if (xfer->xroot->udev->flags.self_suspended) { 1020 /* nothing to do */ 1021 } else if (xfer->endpoint->methods == &ohci_device_bulk_methods) { 1022 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1023 1024 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1025 } else if (xfer->endpoint->methods == &ohci_device_ctrl_methods) { 1026 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1027 1028 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1029 } 1030 } 1031} 1032 1033/*------------------------------------------------------------------------* 1034 * ohci_check_transfer 1035 * 1036 * Return values: 1037 * 0: USB transfer is not finished 1038 * Else: USB transfer is finished 1039 *------------------------------------------------------------------------*/ 1040static uint8_t 1041ohci_check_transfer(struct usb_xfer *xfer) 1042{ 1043 ohci_ed_t *ed; 1044 uint32_t ed_headp; 1045 uint32_t ed_tailp; 1046 1047 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1048 1049 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1050 1051 usb_pc_cpu_invalidate(ed->page_cache); 1052 ed_headp = le32toh(ed->ed_headp); 1053 ed_tailp = le32toh(ed->ed_tailp); 1054 1055 if ((ed_headp & OHCI_HALTED) || 1056 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1057 if (xfer->endpoint->methods == &ohci_device_isoc_methods) { 1058 /* isochronous transfer */ 1059 ohci_isoc_done(xfer); 1060 } else { 1061 if (xfer->flags_int.short_frames_ok) { 1062 ohci_check_transfer_sub(xfer); 1063 if (xfer->td_transfer_cache) { 1064 /* not finished yet */ 1065 return (0); 1066 } 1067 } 1068 /* store data-toggle */ 1069 if (ed_headp & OHCI_TOGGLECARRY) { 1070 xfer->endpoint->toggle_next = 1; 1071 } else { 1072 xfer->endpoint->toggle_next = 0; 1073 } 1074 1075 /* non-isochronous transfer */ 1076 ohci_non_isoc_done(xfer); 1077 } 1078 return (1); 1079 } 1080 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1081 return (0); 1082} 1083 1084static void 1085ohci_rhsc_enable(ohci_softc_t *sc) 1086{ 1087 DPRINTFN(5, "\n"); 1088 1089 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1090 1091 sc->sc_eintrs |= OHCI_RHSC; 1092 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1093 1094 /* acknowledge any RHSC interrupt */ 1095 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1096 1097 ohci_root_intr(sc); 1098} 1099 1100static void 1101ohci_interrupt_poll(ohci_softc_t *sc) 1102{ 1103 struct usb_xfer *xfer; 1104 1105repeat: 1106 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1107 /* 1108 * check if transfer is transferred 1109 */ 1110 if (ohci_check_transfer(xfer)) { 1111 /* queue has been modified */ 1112 goto repeat; 1113 } 1114 } 1115} 1116 1117/*------------------------------------------------------------------------* 1118 * ohci_interrupt - OHCI interrupt handler 1119 * 1120 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1121 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1122 * is present ! 1123 *------------------------------------------------------------------------*/ 1124void 1125ohci_interrupt(ohci_softc_t *sc) 1126{ 1127 struct ohci_hcca *hcca; 1128 uint32_t status; 1129 uint32_t done; 1130 1131 USB_BUS_LOCK(&sc->sc_bus); 1132 1133 hcca = ohci_get_hcca(sc); 1134 1135 DPRINTFN(16, "real interrupt\n"); 1136 1137#ifdef USB_DEBUG 1138 if (ohcidebug > 15) { 1139 ohci_dumpregs(sc); 1140 } 1141#endif 1142 1143 done = le32toh(hcca->hcca_done_head); 1144 1145 /* 1146 * The LSb of done is used to inform the HC Driver that an interrupt 1147 * condition exists for both the Done list and for another event 1148 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1149 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1150 * the interrupt was caused by other than the HccaDoneHead update 1151 * and the HcInterruptStatus register needs to be accessed to 1152 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1153 * then a Done list update interrupt is indicated and if the LSb of 1154 * done is nonzero, then an additional interrupt event is indicated 1155 * and HcInterruptStatus should be checked to determine its cause. 1156 */ 1157 if (done != 0) { 1158 status = 0; 1159 1160 if (done & ~OHCI_DONE_INTRS) { 1161 status |= OHCI_WDH; 1162 } 1163 if (done & OHCI_DONE_INTRS) { 1164 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1165 } 1166 hcca->hcca_done_head = 0; 1167 1168 usb_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1169 } else { 1170 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1171 } 1172 1173 status &= ~OHCI_MIE; 1174 if (status == 0) { 1175 /* 1176 * nothing to be done (PCI shared 1177 * interrupt) 1178 */ 1179 goto done; 1180 } 1181 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1182 1183 status &= sc->sc_eintrs; 1184 if (status == 0) { 1185 goto done; 1186 } 1187 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1188#if 0 1189 if (status & OHCI_SO) { 1190 /* XXX do what */ 1191 } 1192#endif 1193 if (status & OHCI_RD) { 1194 printf("%s: resume detect\n", __FUNCTION__); 1195 /* XXX process resume detect */ 1196 } 1197 if (status & OHCI_UE) { 1198 printf("%s: unrecoverable error, " 1199 "controller halted\n", __FUNCTION__); 1200 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1201 /* XXX what else */ 1202 } 1203 if (status & OHCI_RHSC) { 1204 /* 1205 * Disable RHSC interrupt for now, because it will be 1206 * on until the port has been reset. 1207 */ 1208 sc->sc_eintrs &= ~OHCI_RHSC; 1209 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1210 1211 ohci_root_intr(sc); 1212 1213 /* do not allow RHSC interrupts > 1 per second */ 1214 usb_callout_reset(&sc->sc_tmo_rhsc, hz, 1215 (void *)&ohci_rhsc_enable, sc); 1216 } 1217 } 1218 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1219 if (status != 0) { 1220 /* Block unprocessed interrupts. XXX */ 1221 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1222 sc->sc_eintrs &= ~status; 1223 printf("%s: blocking intrs 0x%x\n", 1224 __FUNCTION__, status); 1225 } 1226 /* poll all the USB transfers */ 1227 ohci_interrupt_poll(sc); 1228 1229done: 1230 USB_BUS_UNLOCK(&sc->sc_bus); 1231} 1232 1233/* 1234 * called when a request does not complete 1235 */ 1236static void 1237ohci_timeout(void *arg) 1238{ 1239 struct usb_xfer *xfer = arg; 1240 1241 DPRINTF("xfer=%p\n", xfer); 1242 1243 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1244 1245 /* transfer is transferred */ 1246 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1247} 1248 1249static void 1250ohci_do_poll(struct usb_bus *bus) 1251{ 1252 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1253 1254 USB_BUS_LOCK(&sc->sc_bus); 1255 ohci_interrupt_poll(sc); 1256 USB_BUS_UNLOCK(&sc->sc_bus); 1257} 1258 1259static void 1260ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1261{ 1262 struct usb_page_search buf_res; 1263 ohci_td_t *td; 1264 ohci_td_t *td_next; 1265 ohci_td_t *td_alt_next; 1266 uint32_t buf_offset; 1267 uint32_t average; 1268 uint32_t len_old; 1269 uint8_t shortpkt_old; 1270 uint8_t precompute; 1271 1272 td_alt_next = NULL; 1273 buf_offset = 0; 1274 shortpkt_old = temp->shortpkt; 1275 len_old = temp->len; 1276 precompute = 1; 1277 1278 /* software is used to detect short incoming transfers */ 1279 1280 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1281 temp->td_flags |= htole32(OHCI_TD_R); 1282 } else { 1283 temp->td_flags &= ~htole32(OHCI_TD_R); 1284 } 1285 1286restart: 1287 1288 td = temp->td; 1289 td_next = temp->td_next; 1290 1291 while (1) { 1292 1293 if (temp->len == 0) { 1294 1295 if (temp->shortpkt) { 1296 break; 1297 } 1298 /* send a Zero Length Packet, ZLP, last */ 1299 1300 temp->shortpkt = 1; 1301 average = 0; 1302 1303 } else { 1304 1305 average = temp->average; 1306 1307 if (temp->len < average) { 1308 if (temp->len % temp->max_frame_size) { 1309 temp->shortpkt = 1; 1310 } 1311 average = temp->len; 1312 } 1313 } 1314 1315 if (td_next == NULL) { 1316 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1317 } 1318 /* get next TD */ 1319 1320 td = td_next; 1321 td_next = td->obj_next; 1322 1323 /* check if we are pre-computing */ 1324 1325 if (precompute) { 1326 1327 /* update remaining length */ 1328 1329 temp->len -= average; 1330 1331 continue; 1332 } 1333 /* fill out current TD */ 1334 td->td_flags = temp->td_flags; 1335 1336 /* the next TD uses TOGGLE_CARRY */ 1337 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1338 1339 if (average == 0) { 1340 /* 1341 * The buffer start and end phys addresses should be 1342 * 0x0 for a zero length packet. 1343 */ 1344 td->td_cbp = 0; 1345 td->td_be = 0; 1346 td->len = 0; 1347 1348 } else { 1349 1350 usbd_get_page(temp->pc, buf_offset, &buf_res); 1351 td->td_cbp = htole32(buf_res.physaddr); 1352 buf_offset += (average - 1); 1353 1354 usbd_get_page(temp->pc, buf_offset, &buf_res); 1355 td->td_be = htole32(buf_res.physaddr); 1356 buf_offset++; 1357 1358 td->len = average; 1359 1360 /* update remaining length */ 1361 1362 temp->len -= average; 1363 } 1364 1365 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1366 /* we need to receive these frames one by one ! */ 1367 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1368 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1369 td->td_next = htole32(OHCI_TD_NEXT_END); 1370 } else { 1371 if (td_next) { 1372 /* link the current TD with the next one */ 1373 td->td_next = td_next->td_self; 1374 } 1375 } 1376 1377 td->alt_next = td_alt_next; 1378 1379 usb_pc_cpu_flush(td->page_cache); 1380 } 1381 1382 if (precompute) { 1383 precompute = 0; 1384 1385 /* setup alt next pointer, if any */ 1386 if (temp->last_frame) { 1387 /* no alternate next */ 1388 td_alt_next = NULL; 1389 } else { 1390 /* we use this field internally */ 1391 td_alt_next = td_next; 1392 } 1393 1394 /* restore */ 1395 temp->shortpkt = shortpkt_old; 1396 temp->len = len_old; 1397 goto restart; 1398 } 1399 temp->td = td; 1400 temp->td_next = td_next; 1401} 1402 1403static void 1404ohci_setup_standard_chain(struct usb_xfer *xfer, ohci_ed_t **ed_last) 1405{ 1406 struct ohci_std_temp temp; 1407 struct usb_pipe_methods *methods; 1408 ohci_ed_t *ed; 1409 ohci_td_t *td; 1410 uint32_t ed_flags; 1411 uint32_t x; 1412 1413 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1414 xfer->address, UE_GET_ADDR(xfer->endpointno), 1415 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1416 1417 temp.average = xfer->max_hc_frame_size; 1418 temp.max_frame_size = xfer->max_frame_size; 1419 1420 /* toggle the DMA set we are using */ 1421 xfer->flags_int.curr_dma_set ^= 1; 1422 1423 /* get next DMA set */ 1424 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1425 1426 xfer->td_transfer_first = td; 1427 xfer->td_transfer_cache = td; 1428 1429 temp.td = NULL; 1430 temp.td_next = td; 1431 temp.last_frame = 0; 1432 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1433 1434 methods = xfer->endpoint->methods; 1435 1436 /* check if we should prepend a setup message */ 1437 1438 if (xfer->flags_int.control_xfr) { 1439 if (xfer->flags_int.control_hdr) { 1440 1441 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1442 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1443 1444 temp.len = xfer->frlengths[0]; 1445 temp.pc = xfer->frbuffers + 0; 1446 temp.shortpkt = temp.len ? 1 : 0; 1447 /* check for last frame */ 1448 if (xfer->nframes == 1) { 1449 /* no STATUS stage yet, SETUP is last */ 1450 if (xfer->flags_int.control_act) { 1451 temp.last_frame = 1; 1452 temp.setup_alt_next = 0; 1453 } 1454 } 1455 ohci_setup_standard_chain_sub(&temp); 1456 1457 /* 1458 * XXX assume that the setup message is 1459 * contained within one USB packet: 1460 */ 1461 xfer->endpoint->toggle_next = 1; 1462 } 1463 x = 1; 1464 } else { 1465 x = 0; 1466 } 1467 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1468 1469 /* set data toggle */ 1470 1471 if (xfer->endpoint->toggle_next) { 1472 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1473 } else { 1474 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1475 } 1476 1477 /* set endpoint direction */ 1478 1479 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1480 temp.td_flags |= htole32(OHCI_TD_IN); 1481 } else { 1482 temp.td_flags |= htole32(OHCI_TD_OUT); 1483 } 1484 1485 while (x != xfer->nframes) { 1486 1487 /* DATA0 / DATA1 message */ 1488 1489 temp.len = xfer->frlengths[x]; 1490 temp.pc = xfer->frbuffers + x; 1491 1492 x++; 1493 1494 if (x == xfer->nframes) { 1495 if (xfer->flags_int.control_xfr) { 1496 /* no STATUS stage yet, DATA is last */ 1497 if (xfer->flags_int.control_act) { 1498 temp.last_frame = 1; 1499 temp.setup_alt_next = 0; 1500 } 1501 } else { 1502 temp.last_frame = 1; 1503 temp.setup_alt_next = 0; 1504 } 1505 } 1506 if (temp.len == 0) { 1507 1508 /* make sure that we send an USB packet */ 1509 1510 temp.shortpkt = 0; 1511 1512 } else { 1513 1514 /* regular data transfer */ 1515 1516 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1517 } 1518 1519 ohci_setup_standard_chain_sub(&temp); 1520 } 1521 1522 /* check if we should append a status stage */ 1523 1524 if (xfer->flags_int.control_xfr && 1525 !xfer->flags_int.control_act) { 1526 1527 /* 1528 * Send a DATA1 message and invert the current endpoint 1529 * direction. 1530 */ 1531 1532 /* set endpoint direction and data toggle */ 1533 1534 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1535 temp.td_flags = htole32(OHCI_TD_OUT | 1536 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1537 } else { 1538 temp.td_flags = htole32(OHCI_TD_IN | 1539 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1540 } 1541 1542 temp.len = 0; 1543 temp.pc = NULL; 1544 temp.shortpkt = 0; 1545 temp.last_frame = 1; 1546 temp.setup_alt_next = 0; 1547 1548 ohci_setup_standard_chain_sub(&temp); 1549 } 1550 td = temp.td; 1551 1552 /* Ensure that last TD is terminating: */ 1553 td->td_next = htole32(OHCI_TD_NEXT_END); 1554 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1555 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1556 1557 usb_pc_cpu_flush(td->page_cache); 1558 1559 /* must have at least one frame! */ 1560 1561 xfer->td_transfer_last = td; 1562 1563#ifdef USB_DEBUG 1564 if (ohcidebug > 8) { 1565 DPRINTF("nexttog=%d; data before transfer:\n", 1566 xfer->endpoint->toggle_next); 1567 ohci_dump_tds(xfer->td_transfer_first); 1568 } 1569#endif 1570 1571 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1572 1573 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1574 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 1575 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1576 1577 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1578 1579 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1580 ed_flags |= OHCI_ED_SPEED; 1581 } 1582 ed->ed_flags = htole32(ed_flags); 1583 1584 td = xfer->td_transfer_first; 1585 1586 ed->ed_headp = td->td_self; 1587 1588 if (xfer->xroot->udev->flags.self_suspended == 0) { 1589 /* the append function will flush the endpoint descriptor */ 1590 OHCI_APPEND_QH(ed, *ed_last); 1591 1592 if (methods == &ohci_device_bulk_methods) { 1593 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1594 1595 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1596 } 1597 if (methods == &ohci_device_ctrl_methods) { 1598 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1599 1600 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1601 } 1602 } else { 1603 usb_pc_cpu_flush(ed->page_cache); 1604 } 1605} 1606 1607static void 1608ohci_root_intr(ohci_softc_t *sc) 1609{ 1610 uint32_t hstatus; 1611 uint16_t i; 1612 uint16_t m; 1613 1614 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1615 1616 /* clear any old interrupt data */ 1617 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 1618 1619 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1620 DPRINTF("sc=%p hstatus=0x%08x\n", 1621 sc, hstatus); 1622 1623 /* set bits */ 1624 m = (sc->sc_noport + 1); 1625 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1626 m = (8 * sizeof(sc->sc_hub_idata)); 1627 } 1628 for (i = 1; i < m; i++) { 1629 /* pick out CHANGE bits from the status register */ 1630 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1631 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1632 DPRINTF("port %d changed\n", i); 1633 } 1634 } 1635 1636 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1637 sizeof(sc->sc_hub_idata)); 1638} 1639 1640/* NOTE: "done" can be run two times in a row, 1641 * from close and from interrupt 1642 */ 1643static void 1644ohci_device_done(struct usb_xfer *xfer, usb_error_t error) 1645{ 1646 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1647 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1648 ohci_ed_t *ed; 1649 1650 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1651 1652 1653 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1654 xfer, xfer->endpoint, error); 1655 1656 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1657 if (ed) { 1658 usb_pc_cpu_invalidate(ed->page_cache); 1659 } 1660 if (methods == &ohci_device_bulk_methods) { 1661 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1662 } 1663 if (methods == &ohci_device_ctrl_methods) { 1664 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1665 } 1666 if (methods == &ohci_device_intr_methods) { 1667 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1668 } 1669 if (methods == &ohci_device_isoc_methods) { 1670 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1671 } 1672 xfer->td_transfer_first = NULL; 1673 xfer->td_transfer_last = NULL; 1674 1675 /* dequeue transfer and start next transfer */ 1676 usbd_transfer_done(xfer, error); 1677} 1678 1679/*------------------------------------------------------------------------* 1680 * ohci bulk support 1681 *------------------------------------------------------------------------*/ 1682static void 1683ohci_device_bulk_open(struct usb_xfer *xfer) 1684{ 1685 return; 1686} 1687 1688static void 1689ohci_device_bulk_close(struct usb_xfer *xfer) 1690{ 1691 ohci_device_done(xfer, USB_ERR_CANCELLED); 1692} 1693 1694static void 1695ohci_device_bulk_enter(struct usb_xfer *xfer) 1696{ 1697 return; 1698} 1699 1700static void 1701ohci_device_bulk_start(struct usb_xfer *xfer) 1702{ 1703 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1704 1705 /* setup TD's and QH */ 1706 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1707 1708 /* put transfer on interrupt queue */ 1709 ohci_transfer_intr_enqueue(xfer); 1710} 1711 1712struct usb_pipe_methods ohci_device_bulk_methods = 1713{ 1714 .open = ohci_device_bulk_open, 1715 .close = ohci_device_bulk_close, 1716 .enter = ohci_device_bulk_enter, 1717 .start = ohci_device_bulk_start, 1718}; 1719 1720/*------------------------------------------------------------------------* 1721 * ohci control support 1722 *------------------------------------------------------------------------*/ 1723static void 1724ohci_device_ctrl_open(struct usb_xfer *xfer) 1725{ 1726 return; 1727} 1728 1729static void 1730ohci_device_ctrl_close(struct usb_xfer *xfer) 1731{ 1732 ohci_device_done(xfer, USB_ERR_CANCELLED); 1733} 1734 1735static void 1736ohci_device_ctrl_enter(struct usb_xfer *xfer) 1737{ 1738 return; 1739} 1740 1741static void 1742ohci_device_ctrl_start(struct usb_xfer *xfer) 1743{ 1744 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1745 1746 /* setup TD's and QH */ 1747 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1748 1749 /* put transfer on interrupt queue */ 1750 ohci_transfer_intr_enqueue(xfer); 1751} 1752 1753struct usb_pipe_methods ohci_device_ctrl_methods = 1754{ 1755 .open = ohci_device_ctrl_open, 1756 .close = ohci_device_ctrl_close, 1757 .enter = ohci_device_ctrl_enter, 1758 .start = ohci_device_ctrl_start, 1759}; 1760 1761/*------------------------------------------------------------------------* 1762 * ohci interrupt support 1763 *------------------------------------------------------------------------*/ 1764static void 1765ohci_device_intr_open(struct usb_xfer *xfer) 1766{ 1767 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1768 uint16_t best; 1769 uint16_t bit; 1770 uint16_t x; 1771 1772 best = 0; 1773 bit = OHCI_NO_EDS / 2; 1774 while (bit) { 1775 if (xfer->interval >= bit) { 1776 x = bit; 1777 best = bit; 1778 while (x & bit) { 1779 if (sc->sc_intr_stat[x] < 1780 sc->sc_intr_stat[best]) { 1781 best = x; 1782 } 1783 x++; 1784 } 1785 break; 1786 } 1787 bit >>= 1; 1788 } 1789 1790 sc->sc_intr_stat[best]++; 1791 xfer->qh_pos = best; 1792 1793 DPRINTFN(3, "best=%d interval=%d\n", 1794 best, xfer->interval); 1795} 1796 1797static void 1798ohci_device_intr_close(struct usb_xfer *xfer) 1799{ 1800 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1801 1802 sc->sc_intr_stat[xfer->qh_pos]--; 1803 1804 ohci_device_done(xfer, USB_ERR_CANCELLED); 1805} 1806 1807static void 1808ohci_device_intr_enter(struct usb_xfer *xfer) 1809{ 1810 return; 1811} 1812 1813static void 1814ohci_device_intr_start(struct usb_xfer *xfer) 1815{ 1816 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1817 1818 /* setup TD's and QH */ 1819 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1820 1821 /* put transfer on interrupt queue */ 1822 ohci_transfer_intr_enqueue(xfer); 1823} 1824 1825struct usb_pipe_methods ohci_device_intr_methods = 1826{ 1827 .open = ohci_device_intr_open, 1828 .close = ohci_device_intr_close, 1829 .enter = ohci_device_intr_enter, 1830 .start = ohci_device_intr_start, 1831}; 1832 1833/*------------------------------------------------------------------------* 1834 * ohci isochronous support 1835 *------------------------------------------------------------------------*/ 1836static void 1837ohci_device_isoc_open(struct usb_xfer *xfer) 1838{ 1839 return; 1840} 1841 1842static void 1843ohci_device_isoc_close(struct usb_xfer *xfer) 1844{ 1845 /**/ 1846 ohci_device_done(xfer, USB_ERR_CANCELLED); 1847} 1848 1849static void 1850ohci_device_isoc_enter(struct usb_xfer *xfer) 1851{ 1852 struct usb_page_search buf_res; 1853 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1854 struct ohci_hcca *hcca; 1855 uint32_t buf_offset; 1856 uint32_t nframes; 1857 uint32_t ed_flags; 1858 uint32_t *plen; 1859 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1860 uint16_t length; 1861 uint8_t ncur; 1862 ohci_itd_t *td; 1863 ohci_itd_t *td_last = NULL; 1864 ohci_ed_t *ed; 1865 1866 hcca = ohci_get_hcca(sc); 1867 1868 nframes = le32toh(hcca->hcca_frame_number); 1869 1870 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1871 xfer, xfer->endpoint->isoc_next, xfer->nframes, nframes); 1872 1873 if ((xfer->endpoint->is_synced == 0) || 1874 (((nframes - xfer->endpoint->isoc_next) & 0xFFFF) < xfer->nframes) || 1875 (((xfer->endpoint->isoc_next - nframes) & 0xFFFF) >= 128)) { 1876 /* 1877 * If there is data underflow or the pipe queue is empty we 1878 * schedule the transfer a few frames ahead of the current 1879 * frame position. Else two isochronous transfers might 1880 * overlap. 1881 */ 1882 xfer->endpoint->isoc_next = (nframes + 3) & 0xFFFF; 1883 xfer->endpoint->is_synced = 1; 1884 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1885 } 1886 /* 1887 * compute how many milliseconds the insertion is ahead of the 1888 * current frame position: 1889 */ 1890 buf_offset = ((xfer->endpoint->isoc_next - nframes) & 0xFFFF); 1891 1892 /* 1893 * pre-compute when the isochronous transfer will be finished: 1894 */ 1895 xfer->isoc_time_complete = 1896 (usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1897 xfer->nframes); 1898 1899 /* get the real number of frames */ 1900 1901 nframes = xfer->nframes; 1902 1903 buf_offset = 0; 1904 1905 plen = xfer->frlengths; 1906 1907 /* toggle the DMA set we are using */ 1908 xfer->flags_int.curr_dma_set ^= 1; 1909 1910 /* get next DMA set */ 1911 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1912 1913 xfer->td_transfer_first = td; 1914 1915 ncur = 0; 1916 length = 0; 1917 1918 while (nframes--) { 1919 if (td == NULL) { 1920 panic("%s:%d: out of TD's\n", 1921 __FUNCTION__, __LINE__); 1922 } 1923 itd_offset[ncur] = length; 1924 buf_offset += *plen; 1925 length += *plen; 1926 plen++; 1927 ncur++; 1928 1929 if ( /* check if the ITD is full */ 1930 (ncur == OHCI_ITD_NOFFSET) || 1931 /* check if we have put more than 4K into the ITD */ 1932 (length & 0xF000) || 1933 /* check if it is the last frame */ 1934 (nframes == 0)) { 1935 1936 /* fill current ITD */ 1937 td->itd_flags = htole32( 1938 OHCI_ITD_NOCC | 1939 OHCI_ITD_SET_SF(xfer->endpoint->isoc_next) | 1940 OHCI_ITD_NOINTR | 1941 OHCI_ITD_SET_FC(ncur)); 1942 1943 td->frames = ncur; 1944 xfer->endpoint->isoc_next += ncur; 1945 1946 if (length == 0) { 1947 /* all zero */ 1948 td->itd_bp0 = 0; 1949 td->itd_be = ~0; 1950 1951 while (ncur--) { 1952 td->itd_offset[ncur] = 1953 htole16(OHCI_ITD_MK_OFFS(0)); 1954 } 1955 } else { 1956 usbd_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1957 length = OHCI_PAGE_MASK(buf_res.physaddr); 1958 buf_res.physaddr = 1959 OHCI_PAGE(buf_res.physaddr); 1960 td->itd_bp0 = htole32(buf_res.physaddr); 1961 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1962 td->itd_be = htole32(buf_res.physaddr); 1963 1964 while (ncur--) { 1965 itd_offset[ncur] += length; 1966 itd_offset[ncur] = 1967 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1968 td->itd_offset[ncur] = 1969 htole16(itd_offset[ncur]); 1970 } 1971 } 1972 ncur = 0; 1973 length = 0; 1974 td_last = td; 1975 td = td->obj_next; 1976 1977 if (td) { 1978 /* link the last TD with the next one */ 1979 td_last->itd_next = td->itd_self; 1980 } 1981 usb_pc_cpu_flush(td_last->page_cache); 1982 } 1983 } 1984 1985 /* update the last TD */ 1986 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 1987 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 1988 td_last->itd_next = 0; 1989 1990 usb_pc_cpu_flush(td_last->page_cache); 1991 1992 xfer->td_transfer_last = td_last; 1993 1994#ifdef USB_DEBUG 1995 if (ohcidebug > 8) { 1996 DPRINTF("data before transfer:\n"); 1997 ohci_dump_itds(xfer->td_transfer_first); 1998 } 1999#endif 2000 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2001 2002 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2003 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 2004 else 2005 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 2006 2007 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 2008 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 2009 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 2010 2011 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 2012 ed_flags |= OHCI_ED_SPEED; 2013 } 2014 ed->ed_flags = htole32(ed_flags); 2015 2016 td = xfer->td_transfer_first; 2017 2018 ed->ed_headp = td->itd_self; 2019 2020 /* isochronous transfers are not affected by suspend / resume */ 2021 /* the append function will flush the endpoint descriptor */ 2022 2023 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2024} 2025 2026static void 2027ohci_device_isoc_start(struct usb_xfer *xfer) 2028{ 2029 /* put transfer on interrupt queue */ 2030 ohci_transfer_intr_enqueue(xfer); 2031} 2032 2033struct usb_pipe_methods ohci_device_isoc_methods = 2034{ 2035 .open = ohci_device_isoc_open, 2036 .close = ohci_device_isoc_close, 2037 .enter = ohci_device_isoc_enter, 2038 .start = ohci_device_isoc_start, 2039}; 2040 2041/*------------------------------------------------------------------------* 2042 * ohci root control support 2043 *------------------------------------------------------------------------* 2044 * Simulate a hardware hub by handling all the necessary requests. 2045 *------------------------------------------------------------------------*/ 2046 2047static const 2048struct usb_device_descriptor ohci_devd = 2049{ 2050 sizeof(struct usb_device_descriptor), 2051 UDESC_DEVICE, /* type */ 2052 {0x00, 0x01}, /* USB version */ 2053 UDCLASS_HUB, /* class */ 2054 UDSUBCLASS_HUB, /* subclass */ 2055 UDPROTO_FSHUB, /* protocol */ 2056 64, /* max packet */ 2057 {0}, {0}, {0x00, 0x01}, /* device id */ 2058 1, 2, 0, /* string indicies */ 2059 1 /* # of configurations */ 2060}; 2061 2062static const 2063struct ohci_config_desc ohci_confd = 2064{ 2065 .confd = { 2066 .bLength = sizeof(struct usb_config_descriptor), 2067 .bDescriptorType = UDESC_CONFIG, 2068 .wTotalLength[0] = sizeof(ohci_confd), 2069 .bNumInterface = 1, 2070 .bConfigurationValue = 1, 2071 .iConfiguration = 0, 2072 .bmAttributes = UC_SELF_POWERED, 2073 .bMaxPower = 0, /* max power */ 2074 }, 2075 .ifcd = { 2076 .bLength = sizeof(struct usb_interface_descriptor), 2077 .bDescriptorType = UDESC_INTERFACE, 2078 .bNumEndpoints = 1, 2079 .bInterfaceClass = UICLASS_HUB, 2080 .bInterfaceSubClass = UISUBCLASS_HUB, 2081 .bInterfaceProtocol = UIPROTO_FSHUB, 2082 }, 2083 .endpd = { 2084 .bLength = sizeof(struct usb_endpoint_descriptor), 2085 .bDescriptorType = UDESC_ENDPOINT, 2086 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2087 .bmAttributes = UE_INTERRUPT, 2088 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2089 .bInterval = 255, 2090 }, 2091}; 2092 2093static const 2094struct usb_hub_descriptor ohci_hubd = 2095{ 2096 0, /* dynamic length */ 2097 UDESC_HUB, 2098 0, 2099 {0, 0}, 2100 0, 2101 0, 2102 {0}, 2103}; 2104 2105static usb_error_t 2106ohci_roothub_exec(struct usb_device *udev, 2107 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2108{ 2109 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2110 const void *ptr; 2111 const char *str_ptr; 2112 uint32_t port; 2113 uint32_t v; 2114 uint16_t len; 2115 uint16_t value; 2116 uint16_t index; 2117 uint8_t l; 2118 usb_error_t err; 2119 2120 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2121 2122 /* buffer reset */ 2123 ptr = (const void *)&sc->sc_hub_desc.temp; 2124 len = 0; 2125 err = 0; 2126 2127 value = UGETW(req->wValue); 2128 index = UGETW(req->wIndex); 2129 2130 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2131 "wValue=0x%04x wIndex=0x%04x\n", 2132 req->bmRequestType, req->bRequest, 2133 UGETW(req->wLength), value, index); 2134 2135#define C(x,y) ((x) | ((y) << 8)) 2136 switch (C(req->bRequest, req->bmRequestType)) { 2137 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2138 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2139 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2140 /* 2141 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2142 * for the integrated root hub. 2143 */ 2144 break; 2145 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2146 len = 1; 2147 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2148 break; 2149 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2150 switch (value >> 8) { 2151 case UDESC_DEVICE: 2152 if ((value & 0xff) != 0) { 2153 err = USB_ERR_IOERROR; 2154 goto done; 2155 } 2156 len = sizeof(ohci_devd); 2157 ptr = (const void *)&ohci_devd; 2158 break; 2159 2160 case UDESC_CONFIG: 2161 if ((value & 0xff) != 0) { 2162 err = USB_ERR_IOERROR; 2163 goto done; 2164 } 2165 len = sizeof(ohci_confd); 2166 ptr = (const void *)&ohci_confd; 2167 break; 2168 2169 case UDESC_STRING: 2170 switch (value & 0xff) { 2171 case 0: /* Language table */ 2172 str_ptr = "\001"; 2173 break; 2174 2175 case 1: /* Vendor */ 2176 str_ptr = sc->sc_vendor; 2177 break; 2178 2179 case 2: /* Product */ 2180 str_ptr = "OHCI root HUB"; 2181 break; 2182 2183 default: 2184 str_ptr = ""; 2185 break; 2186 } 2187 2188 len = usb_make_str_desc( 2189 sc->sc_hub_desc.temp, 2190 sizeof(sc->sc_hub_desc.temp), 2191 str_ptr); 2192 break; 2193 2194 default: 2195 err = USB_ERR_IOERROR; 2196 goto done; 2197 } 2198 break; 2199 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2200 len = 1; 2201 sc->sc_hub_desc.temp[0] = 0; 2202 break; 2203 case C(UR_GET_STATUS, UT_READ_DEVICE): 2204 len = 2; 2205 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2206 break; 2207 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2208 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2209 len = 2; 2210 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2211 break; 2212 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2213 if (value >= OHCI_MAX_DEVICES) { 2214 err = USB_ERR_IOERROR; 2215 goto done; 2216 } 2217 sc->sc_addr = value; 2218 break; 2219 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2220 if ((value != 0) && (value != 1)) { 2221 err = USB_ERR_IOERROR; 2222 goto done; 2223 } 2224 sc->sc_conf = value; 2225 break; 2226 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2227 break; 2228 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2229 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2230 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2231 err = USB_ERR_IOERROR; 2232 goto done; 2233 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2234 break; 2235 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2236 break; 2237 /* Hub requests */ 2238 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2239 break; 2240 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2241 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2242 "port=%d feature=%d\n", 2243 index, value); 2244 if ((index < 1) || 2245 (index > sc->sc_noport)) { 2246 err = USB_ERR_IOERROR; 2247 goto done; 2248 } 2249 port = OHCI_RH_PORT_STATUS(index); 2250 switch (value) { 2251 case UHF_PORT_ENABLE: 2252 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2253 break; 2254 case UHF_PORT_SUSPEND: 2255 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2256 break; 2257 case UHF_PORT_POWER: 2258 /* Yes, writing to the LOW_SPEED bit clears power. */ 2259 OWRITE4(sc, port, UPS_LOW_SPEED); 2260 break; 2261 case UHF_C_PORT_CONNECTION: 2262 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2263 break; 2264 case UHF_C_PORT_ENABLE: 2265 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2266 break; 2267 case UHF_C_PORT_SUSPEND: 2268 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2269 break; 2270 case UHF_C_PORT_OVER_CURRENT: 2271 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2272 break; 2273 case UHF_C_PORT_RESET: 2274 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2275 break; 2276 default: 2277 err = USB_ERR_IOERROR; 2278 goto done; 2279 } 2280 switch (value) { 2281 case UHF_C_PORT_CONNECTION: 2282 case UHF_C_PORT_ENABLE: 2283 case UHF_C_PORT_SUSPEND: 2284 case UHF_C_PORT_OVER_CURRENT: 2285 case UHF_C_PORT_RESET: 2286 /* enable RHSC interrupt if condition is cleared. */ 2287 if ((OREAD4(sc, port) >> 16) == 0) 2288 ohci_rhsc_enable(sc); 2289 break; 2290 default: 2291 break; 2292 } 2293 break; 2294 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2295 if ((value & 0xff) != 0) { 2296 err = USB_ERR_IOERROR; 2297 goto done; 2298 } 2299 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2300 2301 sc->sc_hub_desc.hubd = ohci_hubd; 2302 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2303 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2304 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2305 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2306 /* XXX overcurrent */ 2307 ); 2308 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2309 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2310 2311 for (l = 0; l < sc->sc_noport; l++) { 2312 if (v & 1) { 2313 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2314 } 2315 v >>= 1; 2316 } 2317 sc->sc_hub_desc.hubd.bDescLength = 2318 8 + ((sc->sc_noport + 7) / 8); 2319 len = sc->sc_hub_desc.hubd.bDescLength; 2320 break; 2321 2322 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2323 len = 16; 2324 bzero(sc->sc_hub_desc.temp, 16); 2325 break; 2326 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2327 DPRINTFN(9, "get port status i=%d\n", 2328 index); 2329 if ((index < 1) || 2330 (index > sc->sc_noport)) { 2331 err = USB_ERR_IOERROR; 2332 goto done; 2333 } 2334 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2335 DPRINTFN(9, "port status=0x%04x\n", v); 2336 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2337 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2338 len = sizeof(sc->sc_hub_desc.ps); 2339 break; 2340 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2341 err = USB_ERR_IOERROR; 2342 goto done; 2343 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2344 break; 2345 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2346 if ((index < 1) || 2347 (index > sc->sc_noport)) { 2348 err = USB_ERR_IOERROR; 2349 goto done; 2350 } 2351 port = OHCI_RH_PORT_STATUS(index); 2352 switch (value) { 2353 case UHF_PORT_ENABLE: 2354 OWRITE4(sc, port, UPS_PORT_ENABLED); 2355 break; 2356 case UHF_PORT_SUSPEND: 2357 OWRITE4(sc, port, UPS_SUSPEND); 2358 break; 2359 case UHF_PORT_RESET: 2360 DPRINTFN(6, "reset port %d\n", index); 2361 OWRITE4(sc, port, UPS_RESET); 2362 for (v = 0;; v++) { 2363 if (v < 12) { 2364 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2365 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2366 2367 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2368 break; 2369 } 2370 } else { 2371 err = USB_ERR_TIMEOUT; 2372 goto done; 2373 } 2374 } 2375 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2376 index, OREAD4(sc, port)); 2377 break; 2378 case UHF_PORT_POWER: 2379 DPRINTFN(3, "set port power %d\n", index); 2380 OWRITE4(sc, port, UPS_PORT_POWER); 2381 break; 2382 default: 2383 err = USB_ERR_IOERROR; 2384 goto done; 2385 } 2386 break; 2387 default: 2388 err = USB_ERR_IOERROR; 2389 goto done; 2390 } 2391done: 2392 *plength = len; 2393 *pptr = ptr; 2394 return (err); 2395} 2396 2397static void 2398ohci_xfer_setup(struct usb_setup_params *parm) 2399{ 2400 struct usb_page_search page_info; 2401 struct usb_page_cache *pc; 2402 ohci_softc_t *sc; 2403 struct usb_xfer *xfer; 2404 void *last_obj; 2405 uint32_t ntd; 2406 uint32_t nitd; 2407 uint32_t nqh; 2408 uint32_t n; 2409 2410 sc = OHCI_BUS2SC(parm->udev->bus); 2411 xfer = parm->curr_xfer; 2412 2413 parm->hc_max_packet_size = 0x500; 2414 parm->hc_max_packet_count = 1; 2415 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2416 2417 /* 2418 * calculate ntd and nqh 2419 */ 2420 if (parm->methods == &ohci_device_ctrl_methods) { 2421 xfer->flags_int.bdma_enable = 1; 2422 2423 usbd_transfer_setup_sub(parm); 2424 2425 nitd = 0; 2426 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2427 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2428 nqh = 1; 2429 2430 } else if (parm->methods == &ohci_device_bulk_methods) { 2431 xfer->flags_int.bdma_enable = 1; 2432 2433 usbd_transfer_setup_sub(parm); 2434 2435 nitd = 0; 2436 ntd = ((2 * xfer->nframes) 2437 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2438 nqh = 1; 2439 2440 } else if (parm->methods == &ohci_device_intr_methods) { 2441 xfer->flags_int.bdma_enable = 1; 2442 2443 usbd_transfer_setup_sub(parm); 2444 2445 nitd = 0; 2446 ntd = ((2 * xfer->nframes) 2447 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2448 nqh = 1; 2449 2450 } else if (parm->methods == &ohci_device_isoc_methods) { 2451 xfer->flags_int.bdma_enable = 1; 2452 2453 usbd_transfer_setup_sub(parm); 2454 2455 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2456 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2457 1 /* EXTRA */ ); 2458 ntd = 0; 2459 nqh = 1; 2460 2461 } else { 2462 2463 usbd_transfer_setup_sub(parm); 2464 2465 nitd = 0; 2466 ntd = 0; 2467 nqh = 0; 2468 } 2469 2470alloc_dma_set: 2471 2472 if (parm->err) { 2473 return; 2474 } 2475 last_obj = NULL; 2476 2477 if (usbd_transfer_setup_sub_malloc( 2478 parm, &pc, sizeof(ohci_td_t), 2479 OHCI_TD_ALIGN, ntd)) { 2480 parm->err = USB_ERR_NOMEM; 2481 return; 2482 } 2483 if (parm->buf) { 2484 for (n = 0; n != ntd; n++) { 2485 ohci_td_t *td; 2486 2487 usbd_get_page(pc + n, 0, &page_info); 2488 2489 td = page_info.buffer; 2490 2491 /* init TD */ 2492 td->td_self = htole32(page_info.physaddr); 2493 td->obj_next = last_obj; 2494 td->page_cache = pc + n; 2495 2496 last_obj = td; 2497 2498 usb_pc_cpu_flush(pc + n); 2499 } 2500 } 2501 if (usbd_transfer_setup_sub_malloc( 2502 parm, &pc, sizeof(ohci_itd_t), 2503 OHCI_ITD_ALIGN, nitd)) { 2504 parm->err = USB_ERR_NOMEM; 2505 return; 2506 } 2507 if (parm->buf) { 2508 for (n = 0; n != nitd; n++) { 2509 ohci_itd_t *itd; 2510 2511 usbd_get_page(pc + n, 0, &page_info); 2512 2513 itd = page_info.buffer; 2514 2515 /* init TD */ 2516 itd->itd_self = htole32(page_info.physaddr); 2517 itd->obj_next = last_obj; 2518 itd->page_cache = pc + n; 2519 2520 last_obj = itd; 2521 2522 usb_pc_cpu_flush(pc + n); 2523 } 2524 } 2525 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2526 2527 last_obj = NULL; 2528 2529 if (usbd_transfer_setup_sub_malloc( 2530 parm, &pc, sizeof(ohci_ed_t), 2531 OHCI_ED_ALIGN, nqh)) { 2532 parm->err = USB_ERR_NOMEM; 2533 return; 2534 } 2535 if (parm->buf) { 2536 for (n = 0; n != nqh; n++) { 2537 ohci_ed_t *ed; 2538 2539 usbd_get_page(pc + n, 0, &page_info); 2540 2541 ed = page_info.buffer; 2542 2543 /* init QH */ 2544 ed->ed_self = htole32(page_info.physaddr); 2545 ed->obj_next = last_obj; 2546 ed->page_cache = pc + n; 2547 2548 last_obj = ed; 2549 2550 usb_pc_cpu_flush(pc + n); 2551 } 2552 } 2553 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2554 2555 if (!xfer->flags_int.curr_dma_set) { 2556 xfer->flags_int.curr_dma_set = 1; 2557 goto alloc_dma_set; 2558 } 2559} 2560 2561static void 2562ohci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2563 struct usb_endpoint *ep) 2564{ 2565 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2566 2567 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2568 ep, udev->address, 2569 edesc->bEndpointAddress, udev->flags.usb_mode, 2570 sc->sc_addr); 2571 2572 if (udev->flags.usb_mode != USB_MODE_HOST) { 2573 /* not supported */ 2574 return; 2575 } 2576 if (udev->device_index != sc->sc_addr) { 2577 switch (edesc->bmAttributes & UE_XFERTYPE) { 2578 case UE_CONTROL: 2579 ep->methods = &ohci_device_ctrl_methods; 2580 break; 2581 case UE_INTERRUPT: 2582 ep->methods = &ohci_device_intr_methods; 2583 break; 2584 case UE_ISOCHRONOUS: 2585 if (udev->speed == USB_SPEED_FULL) { 2586 ep->methods = &ohci_device_isoc_methods; 2587 } 2588 break; 2589 case UE_BULK: 2590 if (udev->speed != USB_SPEED_LOW) { 2591 ep->methods = &ohci_device_bulk_methods; 2592 } 2593 break; 2594 default: 2595 /* do nothing */ 2596 break; 2597 } 2598 } 2599} 2600 2601static void 2602ohci_xfer_unsetup(struct usb_xfer *xfer) 2603{ 2604 return; 2605} 2606 2607static void 2608ohci_get_dma_delay(struct usb_bus *bus, uint32_t *pus) 2609{ 2610 /* 2611 * Wait until hardware has finished any possible use of the 2612 * transfer descriptor(s) and QH 2613 */ 2614 *pus = (1125); /* microseconds */ 2615} 2616 2617static void 2618ohci_device_resume(struct usb_device *udev) 2619{ 2620 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2621 struct usb_xfer *xfer; 2622 struct usb_pipe_methods *methods; 2623 ohci_ed_t *ed; 2624 2625 DPRINTF("\n"); 2626 2627 USB_BUS_LOCK(udev->bus); 2628 2629 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2630 2631 if (xfer->xroot->udev == udev) { 2632 2633 methods = xfer->endpoint->methods; 2634 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2635 2636 if (methods == &ohci_device_bulk_methods) { 2637 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2638 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2639 } 2640 if (methods == &ohci_device_ctrl_methods) { 2641 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2642 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2643 } 2644 if (methods == &ohci_device_intr_methods) { 2645 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2646 } 2647 } 2648 } 2649 2650 USB_BUS_UNLOCK(udev->bus); 2651 2652 return; 2653} 2654 2655static void 2656ohci_device_suspend(struct usb_device *udev) 2657{ 2658 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2659 struct usb_xfer *xfer; 2660 struct usb_pipe_methods *methods; 2661 ohci_ed_t *ed; 2662 2663 DPRINTF("\n"); 2664 2665 USB_BUS_LOCK(udev->bus); 2666 2667 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2668 2669 if (xfer->xroot->udev == udev) { 2670 2671 methods = xfer->endpoint->methods; 2672 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2673 2674 if (methods == &ohci_device_bulk_methods) { 2675 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2676 } 2677 if (methods == &ohci_device_ctrl_methods) { 2678 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2679 } 2680 if (methods == &ohci_device_intr_methods) { 2681 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2682 } 2683 } 2684 } 2685 2686 USB_BUS_UNLOCK(udev->bus); 2687 2688 return; 2689} 2690 2691static void 2692ohci_set_hw_power(struct usb_bus *bus) 2693{ 2694 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2695 uint32_t temp; 2696 uint32_t flags; 2697 2698 DPRINTF("\n"); 2699 2700 USB_BUS_LOCK(bus); 2701 2702 flags = bus->hw_power_state; 2703 2704 temp = OREAD4(sc, OHCI_CONTROL); 2705 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2706 2707 if (flags & USB_HW_POWER_CONTROL) 2708 temp |= OHCI_CLE; 2709 2710 if (flags & USB_HW_POWER_BULK) 2711 temp |= OHCI_BLE; 2712 2713 if (flags & USB_HW_POWER_INTERRUPT) 2714 temp |= OHCI_PLE; 2715 2716 if (flags & USB_HW_POWER_ISOC) 2717 temp |= OHCI_IE | OHCI_PLE; 2718 2719 OWRITE4(sc, OHCI_CONTROL, temp); 2720 2721 USB_BUS_UNLOCK(bus); 2722 2723 return; 2724} 2725 2726struct usb_bus_methods ohci_bus_methods = 2727{ 2728 .endpoint_init = ohci_ep_init, 2729 .xfer_setup = ohci_xfer_setup, 2730 .xfer_unsetup = ohci_xfer_unsetup, 2731 .get_dma_delay = ohci_get_dma_delay, 2732 .device_resume = ohci_device_resume, 2733 .device_suspend = ohci_device_suspend, 2734 .set_hw_power = ohci_set_hw_power, 2735 .roothub_exec = ohci_roothub_exec, 2736 .xfer_poll = ohci_do_poll, 2737}; 2738