ohci.c revision 190738
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/usb/controller/ohci.c 190738 2009-04-05 18:21:21Z thompsa $"); 30 31/* 32 * USB Open Host Controller driver. 33 * 34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 */ 37 38#include <dev/usb/usb.h> 39#include <dev/usb/usb_mfunc.h> 40#include <dev/usb/usb_error.h> 41 42#define USB_DEBUG_VAR ohcidebug 43 44#include <dev/usb/usb_core.h> 45#include <dev/usb/usb_debug.h> 46#include <dev/usb/usb_busdma.h> 47#include <dev/usb/usb_process.h> 48#include <dev/usb/usb_sw_transfer.h> 49#include <dev/usb/usb_transfer.h> 50#include <dev/usb/usb_device.h> 51#include <dev/usb/usb_hub.h> 52#include <dev/usb/usb_util.h> 53 54#include <dev/usb/usb_controller.h> 55#include <dev/usb/usb_bus.h> 56#include <dev/usb/controller/ohci.h> 57 58#define OHCI_BUS2SC(bus) \ 59 ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 60 ((uint8_t *)&(((ohci_softc_t *)0)->sc_bus)))) 61 62#if USB_DEBUG 63static int ohcidebug = 0; 64 65SYSCTL_NODE(_hw_usb2, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 66SYSCTL_INT(_hw_usb2_ohci, OID_AUTO, debug, CTLFLAG_RW, 67 &ohcidebug, 0, "ohci debug level"); 68static void ohci_dumpregs(ohci_softc_t *); 69static void ohci_dump_tds(ohci_td_t *); 70static uint8_t ohci_dump_td(ohci_td_t *); 71static void ohci_dump_ed(ohci_ed_t *); 72static uint8_t ohci_dump_itd(ohci_itd_t *); 73static void ohci_dump_itds(ohci_itd_t *); 74 75#endif 76 77#define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 78 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 79#define OWRITE1(sc, r, x) \ 80 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 81#define OWRITE2(sc, r, x) \ 82 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 83#define OWRITE4(sc, r, x) \ 84 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 85#define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 86#define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 87#define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 88 89#define OHCI_INTR_ENDPT 1 90 91extern struct usb2_bus_methods ohci_bus_methods; 92extern struct usb2_pipe_methods ohci_device_bulk_methods; 93extern struct usb2_pipe_methods ohci_device_ctrl_methods; 94extern struct usb2_pipe_methods ohci_device_intr_methods; 95extern struct usb2_pipe_methods ohci_device_isoc_methods; 96 97static void ohci_do_poll(struct usb2_bus *bus); 98static void ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 99static void ohci_timeout(void *arg); 100static uint8_t ohci_check_transfer(struct usb2_xfer *xfer); 101static void ohci_root_intr(ohci_softc_t *sc); 102 103struct ohci_std_temp { 104 struct usb2_page_cache *pc; 105 ohci_td_t *td; 106 ohci_td_t *td_next; 107 uint32_t average; 108 uint32_t td_flags; 109 uint32_t len; 110 uint16_t max_frame_size; 111 uint8_t shortpkt; 112 uint8_t setup_alt_next; 113 uint8_t last_frame; 114}; 115 116static struct ohci_hcca * 117ohci_get_hcca(ohci_softc_t *sc) 118{ 119 usb2_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 120 return (sc->sc_hcca_p); 121} 122 123void 124ohci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 125{ 126 struct ohci_softc *sc = OHCI_BUS2SC(bus); 127 uint32_t i; 128 129 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 130 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 131 132 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 133 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 134 135 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 136 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 137 138 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 139 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 140 141 for (i = 0; i != OHCI_NO_EDS; i++) { 142 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 143 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 144 } 145} 146 147static usb2_error_t 148ohci_controller_init(ohci_softc_t *sc) 149{ 150 struct usb2_page_search buf_res; 151 uint32_t i; 152 uint32_t ctl; 153 uint32_t ival; 154 uint32_t hcr; 155 uint32_t fm; 156 uint32_t per; 157 uint32_t desca; 158 159 /* Determine in what context we are running. */ 160 ctl = OREAD4(sc, OHCI_CONTROL); 161 if (ctl & OHCI_IR) { 162 /* SMM active, request change */ 163 DPRINTF("SMM active, request owner change\n"); 164 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 165 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 166 usb2_pause_mtx(NULL, hz / 1000); 167 ctl = OREAD4(sc, OHCI_CONTROL); 168 } 169 if (ctl & OHCI_IR) { 170 device_printf(sc->sc_bus.bdev, 171 "SMM does not respond, resetting\n"); 172 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 173 goto reset; 174 } 175 } else { 176 DPRINTF("cold started\n"); 177reset: 178 /* controller was cold started */ 179 usb2_pause_mtx(NULL, 180 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 181 } 182 183 /* 184 * This reset should not be necessary according to the OHCI spec, but 185 * without it some controllers do not start. 186 */ 187 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 188 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 189 190 usb2_pause_mtx(NULL, 191 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 192 193 /* we now own the host controller and the bus has been reset */ 194 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 195 196 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 197 /* nominal time for a reset is 10 us */ 198 for (i = 0; i < 10; i++) { 199 DELAY(10); 200 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 201 if (!hcr) { 202 break; 203 } 204 } 205 if (hcr) { 206 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 207 return (USB_ERR_IOERROR); 208 } 209#if USB_DEBUG 210 if (ohcidebug > 15) { 211 ohci_dumpregs(sc); 212 } 213#endif 214 215 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 216 217 /* set up HC registers */ 218 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 219 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 220 221 usb2_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 222 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 223 224 usb2_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 225 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 226 227 /* disable all interrupts and then switch on all desired interrupts */ 228 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 229 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 230 /* switch on desired functional features */ 231 ctl = OREAD4(sc, OHCI_CONTROL); 232 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 233 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 234 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 235 /* And finally start it! */ 236 OWRITE4(sc, OHCI_CONTROL, ctl); 237 238 /* 239 * The controller is now OPERATIONAL. Set a some final 240 * registers that should be set earlier, but that the 241 * controller ignores when in the SUSPEND state. 242 */ 243 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 244 fm |= OHCI_FSMPS(ival) | ival; 245 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 246 per = OHCI_PERIODIC(ival); /* 90% periodic */ 247 OWRITE4(sc, OHCI_PERIODIC_START, per); 248 249 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 250 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 251 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 252 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 253 usb2_pause_mtx(NULL, 254 USB_MS_TO_TICKS(OHCI_ENABLE_POWER_DELAY)); 255 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 256 257 /* 258 * The AMD756 requires a delay before re-reading the register, 259 * otherwise it will occasionally report 0 ports. 260 */ 261 sc->sc_noport = 0; 262 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 263 usb2_pause_mtx(NULL, 264 USB_MS_TO_TICKS(OHCI_READ_DESC_DELAY)); 265 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 266 } 267 268#if USB_DEBUG 269 if (ohcidebug > 5) { 270 ohci_dumpregs(sc); 271 } 272#endif 273 return (USB_ERR_NORMAL_COMPLETION); 274} 275 276static struct ohci_ed * 277ohci_init_ed(struct usb2_page_cache *pc) 278{ 279 struct usb2_page_search buf_res; 280 struct ohci_ed *ed; 281 282 usb2_get_page(pc, 0, &buf_res); 283 284 ed = buf_res.buffer; 285 286 ed->ed_self = htole32(buf_res.physaddr); 287 ed->ed_flags = htole32(OHCI_ED_SKIP); 288 ed->page_cache = pc; 289 290 return (ed); 291} 292 293usb2_error_t 294ohci_init(ohci_softc_t *sc) 295{ 296 struct usb2_page_search buf_res; 297 uint16_t i; 298 uint16_t bit; 299 uint16_t x; 300 uint16_t y; 301 302 DPRINTF("start\n"); 303 304 sc->sc_eintrs = OHCI_NORMAL_INTRS; 305 306 /* 307 * Setup all ED's 308 */ 309 310 sc->sc_ctrl_p_last = 311 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 312 313 sc->sc_bulk_p_last = 314 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 315 316 sc->sc_isoc_p_last = 317 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 318 319 for (i = 0; i != OHCI_NO_EDS; i++) { 320 sc->sc_intr_p_last[i] = 321 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 322 } 323 324 /* 325 * the QHs are arranged to give poll intervals that are 326 * powers of 2 times 1ms 327 */ 328 bit = OHCI_NO_EDS / 2; 329 while (bit) { 330 x = bit; 331 while (x & bit) { 332 ohci_ed_t *ed_x; 333 ohci_ed_t *ed_y; 334 335 y = (x ^ bit) | (bit / 2); 336 337 /* 338 * the next QH has half the poll interval 339 */ 340 ed_x = sc->sc_intr_p_last[x]; 341 ed_y = sc->sc_intr_p_last[y]; 342 343 ed_x->next = NULL; 344 ed_x->ed_next = ed_y->ed_self; 345 346 x++; 347 } 348 bit >>= 1; 349 } 350 351 if (1) { 352 353 ohci_ed_t *ed_int; 354 ohci_ed_t *ed_isc; 355 356 ed_int = sc->sc_intr_p_last[0]; 357 ed_isc = sc->sc_isoc_p_last; 358 359 /* the last (1ms) QH */ 360 ed_int->next = ed_isc; 361 ed_int->ed_next = ed_isc->ed_self; 362 } 363 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 364 365 sc->sc_hcca_p = buf_res.buffer; 366 367 /* 368 * Fill HCCA interrupt table. The bit reversal is to get 369 * the tree set up properly to spread the interrupts. 370 */ 371 for (i = 0; i != OHCI_NO_INTRS; i++) { 372 sc->sc_hcca_p->hcca_interrupt_table[i] = 373 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 374 } 375 /* flush all cache into memory */ 376 377 usb2_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 378 379 /* set up the bus struct */ 380 sc->sc_bus.methods = &ohci_bus_methods; 381 382 usb2_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 383 384#if USB_DEBUG 385 if (ohcidebug > 15) { 386 for (i = 0; i != OHCI_NO_EDS; i++) { 387 printf("ed#%d ", i); 388 ohci_dump_ed(sc->sc_intr_p_last[i]); 389 } 390 printf("iso "); 391 ohci_dump_ed(sc->sc_isoc_p_last); 392 } 393#endif 394 395 sc->sc_bus.usbrev = USB_REV_1_0; 396 397 if (ohci_controller_init(sc)) { 398 return (USB_ERR_INVAL); 399 } else { 400 /* catch any lost interrupts */ 401 ohci_do_poll(&sc->sc_bus); 402 return (USB_ERR_NORMAL_COMPLETION); 403 } 404} 405 406/* 407 * shut down the controller when the system is going down 408 */ 409void 410ohci_detach(struct ohci_softc *sc) 411{ 412 USB_BUS_LOCK(&sc->sc_bus); 413 414 usb2_callout_stop(&sc->sc_tmo_rhsc); 415 416 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 417 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 418 419 USB_BUS_UNLOCK(&sc->sc_bus); 420 421 /* XXX let stray task complete */ 422 usb2_pause_mtx(NULL, hz / 20); 423 424 usb2_callout_drain(&sc->sc_tmo_rhsc); 425} 426 427/* NOTE: suspend/resume is called from 428 * interrupt context and cannot sleep! 429 */ 430void 431ohci_suspend(ohci_softc_t *sc) 432{ 433 uint32_t ctl; 434 435 USB_BUS_LOCK(&sc->sc_bus); 436 437#if USB_DEBUG 438 DPRINTF("\n"); 439 if (ohcidebug > 2) { 440 ohci_dumpregs(sc); 441 } 442#endif 443 444 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 445 if (sc->sc_control == 0) { 446 /* 447 * Preserve register values, in case that APM BIOS 448 * does not recover them. 449 */ 450 sc->sc_control = ctl; 451 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 452 } 453 ctl |= OHCI_HCFS_SUSPEND; 454 OWRITE4(sc, OHCI_CONTROL, ctl); 455 456 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 457 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 458 459 USB_BUS_UNLOCK(&sc->sc_bus); 460} 461 462void 463ohci_resume(ohci_softc_t *sc) 464{ 465 uint32_t ctl; 466 467#if USB_DEBUG 468 DPRINTF("\n"); 469 if (ohcidebug > 2) { 470 ohci_dumpregs(sc); 471 } 472#endif 473 /* some broken BIOSes never initialize the Controller chip */ 474 ohci_controller_init(sc); 475 476 USB_BUS_LOCK(&sc->sc_bus); 477 if (sc->sc_intre) { 478 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 479 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 480 } 481 if (sc->sc_control) 482 ctl = sc->sc_control; 483 else 484 ctl = OREAD4(sc, OHCI_CONTROL); 485 ctl |= OHCI_HCFS_RESUME; 486 OWRITE4(sc, OHCI_CONTROL, ctl); 487 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 488 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 489 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 490 OWRITE4(sc, OHCI_CONTROL, ctl); 491 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 492 USB_MS_TO_TICKS(USB_RESUME_RECOVERY)); 493 sc->sc_control = sc->sc_intre = 0; 494 495 USB_BUS_UNLOCK(&sc->sc_bus); 496 497 /* catch any lost interrupts */ 498 ohci_do_poll(&sc->sc_bus); 499} 500 501#if USB_DEBUG 502static void 503ohci_dumpregs(ohci_softc_t *sc) 504{ 505 struct ohci_hcca *hcca; 506 507 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 508 OREAD4(sc, OHCI_REVISION), 509 OREAD4(sc, OHCI_CONTROL), 510 OREAD4(sc, OHCI_COMMAND_STATUS)); 511 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 512 OREAD4(sc, OHCI_INTERRUPT_STATUS), 513 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 514 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 515 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 516 OREAD4(sc, OHCI_HCCA), 517 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 518 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 519 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 520 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 521 OREAD4(sc, OHCI_BULK_HEAD_ED), 522 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 523 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 524 OREAD4(sc, OHCI_DONE_HEAD), 525 OREAD4(sc, OHCI_FM_INTERVAL), 526 OREAD4(sc, OHCI_FM_REMAINING)); 527 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 528 OREAD4(sc, OHCI_FM_NUMBER), 529 OREAD4(sc, OHCI_PERIODIC_START), 530 OREAD4(sc, OHCI_LS_THRESHOLD)); 531 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 532 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 533 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 534 OREAD4(sc, OHCI_RH_STATUS)); 535 DPRINTF(" port1=0x%08x port2=0x%08x\n", 536 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 537 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 538 539 hcca = ohci_get_hcca(sc); 540 541 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 542 le32toh(hcca->hcca_frame_number), 543 le32toh(hcca->hcca_done_head)); 544} 545static void 546ohci_dump_tds(ohci_td_t *std) 547{ 548 for (; std; std = std->obj_next) { 549 if (ohci_dump_td(std)) { 550 break; 551 } 552 } 553} 554 555static uint8_t 556ohci_dump_td(ohci_td_t *std) 557{ 558 uint32_t td_flags; 559 uint8_t temp; 560 561 usb2_pc_cpu_invalidate(std->page_cache); 562 563 td_flags = le32toh(std->td_flags); 564 temp = (std->td_next == 0); 565 566 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 567 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 568 std, le32toh(std->td_self), 569 (td_flags & OHCI_TD_R) ? "-R" : "", 570 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 571 (td_flags & OHCI_TD_IN) ? "-IN" : "", 572 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 573 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 574 OHCI_TD_GET_DI(td_flags), 575 OHCI_TD_GET_EC(td_flags), 576 OHCI_TD_GET_CC(td_flags), 577 le32toh(std->td_cbp), 578 le32toh(std->td_next), 579 le32toh(std->td_be)); 580 581 return (temp); 582} 583 584static uint8_t 585ohci_dump_itd(ohci_itd_t *sitd) 586{ 587 uint32_t itd_flags; 588 uint16_t i; 589 uint8_t temp; 590 591 usb2_pc_cpu_invalidate(sitd->page_cache); 592 593 itd_flags = le32toh(sitd->itd_flags); 594 temp = (sitd->itd_next == 0); 595 596 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 597 "bp0=0x%08x next=0x%08x be=0x%08x\n", 598 sitd, le32toh(sitd->itd_self), 599 OHCI_ITD_GET_SF(itd_flags), 600 OHCI_ITD_GET_DI(itd_flags), 601 OHCI_ITD_GET_FC(itd_flags), 602 OHCI_ITD_GET_CC(itd_flags), 603 le32toh(sitd->itd_bp0), 604 le32toh(sitd->itd_next), 605 le32toh(sitd->itd_be)); 606 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 607 printf("offs[%d]=0x%04x ", i, 608 (uint32_t)le16toh(sitd->itd_offset[i])); 609 } 610 printf("\n"); 611 612 return (temp); 613} 614 615static void 616ohci_dump_itds(ohci_itd_t *sitd) 617{ 618 for (; sitd; sitd = sitd->obj_next) { 619 if (ohci_dump_itd(sitd)) { 620 break; 621 } 622 } 623} 624 625static void 626ohci_dump_ed(ohci_ed_t *sed) 627{ 628 uint32_t ed_flags; 629 uint32_t ed_headp; 630 631 usb2_pc_cpu_invalidate(sed->page_cache); 632 633 ed_flags = le32toh(sed->ed_flags); 634 ed_headp = le32toh(sed->ed_headp); 635 636 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 637 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 638 sed, le32toh(sed->ed_self), 639 OHCI_ED_GET_FA(ed_flags), 640 OHCI_ED_GET_EN(ed_flags), 641 OHCI_ED_GET_MAXP(ed_flags), 642 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 643 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 644 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 645 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 646 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 647 le32toh(sed->ed_tailp), 648 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 649 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 650 le32toh(sed->ed_headp), 651 le32toh(sed->ed_next)); 652} 653 654#endif 655 656static void 657ohci_transfer_intr_enqueue(struct usb2_xfer *xfer) 658{ 659 /* check for early completion */ 660 if (ohci_check_transfer(xfer)) { 661 return; 662 } 663 /* put transfer on interrupt queue */ 664 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 665 666 /* start timeout, if any */ 667 if (xfer->timeout != 0) { 668 usb2_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 669 } 670} 671 672#define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 673static ohci_ed_t * 674_ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 675{ 676 DPRINTFN(11, "%p to %p\n", sed, last); 677 678 if (sed->prev != NULL) { 679 /* should not happen */ 680 DPRINTFN(0, "ED already linked!\n"); 681 return (last); 682 } 683 /* (sc->sc_bus.bus_mtx) must be locked */ 684 685 sed->next = last->next; 686 sed->ed_next = last->ed_next; 687 sed->ed_tailp = 0; 688 689 sed->prev = last; 690 691 usb2_pc_cpu_flush(sed->page_cache); 692 693 /* 694 * the last->next->prev is never followed: sed->next->prev = sed; 695 */ 696 697 last->next = sed; 698 last->ed_next = sed->ed_self; 699 700 usb2_pc_cpu_flush(last->page_cache); 701 702 return (sed); 703} 704 705#define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 706static ohci_ed_t * 707_ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 708{ 709 DPRINTFN(11, "%p from %p\n", sed, last); 710 711 /* (sc->sc_bus.bus_mtx) must be locked */ 712 713 /* only remove if not removed from a queue */ 714 if (sed->prev) { 715 716 sed->prev->next = sed->next; 717 sed->prev->ed_next = sed->ed_next; 718 719 usb2_pc_cpu_flush(sed->prev->page_cache); 720 721 if (sed->next) { 722 sed->next->prev = sed->prev; 723 usb2_pc_cpu_flush(sed->next->page_cache); 724 } 725 last = ((last == sed) ? sed->prev : last); 726 727 sed->prev = 0; 728 729 usb2_pc_cpu_flush(sed->page_cache); 730 } 731 return (last); 732} 733 734static void 735ohci_isoc_done(struct usb2_xfer *xfer) 736{ 737 uint8_t nframes; 738 uint32_t *plen = xfer->frlengths; 739 volatile uint16_t *olen; 740 uint16_t len = 0; 741 ohci_itd_t *td = xfer->td_transfer_first; 742 743 while (1) { 744 if (td == NULL) { 745 panic("%s:%d: out of TD's\n", 746 __FUNCTION__, __LINE__); 747 } 748#if USB_DEBUG 749 if (ohcidebug > 5) { 750 DPRINTF("isoc TD\n"); 751 ohci_dump_itd(td); 752 } 753#endif 754 usb2_pc_cpu_invalidate(td->page_cache); 755 756 nframes = td->frames; 757 olen = &td->itd_offset[0]; 758 759 if (nframes > 8) { 760 nframes = 8; 761 } 762 while (nframes--) { 763 len = le16toh(*olen); 764 765 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 766 len = 0; 767 } else { 768 len &= ((1 << 12) - 1); 769 } 770 771 if (len > *plen) { 772 len = 0;/* invalid length */ 773 } 774 *plen = len; 775 plen++; 776 olen++; 777 } 778 779 if (((void *)td) == xfer->td_transfer_last) { 780 break; 781 } 782 td = td->obj_next; 783 } 784 785 xfer->aframes = xfer->nframes; 786 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 787} 788 789#if USB_DEBUG 790static const char *const 791 ohci_cc_strs[] = 792{ 793 "NO_ERROR", 794 "CRC", 795 "BIT_STUFFING", 796 "DATA_TOGGLE_MISMATCH", 797 798 "STALL", 799 "DEVICE_NOT_RESPONDING", 800 "PID_CHECK_FAILURE", 801 "UNEXPECTED_PID", 802 803 "DATA_OVERRUN", 804 "DATA_UNDERRUN", 805 "BUFFER_OVERRUN", 806 "BUFFER_UNDERRUN", 807 808 "reserved", 809 "reserved", 810 "NOT_ACCESSED", 811 "NOT_ACCESSED" 812}; 813 814#endif 815 816static usb2_error_t 817ohci_non_isoc_done_sub(struct usb2_xfer *xfer) 818{ 819 ohci_td_t *td; 820 ohci_td_t *td_alt_next; 821 uint32_t temp; 822 uint32_t phy_start; 823 uint32_t phy_end; 824 uint32_t td_flags; 825 uint16_t cc; 826 827 td = xfer->td_transfer_cache; 828 td_alt_next = td->alt_next; 829 td_flags = 0; 830 831 if (xfer->aframes != xfer->nframes) { 832 xfer->frlengths[xfer->aframes] = 0; 833 } 834 while (1) { 835 836 usb2_pc_cpu_invalidate(td->page_cache); 837 phy_start = le32toh(td->td_cbp); 838 td_flags = le32toh(td->td_flags); 839 cc = OHCI_TD_GET_CC(td_flags); 840 841 if (phy_start) { 842 /* 843 * short transfer - compute the number of remaining 844 * bytes in the hardware buffer: 845 */ 846 phy_end = le32toh(td->td_be); 847 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 848 (OHCI_PAGE_SIZE + 1) : 0x0001); 849 temp += OHCI_PAGE_OFFSET(phy_end); 850 temp -= OHCI_PAGE_OFFSET(phy_start); 851 852 if (temp > td->len) { 853 /* guard against corruption */ 854 cc = OHCI_CC_STALL; 855 } else if (xfer->aframes != xfer->nframes) { 856 /* 857 * Sum up total transfer length 858 * in "frlengths[]": 859 */ 860 xfer->frlengths[xfer->aframes] += td->len - temp; 861 } 862 } else { 863 if (xfer->aframes != xfer->nframes) { 864 /* transfer was complete */ 865 xfer->frlengths[xfer->aframes] += td->len; 866 } 867 } 868 /* Check for last transfer */ 869 if (((void *)td) == xfer->td_transfer_last) { 870 td = NULL; 871 break; 872 } 873 /* Check transfer status */ 874 if (cc) { 875 /* the transfer is finished */ 876 td = NULL; 877 break; 878 } 879 /* Check for short transfer */ 880 if (phy_start) { 881 if (xfer->flags_int.short_frames_ok) { 882 /* follow alt next */ 883 td = td->alt_next; 884 } else { 885 /* the transfer is finished */ 886 td = NULL; 887 } 888 break; 889 } 890 td = td->obj_next; 891 892 if (td->alt_next != td_alt_next) { 893 /* this USB frame is complete */ 894 break; 895 } 896 } 897 898 /* update transfer cache */ 899 900 xfer->td_transfer_cache = td; 901 902 DPRINTFN(16, "error cc=%d (%s)\n", 903 cc, ohci_cc_strs[cc]); 904 905 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 906 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 907} 908 909static void 910ohci_non_isoc_done(struct usb2_xfer *xfer) 911{ 912 usb2_error_t err = 0; 913 914 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 915 xfer, xfer->pipe); 916 917#if USB_DEBUG 918 if (ohcidebug > 10) { 919 ohci_dump_tds(xfer->td_transfer_first); 920 } 921#endif 922 923 /* reset scanner */ 924 925 xfer->td_transfer_cache = xfer->td_transfer_first; 926 927 if (xfer->flags_int.control_xfr) { 928 929 if (xfer->flags_int.control_hdr) { 930 931 err = ohci_non_isoc_done_sub(xfer); 932 } 933 xfer->aframes = 1; 934 935 if (xfer->td_transfer_cache == NULL) { 936 goto done; 937 } 938 } 939 while (xfer->aframes != xfer->nframes) { 940 941 err = ohci_non_isoc_done_sub(xfer); 942 xfer->aframes++; 943 944 if (xfer->td_transfer_cache == NULL) { 945 goto done; 946 } 947 } 948 949 if (xfer->flags_int.control_xfr && 950 !xfer->flags_int.control_act) { 951 952 err = ohci_non_isoc_done_sub(xfer); 953 } 954done: 955 ohci_device_done(xfer, err); 956} 957 958/*------------------------------------------------------------------------* 959 * ohci_check_transfer_sub 960 *------------------------------------------------------------------------*/ 961static void 962ohci_check_transfer_sub(struct usb2_xfer *xfer) 963{ 964 ohci_td_t *td; 965 ohci_ed_t *ed; 966 uint32_t phy_start; 967 uint32_t td_flags; 968 uint32_t td_next; 969 uint16_t cc; 970 971 td = xfer->td_transfer_cache; 972 973 while (1) { 974 975 usb2_pc_cpu_invalidate(td->page_cache); 976 phy_start = le32toh(td->td_cbp); 977 td_flags = le32toh(td->td_flags); 978 td_next = le32toh(td->td_next); 979 980 /* Check for last transfer */ 981 if (((void *)td) == xfer->td_transfer_last) { 982 /* the transfer is finished */ 983 td = NULL; 984 break; 985 } 986 /* Check transfer status */ 987 cc = OHCI_TD_GET_CC(td_flags); 988 if (cc) { 989 /* the transfer is finished */ 990 td = NULL; 991 break; 992 } 993 /* 994 * Check if we reached the last packet 995 * or if there is a short packet: 996 */ 997 998 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 999 /* follow alt next */ 1000 td = td->alt_next; 1001 break; 1002 } 1003 td = td->obj_next; 1004 } 1005 1006 /* update transfer cache */ 1007 1008 xfer->td_transfer_cache = td; 1009 1010 if (td) { 1011 1012 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1013 1014 ed->ed_headp = td->td_self; 1015 usb2_pc_cpu_flush(ed->page_cache); 1016 1017 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1018 1019 /* 1020 * Make sure that the OHCI re-scans the schedule by 1021 * writing the BLF and CLF bits: 1022 */ 1023 1024 if (xfer->xroot->udev->pwr_save.suspended) { 1025 /* nothing to do */ 1026 } else if (xfer->pipe->methods == &ohci_device_bulk_methods) { 1027 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1028 1029 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1030 } else if (xfer->pipe->methods == &ohci_device_ctrl_methods) { 1031 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1032 1033 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1034 } 1035 } 1036} 1037 1038/*------------------------------------------------------------------------* 1039 * ohci_check_transfer 1040 * 1041 * Return values: 1042 * 0: USB transfer is not finished 1043 * Else: USB transfer is finished 1044 *------------------------------------------------------------------------*/ 1045static uint8_t 1046ohci_check_transfer(struct usb2_xfer *xfer) 1047{ 1048 ohci_ed_t *ed; 1049 uint32_t ed_headp; 1050 uint32_t ed_tailp; 1051 1052 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1053 1054 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1055 1056 usb2_pc_cpu_invalidate(ed->page_cache); 1057 ed_headp = le32toh(ed->ed_headp); 1058 ed_tailp = le32toh(ed->ed_tailp); 1059 1060 if ((ed_headp & OHCI_HALTED) || 1061 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1062 if (xfer->pipe->methods == &ohci_device_isoc_methods) { 1063 /* isochronous transfer */ 1064 ohci_isoc_done(xfer); 1065 } else { 1066 if (xfer->flags_int.short_frames_ok) { 1067 ohci_check_transfer_sub(xfer); 1068 if (xfer->td_transfer_cache) { 1069 /* not finished yet */ 1070 return (0); 1071 } 1072 } 1073 /* store data-toggle */ 1074 if (ed_headp & OHCI_TOGGLECARRY) { 1075 xfer->pipe->toggle_next = 1; 1076 } else { 1077 xfer->pipe->toggle_next = 0; 1078 } 1079 1080 /* non-isochronous transfer */ 1081 ohci_non_isoc_done(xfer); 1082 } 1083 return (1); 1084 } 1085 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1086 return (0); 1087} 1088 1089static void 1090ohci_rhsc_enable(ohci_softc_t *sc) 1091{ 1092 DPRINTFN(5, "\n"); 1093 1094 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1095 1096 sc->sc_eintrs |= OHCI_RHSC; 1097 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1098 1099 /* acknowledge any RHSC interrupt */ 1100 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1101 1102 ohci_root_intr(sc); 1103} 1104 1105static void 1106ohci_interrupt_poll(ohci_softc_t *sc) 1107{ 1108 struct usb2_xfer *xfer; 1109 1110repeat: 1111 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1112 /* 1113 * check if transfer is transferred 1114 */ 1115 if (ohci_check_transfer(xfer)) { 1116 /* queue has been modified */ 1117 goto repeat; 1118 } 1119 } 1120} 1121 1122/*------------------------------------------------------------------------* 1123 * ohci_interrupt - OHCI interrupt handler 1124 * 1125 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1126 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1127 * is present ! 1128 *------------------------------------------------------------------------*/ 1129void 1130ohci_interrupt(ohci_softc_t *sc) 1131{ 1132 struct ohci_hcca *hcca; 1133 uint32_t status; 1134 uint32_t done; 1135 1136 USB_BUS_LOCK(&sc->sc_bus); 1137 1138 hcca = ohci_get_hcca(sc); 1139 1140 DPRINTFN(16, "real interrupt\n"); 1141 1142#if USB_DEBUG 1143 if (ohcidebug > 15) { 1144 ohci_dumpregs(sc); 1145 } 1146#endif 1147 1148 done = le32toh(hcca->hcca_done_head); 1149 1150 /* 1151 * The LSb of done is used to inform the HC Driver that an interrupt 1152 * condition exists for both the Done list and for another event 1153 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1154 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1155 * the interrupt was caused by other than the HccaDoneHead update 1156 * and the HcInterruptStatus register needs to be accessed to 1157 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1158 * then a Done list update interrupt is indicated and if the LSb of 1159 * done is nonzero, then an additional interrupt event is indicated 1160 * and HcInterruptStatus should be checked to determine its cause. 1161 */ 1162 if (done != 0) { 1163 status = 0; 1164 1165 if (done & ~OHCI_DONE_INTRS) { 1166 status |= OHCI_WDH; 1167 } 1168 if (done & OHCI_DONE_INTRS) { 1169 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1170 } 1171 hcca->hcca_done_head = 0; 1172 1173 usb2_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1174 } else { 1175 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1176 } 1177 1178 status &= ~OHCI_MIE; 1179 if (status == 0) { 1180 /* 1181 * nothing to be done (PCI shared 1182 * interrupt) 1183 */ 1184 goto done; 1185 } 1186 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1187 1188 status &= sc->sc_eintrs; 1189 if (status == 0) { 1190 goto done; 1191 } 1192 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1193#if 0 1194 if (status & OHCI_SO) { 1195 /* XXX do what */ 1196 } 1197#endif 1198 if (status & OHCI_RD) { 1199 printf("%s: resume detect\n", __FUNCTION__); 1200 /* XXX process resume detect */ 1201 } 1202 if (status & OHCI_UE) { 1203 printf("%s: unrecoverable error, " 1204 "controller halted\n", __FUNCTION__); 1205 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1206 /* XXX what else */ 1207 } 1208 if (status & OHCI_RHSC) { 1209 /* 1210 * Disable RHSC interrupt for now, because it will be 1211 * on until the port has been reset. 1212 */ 1213 sc->sc_eintrs &= ~OHCI_RHSC; 1214 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1215 1216 ohci_root_intr(sc); 1217 1218 /* do not allow RHSC interrupts > 1 per second */ 1219 usb2_callout_reset(&sc->sc_tmo_rhsc, hz, 1220 (void *)&ohci_rhsc_enable, sc); 1221 } 1222 } 1223 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1224 if (status != 0) { 1225 /* Block unprocessed interrupts. XXX */ 1226 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1227 sc->sc_eintrs &= ~status; 1228 printf("%s: blocking intrs 0x%x\n", 1229 __FUNCTION__, status); 1230 } 1231 /* poll all the USB transfers */ 1232 ohci_interrupt_poll(sc); 1233 1234done: 1235 USB_BUS_UNLOCK(&sc->sc_bus); 1236} 1237 1238/* 1239 * called when a request does not complete 1240 */ 1241static void 1242ohci_timeout(void *arg) 1243{ 1244 struct usb2_xfer *xfer = arg; 1245 1246 DPRINTF("xfer=%p\n", xfer); 1247 1248 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1249 1250 /* transfer is transferred */ 1251 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1252} 1253 1254static void 1255ohci_do_poll(struct usb2_bus *bus) 1256{ 1257 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1258 1259 USB_BUS_LOCK(&sc->sc_bus); 1260 ohci_interrupt_poll(sc); 1261 USB_BUS_UNLOCK(&sc->sc_bus); 1262} 1263 1264static void 1265ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1266{ 1267 struct usb2_page_search buf_res; 1268 ohci_td_t *td; 1269 ohci_td_t *td_next; 1270 ohci_td_t *td_alt_next; 1271 uint32_t buf_offset; 1272 uint32_t average; 1273 uint32_t len_old; 1274 uint8_t shortpkt_old; 1275 uint8_t precompute; 1276 1277 td_alt_next = NULL; 1278 buf_offset = 0; 1279 shortpkt_old = temp->shortpkt; 1280 len_old = temp->len; 1281 precompute = 1; 1282 1283 /* software is used to detect short incoming transfers */ 1284 1285 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1286 temp->td_flags |= htole32(OHCI_TD_R); 1287 } else { 1288 temp->td_flags &= ~htole32(OHCI_TD_R); 1289 } 1290 1291restart: 1292 1293 td = temp->td; 1294 td_next = temp->td_next; 1295 1296 while (1) { 1297 1298 if (temp->len == 0) { 1299 1300 if (temp->shortpkt) { 1301 break; 1302 } 1303 /* send a Zero Length Packet, ZLP, last */ 1304 1305 temp->shortpkt = 1; 1306 average = 0; 1307 1308 } else { 1309 1310 average = temp->average; 1311 1312 if (temp->len < average) { 1313 if (temp->len % temp->max_frame_size) { 1314 temp->shortpkt = 1; 1315 } 1316 average = temp->len; 1317 } 1318 } 1319 1320 if (td_next == NULL) { 1321 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1322 } 1323 /* get next TD */ 1324 1325 td = td_next; 1326 td_next = td->obj_next; 1327 1328 /* check if we are pre-computing */ 1329 1330 if (precompute) { 1331 1332 /* update remaining length */ 1333 1334 temp->len -= average; 1335 1336 continue; 1337 } 1338 /* fill out current TD */ 1339 td->td_flags = temp->td_flags; 1340 1341 /* the next TD uses TOGGLE_CARRY */ 1342 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1343 1344 if (average == 0) { 1345 /* 1346 * The buffer start and end phys addresses should be 1347 * 0x0 for a zero length packet. 1348 */ 1349 td->td_cbp = 0; 1350 td->td_be = 0; 1351 td->len = 0; 1352 1353 } else { 1354 1355 usb2_get_page(temp->pc, buf_offset, &buf_res); 1356 td->td_cbp = htole32(buf_res.physaddr); 1357 buf_offset += (average - 1); 1358 1359 usb2_get_page(temp->pc, buf_offset, &buf_res); 1360 td->td_be = htole32(buf_res.physaddr); 1361 buf_offset++; 1362 1363 td->len = average; 1364 1365 /* update remaining length */ 1366 1367 temp->len -= average; 1368 } 1369 1370 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1371 /* we need to receive these frames one by one ! */ 1372 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1373 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1374 td->td_next = htole32(OHCI_TD_NEXT_END); 1375 } else { 1376 if (td_next) { 1377 /* link the current TD with the next one */ 1378 td->td_next = td_next->td_self; 1379 } 1380 } 1381 1382 td->alt_next = td_alt_next; 1383 1384 usb2_pc_cpu_flush(td->page_cache); 1385 } 1386 1387 if (precompute) { 1388 precompute = 0; 1389 1390 /* setup alt next pointer, if any */ 1391 if (temp->last_frame) { 1392 /* no alternate next */ 1393 td_alt_next = NULL; 1394 } else { 1395 /* we use this field internally */ 1396 td_alt_next = td_next; 1397 } 1398 1399 /* restore */ 1400 temp->shortpkt = shortpkt_old; 1401 temp->len = len_old; 1402 goto restart; 1403 } 1404 temp->td = td; 1405 temp->td_next = td_next; 1406} 1407 1408static void 1409ohci_setup_standard_chain(struct usb2_xfer *xfer, ohci_ed_t **ed_last) 1410{ 1411 struct ohci_std_temp temp; 1412 struct usb2_pipe_methods *methods; 1413 ohci_ed_t *ed; 1414 ohci_td_t *td; 1415 uint32_t ed_flags; 1416 uint32_t x; 1417 1418 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1419 xfer->address, UE_GET_ADDR(xfer->endpoint), 1420 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1421 1422 temp.average = xfer->max_hc_frame_size; 1423 temp.max_frame_size = xfer->max_frame_size; 1424 1425 /* toggle the DMA set we are using */ 1426 xfer->flags_int.curr_dma_set ^= 1; 1427 1428 /* get next DMA set */ 1429 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1430 1431 xfer->td_transfer_first = td; 1432 xfer->td_transfer_cache = td; 1433 1434 temp.td = NULL; 1435 temp.td_next = td; 1436 temp.last_frame = 0; 1437 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1438 1439 methods = xfer->pipe->methods; 1440 1441 /* check if we should prepend a setup message */ 1442 1443 if (xfer->flags_int.control_xfr) { 1444 if (xfer->flags_int.control_hdr) { 1445 1446 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1447 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1448 1449 temp.len = xfer->frlengths[0]; 1450 temp.pc = xfer->frbuffers + 0; 1451 temp.shortpkt = temp.len ? 1 : 0; 1452 /* check for last frame */ 1453 if (xfer->nframes == 1) { 1454 /* no STATUS stage yet, SETUP is last */ 1455 if (xfer->flags_int.control_act) { 1456 temp.last_frame = 1; 1457 temp.setup_alt_next = 0; 1458 } 1459 } 1460 ohci_setup_standard_chain_sub(&temp); 1461 1462 /* 1463 * XXX assume that the setup message is 1464 * contained within one USB packet: 1465 */ 1466 xfer->pipe->toggle_next = 1; 1467 } 1468 x = 1; 1469 } else { 1470 x = 0; 1471 } 1472 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1473 1474 /* set data toggle */ 1475 1476 if (xfer->pipe->toggle_next) { 1477 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1478 } else { 1479 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1480 } 1481 1482 /* set endpoint direction */ 1483 1484 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1485 temp.td_flags |= htole32(OHCI_TD_IN); 1486 } else { 1487 temp.td_flags |= htole32(OHCI_TD_OUT); 1488 } 1489 1490 while (x != xfer->nframes) { 1491 1492 /* DATA0 / DATA1 message */ 1493 1494 temp.len = xfer->frlengths[x]; 1495 temp.pc = xfer->frbuffers + x; 1496 1497 x++; 1498 1499 if (x == xfer->nframes) { 1500 if (xfer->flags_int.control_xfr) { 1501 /* no STATUS stage yet, DATA is last */ 1502 if (xfer->flags_int.control_act) { 1503 temp.last_frame = 1; 1504 temp.setup_alt_next = 0; 1505 } 1506 } else { 1507 temp.last_frame = 1; 1508 temp.setup_alt_next = 0; 1509 } 1510 } 1511 if (temp.len == 0) { 1512 1513 /* make sure that we send an USB packet */ 1514 1515 temp.shortpkt = 0; 1516 1517 } else { 1518 1519 /* regular data transfer */ 1520 1521 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1522 } 1523 1524 ohci_setup_standard_chain_sub(&temp); 1525 } 1526 1527 /* check if we should append a status stage */ 1528 1529 if (xfer->flags_int.control_xfr && 1530 !xfer->flags_int.control_act) { 1531 1532 /* 1533 * Send a DATA1 message and invert the current endpoint 1534 * direction. 1535 */ 1536 1537 /* set endpoint direction and data toggle */ 1538 1539 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1540 temp.td_flags = htole32(OHCI_TD_OUT | 1541 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1542 } else { 1543 temp.td_flags = htole32(OHCI_TD_IN | 1544 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1545 } 1546 1547 temp.len = 0; 1548 temp.pc = NULL; 1549 temp.shortpkt = 0; 1550 temp.last_frame = 1; 1551 temp.setup_alt_next = 0; 1552 1553 ohci_setup_standard_chain_sub(&temp); 1554 } 1555 td = temp.td; 1556 1557 /* Ensure that last TD is terminating: */ 1558 td->td_next = htole32(OHCI_TD_NEXT_END); 1559 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1560 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1561 1562 usb2_pc_cpu_flush(td->page_cache); 1563 1564 /* must have at least one frame! */ 1565 1566 xfer->td_transfer_last = td; 1567 1568#if USB_DEBUG 1569 if (ohcidebug > 8) { 1570 DPRINTF("nexttog=%d; data before transfer:\n", 1571 xfer->pipe->toggle_next); 1572 ohci_dump_tds(xfer->td_transfer_first); 1573 } 1574#endif 1575 1576 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1577 1578 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1579 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 1580 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1581 1582 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1583 1584 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1585 ed_flags |= OHCI_ED_SPEED; 1586 } 1587 ed->ed_flags = htole32(ed_flags); 1588 1589 td = xfer->td_transfer_first; 1590 1591 ed->ed_headp = td->td_self; 1592 1593 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1594 /* the append function will flush the endpoint descriptor */ 1595 OHCI_APPEND_QH(ed, *ed_last); 1596 1597 if (methods == &ohci_device_bulk_methods) { 1598 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1599 1600 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1601 } 1602 if (methods == &ohci_device_ctrl_methods) { 1603 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1604 1605 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1606 } 1607 } else { 1608 usb2_pc_cpu_flush(ed->page_cache); 1609 } 1610} 1611 1612static void 1613ohci_root_intr(ohci_softc_t *sc) 1614{ 1615 uint32_t hstatus; 1616 uint16_t i; 1617 uint16_t m; 1618 1619 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1620 1621 /* clear any old interrupt data */ 1622 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 1623 1624 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1625 DPRINTF("sc=%p hstatus=0x%08x\n", 1626 sc, hstatus); 1627 1628 /* set bits */ 1629 m = (sc->sc_noport + 1); 1630 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1631 m = (8 * sizeof(sc->sc_hub_idata)); 1632 } 1633 for (i = 1; i < m; i++) { 1634 /* pick out CHANGE bits from the status register */ 1635 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1636 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1637 DPRINTF("port %d changed\n", i); 1638 } 1639 } 1640 1641 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1642 sizeof(sc->sc_hub_idata)); 1643} 1644 1645/* NOTE: "done" can be run two times in a row, 1646 * from close and from interrupt 1647 */ 1648static void 1649ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1650{ 1651 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1652 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1653 ohci_ed_t *ed; 1654 1655 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1656 1657 1658 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1659 xfer, xfer->pipe, error); 1660 1661 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1662 if (ed) { 1663 usb2_pc_cpu_invalidate(ed->page_cache); 1664 } 1665 if (methods == &ohci_device_bulk_methods) { 1666 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1667 } 1668 if (methods == &ohci_device_ctrl_methods) { 1669 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1670 } 1671 if (methods == &ohci_device_intr_methods) { 1672 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1673 } 1674 if (methods == &ohci_device_isoc_methods) { 1675 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1676 } 1677 xfer->td_transfer_first = NULL; 1678 xfer->td_transfer_last = NULL; 1679 1680 /* dequeue transfer and start next transfer */ 1681 usb2_transfer_done(xfer, error); 1682} 1683 1684/*------------------------------------------------------------------------* 1685 * ohci bulk support 1686 *------------------------------------------------------------------------*/ 1687static void 1688ohci_device_bulk_open(struct usb2_xfer *xfer) 1689{ 1690 return; 1691} 1692 1693static void 1694ohci_device_bulk_close(struct usb2_xfer *xfer) 1695{ 1696 ohci_device_done(xfer, USB_ERR_CANCELLED); 1697} 1698 1699static void 1700ohci_device_bulk_enter(struct usb2_xfer *xfer) 1701{ 1702 return; 1703} 1704 1705static void 1706ohci_device_bulk_start(struct usb2_xfer *xfer) 1707{ 1708 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1709 1710 /* setup TD's and QH */ 1711 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1712 1713 /* put transfer on interrupt queue */ 1714 ohci_transfer_intr_enqueue(xfer); 1715} 1716 1717struct usb2_pipe_methods ohci_device_bulk_methods = 1718{ 1719 .open = ohci_device_bulk_open, 1720 .close = ohci_device_bulk_close, 1721 .enter = ohci_device_bulk_enter, 1722 .start = ohci_device_bulk_start, 1723}; 1724 1725/*------------------------------------------------------------------------* 1726 * ohci control support 1727 *------------------------------------------------------------------------*/ 1728static void 1729ohci_device_ctrl_open(struct usb2_xfer *xfer) 1730{ 1731 return; 1732} 1733 1734static void 1735ohci_device_ctrl_close(struct usb2_xfer *xfer) 1736{ 1737 ohci_device_done(xfer, USB_ERR_CANCELLED); 1738} 1739 1740static void 1741ohci_device_ctrl_enter(struct usb2_xfer *xfer) 1742{ 1743 return; 1744} 1745 1746static void 1747ohci_device_ctrl_start(struct usb2_xfer *xfer) 1748{ 1749 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1750 1751 /* setup TD's and QH */ 1752 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1753 1754 /* put transfer on interrupt queue */ 1755 ohci_transfer_intr_enqueue(xfer); 1756} 1757 1758struct usb2_pipe_methods ohci_device_ctrl_methods = 1759{ 1760 .open = ohci_device_ctrl_open, 1761 .close = ohci_device_ctrl_close, 1762 .enter = ohci_device_ctrl_enter, 1763 .start = ohci_device_ctrl_start, 1764}; 1765 1766/*------------------------------------------------------------------------* 1767 * ohci interrupt support 1768 *------------------------------------------------------------------------*/ 1769static void 1770ohci_device_intr_open(struct usb2_xfer *xfer) 1771{ 1772 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1773 uint16_t best; 1774 uint16_t bit; 1775 uint16_t x; 1776 1777 best = 0; 1778 bit = OHCI_NO_EDS / 2; 1779 while (bit) { 1780 if (xfer->interval >= bit) { 1781 x = bit; 1782 best = bit; 1783 while (x & bit) { 1784 if (sc->sc_intr_stat[x] < 1785 sc->sc_intr_stat[best]) { 1786 best = x; 1787 } 1788 x++; 1789 } 1790 break; 1791 } 1792 bit >>= 1; 1793 } 1794 1795 sc->sc_intr_stat[best]++; 1796 xfer->qh_pos = best; 1797 1798 DPRINTFN(3, "best=%d interval=%d\n", 1799 best, xfer->interval); 1800} 1801 1802static void 1803ohci_device_intr_close(struct usb2_xfer *xfer) 1804{ 1805 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1806 1807 sc->sc_intr_stat[xfer->qh_pos]--; 1808 1809 ohci_device_done(xfer, USB_ERR_CANCELLED); 1810} 1811 1812static void 1813ohci_device_intr_enter(struct usb2_xfer *xfer) 1814{ 1815 return; 1816} 1817 1818static void 1819ohci_device_intr_start(struct usb2_xfer *xfer) 1820{ 1821 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1822 1823 /* setup TD's and QH */ 1824 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1825 1826 /* put transfer on interrupt queue */ 1827 ohci_transfer_intr_enqueue(xfer); 1828} 1829 1830struct usb2_pipe_methods ohci_device_intr_methods = 1831{ 1832 .open = ohci_device_intr_open, 1833 .close = ohci_device_intr_close, 1834 .enter = ohci_device_intr_enter, 1835 .start = ohci_device_intr_start, 1836}; 1837 1838/*------------------------------------------------------------------------* 1839 * ohci isochronous support 1840 *------------------------------------------------------------------------*/ 1841static void 1842ohci_device_isoc_open(struct usb2_xfer *xfer) 1843{ 1844 return; 1845} 1846 1847static void 1848ohci_device_isoc_close(struct usb2_xfer *xfer) 1849{ 1850 /**/ 1851 ohci_device_done(xfer, USB_ERR_CANCELLED); 1852} 1853 1854static void 1855ohci_device_isoc_enter(struct usb2_xfer *xfer) 1856{ 1857 struct usb2_page_search buf_res; 1858 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1859 struct ohci_hcca *hcca; 1860 uint32_t buf_offset; 1861 uint32_t nframes; 1862 uint32_t ed_flags; 1863 uint32_t *plen; 1864 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1865 uint16_t length; 1866 uint8_t ncur; 1867 ohci_itd_t *td; 1868 ohci_itd_t *td_last = NULL; 1869 ohci_ed_t *ed; 1870 1871 hcca = ohci_get_hcca(sc); 1872 1873 nframes = le32toh(hcca->hcca_frame_number); 1874 1875 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1876 xfer, xfer->pipe->isoc_next, xfer->nframes, nframes); 1877 1878 if ((xfer->pipe->is_synced == 0) || 1879 (((nframes - xfer->pipe->isoc_next) & 0xFFFF) < xfer->nframes) || 1880 (((xfer->pipe->isoc_next - nframes) & 0xFFFF) >= 128)) { 1881 /* 1882 * If there is data underflow or the pipe queue is empty we 1883 * schedule the transfer a few frames ahead of the current 1884 * frame position. Else two isochronous transfers might 1885 * overlap. 1886 */ 1887 xfer->pipe->isoc_next = (nframes + 3) & 0xFFFF; 1888 xfer->pipe->is_synced = 1; 1889 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1890 } 1891 /* 1892 * compute how many milliseconds the insertion is ahead of the 1893 * current frame position: 1894 */ 1895 buf_offset = ((xfer->pipe->isoc_next - nframes) & 0xFFFF); 1896 1897 /* 1898 * pre-compute when the isochronous transfer will be finished: 1899 */ 1900 xfer->isoc_time_complete = 1901 (usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1902 xfer->nframes); 1903 1904 /* get the real number of frames */ 1905 1906 nframes = xfer->nframes; 1907 1908 buf_offset = 0; 1909 1910 plen = xfer->frlengths; 1911 1912 /* toggle the DMA set we are using */ 1913 xfer->flags_int.curr_dma_set ^= 1; 1914 1915 /* get next DMA set */ 1916 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1917 1918 xfer->td_transfer_first = td; 1919 1920 ncur = 0; 1921 length = 0; 1922 1923 while (nframes--) { 1924 if (td == NULL) { 1925 panic("%s:%d: out of TD's\n", 1926 __FUNCTION__, __LINE__); 1927 } 1928 itd_offset[ncur] = length; 1929 buf_offset += *plen; 1930 length += *plen; 1931 plen++; 1932 ncur++; 1933 1934 if ( /* check if the ITD is full */ 1935 (ncur == OHCI_ITD_NOFFSET) || 1936 /* check if we have put more than 4K into the ITD */ 1937 (length & 0xF000) || 1938 /* check if it is the last frame */ 1939 (nframes == 0)) { 1940 1941 /* fill current ITD */ 1942 td->itd_flags = htole32( 1943 OHCI_ITD_NOCC | 1944 OHCI_ITD_SET_SF(xfer->pipe->isoc_next) | 1945 OHCI_ITD_NOINTR | 1946 OHCI_ITD_SET_FC(ncur)); 1947 1948 td->frames = ncur; 1949 xfer->pipe->isoc_next += ncur; 1950 1951 if (length == 0) { 1952 /* all zero */ 1953 td->itd_bp0 = 0; 1954 td->itd_be = ~0; 1955 1956 while (ncur--) { 1957 td->itd_offset[ncur] = 1958 htole16(OHCI_ITD_MK_OFFS(0)); 1959 } 1960 } else { 1961 usb2_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1962 length = OHCI_PAGE_MASK(buf_res.physaddr); 1963 buf_res.physaddr = 1964 OHCI_PAGE(buf_res.physaddr); 1965 td->itd_bp0 = htole32(buf_res.physaddr); 1966 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1967 td->itd_be = htole32(buf_res.physaddr); 1968 1969 while (ncur--) { 1970 itd_offset[ncur] += length; 1971 itd_offset[ncur] = 1972 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1973 td->itd_offset[ncur] = 1974 htole16(itd_offset[ncur]); 1975 } 1976 } 1977 ncur = 0; 1978 length = 0; 1979 td_last = td; 1980 td = td->obj_next; 1981 1982 if (td) { 1983 /* link the last TD with the next one */ 1984 td_last->itd_next = td->itd_self; 1985 } 1986 usb2_pc_cpu_flush(td_last->page_cache); 1987 } 1988 } 1989 1990 /* update the last TD */ 1991 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 1992 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 1993 td_last->itd_next = 0; 1994 1995 usb2_pc_cpu_flush(td_last->page_cache); 1996 1997 xfer->td_transfer_last = td_last; 1998 1999#if USB_DEBUG 2000 if (ohcidebug > 8) { 2001 DPRINTF("data before transfer:\n"); 2002 ohci_dump_itds(xfer->td_transfer_first); 2003 } 2004#endif 2005 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2006 2007 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) 2008 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 2009 else 2010 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 2011 2012 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 2013 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 2014 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 2015 2016 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 2017 ed_flags |= OHCI_ED_SPEED; 2018 } 2019 ed->ed_flags = htole32(ed_flags); 2020 2021 td = xfer->td_transfer_first; 2022 2023 ed->ed_headp = td->itd_self; 2024 2025 /* isochronous transfers are not affected by suspend / resume */ 2026 /* the append function will flush the endpoint descriptor */ 2027 2028 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2029} 2030 2031static void 2032ohci_device_isoc_start(struct usb2_xfer *xfer) 2033{ 2034 /* put transfer on interrupt queue */ 2035 ohci_transfer_intr_enqueue(xfer); 2036} 2037 2038struct usb2_pipe_methods ohci_device_isoc_methods = 2039{ 2040 .open = ohci_device_isoc_open, 2041 .close = ohci_device_isoc_close, 2042 .enter = ohci_device_isoc_enter, 2043 .start = ohci_device_isoc_start, 2044}; 2045 2046/*------------------------------------------------------------------------* 2047 * ohci root control support 2048 *------------------------------------------------------------------------* 2049 * Simulate a hardware hub by handling all the necessary requests. 2050 *------------------------------------------------------------------------*/ 2051 2052static const 2053struct usb2_device_descriptor ohci_devd = 2054{ 2055 sizeof(struct usb2_device_descriptor), 2056 UDESC_DEVICE, /* type */ 2057 {0x00, 0x01}, /* USB version */ 2058 UDCLASS_HUB, /* class */ 2059 UDSUBCLASS_HUB, /* subclass */ 2060 UDPROTO_FSHUB, /* protocol */ 2061 64, /* max packet */ 2062 {0}, {0}, {0x00, 0x01}, /* device id */ 2063 1, 2, 0, /* string indicies */ 2064 1 /* # of configurations */ 2065}; 2066 2067static const 2068struct ohci_config_desc ohci_confd = 2069{ 2070 .confd = { 2071 .bLength = sizeof(struct usb2_config_descriptor), 2072 .bDescriptorType = UDESC_CONFIG, 2073 .wTotalLength[0] = sizeof(ohci_confd), 2074 .bNumInterface = 1, 2075 .bConfigurationValue = 1, 2076 .iConfiguration = 0, 2077 .bmAttributes = UC_SELF_POWERED, 2078 .bMaxPower = 0, /* max power */ 2079 }, 2080 .ifcd = { 2081 .bLength = sizeof(struct usb2_interface_descriptor), 2082 .bDescriptorType = UDESC_INTERFACE, 2083 .bNumEndpoints = 1, 2084 .bInterfaceClass = UICLASS_HUB, 2085 .bInterfaceSubClass = UISUBCLASS_HUB, 2086 .bInterfaceProtocol = UIPROTO_FSHUB, 2087 }, 2088 .endpd = { 2089 .bLength = sizeof(struct usb2_endpoint_descriptor), 2090 .bDescriptorType = UDESC_ENDPOINT, 2091 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2092 .bmAttributes = UE_INTERRUPT, 2093 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2094 .bInterval = 255, 2095 }, 2096}; 2097 2098static const 2099struct usb2_hub_descriptor ohci_hubd = 2100{ 2101 0, /* dynamic length */ 2102 UDESC_HUB, 2103 0, 2104 {0, 0}, 2105 0, 2106 0, 2107 {0}, 2108}; 2109 2110static void 2111ohci_roothub_exec(struct usb2_bus *bus) 2112{ 2113 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2114 struct usb2_sw_transfer *std = &sc->sc_bus.roothub_req; 2115 char *ptr; 2116 uint32_t port; 2117 uint32_t v; 2118 uint16_t value; 2119 uint16_t index; 2120 uint8_t l; 2121 2122 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2123 2124 /* buffer reset */ 2125 std->ptr = sc->sc_hub_desc.temp; 2126 std->len = 0; 2127 2128 value = UGETW(std->req.wValue); 2129 index = UGETW(std->req.wIndex); 2130 2131 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2132 "wValue=0x%04x wIndex=0x%04x\n", 2133 std->req.bmRequestType, std->req.bRequest, 2134 UGETW(std->req.wLength), value, index); 2135 2136#define C(x,y) ((x) | ((y) << 8)) 2137 switch (C(std->req.bRequest, std->req.bmRequestType)) { 2138 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2139 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2140 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2141 /* 2142 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2143 * for the integrated root hub. 2144 */ 2145 break; 2146 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2147 std->len = 1; 2148 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2149 break; 2150 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2151 switch (value >> 8) { 2152 case UDESC_DEVICE: 2153 if ((value & 0xff) != 0) { 2154 std->err = USB_ERR_IOERROR; 2155 goto done; 2156 } 2157 std->len = sizeof(ohci_devd); 2158 sc->sc_hub_desc.devd = ohci_devd; 2159 break; 2160 2161 case UDESC_CONFIG: 2162 if ((value & 0xff) != 0) { 2163 std->err = USB_ERR_IOERROR; 2164 goto done; 2165 } 2166 std->len = sizeof(ohci_confd); 2167 std->ptr = USB_ADD_BYTES(&ohci_confd, 0); 2168 break; 2169 2170 case UDESC_STRING: 2171 switch (value & 0xff) { 2172 case 0: /* Language table */ 2173 ptr = "\001"; 2174 break; 2175 2176 case 1: /* Vendor */ 2177 ptr = sc->sc_vendor; 2178 break; 2179 2180 case 2: /* Product */ 2181 ptr = "OHCI root HUB"; 2182 break; 2183 2184 default: 2185 ptr = ""; 2186 break; 2187 } 2188 2189 std->len = usb2_make_str_desc 2190 (sc->sc_hub_desc.temp, 2191 sizeof(sc->sc_hub_desc.temp), 2192 ptr); 2193 break; 2194 2195 default: 2196 std->err = USB_ERR_IOERROR; 2197 goto done; 2198 } 2199 break; 2200 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2201 std->len = 1; 2202 sc->sc_hub_desc.temp[0] = 0; 2203 break; 2204 case C(UR_GET_STATUS, UT_READ_DEVICE): 2205 std->len = 2; 2206 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2207 break; 2208 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2209 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2210 std->len = 2; 2211 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2212 break; 2213 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2214 if (value >= OHCI_MAX_DEVICES) { 2215 std->err = USB_ERR_IOERROR; 2216 goto done; 2217 } 2218 sc->sc_addr = value; 2219 break; 2220 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2221 if ((value != 0) && (value != 1)) { 2222 std->err = USB_ERR_IOERROR; 2223 goto done; 2224 } 2225 sc->sc_conf = value; 2226 break; 2227 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2228 break; 2229 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2230 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2231 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2232 std->err = USB_ERR_IOERROR; 2233 goto done; 2234 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2235 break; 2236 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2237 break; 2238 /* Hub requests */ 2239 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2240 break; 2241 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2242 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2243 "port=%d feature=%d\n", 2244 index, value); 2245 if ((index < 1) || 2246 (index > sc->sc_noport)) { 2247 std->err = USB_ERR_IOERROR; 2248 goto done; 2249 } 2250 port = OHCI_RH_PORT_STATUS(index); 2251 switch (value) { 2252 case UHF_PORT_ENABLE: 2253 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2254 break; 2255 case UHF_PORT_SUSPEND: 2256 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2257 break; 2258 case UHF_PORT_POWER: 2259 /* Yes, writing to the LOW_SPEED bit clears power. */ 2260 OWRITE4(sc, port, UPS_LOW_SPEED); 2261 break; 2262 case UHF_C_PORT_CONNECTION: 2263 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2264 break; 2265 case UHF_C_PORT_ENABLE: 2266 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2267 break; 2268 case UHF_C_PORT_SUSPEND: 2269 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2270 break; 2271 case UHF_C_PORT_OVER_CURRENT: 2272 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2273 break; 2274 case UHF_C_PORT_RESET: 2275 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2276 break; 2277 default: 2278 std->err = USB_ERR_IOERROR; 2279 goto done; 2280 } 2281 switch (value) { 2282 case UHF_C_PORT_CONNECTION: 2283 case UHF_C_PORT_ENABLE: 2284 case UHF_C_PORT_SUSPEND: 2285 case UHF_C_PORT_OVER_CURRENT: 2286 case UHF_C_PORT_RESET: 2287 /* enable RHSC interrupt if condition is cleared. */ 2288 if ((OREAD4(sc, port) >> 16) == 0) 2289 ohci_rhsc_enable(sc); 2290 break; 2291 default: 2292 break; 2293 } 2294 break; 2295 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2296 if ((value & 0xff) != 0) { 2297 std->err = USB_ERR_IOERROR; 2298 goto done; 2299 } 2300 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2301 2302 sc->sc_hub_desc.hubd = ohci_hubd; 2303 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2304 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2305 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2306 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2307 /* XXX overcurrent */ 2308 ); 2309 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2310 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2311 2312 for (l = 0; l < sc->sc_noport; l++) { 2313 if (v & 1) { 2314 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2315 } 2316 v >>= 1; 2317 } 2318 sc->sc_hub_desc.hubd.bDescLength = 2319 8 + ((sc->sc_noport + 7) / 8); 2320 std->len = sc->sc_hub_desc.hubd.bDescLength; 2321 break; 2322 2323 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2324 std->len = 16; 2325 bzero(sc->sc_hub_desc.temp, 16); 2326 break; 2327 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2328 DPRINTFN(9, "get port status i=%d\n", 2329 index); 2330 if ((index < 1) || 2331 (index > sc->sc_noport)) { 2332 std->err = USB_ERR_IOERROR; 2333 goto done; 2334 } 2335 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2336 DPRINTFN(9, "port status=0x%04x\n", v); 2337 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2338 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2339 std->len = sizeof(sc->sc_hub_desc.ps); 2340 break; 2341 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2342 std->err = USB_ERR_IOERROR; 2343 goto done; 2344 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2345 break; 2346 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2347 if ((index < 1) || 2348 (index > sc->sc_noport)) { 2349 std->err = USB_ERR_IOERROR; 2350 goto done; 2351 } 2352 port = OHCI_RH_PORT_STATUS(index); 2353 switch (value) { 2354 case UHF_PORT_ENABLE: 2355 OWRITE4(sc, port, UPS_PORT_ENABLED); 2356 break; 2357 case UHF_PORT_SUSPEND: 2358 OWRITE4(sc, port, UPS_SUSPEND); 2359 break; 2360 case UHF_PORT_RESET: 2361 DPRINTFN(6, "reset port %d\n", index); 2362 OWRITE4(sc, port, UPS_RESET); 2363 for (v = 0;; v++) { 2364 if (v < 12) { 2365 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2366 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2367 2368 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2369 break; 2370 } 2371 } else { 2372 std->err = USB_ERR_TIMEOUT; 2373 goto done; 2374 } 2375 } 2376 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2377 index, OREAD4(sc, port)); 2378 break; 2379 case UHF_PORT_POWER: 2380 DPRINTFN(3, "set port power %d\n", index); 2381 OWRITE4(sc, port, UPS_PORT_POWER); 2382 break; 2383 default: 2384 std->err = USB_ERR_IOERROR; 2385 goto done; 2386 } 2387 break; 2388 default: 2389 std->err = USB_ERR_IOERROR; 2390 goto done; 2391 } 2392done: 2393 return; 2394} 2395 2396static void 2397ohci_xfer_setup(struct usb2_setup_params *parm) 2398{ 2399 struct usb2_page_search page_info; 2400 struct usb2_page_cache *pc; 2401 ohci_softc_t *sc; 2402 struct usb2_xfer *xfer; 2403 void *last_obj; 2404 uint32_t ntd; 2405 uint32_t nitd; 2406 uint32_t nqh; 2407 uint32_t n; 2408 2409 sc = OHCI_BUS2SC(parm->udev->bus); 2410 xfer = parm->curr_xfer; 2411 2412 parm->hc_max_packet_size = 0x500; 2413 parm->hc_max_packet_count = 1; 2414 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2415 2416 /* 2417 * calculate ntd and nqh 2418 */ 2419 if (parm->methods == &ohci_device_ctrl_methods) { 2420 xfer->flags_int.bdma_enable = 1; 2421 2422 usb2_transfer_setup_sub(parm); 2423 2424 nitd = 0; 2425 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2426 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2427 nqh = 1; 2428 2429 } else if (parm->methods == &ohci_device_bulk_methods) { 2430 xfer->flags_int.bdma_enable = 1; 2431 2432 usb2_transfer_setup_sub(parm); 2433 2434 nitd = 0; 2435 ntd = ((2 * xfer->nframes) 2436 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2437 nqh = 1; 2438 2439 } else if (parm->methods == &ohci_device_intr_methods) { 2440 xfer->flags_int.bdma_enable = 1; 2441 2442 usb2_transfer_setup_sub(parm); 2443 2444 nitd = 0; 2445 ntd = ((2 * xfer->nframes) 2446 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2447 nqh = 1; 2448 2449 } else if (parm->methods == &ohci_device_isoc_methods) { 2450 xfer->flags_int.bdma_enable = 1; 2451 2452 usb2_transfer_setup_sub(parm); 2453 2454 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2455 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2456 1 /* EXTRA */ ); 2457 ntd = 0; 2458 nqh = 1; 2459 2460 } else { 2461 2462 usb2_transfer_setup_sub(parm); 2463 2464 nitd = 0; 2465 ntd = 0; 2466 nqh = 0; 2467 } 2468 2469alloc_dma_set: 2470 2471 if (parm->err) { 2472 return; 2473 } 2474 last_obj = NULL; 2475 2476 if (usb2_transfer_setup_sub_malloc( 2477 parm, &pc, sizeof(ohci_td_t), 2478 OHCI_TD_ALIGN, ntd)) { 2479 parm->err = USB_ERR_NOMEM; 2480 return; 2481 } 2482 if (parm->buf) { 2483 for (n = 0; n != ntd; n++) { 2484 ohci_td_t *td; 2485 2486 usb2_get_page(pc + n, 0, &page_info); 2487 2488 td = page_info.buffer; 2489 2490 /* init TD */ 2491 td->td_self = htole32(page_info.physaddr); 2492 td->obj_next = last_obj; 2493 td->page_cache = pc + n; 2494 2495 last_obj = td; 2496 2497 usb2_pc_cpu_flush(pc + n); 2498 } 2499 } 2500 if (usb2_transfer_setup_sub_malloc( 2501 parm, &pc, sizeof(ohci_itd_t), 2502 OHCI_ITD_ALIGN, nitd)) { 2503 parm->err = USB_ERR_NOMEM; 2504 return; 2505 } 2506 if (parm->buf) { 2507 for (n = 0; n != nitd; n++) { 2508 ohci_itd_t *itd; 2509 2510 usb2_get_page(pc + n, 0, &page_info); 2511 2512 itd = page_info.buffer; 2513 2514 /* init TD */ 2515 itd->itd_self = htole32(page_info.physaddr); 2516 itd->obj_next = last_obj; 2517 itd->page_cache = pc + n; 2518 2519 last_obj = itd; 2520 2521 usb2_pc_cpu_flush(pc + n); 2522 } 2523 } 2524 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2525 2526 last_obj = NULL; 2527 2528 if (usb2_transfer_setup_sub_malloc( 2529 parm, &pc, sizeof(ohci_ed_t), 2530 OHCI_ED_ALIGN, nqh)) { 2531 parm->err = USB_ERR_NOMEM; 2532 return; 2533 } 2534 if (parm->buf) { 2535 for (n = 0; n != nqh; n++) { 2536 ohci_ed_t *ed; 2537 2538 usb2_get_page(pc + n, 0, &page_info); 2539 2540 ed = page_info.buffer; 2541 2542 /* init QH */ 2543 ed->ed_self = htole32(page_info.physaddr); 2544 ed->obj_next = last_obj; 2545 ed->page_cache = pc + n; 2546 2547 last_obj = ed; 2548 2549 usb2_pc_cpu_flush(pc + n); 2550 } 2551 } 2552 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2553 2554 if (!xfer->flags_int.curr_dma_set) { 2555 xfer->flags_int.curr_dma_set = 1; 2556 goto alloc_dma_set; 2557 } 2558} 2559 2560static void 2561ohci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2562 struct usb2_pipe *pipe) 2563{ 2564 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2565 2566 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2567 pipe, udev->address, 2568 edesc->bEndpointAddress, udev->flags.usb2_mode, 2569 sc->sc_addr); 2570 2571 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2572 /* not supported */ 2573 return; 2574 } 2575 if (udev->device_index != sc->sc_addr) { 2576 switch (edesc->bmAttributes & UE_XFERTYPE) { 2577 case UE_CONTROL: 2578 pipe->methods = &ohci_device_ctrl_methods; 2579 break; 2580 case UE_INTERRUPT: 2581 pipe->methods = &ohci_device_intr_methods; 2582 break; 2583 case UE_ISOCHRONOUS: 2584 if (udev->speed == USB_SPEED_FULL) { 2585 pipe->methods = &ohci_device_isoc_methods; 2586 } 2587 break; 2588 case UE_BULK: 2589 if (udev->speed != USB_SPEED_LOW) { 2590 pipe->methods = &ohci_device_bulk_methods; 2591 } 2592 break; 2593 default: 2594 /* do nothing */ 2595 break; 2596 } 2597 } 2598} 2599 2600static void 2601ohci_xfer_unsetup(struct usb2_xfer *xfer) 2602{ 2603 return; 2604} 2605 2606static void 2607ohci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 2608{ 2609 /* 2610 * Wait until hardware has finished any possible use of the 2611 * transfer descriptor(s) and QH 2612 */ 2613 *pus = (1125); /* microseconds */ 2614} 2615 2616static void 2617ohci_device_resume(struct usb2_device *udev) 2618{ 2619 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2620 struct usb2_xfer *xfer; 2621 struct usb2_pipe_methods *methods; 2622 ohci_ed_t *ed; 2623 2624 DPRINTF("\n"); 2625 2626 USB_BUS_LOCK(udev->bus); 2627 2628 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2629 2630 if (xfer->xroot->udev == udev) { 2631 2632 methods = xfer->pipe->methods; 2633 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2634 2635 if (methods == &ohci_device_bulk_methods) { 2636 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2637 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2638 } 2639 if (methods == &ohci_device_ctrl_methods) { 2640 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2641 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2642 } 2643 if (methods == &ohci_device_intr_methods) { 2644 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2645 } 2646 } 2647 } 2648 2649 USB_BUS_UNLOCK(udev->bus); 2650 2651 return; 2652} 2653 2654static void 2655ohci_device_suspend(struct usb2_device *udev) 2656{ 2657 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2658 struct usb2_xfer *xfer; 2659 struct usb2_pipe_methods *methods; 2660 ohci_ed_t *ed; 2661 2662 DPRINTF("\n"); 2663 2664 USB_BUS_LOCK(udev->bus); 2665 2666 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2667 2668 if (xfer->xroot->udev == udev) { 2669 2670 methods = xfer->pipe->methods; 2671 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2672 2673 if (methods == &ohci_device_bulk_methods) { 2674 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2675 } 2676 if (methods == &ohci_device_ctrl_methods) { 2677 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2678 } 2679 if (methods == &ohci_device_intr_methods) { 2680 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2681 } 2682 } 2683 } 2684 2685 USB_BUS_UNLOCK(udev->bus); 2686 2687 return; 2688} 2689 2690static void 2691ohci_set_hw_power(struct usb2_bus *bus) 2692{ 2693 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2694 uint32_t temp; 2695 uint32_t flags; 2696 2697 DPRINTF("\n"); 2698 2699 USB_BUS_LOCK(bus); 2700 2701 flags = bus->hw_power_state; 2702 2703 temp = OREAD4(sc, OHCI_CONTROL); 2704 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2705 2706 if (flags & USB_HW_POWER_CONTROL) 2707 temp |= OHCI_CLE; 2708 2709 if (flags & USB_HW_POWER_BULK) 2710 temp |= OHCI_BLE; 2711 2712 if (flags & USB_HW_POWER_INTERRUPT) 2713 temp |= OHCI_PLE; 2714 2715 if (flags & USB_HW_POWER_ISOC) 2716 temp |= OHCI_IE | OHCI_PLE; 2717 2718 OWRITE4(sc, OHCI_CONTROL, temp); 2719 2720 USB_BUS_UNLOCK(bus); 2721 2722 return; 2723} 2724 2725struct usb2_bus_methods ohci_bus_methods = 2726{ 2727 .pipe_init = ohci_pipe_init, 2728 .xfer_setup = ohci_xfer_setup, 2729 .xfer_unsetup = ohci_xfer_unsetup, 2730 .get_dma_delay = ohci_get_dma_delay, 2731 .device_resume = ohci_device_resume, 2732 .device_suspend = ohci_device_suspend, 2733 .set_hw_power = ohci_set_hw_power, 2734 .roothub_exec = ohci_roothub_exec, 2735}; 2736