ehci.h revision 189496
157429Smarkm/* $FreeBSD: head/sys/dev/usb/controller/ehci.h 189496 2009-03-07 19:49:47Z thompsa $ */ 257429Smarkm/*- 357429Smarkm * Copyright (c) 2001 The NetBSD Foundation, Inc. 457429Smarkm * All rights reserved. 560576Skris * 665674Skris * This code is derived from software contributed to The NetBSD Foundation 765674Skris * by Lennart Augustsson (lennart@augustsson.net). 865674Skris * 965674Skris * Redistribution and use in source and binary forms, with or without 1065674Skris * modification, are permitted provided that the following conditions 1160576Skris * are met: 1265674Skris * 1. Redistributions of source code must retain the above copyright 1365674Skris * notice, this list of conditions and the following disclaimer. 1492559Sdes * 2. Redistributions in binary form must reproduce the above copyright 1565674Skris * notice, this list of conditions and the following disclaimer in the 1665674Skris * documentation and/or other materials provided with the distribution. 1765674Skris * 3. All advertising materials mentioning features or use of this software 1865674Skris * must display the following acknowledgement: 1965674Skris * This product includes software developed by the NetBSD 2065674Skris * Foundation, Inc. and its contributors. 2165674Skris * 4. Neither the name of The NetBSD Foundation nor the names of its 2265674Skris * contributors may be used to endorse or promote products derived 2365674Skris * from this software without specific prior written permission. 2465674Skris * 2565674Skris * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 2665674Skris * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2765674Skris * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2865674Skris * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2965674Skris * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 3065674Skris * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 3165674Skris * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 3265674Skris * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 3365674Skris * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3465674Skris * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3557429Smarkm * POSSIBILITY OF SUCH DAMAGE. 3657429Smarkm */ 3757429Smarkm 38126277Sdes#ifndef _EHCI_H_ 3957429Smarkm#define _EHCI_H_ 4060576Skris 4176262Sgreen#define EHCI_MAX_DEVICES USB_MAX_DEVICES 4276262Sgreen 4357429Smarkm/* PCI config registers */ 4457464Sgreen#define PCI_CBMEM 0x10 /* configuration base MEM */ 4598684Sdes#define PCI_INTERFACE_EHCI 0x20 4698941Sdes#define PCI_USBREV 0x60 /* RO USB protocol revision */ 4798941Sdes#define PCI_USB_REV_MASK 0xff 4898941Sdes#define PCI_USB_REV_PRE_1_0 0x00 4998941Sdes#define PCI_USB_REV_1_0 0x10 5098941Sdes#define PCI_USB_REV_1_1 0x11 5198684Sdes#define PCI_USB_REV_2_0 0x20 52124211Sdes#define PCI_EHCI_FLADJ 0x61 /* RW Frame len adj, SOF=59488+6*fladj */ 53124211Sdes#define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */ 5498684Sdes 55126277Sdes/* EHCI Extended Capabilities */ 56126277Sdes#define EHCI_EC_LEGSUP 0x01 57126277Sdes#define EHCI_EECP_NEXT(x) (((x) >> 8) & 0xff) 58126277Sdes#define EHCI_EECP_ID(x) ((x) & 0xff) 59126277Sdes 60126277Sdes/* Legacy support extended capability */ 61126277Sdes#define EHCI_LEGSUP_BIOS_SEM 0x02 62126277Sdes#define EHCI_LEGSUP_OS_SEM 0x03 63126277Sdes#define EHCI_LEGSUP_USBLEGCTLSTS 0x04 64126277Sdes 65126277Sdes/* EHCI capability registers */ 66124211Sdes#define EHCI_CAPLENGTH 0x00 /* RO Capability register length field */ 67124211Sdes/* reserved 0x01 */ 68124211Sdes#define EHCI_HCIVERSION 0x02 /* RO Interface version number */ 69124211Sdes#define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */ 70124211Sdes#define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf) 7157429Smarkm#define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000) 7292559Sdes#define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */ 7392559Sdes#define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */ 7492559Sdes#define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */ 7592559Sdes#define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */ 7692559Sdes#define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */ 7798684Sdes#define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */ 7892559Sdes#define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */ 7992559Sdes#define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */ 8092559Sdes#define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */ 8192559Sdes#define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */ 8292559Sdes#define EHCI_HCSP_PORTROUTE 0x0c /* RO Companion port route description */ 8369591Sgreen 8492559Sdes/* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */ 8592559Sdes#define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */ 8692559Sdes#define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */ 8792559Sdes#define EHCI_CMD_ITC_1 0x00010000 8898684Sdes#define EHCI_CMD_ITC_2 0x00020000 8992559Sdes#define EHCI_CMD_ITC_4 0x00040000 9092559Sdes#define EHCI_CMD_ITC_8 0x00080000 9192559Sdes#define EHCI_CMD_ITC_16 0x00100000 9298684Sdes#define EHCI_CMD_ITC_32 0x00200000 9398684Sdes#define EHCI_CMD_ITC_64 0x00400000 9498684Sdes#define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */ 9598684Sdes#define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */ 9698684Sdes#define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */ 9798684Sdes#define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door 9898684Sdes * bell */ 9998684Sdes#define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */ 10098684Sdes#define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */ 101126277Sdes#define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */ 102124211Sdes#define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */ 103124211Sdes#define EHCI_CMD_HCRESET 0x00000002 /* RW reset */ 104124211Sdes#define EHCI_CMD_RS 0x00000001 /* RW run/stop */ 105124211Sdes#define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */ 106126277Sdes#define EHCI_STS_ASS 0x00008000 /* RO async sched status */ 107126277Sdes#define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */ 108126277Sdes#define EHCI_STS_REC 0x00002000 /* RO reclamation */ 10992559Sdes#define EHCI_STS_HCH 0x00001000 /* RO host controller halted */ 11092559Sdes#define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */ 11169591Sgreen#define EHCI_STS_HSE 0x00000010 /* RWC host system error */ 11292559Sdes#define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */ 11357429Smarkm#define EHCI_STS_PCD 0x00000004 /* RWC port change detect */ 11498684Sdes#define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */ 115126277Sdes#define EHCI_STS_INT 0x00000001 /* RWC interrupt */ 11657429Smarkm#define EHCI_STS_INTRS(x) ((x) & 0x3f) 11792559Sdes 11857429Smarkm/* 11999063Sdes * NOTE: the doorbell interrupt is enabled, but the doorbell is never 12098684Sdes * used! SiS chipsets require this. 121126277Sdes */ 12269591Sgreen#define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | \ 12392559Sdes EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT) 12469591Sgreen 12599063Sdes#define EHCI_USBINTR 0x08 /* RW Interrupt register */ 12698684Sdes#define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance 127126277Sdes * ena */ 12898684Sdes#define EHCI_INTR_HSEE 0x00000010 /* host system error ena */ 12998684Sdes#define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */ 13098684Sdes#define EHCI_INTR_PCIE 0x00000004 /* port change ena */ 13169591Sgreen#define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */ 13276262Sgreen#define EHCI_INTR_UIE 0x00000001 /* USB intr ena */ 13369591Sgreen 13457429Smarkm#define EHCI_FRINDEX 0x0c /* RW Frame Index register */ 13576262Sgreen 13692559Sdes#define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */ 13757429Smarkm 13869591Sgreen#define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */ 13969591Sgreen#define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */ 14069591Sgreen 14157429Smarkm#define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */ 14257429Smarkm#define EHCI_CONF_CF 0x00000001 /* RW configure flag */ 14369591Sgreen 14469591Sgreen#define EHCI_PORTSC(n) (0x40+(4*(n))) /* RO, RW, RWC Port Status reg */ 14569591Sgreen#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */ 14660576Skris#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */ 14769591Sgreen#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */ 14869591Sgreen#define EHCI_PS_PTC 0x000f0000 /* RW port test control */ 14969591Sgreen#define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */ 15069591Sgreen#define EHCI_PS_PO 0x00002000 /* RW port owner */ 15169591Sgreen#define EHCI_PS_PP 0x00001000 /* RW,RO port power */ 15260576Skris#define EHCI_PS_LS 0x00000c00 /* RO line status */ 15357429Smarkm#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400) 15469591Sgreen#define EHCI_PS_PR 0x00000100 /* RW port reset */ 15569591Sgreen#define EHCI_PS_SUSP 0x00000080 /* RW suspend */ 15657429Smarkm#define EHCI_PS_FPR 0x00000040 /* RW force port resume */ 15769591Sgreen#define EHCI_PS_OCC 0x00000020 /* RWC over current change */ 15869591Sgreen#define EHCI_PS_OCA 0x00000010 /* RO over current active */ 15969591Sgreen#define EHCI_PS_PEC 0x00000008 /* RWC port enable change */ 16069591Sgreen#define EHCI_PS_PE 0x00000004 /* RW port enable */ 16169591Sgreen#define EHCI_PS_CSC 0x00000002 /* RWC connect status change */ 16257429Smarkm#define EHCI_PS_CS 0x00000001 /* RO connect status */ 16357429Smarkm#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC) 16460576Skris 16560576Skris#define EHCI_USBMODE 0x68 /* RW USB Device mode register */ 16660576Skris#define EHCI_UM_CM 0x00000003 /* R/WO Controller Mode */ 16760576Skris#define EHCI_UM_CM_IDLE 0x0 /* Idle */ 16869591Sgreen#define EHCI_UM_CM_HOST 0x3 /* Host Controller */ 16965674Skris#define EHCI_UM_ES 0x00000004 /* R/WO Endian Select */ 17060576Skris#define EHCI_UM_ES_LE 0x0 /* Little-endian byte alignment */ 17160576Skris#define EHCI_UM_ES_BE 0x4 /* Big-endian byte alignment */ 17261212Skris#define EHCI_UM_SDIS 0x00000010 /* R/WO Stream Disable Mode */ 17360576Skris 17465674Skris#define EHCI_PORT_RESET_COMPLETE 2 /* ms */ 17569591Sgreen 17692559Sdes/* 17769591Sgreen * Alignment NOTE: structures must be aligned so that the hardware can index 17869591Sgreen * without performing addition. 17969591Sgreen */ 18060576Skris#define EHCI_FRAMELIST_ALIGN 0x1000 /* bytes */ 18160576Skris#define EHCI_FRAMELIST_COUNT 1024 /* units */ 18269591Sgreen#define EHCI_VIRTUAL_FRAMELIST_COUNT 128 /* units */ 18369591Sgreen 18460576Skris#if ((8*EHCI_VIRTUAL_FRAMELIST_COUNT) < USB_MAX_HS_ISOC_FRAMES_PER_XFER) 18560576Skris#error "maximum number of high-speed isochronous frames is higher than supported!" 18669591Sgreen#endif 18760576Skris 18860576Skris#if (EHCI_VIRTUAL_FRAMELIST_COUNT < USB_MAX_FS_ISOC_FRAMES_PER_XFER) 18960576Skris#error "maximum number of full-speed isochronous frames is higher than supported!" 19060576Skris#endif 19157429Smarkm 19257429Smarkm/* Link types */ 19357429Smarkm#define EHCI_LINK_TERMINATE 0x00000001 19457429Smarkm#define EHCI_LINK_TYPE(x) ((x) & 0x00000006) 19557429Smarkm#define EHCI_LINK_ITD 0x0 19657429Smarkm#define EHCI_LINK_QH 0x2 19757429Smarkm#define EHCI_LINK_SITD 0x4 19857429Smarkm#define EHCI_LINK_FSTN 0x6 19969591Sgreen#define EHCI_LINK_ADDR(x) ((x) &~ 0x1f) 20061212Skris 20161212Skris/* Structures alignment (bytes) */ 20269591Sgreen#define EHCI_ITD_ALIGN 128 20369591Sgreen#define EHCI_SITD_ALIGN 64 20457429Smarkm#define EHCI_QTD_ALIGN 64 20557429Smarkm#define EHCI_QH_ALIGN 128 20669591Sgreen#define EHCI_FSTN_ALIGN 32 20769591Sgreen/* Data buffers are divided into one or more pages */ 20857429Smarkm#define EHCI_PAGE_SIZE 0x1000 20969591Sgreen#if ((USB_PAGE_SIZE < EHCI_PAGE_SIZE) || (EHCI_PAGE_SIZE == 0) || \ 21069591Sgreen (USB_PAGE_SIZE < EHCI_ITD_ALIGN) || (EHCI_ITD_ALIGN == 0) || \ 21157429Smarkm (USB_PAGE_SIZE < EHCI_SITD_ALIGN) || (EHCI_SITD_ALIGN == 0) || \ 21257429Smarkm (USB_PAGE_SIZE < EHCI_QTD_ALIGN) || (EHCI_QTD_ALIGN == 0) || \ 21360576Skris (USB_PAGE_SIZE < EHCI_QH_ALIGN) || (EHCI_QH_ALIGN == 0) || \ 21469591Sgreen (USB_PAGE_SIZE < EHCI_FSTN_ALIGN) || (EHCI_FSTN_ALIGN == 0)) 21592559Sdes#error "Invalid USB page size!" 21692559Sdes#endif 21757429Smarkm 21892559Sdes 21998941Sdes/* 22098941Sdes * Isochronous Transfer Descriptor. This descriptor is used for high speed 22198941Sdes * transfers only. 22292559Sdes */ 22398941Sdesstruct ehci_itd { 22492559Sdes volatile uint32_t itd_next; 22592559Sdes volatile uint32_t itd_status[8]; 22692559Sdes#define EHCI_ITD_SET_LEN(x) ((x) << 16) 22792559Sdes#define EHCI_ITD_GET_LEN(x) (((x) >> 16) & 0xFFF) 22892559Sdes#define EHCI_ITD_IOC (1 << 15) 22992559Sdes#define EHCI_ITD_SET_PG(x) ((x) << 12) 23092559Sdes#define EHCI_ITD_GET_PG(x) (((x) >> 12) & 0x7) 23192559Sdes#define EHCI_ITD_SET_OFFS(x) (x) 23292559Sdes#define EHCI_ITD_GET_OFFS(x) (((x) >> 0) & 0xFFF) 23392559Sdes#define EHCI_ITD_ACTIVE (1 << 31) 23492559Sdes#define EHCI_ITD_DATABUFERR (1 << 30) 23592559Sdes#define EHCI_ITD_BABBLE (1 << 29) 23692559Sdes#define EHCI_ITD_XACTERR (1 << 28) 23769591Sgreen volatile uint32_t itd_bp[7]; 23869591Sgreen /* itd_bp[0] */ 23969591Sgreen#define EHCI_ITD_SET_ADDR(x) (x) 24069591Sgreen#define EHCI_ITD_GET_ADDR(x) (((x) >> 0) & 0x7F) 24169591Sgreen#define EHCI_ITD_SET_ENDPT(x) ((x) << 8) 24269591Sgreen#define EHCI_ITD_GET_ENDPT(x) (((x) >> 8) & 0xF) 24369591Sgreen /* itd_bp[1] */ 24492559Sdes#define EHCI_ITD_SET_DIR_IN (1 << 11) 24592559Sdes#define EHCI_ITD_SET_DIR_OUT (0 << 11) 24692559Sdes#define EHCI_ITD_SET_MPL(x) (x) 24792559Sdes#define EHCI_ITD_GET_MPL(x) (((x) >> 0) & 0x7FF) 24898941Sdes volatile uint32_t itd_bp_hi[7]; 24998941Sdes/* 25098941Sdes * Extra information needed: 25198941Sdes */ 25298941Sdes uint32_t itd_self; 25398941Sdes struct ehci_itd *next; 25498941Sdes struct ehci_itd *prev; 25598941Sdes struct ehci_itd *obj_next; 25698941Sdes struct usb2_page_cache *page_cache; 25792559Sdes} __aligned(EHCI_ITD_ALIGN); 25892559Sdes 25992559Sdestypedef struct ehci_itd ehci_itd_t; 26092559Sdes 26192559Sdes/* 26292559Sdes * Split Transaction Isochronous Transfer Descriptor. This descriptor is used 263113911Sdes * for full speed transfers only. 26492559Sdes */ 26592559Sdesstruct ehci_sitd { 26692559Sdes volatile uint32_t sitd_next; 26792559Sdes volatile uint32_t sitd_portaddr; 26892559Sdes#define EHCI_SITD_SET_DIR_OUT (0 << 31) 26992559Sdes#define EHCI_SITD_SET_DIR_IN (1 << 31) 27092559Sdes#define EHCI_SITD_SET_ADDR(x) (x) 27198941Sdes#define EHCI_SITD_GET_ADDR(x) ((x) & 0x7F) 27257429Smarkm#define EHCI_SITD_SET_ENDPT(x) ((x) << 8) 27357429Smarkm#define EHCI_SITD_GET_ENDPT(x) (((x) >> 8) & 0xF) 27460576Skris#define EHCI_SITD_GET_DIR(x) ((x) >> 31) 27592559Sdes#define EHCI_SITD_SET_PORT(x) ((x) << 24) 27660576Skris#define EHCI_SITD_GET_PORT(x) (((x) >> 24) & 0x7F) 27769591Sgreen#define EHCI_SITD_SET_HUBA(x) ((x) << 16) 27869591Sgreen#define EHCI_SITD_GET_HUBA(x) (((x) >> 16) & 0x7F) 27998941Sdes volatile uint32_t sitd_mask; 28098941Sdes#define EHCI_SITD_SET_SMASK(x) (x) 28198941Sdes#define EHCI_SITD_SET_CMASK(x) ((x) << 8) 28292559Sdes volatile uint32_t sitd_status; 28392559Sdes#define EHCI_SITD_COMPLETE_SPLIT (1<<1) 28498941Sdes#define EHCI_SITD_START_SPLIT (0<<1) 28560576Skris#define EHCI_SITD_MISSED_MICRO_FRAME (1<<2) 28660576Skris#define EHCI_SITD_XACTERR (1<<3) 28760576Skris#define EHCI_SITD_BABBLE (1<<4) 28892559Sdes#define EHCI_SITD_DATABUFERR (1<<5) 28957429Smarkm#define EHCI_SITD_ERROR (1<<6) 29098941Sdes#define EHCI_SITD_ACTIVE (1<<7) 29198941Sdes#define EHCI_SITD_IOC (1<<31) 29298941Sdes#define EHCI_SITD_SET_LEN(len) ((len)<<16) 29392559Sdes#define EHCI_SITD_GET_LEN(x) (((x)>>16) & 0x3FF) 29492559Sdes volatile uint32_t sitd_bp[2]; 29598941Sdes volatile uint32_t sitd_back; 29657429Smarkm volatile uint32_t sitd_bp_hi[2]; 29757429Smarkm/* 29869591Sgreen * Extra information needed: 29969591Sgreen */ 30069591Sgreen uint32_t sitd_self; 30169591Sgreen struct ehci_sitd *next; 30257429Smarkm struct ehci_sitd *prev; 30360576Skris struct ehci_sitd *obj_next; 30469591Sgreen struct usb2_page_cache *page_cache; 30592559Sdes} __aligned(EHCI_SITD_ALIGN); 30657429Smarkm 30769591Sgreentypedef struct ehci_sitd ehci_sitd_t; 30876262Sgreen 30957429Smarkm/* Queue Element Transfer Descriptor */ 31069591Sgreenstruct ehci_qtd { 31169591Sgreen volatile uint32_t qtd_next; 31269591Sgreen volatile uint32_t qtd_altnext; 31357429Smarkm volatile uint32_t qtd_status; 31492559Sdes#define EHCI_QTD_GET_STATUS(x) (((x) >> 0) & 0xff) 31557429Smarkm#define EHCI_QTD_SET_STATUS(x) ((x) << 0) 31669591Sgreen#define EHCI_QTD_ACTIVE 0x80 31769591Sgreen#define EHCI_QTD_HALTED 0x40 31857429Smarkm#define EHCI_QTD_BUFERR 0x20 31992559Sdes#define EHCI_QTD_BABBLE 0x10 32092559Sdes#define EHCI_QTD_XACTERR 0x08 32198684Sdes#define EHCI_QTD_MISSEDMICRO 0x04 32298684Sdes#define EHCI_QTD_SPLITXSTATE 0x02 32398684Sdes#define EHCI_QTD_PINGSTATE 0x01 32498684Sdes#define EHCI_QTD_STATERRS 0x74 32598684Sdes#define EHCI_QTD_GET_PID(x) (((x) >> 8) & 0x3) 32698684Sdes#define EHCI_QTD_SET_PID(x) ((x) << 8) 327126277Sdes#define EHCI_QTD_PID_OUT 0x0 32898684Sdes#define EHCI_QTD_PID_IN 0x1 32998684Sdes#define EHCI_QTD_PID_SETUP 0x2 33098684Sdes#define EHCI_QTD_GET_CERR(x) (((x) >> 10) & 0x3) 33198684Sdes#define EHCI_QTD_SET_CERR(x) ((x) << 10) 33298684Sdes#define EHCI_QTD_GET_C_PAGE(x) (((x) >> 12) & 0x7) 33398684Sdes#define EHCI_QTD_SET_C_PAGE(x) ((x) << 12) 33498684Sdes#define EHCI_QTD_GET_IOC(x) (((x) >> 15) & 0x1) 33598684Sdes#define EHCI_QTD_IOC 0x00008000 33698684Sdes#define EHCI_QTD_GET_BYTES(x) (((x) >> 16) & 0x7fff) 33798684Sdes#define EHCI_QTD_SET_BYTES(x) ((x) << 16) 33898684Sdes#define EHCI_QTD_GET_TOGGLE(x) (((x) >> 31) & 0x1) 33998684Sdes#define EHCI_QTD_SET_TOGGLE(x) ((x) << 31) 34098684Sdes#define EHCI_QTD_TOGGLE_MASK 0x80000000 34198684Sdes#define EHCI_QTD_NBUFFERS 5 34298684Sdes#define EHCI_QTD_PAYLOAD_MAX ((EHCI_QTD_NBUFFERS-1)*EHCI_PAGE_SIZE) 34398684Sdes volatile uint32_t qtd_buffer[EHCI_QTD_NBUFFERS]; 34498684Sdes volatile uint32_t qtd_buffer_hi[EHCI_QTD_NBUFFERS]; 34598684Sdes/* 34698684Sdes * Extra information needed: 34798684Sdes */ 34898684Sdes struct ehci_qtd *alt_next; 34998684Sdes struct ehci_qtd *obj_next; 35098684Sdes struct usb2_page_cache *page_cache; 35198684Sdes uint32_t qtd_self; 35298684Sdes uint16_t len; 35398684Sdes} __aligned(EHCI_QTD_ALIGN); 35498684Sdes 35598684Sdestypedef struct ehci_qtd ehci_qtd_t; 356124211Sdes 357124211Sdes/* Queue Head Sub Structure */ 358124211Sdesstruct ehci_qh_sub { 35998684Sdes volatile uint32_t qtd_next; 360124211Sdes volatile uint32_t qtd_altnext; 361124211Sdes volatile uint32_t qtd_status; 362124211Sdes volatile uint32_t qtd_buffer[EHCI_QTD_NBUFFERS]; 363124211Sdes volatile uint32_t qtd_buffer_hi[EHCI_QTD_NBUFFERS]; 36498684Sdes} __aligned(4); 365124211Sdes 366124211Sdes/* Queue Head */ 367124211Sdesstruct ehci_qh { 36898684Sdes volatile uint32_t qh_link; 36998684Sdes volatile uint32_t qh_endp; 37098684Sdes#define EHCI_QH_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */ 37198684Sdes#define EHCI_QH_SET_ADDR(x) (x) 37298684Sdes#define EHCI_QH_ADDRMASK 0x0000007f 37398684Sdes#define EHCI_QH_GET_INACT(x) (((x) >> 7) & 0x01) /* inactivate on next */ 37498684Sdes#define EHCI_QH_INACT 0x00000080 37598684Sdes#define EHCI_QH_GET_ENDPT(x) (((x) >> 8) & 0x0f) /* endpoint no */ 37698684Sdes#define EHCI_QH_SET_ENDPT(x) ((x) << 8) 37798684Sdes#define EHCI_QH_GET_EPS(x) (((x) >> 12) & 0x03) /* endpoint speed */ 37898684Sdes#define EHCI_QH_SET_EPS(x) ((x) << 12) 37998684Sdes#define EHCI_QH_SPEED_FULL 0x0 38098684Sdes#define EHCI_QH_SPEED_LOW 0x1 38198684Sdes#define EHCI_QH_SPEED_HIGH 0x2 38298684Sdes#define EHCI_QH_GET_DTC(x) (((x) >> 14) & 0x01) /* data toggle control */ 38398684Sdes#define EHCI_QH_DTC 0x00004000 38498684Sdes#define EHCI_QH_GET_HRECL(x) (((x) >> 15) & 0x01) /* head of reclamation */ 38598684Sdes#define EHCI_QH_HRECL 0x00008000 38698684Sdes#define EHCI_QH_GET_MPL(x) (((x) >> 16) & 0x7ff) /* max packet len */ 387124211Sdes#define EHCI_QH_SET_MPL(x) ((x) << 16) 388124211Sdes#define EHCI_QH_MPLMASK 0x07ff0000 389124211Sdes#define EHCI_QH_GET_CTL(x) (((x) >> 27) & 0x01) /* control endpoint */ 39098684Sdes#define EHCI_QH_CTL 0x08000000 391124211Sdes#define EHCI_QH_GET_NRL(x) (((x) >> 28) & 0x0f) /* NAK reload */ 392124211Sdes#define EHCI_QH_SET_NRL(x) ((x) << 28) 393124211Sdes volatile uint32_t qh_endphub; 394124211Sdes#define EHCI_QH_GET_SMASK(x) (((x) >> 0) & 0xff) /* intr sched mask */ 39598684Sdes#define EHCI_QH_SET_SMASK(x) ((x) << 0) 396124211Sdes#define EHCI_QH_GET_CMASK(x) (((x) >> 8) & 0xff) /* split completion mask */ 397124211Sdes#define EHCI_QH_SET_CMASK(x) ((x) << 8) 398124211Sdes#define EHCI_QH_GET_HUBA(x) (((x) >> 16) & 0x7f) /* hub address */ 39998684Sdes#define EHCI_QH_SET_HUBA(x) ((x) << 16) 40098684Sdes#define EHCI_QH_GET_PORT(x) (((x) >> 23) & 0x7f) /* hub port */ 40198684Sdes#define EHCI_QH_SET_PORT(x) ((x) << 23) 40298684Sdes#define EHCI_QH_GET_MULT(x) (((x) >> 30) & 0x03) /* pipe multiplier */ 40398684Sdes#define EHCI_QH_SET_MULT(x) ((x) << 30) 40498684Sdes volatile uint32_t qh_curqtd; 40598684Sdes struct ehci_qh_sub qh_qtd; 40698684Sdes/* 40798684Sdes * Extra information needed: 40898684Sdes */ 40998684Sdes struct ehci_qh *next; 41098684Sdes struct ehci_qh *prev; 41198684Sdes struct ehci_qh *obj_next; 41298684Sdes struct usb2_page_cache *page_cache; 413126277Sdes uint32_t qh_self; 41498684Sdes} __aligned(EHCI_QH_ALIGN); 41598684Sdes 41698684Sdestypedef struct ehci_qh ehci_qh_t; 41798684Sdes 418126277Sdes/* Periodic Frame Span Traversal Node */ 41998684Sdesstruct ehci_fstn { 42098684Sdes volatile uint32_t fstn_link; 42198684Sdes volatile uint32_t fstn_back; 42298684Sdes} __aligned(EHCI_FSTN_ALIGN); 42398684Sdes 42498684Sdestypedef struct ehci_fstn ehci_fstn_t; 42598684Sdes 42698684Sdesstruct ehci_hw_softc { 42798684Sdes struct usb2_page_cache pframes_pc; 42898684Sdes struct usb2_page_cache async_start_pc; 42998684Sdes struct usb2_page_cache intr_start_pc[EHCI_VIRTUAL_FRAMELIST_COUNT]; 43098684Sdes struct usb2_page_cache isoc_hs_start_pc[EHCI_VIRTUAL_FRAMELIST_COUNT]; 43198684Sdes struct usb2_page_cache isoc_fs_start_pc[EHCI_VIRTUAL_FRAMELIST_COUNT]; 43298684Sdes 433126277Sdes struct usb2_page pframes_pg; 43498684Sdes struct usb2_page async_start_pg; 43598684Sdes struct usb2_page intr_start_pg[EHCI_VIRTUAL_FRAMELIST_COUNT]; 43698684Sdes struct usb2_page isoc_hs_start_pg[EHCI_VIRTUAL_FRAMELIST_COUNT]; 43798684Sdes struct usb2_page isoc_fs_start_pg[EHCI_VIRTUAL_FRAMELIST_COUNT]; 438}; 439 440struct ehci_config_desc { 441 struct usb2_config_descriptor confd; 442 struct usb2_interface_descriptor ifcd; 443 struct usb2_endpoint_descriptor endpd; 444} __packed; 445 446union ehci_hub_desc { 447 struct usb2_status stat; 448 struct usb2_port_status ps; 449 struct usb2_device_descriptor devd; 450 struct usb2_device_qualifier odevd; 451 struct usb2_hub_descriptor hubd; 452 uint8_t temp[128]; 453}; 454 455typedef struct ehci_softc { 456 struct ehci_hw_softc sc_hw; 457 struct usb2_bus sc_bus; /* base device */ 458 struct usb2_callout sc_tmo_pcd; 459 union ehci_hub_desc sc_hub_desc; 460 struct usb2_sw_transfer sc_root_ctrl; 461 struct usb2_sw_transfer sc_root_intr; 462 463 struct usb2_device *sc_devices[EHCI_MAX_DEVICES]; 464 struct resource *sc_io_res; 465 struct resource *sc_irq_res; 466 struct ehci_qh *sc_async_p_last; 467 struct ehci_qh *sc_intr_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]; 468 struct ehci_sitd *sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]; 469 struct ehci_itd *sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]; 470 void *sc_intr_hdl; 471 bus_size_t sc_io_size; 472 bus_space_tag_t sc_io_tag; 473 bus_space_handle_t sc_io_hdl; 474 475 uint32_t sc_eintrs; 476 uint32_t sc_cmd; /* shadow of cmd register during 477 * suspend */ 478 479 uint16_t sc_intr_stat[EHCI_VIRTUAL_FRAMELIST_COUNT]; 480 uint16_t sc_id_vendor; /* vendor ID for root hub */ 481 uint16_t sc_flags; /* chip specific flags */ 482#define EHCI_SCFLG_SETMODE 0x0001 /* set bridge mode again after init */ 483#define EHCI_SCFLG_FORCESPEED 0x0002 /* force speed */ 484#define EHCI_SCFLG_NORESTERM 0x0004 /* don't terminate reset sequence */ 485#define EHCI_SCFLG_BIGEDESC 0x0008 /* big-endian byte order descriptors */ 486#define EHCI_SCFLG_BIGEMMIO 0x0010 /* big-endian byte order MMIO */ 487#define EHCI_SCFLG_TT 0x0020 /* transaction translator present */ 488 489 uint8_t sc_offs; /* offset to operational registers */ 490 uint8_t sc_doorbell_disable; /* set on doorbell failure */ 491 uint8_t sc_noport; 492 uint8_t sc_addr; /* device address */ 493 uint8_t sc_conf; /* device configuration */ 494 uint8_t sc_isreset; 495 uint8_t sc_hub_idata[8]; 496 497 char sc_vendor[16]; /* vendor string for root hub */ 498 499} ehci_softc_t; 500 501#define EREAD1(sc, a) bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (a)) 502#define EREAD2(sc, a) bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (a)) 503#define EREAD4(sc, a) bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (a)) 504#define EWRITE1(sc, a, x) \ 505 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (a), (x)) 506#define EWRITE2(sc, a, x) \ 507 bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (a), (x)) 508#define EWRITE4(sc, a, x) \ 509 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (a), (x)) 510#define EOREAD1(sc, a) \ 511 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (sc)->sc_offs+(a)) 512#define EOREAD2(sc, a) \ 513 bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (sc)->sc_offs+(a)) 514#define EOREAD4(sc, a) \ 515 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (sc)->sc_offs+(a)) 516#define EOWRITE1(sc, a, x) \ 517 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (sc)->sc_offs+(a), (x)) 518#define EOWRITE2(sc, a, x) \ 519 bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (sc)->sc_offs+(a), (x)) 520#define EOWRITE4(sc, a, x) \ 521 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (sc)->sc_offs+(a), (x)) 522 523#ifdef USB_EHCI_BIG_ENDIAN_DESC 524/* 525 * Handle byte order conversion between host and ``host controller''. 526 * Typically the latter is little-endian but some controllers require 527 * big-endian in which case we may need to manually swap. 528 */ 529static __inline uint32_t 530htohc32(const struct ehci_softc *sc, const uint32_t v) 531{ 532 return sc->sc_flags & EHCI_SCFLG_BIGEDESC ? htobe32(v) : htole32(v); 533} 534 535static __inline uint16_t 536htohc16(const struct ehci_softc *sc, const uint16_t v) 537{ 538 return sc->sc_flags & EHCI_SCFLG_BIGEDESC ? htobe16(v) : htole16(v); 539} 540 541static __inline uint32_t 542hc32toh(const struct ehci_softc *sc, const uint32_t v) 543{ 544 return sc->sc_flags & EHCI_SCFLG_BIGEDESC ? be32toh(v) : le32toh(v); 545} 546 547static __inline uint16_t 548hc16toh(const struct ehci_softc *sc, const uint16_t v) 549{ 550 return sc->sc_flags & EHCI_SCFLG_BIGEDESC ? be16toh(v) : le16toh(v); 551} 552#else 553/* 554 * Normal little-endian only conversion routines. 555 */ 556static __inline uint32_t 557htohc32(const struct ehci_softc *sc, const uint32_t v) 558{ 559 return htole32(v); 560} 561 562static __inline uint16_t 563htohc16(const struct ehci_softc *sc, const uint16_t v) 564{ 565 return htole16(v); 566} 567 568static __inline uint32_t 569hc32toh(const struct ehci_softc *sc, const uint32_t v) 570{ 571 return le32toh(v); 572} 573 574static __inline uint16_t 575hc16toh(const struct ehci_softc *sc, const uint16_t v) 576{ 577 return le16toh(v); 578} 579#endif 580 581usb2_bus_mem_cb_t ehci_iterate_hw_softc; 582 583usb2_error_t ehci_reset(ehci_softc_t *sc); 584usb2_error_t ehci_init(ehci_softc_t *sc); 585void ehci_detach(struct ehci_softc *sc); 586void ehci_suspend(struct ehci_softc *sc); 587void ehci_resume(struct ehci_softc *sc); 588void ehci_shutdown(ehci_softc_t *sc); 589void ehci_interrupt(ehci_softc_t *sc); 590 591#endif /* _EHCI_H_ */ 592