1230424Shselasky/* $FreeBSD$ */ 2230424Shselasky/*- 3230424Shselasky * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4230424Shselasky * 5230424Shselasky * Redistribution and use in source and binary forms, with or without 6230424Shselasky * modification, are permitted provided that the following conditions 7230424Shselasky * are met: 8230424Shselasky * 1. Redistributions of source code must retain the above copyright 9230424Shselasky * notice, this list of conditions and the following disclaimer. 10230424Shselasky * 2. Redistributions in binary form must reproduce the above copyright 11230424Shselasky * notice, this list of conditions and the following disclaimer in the 12230424Shselasky * documentation and/or other materials provided with the distribution. 13230424Shselasky * 14230424Shselasky * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15230424Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16230424Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17230424Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18230424Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19230424Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20230424Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21230424Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22230424Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23230424Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24230424Shselasky * SUCH DAMAGE. 25230424Shselasky */ 26230424Shselasky 27230424Shselasky#ifndef _DWC_OTG_H_ 28230424Shselasky#define _DWC_OTG_H_ 29230424Shselasky 30240279Shselasky#define DWC_OTG_MAX_DEVICES MIN(USB_MAX_DEVICES, 32) 31230424Shselasky#define DWC_OTG_FRAME_MASK 0x7FF 32230424Shselasky#define DWC_OTG_MAX_TXP 4 33230424Shselasky#define DWC_OTG_MAX_TXN (0x200 * DWC_OTG_MAX_TXP) 34240279Shselasky#define DWC_OTG_MAX_CHANNELS 16 35240279Shselasky#define DWC_OTG_MAX_ENDPOINTS 16 36240857Shselasky#define DWC_OTG_HOST_TIMER_RATE 10 /* ms */ 37230424Shselasky 38230424Shselasky#define DWC_OTG_READ_4(sc, reg) \ 39230424Shselasky bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 40230424Shselasky 41230424Shselasky#define DWC_OTG_WRITE_4(sc, reg, data) \ 42230424Shselasky bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 43230424Shselasky 44230424Shselaskystruct dwc_otg_td; 45230424Shselaskystruct dwc_otg_softc; 46230424Shselasky 47230424Shselaskytypedef uint8_t (dwc_otg_cmd_t)(struct dwc_otg_td *td); 48230424Shselasky 49230424Shselaskystruct dwc_otg_td { 50230424Shselasky struct dwc_otg_td *obj_next; 51230424Shselasky dwc_otg_cmd_t *func; 52230424Shselasky struct usb_page_cache *pc; 53230424Shselasky uint32_t tx_bytes; 54230424Shselasky uint32_t offset; 55230424Shselasky uint32_t remainder; 56240279Shselasky uint32_t hcchar; /* HOST CFG */ 57240279Shselasky uint32_t hcsplt; /* HOST CFG */ 58230424Shselasky uint16_t max_packet_size; /* packet_size */ 59230424Shselasky uint16_t npkt; 60240857Shselasky uint8_t errcnt; 61240857Shselasky uint8_t tmr_res; 62240857Shselasky uint8_t tmr_val; 63242829Shselasky uint8_t curr_frame; 64230424Shselasky uint8_t ep_no; 65240279Shselasky uint8_t channel; 66240857Shselasky uint8_t state; 67240857Shselasky#define DWC_CHAN_ST_START 0 68240857Shselasky#define DWC_CHAN_ST_WAIT_ANE 1 69240857Shselasky#define DWC_CHAN_ST_WAIT_S_ANE 2 70240857Shselasky#define DWC_CHAN_ST_WAIT_C_ANE 3 71240857Shselasky#define DWC_CHAN_ST_RX_PKT 4 72240857Shselasky#define DWC_CHAN_ST_RX_SPKT 5 73242829Shselasky#define DWC_CHAN_ST_RX_SPKT_SYNC 6 74240857Shselasky#define DWC_CHAN_ST_TX_PKT 4 75240857Shselasky#define DWC_CHAN_ST_TX_CPKT 5 76242829Shselasky#define DWC_CHAN_ST_TX_PKT_SYNC 6 77230424Shselasky uint8_t error:1; 78240279Shselasky uint8_t error_any:1; 79240279Shselasky uint8_t error_stall:1; 80230424Shselasky uint8_t alt_next:1; 81230424Shselasky uint8_t short_pkt:1; 82230424Shselasky uint8_t did_stall:1; 83240279Shselasky uint8_t toggle:1; 84240279Shselasky uint8_t set_toggle:1; 85240419Shselasky uint8_t got_short:1; 86240857Shselasky uint8_t did_nak:1; 87230424Shselasky}; 88230424Shselasky 89230424Shselaskystruct dwc_otg_std_temp { 90230424Shselasky dwc_otg_cmd_t *func; 91230424Shselasky struct usb_page_cache *pc; 92230424Shselasky struct dwc_otg_td *td; 93230424Shselasky struct dwc_otg_td *td_next; 94230424Shselasky uint32_t len; 95230424Shselasky uint32_t offset; 96230424Shselasky uint16_t max_frame_size; 97230424Shselasky uint8_t short_pkt; 98240279Shselasky 99230424Shselasky /* 100230424Shselasky * short_pkt = 0: transfer should be short terminated 101230424Shselasky * short_pkt = 1: transfer should not be short terminated 102230424Shselasky */ 103230424Shselasky uint8_t setup_alt_next; 104230424Shselasky uint8_t did_stall; 105230424Shselasky uint8_t bulk_or_control; 106230424Shselasky}; 107230424Shselasky 108230424Shselaskystruct dwc_otg_config_desc { 109230424Shselasky struct usb_config_descriptor confd; 110230424Shselasky struct usb_interface_descriptor ifcd; 111230424Shselasky struct usb_endpoint_descriptor endpd; 112230424Shselasky} __packed; 113230424Shselasky 114230424Shselaskyunion dwc_otg_hub_temp { 115230424Shselasky uWord wValue; 116230424Shselasky struct usb_port_status ps; 117230424Shselasky}; 118230424Shselasky 119230424Shselaskystruct dwc_otg_flags { 120230424Shselasky uint8_t change_connect:1; 121230424Shselasky uint8_t change_suspend:1; 122240279Shselasky uint8_t change_reset:1; 123240279Shselasky uint8_t change_enabled:1; 124240279Shselasky uint8_t change_over_current:1; 125230424Shselasky uint8_t status_suspend:1; /* set if suspended */ 126230424Shselasky uint8_t status_vbus:1; /* set if present */ 127230424Shselasky uint8_t status_bus_reset:1; /* set if reset complete */ 128230424Shselasky uint8_t status_high_speed:1; /* set if High Speed is selected */ 129240279Shselasky uint8_t status_low_speed:1; /* set if Low Speed is selected */ 130240279Shselasky uint8_t status_device_mode:1; /* set if device mode */ 131230424Shselasky uint8_t self_powered:1; 132230424Shselasky uint8_t clocks_off:1; 133230424Shselasky uint8_t port_powered:1; 134230424Shselasky uint8_t port_enabled:1; 135240279Shselasky uint8_t port_over_current:1; 136230424Shselasky uint8_t d_pulled_up:1; 137230424Shselasky}; 138230424Shselasky 139230424Shselaskystruct dwc_otg_profile { 140230424Shselasky struct usb_hw_ep_profile usb; 141230424Shselasky uint16_t max_buffer; 142230424Shselasky}; 143230424Shselasky 144240482Shselaskystruct dwc_otg_chan_state { 145240482Shselasky uint32_t hcint; 146240998Shselasky uint8_t wait_sof; 147240857Shselasky uint8_t allocated; 148240857Shselasky uint8_t suspended; 149240482Shselasky}; 150240482Shselasky 151230424Shselaskystruct dwc_otg_softc { 152230424Shselasky struct usb_bus sc_bus; 153230424Shselasky union dwc_otg_hub_temp sc_hub_temp; 154240279Shselasky struct dwc_otg_profile sc_hw_ep_profile[DWC_OTG_MAX_ENDPOINTS]; 155240857Shselasky struct usb_callout sc_timer; 156230424Shselasky 157230424Shselasky struct usb_device *sc_devices[DWC_OTG_MAX_DEVICES]; 158230424Shselasky struct resource *sc_io_res; 159230424Shselasky struct resource *sc_irq_res; 160230424Shselasky void *sc_intr_hdl; 161230424Shselasky bus_size_t sc_io_size; 162230424Shselasky bus_space_tag_t sc_io_tag; 163230424Shselasky bus_space_handle_t sc_io_hdl; 164230424Shselasky 165230424Shselasky uint32_t sc_rx_bounce_buffer[1024 / 4]; 166230424Shselasky uint32_t sc_tx_bounce_buffer[(512 * DWC_OTG_MAX_TXP) / 4]; 167230424Shselasky 168230424Shselasky uint32_t sc_fifo_size; 169230424Shselasky uint32_t sc_irq_mask; 170230424Shselasky uint32_t sc_last_rx_status; 171240279Shselasky uint32_t sc_out_ctl[DWC_OTG_MAX_ENDPOINTS]; 172240279Shselasky uint32_t sc_in_ctl[DWC_OTG_MAX_ENDPOINTS]; 173240482Shselasky struct dwc_otg_chan_state sc_chan_state[DWC_OTG_MAX_CHANNELS]; 174240857Shselasky uint32_t sc_tmr_val; 175240279Shselasky uint32_t sc_hprt_val; 176230424Shselasky 177240279Shselasky uint16_t sc_active_rx_ep; 178230424Shselasky 179240857Shselasky uint8_t sc_timer_active; 180230424Shselasky uint8_t sc_dev_ep_max; 181230424Shselasky uint8_t sc_dev_in_ep_max; 182240279Shselasky uint8_t sc_host_ch_max; 183230424Shselasky uint8_t sc_rt_addr; /* root HUB address */ 184230424Shselasky uint8_t sc_conf; /* root HUB config */ 185240279Shselasky uint8_t sc_mode; /* mode of operation */ 186240279Shselasky#define DWC_MODE_OTG 0 /* both modes */ 187240279Shselasky#define DWC_MODE_DEVICE 1 /* device only */ 188240279Shselasky#define DWC_MODE_HOST 2 /* host only */ 189230424Shselasky 190230424Shselasky uint8_t sc_hub_idata[1]; 191230424Shselasky 192230424Shselasky struct dwc_otg_flags sc_flags; 193230424Shselasky}; 194230424Shselasky 195230424Shselasky/* prototypes */ 196230424Shselasky 197230424Shselaskyvoid dwc_otg_interrupt(struct dwc_otg_softc *); 198230424Shselaskyint dwc_otg_init(struct dwc_otg_softc *); 199230424Shselaskyvoid dwc_otg_uninit(struct dwc_otg_softc *); 200230424Shselasky 201230424Shselasky#endif /* _DWC_OTG_H_ */ 202