1139749Simp/*- 2119815Smarcel * Copyright (c) 2003 Marcel Moolenaar 3119815Smarcel * All rights reserved. 4119815Smarcel * 5119815Smarcel * Redistribution and use in source and binary forms, with or without 6119815Smarcel * modification, are permitted provided that the following conditions 7119815Smarcel * are met: 8119815Smarcel * 9119815Smarcel * 1. Redistributions of source code must retain the above copyright 10119815Smarcel * notice, this list of conditions and the following disclaimer. 11119815Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12119815Smarcel * notice, this list of conditions and the following disclaimer in the 13119815Smarcel * documentation and/or other materials provided with the distribution. 14119815Smarcel * 15119815Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16119815Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17119815Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18119815Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19119815Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20119815Smarcel * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21119815Smarcel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22119815Smarcel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23119815Smarcel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24119815Smarcel * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25119815Smarcel */ 26119815Smarcel 27247519Sganbold#include "opt_platform.h" 28247519Sganbold 29119815Smarcel#include <sys/cdefs.h> 30119815Smarcel__FBSDID("$FreeBSD$"); 31119815Smarcel 32119815Smarcel#include <sys/param.h> 33119815Smarcel#include <sys/systm.h> 34119815Smarcel#include <sys/bus.h> 35119815Smarcel#include <sys/conf.h> 36246016Scperciva#include <sys/kernel.h> 37246016Scperciva#include <sys/sysctl.h> 38119815Smarcel#include <machine/bus.h> 39119815Smarcel 40247519Sganbold#ifdef FDT 41247519Sganbold#include <dev/fdt/fdt_common.h> 42247519Sganbold#include <dev/ofw/ofw_bus.h> 43247519Sganbold#include <dev/ofw/ofw_bus_subr.h> 44247519Sganbold#endif 45247519Sganbold 46119815Smarcel#include <dev/uart/uart.h> 47119815Smarcel#include <dev/uart/uart_cpu.h> 48119815Smarcel#include <dev/uart/uart_bus.h> 49254597Sian#include <dev/uart/uart_dev_ns8250.h> 50119815Smarcel 51137949Smarcel#include <dev/ic/ns16550.h> 52137949Smarcel 53119815Smarcel#include "uart_if.h" 54119815Smarcel 55119815Smarcel#define DEFAULT_RCLK 1843200 56119815Smarcel 57247519Sganboldstatic int broken_txfifo = 0; 58247519SganboldSYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN, 59247519Sganbold &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 60247519SganboldTUNABLE_INT("hw.broken_txfifo", &broken_txfifo); 61247519Sganbold 62119815Smarcel/* 63119815Smarcel * Clear pending interrupts. THRE is cleared by reading IIR. Data 64119815Smarcel * that may have been received gets lost here. 65119815Smarcel */ 66119815Smarcelstatic void 67119815Smarcelns8250_clrint(struct uart_bas *bas) 68119815Smarcel{ 69190834Smarcel uint8_t iir, lsr; 70119815Smarcel 71119815Smarcel iir = uart_getreg(bas, REG_IIR); 72119815Smarcel while ((iir & IIR_NOPEND) == 0) { 73119815Smarcel iir &= IIR_IMASK; 74190834Smarcel if (iir == IIR_RLS) { 75190834Smarcel lsr = uart_getreg(bas, REG_LSR); 76190834Smarcel if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 77190834Smarcel (void)uart_getreg(bas, REG_DATA); 78190834Smarcel } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 79119815Smarcel (void)uart_getreg(bas, REG_DATA); 80119815Smarcel else if (iir == IIR_MLSC) 81119815Smarcel (void)uart_getreg(bas, REG_MSR); 82119815Smarcel uart_barrier(bas); 83119815Smarcel iir = uart_getreg(bas, REG_IIR); 84119815Smarcel } 85119815Smarcel} 86119815Smarcel 87119815Smarcelstatic int 88119815Smarcelns8250_delay(struct uart_bas *bas) 89119815Smarcel{ 90119815Smarcel int divisor; 91119815Smarcel u_char lcr; 92119815Smarcel 93119815Smarcel lcr = uart_getreg(bas, REG_LCR); 94119815Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 95119815Smarcel uart_barrier(bas); 96158844Sbenno divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 97119815Smarcel uart_barrier(bas); 98119815Smarcel uart_setreg(bas, REG_LCR, lcr); 99119815Smarcel uart_barrier(bas); 100119815Smarcel 101119815Smarcel /* 1/10th the time to transmit 1 character (estimate). */ 102168000Smarcel if (divisor <= 134) 103168000Smarcel return (16000000 * divisor / bas->rclk); 104168000Smarcel return (16000 * divisor / (bas->rclk / 1000)); 105119815Smarcel} 106119815Smarcel 107119815Smarcelstatic int 108119815Smarcelns8250_divisor(int rclk, int baudrate) 109119815Smarcel{ 110119815Smarcel int actual_baud, divisor; 111119815Smarcel int error; 112119815Smarcel 113119815Smarcel if (baudrate == 0) 114119815Smarcel return (0); 115119815Smarcel 116119815Smarcel divisor = (rclk / (baudrate << 3) + 1) >> 1; 117119815Smarcel if (divisor == 0 || divisor >= 65536) 118119815Smarcel return (0); 119119815Smarcel actual_baud = rclk / (divisor << 4); 120119815Smarcel 121119815Smarcel /* 10 times error in percent: */ 122119815Smarcel error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 123119815Smarcel 124119815Smarcel /* 3.0% maximum error tolerance: */ 125119815Smarcel if (error < -30 || error > 30) 126119815Smarcel return (0); 127119815Smarcel 128119815Smarcel return (divisor); 129119815Smarcel} 130119815Smarcel 131119815Smarcelstatic int 132119815Smarcelns8250_drain(struct uart_bas *bas, int what) 133119815Smarcel{ 134119815Smarcel int delay, limit; 135119815Smarcel 136119815Smarcel delay = ns8250_delay(bas); 137119815Smarcel 138119815Smarcel if (what & UART_DRAIN_TRANSMITTER) { 139119815Smarcel /* 140119815Smarcel * Pick an arbitrary high limit to avoid getting stuck in 141119815Smarcel * an infinite loop when the hardware is broken. Make the 142119815Smarcel * limit high enough to handle large FIFOs. 143119815Smarcel */ 144119815Smarcel limit = 10*1024; 145119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 146119815Smarcel DELAY(delay); 147119815Smarcel if (limit == 0) { 148119815Smarcel /* printf("ns8250: transmitter appears stuck... "); */ 149119815Smarcel return (EIO); 150119815Smarcel } 151119815Smarcel } 152119815Smarcel 153119815Smarcel if (what & UART_DRAIN_RECEIVER) { 154119815Smarcel /* 155119815Smarcel * Pick an arbitrary high limit to avoid getting stuck in 156119815Smarcel * an infinite loop when the hardware is broken. Make the 157119815Smarcel * limit high enough to handle large FIFOs and integrated 158119815Smarcel * UARTs. The HP rx2600 for example has 3 UARTs on the 159119815Smarcel * management board that tend to get a lot of data send 160119815Smarcel * to it when the UART is first activated. 161119815Smarcel */ 162119815Smarcel limit=10*4096; 163119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 164119815Smarcel (void)uart_getreg(bas, REG_DATA); 165119815Smarcel uart_barrier(bas); 166119815Smarcel DELAY(delay << 2); 167119815Smarcel } 168119815Smarcel if (limit == 0) { 169119815Smarcel /* printf("ns8250: receiver appears broken... "); */ 170119815Smarcel return (EIO); 171119815Smarcel } 172119815Smarcel } 173119815Smarcel 174119815Smarcel return (0); 175119815Smarcel} 176119815Smarcel 177119815Smarcel/* 178119815Smarcel * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 179119815Smarcel * drained. WARNING: this function clobbers the FIFO setting! 180119815Smarcel */ 181119815Smarcelstatic void 182119815Smarcelns8250_flush(struct uart_bas *bas, int what) 183119815Smarcel{ 184119815Smarcel uint8_t fcr; 185119815Smarcel 186119815Smarcel fcr = FCR_ENABLE; 187119815Smarcel if (what & UART_FLUSH_TRANSMITTER) 188119815Smarcel fcr |= FCR_XMT_RST; 189119815Smarcel if (what & UART_FLUSH_RECEIVER) 190119815Smarcel fcr |= FCR_RCV_RST; 191119815Smarcel uart_setreg(bas, REG_FCR, fcr); 192119815Smarcel uart_barrier(bas); 193119815Smarcel} 194119815Smarcel 195119815Smarcelstatic int 196119815Smarcelns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 197119815Smarcel int parity) 198119815Smarcel{ 199119815Smarcel int divisor; 200119815Smarcel uint8_t lcr; 201119815Smarcel 202119815Smarcel lcr = 0; 203119815Smarcel if (databits >= 8) 204119815Smarcel lcr |= LCR_8BITS; 205119815Smarcel else if (databits == 7) 206119815Smarcel lcr |= LCR_7BITS; 207119815Smarcel else if (databits == 6) 208119815Smarcel lcr |= LCR_6BITS; 209119815Smarcel else 210119815Smarcel lcr |= LCR_5BITS; 211119815Smarcel if (stopbits > 1) 212119815Smarcel lcr |= LCR_STOPB; 213119815Smarcel lcr |= parity << 3; 214119815Smarcel 215119815Smarcel /* Set baudrate. */ 216119815Smarcel if (baudrate > 0) { 217119815Smarcel divisor = ns8250_divisor(bas->rclk, baudrate); 218119815Smarcel if (divisor == 0) 219119815Smarcel return (EINVAL); 220157989Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 221157989Smarcel uart_barrier(bas); 222158844Sbenno uart_setreg(bas, REG_DLL, divisor & 0xff); 223158844Sbenno uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 224119815Smarcel uart_barrier(bas); 225119815Smarcel } 226119815Smarcel 227119815Smarcel /* Set LCR and clear DLAB. */ 228119815Smarcel uart_setreg(bas, REG_LCR, lcr); 229119815Smarcel uart_barrier(bas); 230119815Smarcel return (0); 231119815Smarcel} 232119815Smarcel 233119815Smarcel/* 234119815Smarcel * Low-level UART interface. 235119815Smarcel */ 236119815Smarcelstatic int ns8250_probe(struct uart_bas *bas); 237119815Smarcelstatic void ns8250_init(struct uart_bas *bas, int, int, int, int); 238119815Smarcelstatic void ns8250_term(struct uart_bas *bas); 239119815Smarcelstatic void ns8250_putc(struct uart_bas *bas, int); 240166100Smariusstatic int ns8250_rxready(struct uart_bas *bas); 241157380Smarcelstatic int ns8250_getc(struct uart_bas *bas, struct mtx *); 242119815Smarcel 243254597Sianstruct uart_ops uart_ns8250_ops = { 244119815Smarcel .probe = ns8250_probe, 245119815Smarcel .init = ns8250_init, 246119815Smarcel .term = ns8250_term, 247119815Smarcel .putc = ns8250_putc, 248166100Smarius .rxready = ns8250_rxready, 249119815Smarcel .getc = ns8250_getc, 250119815Smarcel}; 251119815Smarcel 252119815Smarcelstatic int 253119815Smarcelns8250_probe(struct uart_bas *bas) 254119815Smarcel{ 255158849Sbenno u_char val; 256119815Smarcel 257119815Smarcel /* Check known 0 bits that don't depend on DLAB. */ 258119815Smarcel val = uart_getreg(bas, REG_IIR); 259119815Smarcel if (val & 0x30) 260119815Smarcel return (ENXIO); 261222317Smarcel /* 262222317Smarcel * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 263222317Smarcel * chip, but otherwise doesn't seem to have a function. In 264222317Smarcel * other words, uart(4) works regardless. Ignore that bit so 265222317Smarcel * the probe succeeds. 266222317Smarcel */ 267119815Smarcel val = uart_getreg(bas, REG_MCR); 268222317Smarcel if (val & 0xa0) 269119815Smarcel return (ENXIO); 270119815Smarcel 271119815Smarcel return (0); 272119815Smarcel} 273119815Smarcel 274119815Smarcelstatic void 275119815Smarcelns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 276119815Smarcel int parity) 277119815Smarcel{ 278158844Sbenno u_char ier; 279119815Smarcel 280119815Smarcel if (bas->rclk == 0) 281119815Smarcel bas->rclk = DEFAULT_RCLK; 282119815Smarcel ns8250_param(bas, baudrate, databits, stopbits, parity); 283119815Smarcel 284119815Smarcel /* Disable all interrupt sources. */ 285179420Sbenno /* 286179420Sbenno * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 287179420Sbenno * UARTs split the receive time-out interrupt bit out separately as 288179420Sbenno * 0x10. This gets handled by ier_mask and ier_rxbits below. 289179420Sbenno */ 290179420Sbenno ier = uart_getreg(bas, REG_IER) & 0xe0; 291158844Sbenno uart_setreg(bas, REG_IER, ier); 292119815Smarcel uart_barrier(bas); 293119815Smarcel 294119815Smarcel /* Disable the FIFO (if present). */ 295119815Smarcel uart_setreg(bas, REG_FCR, 0); 296119815Smarcel uart_barrier(bas); 297119815Smarcel 298119815Smarcel /* Set RTS & DTR. */ 299119815Smarcel uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 300119815Smarcel uart_barrier(bas); 301119815Smarcel 302119815Smarcel ns8250_clrint(bas); 303119815Smarcel} 304119815Smarcel 305119815Smarcelstatic void 306119815Smarcelns8250_term(struct uart_bas *bas) 307119815Smarcel{ 308119815Smarcel 309119815Smarcel /* Clear RTS & DTR. */ 310119815Smarcel uart_setreg(bas, REG_MCR, MCR_IE); 311119815Smarcel uart_barrier(bas); 312119815Smarcel} 313119815Smarcel 314119815Smarcelstatic void 315119815Smarcelns8250_putc(struct uart_bas *bas, int c) 316119815Smarcel{ 317168285Smarcel int limit; 318119815Smarcel 319168285Smarcel limit = 250000; 320119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 321168285Smarcel DELAY(4); 322119815Smarcel uart_setreg(bas, REG_DATA, c); 323127742Smarcel uart_barrier(bas); 324168285Smarcel limit = 250000; 325119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 326168285Smarcel DELAY(4); 327119815Smarcel} 328119815Smarcel 329119815Smarcelstatic int 330166100Smariusns8250_rxready(struct uart_bas *bas) 331119815Smarcel{ 332119815Smarcel 333166100Smarius return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 334119815Smarcel} 335119815Smarcel 336119815Smarcelstatic int 337157380Smarcelns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 338119815Smarcel{ 339168285Smarcel int c; 340119815Smarcel 341157380Smarcel uart_lock(hwmtx); 342157380Smarcel 343157380Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 344157380Smarcel uart_unlock(hwmtx); 345168285Smarcel DELAY(4); 346157380Smarcel uart_lock(hwmtx); 347157380Smarcel } 348157380Smarcel 349157380Smarcel c = uart_getreg(bas, REG_DATA); 350157380Smarcel 351157380Smarcel uart_unlock(hwmtx); 352157380Smarcel 353157380Smarcel return (c); 354119815Smarcel} 355119815Smarcel 356119815Smarcelstatic kobj_method_t ns8250_methods[] = { 357119815Smarcel KOBJMETHOD(uart_attach, ns8250_bus_attach), 358119815Smarcel KOBJMETHOD(uart_detach, ns8250_bus_detach), 359119815Smarcel KOBJMETHOD(uart_flush, ns8250_bus_flush), 360119815Smarcel KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 361119815Smarcel KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 362119815Smarcel KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 363119815Smarcel KOBJMETHOD(uart_param, ns8250_bus_param), 364119815Smarcel KOBJMETHOD(uart_probe, ns8250_bus_probe), 365119815Smarcel KOBJMETHOD(uart_receive, ns8250_bus_receive), 366119815Smarcel KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 367119815Smarcel KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 368119815Smarcel { 0, 0 } 369119815Smarcel}; 370119815Smarcel 371119815Smarcelstruct uart_class uart_ns8250_class = { 372168281Smarcel "ns8250", 373119815Smarcel ns8250_methods, 374119815Smarcel sizeof(struct ns8250_softc), 375168281Smarcel .uc_ops = &uart_ns8250_ops, 376119815Smarcel .uc_range = 8, 377119815Smarcel .uc_rclk = DEFAULT_RCLK 378119815Smarcel}; 379119815Smarcel 380119815Smarcel#define SIGCHG(c, i, s, d) \ 381119815Smarcel if (c) { \ 382119815Smarcel i |= (i & s) ? s : s | d; \ 383119815Smarcel } else { \ 384119815Smarcel i = (i & s) ? (i & ~s) | d : i; \ 385119815Smarcel } 386119815Smarcel 387254597Sianint 388119815Smarcelns8250_bus_attach(struct uart_softc *sc) 389119815Smarcel{ 390119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 391119815Smarcel struct uart_bas *bas; 392177117Ssam unsigned int ivar; 393247519Sganbold#ifdef FDT 394247519Sganbold phandle_t node; 395247519Sganbold pcell_t cell; 396247519Sganbold#endif 397119815Smarcel 398247519Sganbold ns8250->busy_detect = 0; 399247519Sganbold 400247519Sganbold#ifdef FDT 401247519Sganbold /* 402247519Sganbold * Check whether uart requires to read USR reg when IIR_BUSY and 403247519Sganbold * has broken txfifo. 404247519Sganbold */ 405247519Sganbold node = ofw_bus_get_node(sc->sc_dev); 406247519Sganbold if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 407247519Sganbold ns8250->busy_detect = 1; 408247519Sganbold if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 409247519Sganbold broken_txfifo = 1; 410247519Sganbold#endif 411247519Sganbold 412119815Smarcel bas = &sc->sc_bas; 413119815Smarcel 414119815Smarcel ns8250->mcr = uart_getreg(bas, REG_MCR); 415177117Ssam ns8250->fcr = FCR_ENABLE; 416177117Ssam if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 417177117Ssam &ivar)) { 418177117Ssam if (UART_FLAGS_FCR_RX_LOW(ivar)) 419177117Ssam ns8250->fcr |= FCR_RX_LOW; 420177117Ssam else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 421177117Ssam ns8250->fcr |= FCR_RX_MEDL; 422177117Ssam else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 423177117Ssam ns8250->fcr |= FCR_RX_HIGH; 424177117Ssam else 425177117Ssam ns8250->fcr |= FCR_RX_MEDH; 426177117Ssam } else 427177117Ssam ns8250->fcr |= FCR_RX_MEDH; 428179420Sbenno 429179420Sbenno /* Get IER mask */ 430179420Sbenno ivar = 0xf0; 431179420Sbenno resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 432179420Sbenno &ivar); 433179420Sbenno ns8250->ier_mask = (uint8_t)(ivar & 0xff); 434179420Sbenno 435179420Sbenno /* Get IER RX interrupt bits */ 436179420Sbenno ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 437179420Sbenno resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 438179420Sbenno &ivar); 439179420Sbenno ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 440179420Sbenno 441119815Smarcel uart_setreg(bas, REG_FCR, ns8250->fcr); 442119815Smarcel uart_barrier(bas); 443119815Smarcel ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 444119815Smarcel 445119815Smarcel if (ns8250->mcr & MCR_DTR) 446131043Sphk sc->sc_hwsig |= SER_DTR; 447119815Smarcel if (ns8250->mcr & MCR_RTS) 448131043Sphk sc->sc_hwsig |= SER_RTS; 449119815Smarcel ns8250_bus_getsig(sc); 450119815Smarcel 451119815Smarcel ns8250_clrint(bas); 452179420Sbenno ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 453179420Sbenno ns8250->ier |= ns8250->ier_rxbits; 454119815Smarcel uart_setreg(bas, REG_IER, ns8250->ier); 455119815Smarcel uart_barrier(bas); 456255031Smarcel 457255031Smarcel /* 458255031Smarcel * Timing of the H/W access was changed with r253161 of uart_core.c 459255031Smarcel * It has been observed that an ITE IT8513E would signal a break 460255031Smarcel * condition with pretty much every character it received, unless 461255031Smarcel * it had enough time to settle between ns8250_bus_attach() and 462255031Smarcel * ns8250_bus_ipend() -- which it accidentally had before r253161. 463255031Smarcel * It's not understood why the UART chip behaves this way and it 464255031Smarcel * could very well be that the DELAY make the H/W work in the same 465255031Smarcel * accidental manner as before. More analysis is warranted, but 466255031Smarcel * at least now we fixed a known regression. 467255031Smarcel */ 468255074Smarcel DELAY(200); 469119815Smarcel return (0); 470119815Smarcel} 471119815Smarcel 472254597Sianint 473119815Smarcelns8250_bus_detach(struct uart_softc *sc) 474119815Smarcel{ 475179420Sbenno struct ns8250_softc *ns8250; 476119815Smarcel struct uart_bas *bas; 477158844Sbenno u_char ier; 478119815Smarcel 479179420Sbenno ns8250 = (struct ns8250_softc *)sc; 480119815Smarcel bas = &sc->sc_bas; 481179420Sbenno ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 482158844Sbenno uart_setreg(bas, REG_IER, ier); 483119815Smarcel uart_barrier(bas); 484119815Smarcel ns8250_clrint(bas); 485119815Smarcel return (0); 486119815Smarcel} 487119815Smarcel 488254597Sianint 489119815Smarcelns8250_bus_flush(struct uart_softc *sc, int what) 490119815Smarcel{ 491119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 492119815Smarcel struct uart_bas *bas; 493120143Smarcel int error; 494119815Smarcel 495119815Smarcel bas = &sc->sc_bas; 496157300Smarcel uart_lock(sc->sc_hwmtx); 497157418Smarcel if (sc->sc_rxfifosz > 1) { 498119815Smarcel ns8250_flush(bas, what); 499119815Smarcel uart_setreg(bas, REG_FCR, ns8250->fcr); 500119815Smarcel uart_barrier(bas); 501120143Smarcel error = 0; 502120143Smarcel } else 503120143Smarcel error = ns8250_drain(bas, what); 504157300Smarcel uart_unlock(sc->sc_hwmtx); 505120143Smarcel return (error); 506119815Smarcel} 507119815Smarcel 508254597Sianint 509119815Smarcelns8250_bus_getsig(struct uart_softc *sc) 510119815Smarcel{ 511119815Smarcel uint32_t new, old, sig; 512119815Smarcel uint8_t msr; 513119815Smarcel 514119815Smarcel do { 515119815Smarcel old = sc->sc_hwsig; 516119815Smarcel sig = old; 517157300Smarcel uart_lock(sc->sc_hwmtx); 518119815Smarcel msr = uart_getreg(&sc->sc_bas, REG_MSR); 519157300Smarcel uart_unlock(sc->sc_hwmtx); 520131043Sphk SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 521131043Sphk SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 522131043Sphk SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 523131043Sphk SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 524155973Smarcel new = sig & ~SER_MASK_DELTA; 525119815Smarcel } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 526119815Smarcel return (sig); 527119815Smarcel} 528119815Smarcel 529254597Sianint 530119815Smarcelns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 531119815Smarcel{ 532119815Smarcel struct uart_bas *bas; 533137709Smarcel int baudrate, divisor, error; 534120022Smarcel uint8_t efr, lcr; 535119815Smarcel 536119815Smarcel bas = &sc->sc_bas; 537120143Smarcel error = 0; 538157300Smarcel uart_lock(sc->sc_hwmtx); 539119815Smarcel switch (request) { 540119815Smarcel case UART_IOCTL_BREAK: 541119815Smarcel lcr = uart_getreg(bas, REG_LCR); 542119815Smarcel if (data) 543119815Smarcel lcr |= LCR_SBREAK; 544119815Smarcel else 545119815Smarcel lcr &= ~LCR_SBREAK; 546119815Smarcel uart_setreg(bas, REG_LCR, lcr); 547119815Smarcel uart_barrier(bas); 548119815Smarcel break; 549120022Smarcel case UART_IOCTL_IFLOW: 550120022Smarcel lcr = uart_getreg(bas, REG_LCR); 551120022Smarcel uart_barrier(bas); 552120022Smarcel uart_setreg(bas, REG_LCR, 0xbf); 553120022Smarcel uart_barrier(bas); 554120022Smarcel efr = uart_getreg(bas, REG_EFR); 555120022Smarcel if (data) 556120022Smarcel efr |= EFR_RTS; 557120022Smarcel else 558120022Smarcel efr &= ~EFR_RTS; 559120022Smarcel uart_setreg(bas, REG_EFR, efr); 560120022Smarcel uart_barrier(bas); 561120022Smarcel uart_setreg(bas, REG_LCR, lcr); 562120022Smarcel uart_barrier(bas); 563120022Smarcel break; 564120022Smarcel case UART_IOCTL_OFLOW: 565120022Smarcel lcr = uart_getreg(bas, REG_LCR); 566120022Smarcel uart_barrier(bas); 567120022Smarcel uart_setreg(bas, REG_LCR, 0xbf); 568120022Smarcel uart_barrier(bas); 569120022Smarcel efr = uart_getreg(bas, REG_EFR); 570120022Smarcel if (data) 571120022Smarcel efr |= EFR_CTS; 572120022Smarcel else 573120022Smarcel efr &= ~EFR_CTS; 574120022Smarcel uart_setreg(bas, REG_EFR, efr); 575120022Smarcel uart_barrier(bas); 576120022Smarcel uart_setreg(bas, REG_LCR, lcr); 577120022Smarcel uart_barrier(bas); 578120022Smarcel break; 579137707Smarcel case UART_IOCTL_BAUD: 580137707Smarcel lcr = uart_getreg(bas, REG_LCR); 581137707Smarcel uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 582137707Smarcel uart_barrier(bas); 583158844Sbenno divisor = uart_getreg(bas, REG_DLL) | 584158844Sbenno (uart_getreg(bas, REG_DLH) << 8); 585137707Smarcel uart_barrier(bas); 586137707Smarcel uart_setreg(bas, REG_LCR, lcr); 587137707Smarcel uart_barrier(bas); 588137709Smarcel baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 589137709Smarcel if (baudrate > 0) 590137709Smarcel *(int*)data = baudrate; 591137709Smarcel else 592137709Smarcel error = ENXIO; 593137707Smarcel break; 594119815Smarcel default: 595120143Smarcel error = EINVAL; 596120143Smarcel break; 597119815Smarcel } 598157300Smarcel uart_unlock(sc->sc_hwmtx); 599120143Smarcel return (error); 600119815Smarcel} 601119815Smarcel 602254597Sianint 603119815Smarcelns8250_bus_ipend(struct uart_softc *sc) 604119815Smarcel{ 605119815Smarcel struct uart_bas *bas; 606227032Scognet struct ns8250_softc *ns8250; 607119815Smarcel int ipend; 608119815Smarcel uint8_t iir, lsr; 609119815Smarcel 610227032Scognet ns8250 = (struct ns8250_softc *)sc; 611119815Smarcel bas = &sc->sc_bas; 612157300Smarcel uart_lock(sc->sc_hwmtx); 613119815Smarcel iir = uart_getreg(bas, REG_IIR); 614247519Sganbold 615247519Sganbold if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 616247519Sganbold (void)uart_getreg(bas, DW_REG_USR); 617247519Sganbold uart_unlock(sc->sc_hwmtx); 618247519Sganbold return (0); 619247519Sganbold } 620120143Smarcel if (iir & IIR_NOPEND) { 621157300Smarcel uart_unlock(sc->sc_hwmtx); 622119815Smarcel return (0); 623120143Smarcel } 624119815Smarcel ipend = 0; 625119815Smarcel if (iir & IIR_RXRDY) { 626119815Smarcel lsr = uart_getreg(bas, REG_LSR); 627119815Smarcel if (lsr & LSR_OE) 628155971Smarcel ipend |= SER_INT_OVERRUN; 629119815Smarcel if (lsr & LSR_BI) 630155971Smarcel ipend |= SER_INT_BREAK; 631119815Smarcel if (lsr & LSR_RXRDY) 632155971Smarcel ipend |= SER_INT_RXREADY; 633119815Smarcel } else { 634227032Scognet if (iir & IIR_TXRDY) { 635155971Smarcel ipend |= SER_INT_TXIDLE; 636227032Scognet uart_setreg(bas, REG_IER, ns8250->ier); 637227032Scognet } else 638155971Smarcel ipend |= SER_INT_SIGCHG; 639119815Smarcel } 640190834Smarcel if (ipend == 0) 641190834Smarcel ns8250_clrint(bas); 642190834Smarcel uart_unlock(sc->sc_hwmtx); 643207533Smarius return (ipend); 644119815Smarcel} 645119815Smarcel 646254597Sianint 647119815Smarcelns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 648119815Smarcel int stopbits, int parity) 649119815Smarcel{ 650119815Smarcel struct uart_bas *bas; 651120143Smarcel int error; 652119815Smarcel 653119815Smarcel bas = &sc->sc_bas; 654157300Smarcel uart_lock(sc->sc_hwmtx); 655120143Smarcel error = ns8250_param(bas, baudrate, databits, stopbits, parity); 656157300Smarcel uart_unlock(sc->sc_hwmtx); 657120143Smarcel return (error); 658119815Smarcel} 659119815Smarcel 660254597Sianint 661119815Smarcelns8250_bus_probe(struct uart_softc *sc) 662119815Smarcel{ 663179420Sbenno struct ns8250_softc *ns8250; 664119815Smarcel struct uart_bas *bas; 665119815Smarcel int count, delay, error, limit; 666158844Sbenno uint8_t lsr, mcr, ier; 667119815Smarcel 668179420Sbenno ns8250 = (struct ns8250_softc *)sc; 669119815Smarcel bas = &sc->sc_bas; 670119815Smarcel 671119815Smarcel error = ns8250_probe(bas); 672119815Smarcel if (error) 673119815Smarcel return (error); 674119815Smarcel 675119815Smarcel mcr = MCR_IE; 676119815Smarcel if (sc->sc_sysdev == NULL) { 677119815Smarcel /* By using ns8250_init() we also set DTR and RTS. */ 678158069Smarcel ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 679119815Smarcel } else 680119815Smarcel mcr |= MCR_DTR | MCR_RTS; 681119815Smarcel 682119815Smarcel error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 683119815Smarcel if (error) 684119815Smarcel return (error); 685119815Smarcel 686119815Smarcel /* 687119815Smarcel * Set loopback mode. This avoids having garbage on the wire and 688119815Smarcel * also allows us send and receive data. We set DTR and RTS to 689119815Smarcel * avoid the possibility that automatic flow-control prevents 690129757Stmm * any data from being sent. 691119815Smarcel */ 692129757Stmm uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 693119815Smarcel uart_barrier(bas); 694119815Smarcel 695119815Smarcel /* 696119815Smarcel * Enable FIFOs. And check that the UART has them. If not, we're 697129757Stmm * done. Since this is the first time we enable the FIFOs, we reset 698129757Stmm * them. 699119815Smarcel */ 700119815Smarcel uart_setreg(bas, REG_FCR, FCR_ENABLE); 701119815Smarcel uart_barrier(bas); 702157418Smarcel if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 703119815Smarcel /* 704119815Smarcel * NS16450 or INS8250. We don't bother to differentiate 705119815Smarcel * between them. They're too old to be interesting. 706119815Smarcel */ 707119815Smarcel uart_setreg(bas, REG_MCR, mcr); 708119815Smarcel uart_barrier(bas); 709157418Smarcel sc->sc_rxfifosz = sc->sc_txfifosz = 1; 710119815Smarcel device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 711119815Smarcel return (0); 712119815Smarcel } 713119815Smarcel 714129757Stmm uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 715119815Smarcel uart_barrier(bas); 716119815Smarcel 717119815Smarcel count = 0; 718119815Smarcel delay = ns8250_delay(bas); 719119815Smarcel 720119815Smarcel /* We have FIFOs. Drain the transmitter and receiver. */ 721119815Smarcel error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 722119815Smarcel if (error) { 723119815Smarcel uart_setreg(bas, REG_MCR, mcr); 724119815Smarcel uart_setreg(bas, REG_FCR, 0); 725119815Smarcel uart_barrier(bas); 726119815Smarcel goto describe; 727119815Smarcel } 728119815Smarcel 729119815Smarcel /* 730119815Smarcel * We should have a sufficiently clean "pipe" to determine the 731119815Smarcel * size of the FIFOs. We send as much characters as is reasonable 732218909Sbrucec * and wait for the overflow bit in the LSR register to be 733129757Stmm * asserted, counting the characters as we send them. Based on 734129757Stmm * that count we know the FIFO size. 735119815Smarcel */ 736129757Stmm do { 737119815Smarcel uart_setreg(bas, REG_DATA, 0); 738119815Smarcel uart_barrier(bas); 739119815Smarcel count++; 740119815Smarcel 741119815Smarcel limit = 30; 742129757Stmm lsr = 0; 743129757Stmm /* 744129757Stmm * LSR bits are cleared upon read, so we must accumulate 745129757Stmm * them to be able to test LSR_OE below. 746129757Stmm */ 747129757Stmm while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 748129757Stmm --limit) 749119815Smarcel DELAY(delay); 750119815Smarcel if (limit == 0) { 751179420Sbenno ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 752158844Sbenno uart_setreg(bas, REG_IER, ier); 753119815Smarcel uart_setreg(bas, REG_MCR, mcr); 754119815Smarcel uart_setreg(bas, REG_FCR, 0); 755119815Smarcel uart_barrier(bas); 756119815Smarcel count = 0; 757119815Smarcel goto describe; 758119815Smarcel } 759132650Smarcel } while ((lsr & LSR_OE) == 0 && count < 130); 760129757Stmm count--; 761119815Smarcel 762119815Smarcel uart_setreg(bas, REG_MCR, mcr); 763119815Smarcel 764119815Smarcel /* Reset FIFOs. */ 765119815Smarcel ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 766119815Smarcel 767119815Smarcel describe: 768129757Stmm if (count >= 14 && count <= 16) { 769119815Smarcel sc->sc_rxfifosz = 16; 770119815Smarcel device_set_desc(sc->sc_dev, "16550 or compatible"); 771129757Stmm } else if (count >= 28 && count <= 32) { 772119815Smarcel sc->sc_rxfifosz = 32; 773119815Smarcel device_set_desc(sc->sc_dev, "16650 or compatible"); 774129757Stmm } else if (count >= 56 && count <= 64) { 775119815Smarcel sc->sc_rxfifosz = 64; 776119815Smarcel device_set_desc(sc->sc_dev, "16750 or compatible"); 777129757Stmm } else if (count >= 112 && count <= 128) { 778119815Smarcel sc->sc_rxfifosz = 128; 779119815Smarcel device_set_desc(sc->sc_dev, "16950 or compatible"); 780119815Smarcel } else { 781119943Smarcel sc->sc_rxfifosz = 16; 782119815Smarcel device_set_desc(sc->sc_dev, 783119815Smarcel "Non-standard ns8250 class UART with FIFOs"); 784119815Smarcel } 785119815Smarcel 786119815Smarcel /* 787119815Smarcel * Force the Tx FIFO size to 16 bytes for now. We don't program the 788119815Smarcel * Tx trigger. Also, we assume that all data has been sent when the 789119815Smarcel * interrupt happens. 790119815Smarcel */ 791119815Smarcel sc->sc_txfifosz = 16; 792119815Smarcel 793133220Smarcel#if 0 794133220Smarcel /* 795133220Smarcel * XXX there are some issues related to hardware flow control and 796133220Smarcel * it's likely that uart(4) is the cause. This basicly needs more 797133220Smarcel * investigation, but we avoid using for hardware flow control 798133220Smarcel * until then. 799133220Smarcel */ 800120022Smarcel /* 16650s or higher have automatic flow control. */ 801120022Smarcel if (sc->sc_rxfifosz > 16) { 802120022Smarcel sc->sc_hwiflow = 1; 803120022Smarcel sc->sc_hwoflow = 1; 804120022Smarcel } 805133220Smarcel#endif 806120022Smarcel 807119815Smarcel return (0); 808119815Smarcel} 809119815Smarcel 810254597Sianint 811119815Smarcelns8250_bus_receive(struct uart_softc *sc) 812119815Smarcel{ 813119815Smarcel struct uart_bas *bas; 814119815Smarcel int xc; 815119815Smarcel uint8_t lsr; 816119815Smarcel 817119815Smarcel bas = &sc->sc_bas; 818157300Smarcel uart_lock(sc->sc_hwmtx); 819120146Smarcel lsr = uart_getreg(bas, REG_LSR); 820120146Smarcel while (lsr & LSR_RXRDY) { 821120146Smarcel if (uart_rx_full(sc)) { 822120146Smarcel sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 823119815Smarcel break; 824120146Smarcel } 825119815Smarcel xc = uart_getreg(bas, REG_DATA); 826119815Smarcel if (lsr & LSR_FE) 827119815Smarcel xc |= UART_STAT_FRAMERR; 828119815Smarcel if (lsr & LSR_PE) 829119815Smarcel xc |= UART_STAT_PARERR; 830119815Smarcel uart_rx_put(sc, xc); 831120146Smarcel lsr = uart_getreg(bas, REG_LSR); 832119815Smarcel } 833120146Smarcel /* Discard everything left in the Rx FIFO. */ 834120146Smarcel while (lsr & LSR_RXRDY) { 835120146Smarcel (void)uart_getreg(bas, REG_DATA); 836120146Smarcel uart_barrier(bas); 837120146Smarcel lsr = uart_getreg(bas, REG_LSR); 838120146Smarcel } 839157300Smarcel uart_unlock(sc->sc_hwmtx); 840119815Smarcel return (0); 841119815Smarcel} 842119815Smarcel 843254597Sianint 844119815Smarcelns8250_bus_setsig(struct uart_softc *sc, int sig) 845119815Smarcel{ 846119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 847119815Smarcel struct uart_bas *bas; 848119815Smarcel uint32_t new, old; 849119815Smarcel 850119815Smarcel bas = &sc->sc_bas; 851119815Smarcel do { 852119815Smarcel old = sc->sc_hwsig; 853119815Smarcel new = old; 854131043Sphk if (sig & SER_DDTR) { 855131043Sphk SIGCHG(sig & SER_DTR, new, SER_DTR, 856131043Sphk SER_DDTR); 857119815Smarcel } 858131043Sphk if (sig & SER_DRTS) { 859131043Sphk SIGCHG(sig & SER_RTS, new, SER_RTS, 860131043Sphk SER_DRTS); 861119815Smarcel } 862119815Smarcel } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 863157300Smarcel uart_lock(sc->sc_hwmtx); 864119815Smarcel ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 865131043Sphk if (new & SER_DTR) 866119815Smarcel ns8250->mcr |= MCR_DTR; 867131043Sphk if (new & SER_RTS) 868119815Smarcel ns8250->mcr |= MCR_RTS; 869119815Smarcel uart_setreg(bas, REG_MCR, ns8250->mcr); 870119815Smarcel uart_barrier(bas); 871157300Smarcel uart_unlock(sc->sc_hwmtx); 872119815Smarcel return (0); 873119815Smarcel} 874119815Smarcel 875254597Sianint 876119815Smarcelns8250_bus_transmit(struct uart_softc *sc) 877119815Smarcel{ 878119815Smarcel struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 879119815Smarcel struct uart_bas *bas; 880119815Smarcel int i; 881119815Smarcel 882119815Smarcel bas = &sc->sc_bas; 883157300Smarcel uart_lock(sc->sc_hwmtx); 884119815Smarcel while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 885119815Smarcel ; 886119815Smarcel uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 887119815Smarcel uart_barrier(bas); 888119815Smarcel for (i = 0; i < sc->sc_txdatasz; i++) { 889119815Smarcel uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 890119815Smarcel uart_barrier(bas); 891119815Smarcel } 892246016Scperciva if (broken_txfifo) 893246016Scperciva ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 894246016Scperciva else 895246016Scperciva sc->sc_txbusy = 1; 896157300Smarcel uart_unlock(sc->sc_hwmtx); 897246016Scperciva if (broken_txfifo) 898246016Scperciva uart_sched_softih(sc, SER_INT_TXIDLE); 899119815Smarcel return (0); 900119815Smarcel} 901