1176774Sraj/*- 2188711Sraj * Copyright (C) 2008-2009 Semihalf, Piotr Ziecik 3188711Sraj * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski 4176774Sraj * All rights reserved. 5176774Sraj * 6176774Sraj * Redistribution and use in source and binary forms, with or without 7176774Sraj * modification, are permitted provided that the following conditions 8176774Sraj * are met: 9176774Sraj * 1. Redistributions of source code must retain the above copyright 10176774Sraj * notice, this list of conditions and the following disclaimer. 11176774Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176774Sraj * notice, this list of conditions and the following disclaimer in the 13176774Sraj * documentation and/or other materials provided with the distribution. 14176774Sraj * 15176774Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176774Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176774Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18176774Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19176774Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20176774Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21176774Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22176774Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23176774Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24176774Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176774Sraj * 26176774Sraj * $FreeBSD$ 27176774Sraj */ 28176774Sraj 29176774Sraj#define TSEC_REG_ID 0x000 /* Controller ID register #1. */ 30176774Sraj#define TSEC_REG_ID2 0x004 /* Controller ID register #2. */ 31176774Sraj 32176774Sraj/* TSEC General Control and Status Registers */ 33176774Sraj#define TSEC_REG_IEVENT 0x010 /* Interrupt event register */ 34176774Sraj#define TSEC_REG_IMASK 0x014 /* Interrupt mask register */ 35176774Sraj#define TSEC_REG_EDIS 0x018 /* Error disabled register */ 36176774Sraj#define TSEC_REG_ECNTRL 0x020 /* Ethernet control register */ 37176774Sraj#define TSEC_REG_MINFLR 0x024 /* Minimum frame length register */ 38176774Sraj#define TSEC_REG_PTV 0x028 /* Pause time value register */ 39176774Sraj#define TSEC_REG_DMACTRL 0x02c /* DMA control register */ 40176774Sraj#define TSEC_REG_TBIPA 0x030 /* TBI PHY address register */ 41176774Sraj 42176774Sraj/* TSEC FIFO Control and Status Registers */ 43176774Sraj#define TSEC_REG_FIFO_PAUSE_CTRL 0x04c /* FIFO pause control register */ 44176774Sraj#define TSEC_REG_FIFO_TX_THR 0x08c /* FIFO transmit threshold register */ 45176774Sraj#define TSEC_REG_FIFO_TX_STARVE 0x098 /* FIFO transmit starve register */ 46176774Sraj#define TSEC_REG_FIFO_TX_STARVE_SHUTOFF 0x09c /* FIFO transmit starve shutoff 47176774Sraj * register */ 48176774Sraj 49176774Sraj/* TSEC Transmit Control and Status Registers */ 50176774Sraj#define TSEC_REG_TCTRL 0x100 /* Transmit control register */ 51176774Sraj#define TSEC_REG_TSTAT 0x104 /* Transmit Status Register */ 52176774Sraj#define TSEC_REG_TBDLEN 0x10c /* TxBD data length register */ 53176774Sraj#define TSEC_REG_TXIC 0x110 /* Transmit interrupt coalescing 54176774Sraj * configuration register */ 55176774Sraj#define TSEC_REG_CTBPTR 0x124 /* Current TxBD pointer register */ 56176774Sraj#define TSEC_REG_TBPTR 0x184 /* TxBD pointer register */ 57176774Sraj#define TSEC_REG_TBASE 0x204 /* TxBD base address register */ 58176774Sraj#define TSEC_REG_OSTBD 0x2b0 /* Out-of-sequence TxBD register */ 59176774Sraj#define TSEC_REG_OSTBDP 0x2b4 /* Out-of-sequence Tx data buffer pointer 60176774Sraj * register */ 61176774Sraj 62176774Sraj/* TSEC Receive Control and Status Registers */ 63176774Sraj#define TSEC_REG_RCTRL 0x300 /* Receive control register */ 64176774Sraj#define TSEC_REG_RSTAT 0x304 /* Receive status register */ 65176774Sraj#define TSEC_REG_RBDLEN 0x30c /* RxBD data length register */ 66176774Sraj#define TSEC_REG_RXIC 0x310 /* Receive interrupt coalescing 67176774Sraj * configuration register */ 68176774Sraj#define TSEC_REG_CRBPTR 0x324 /* Current RxBD pointer register */ 69176774Sraj#define TSEC_REG_MRBLR 0x340 /* Maximum receive buffer length register */ 70176774Sraj#define TSEC_REG_RBPTR 0x384 /* RxBD pointer register */ 71176774Sraj#define TSEC_REG_RBASE 0x404 /* RxBD base address register */ 72176774Sraj 73176774Sraj/* TSEC MAC Registers */ 74176774Sraj#define TSEC_REG_MACCFG1 0x500 /* MAC configuration 1 register */ 75176774Sraj#define TSEC_REG_MACCFG2 0x504 /* MAC configuration 2 register */ 76176774Sraj#define TSEC_REG_IPGIFG 0x508 /* Inter-packet gap/inter-frame gap 77176774Sraj * register */ 78176774Sraj#define TSEC_REG_HAFDUP 0x50c /* Half-duplex register */ 79176774Sraj#define TSEC_REG_MAXFRM 0x510 /* Maximum frame length register */ 80176774Sraj#define TSEC_REG_MIIMCFG 0x520 /* MII Management configuration register */ 81176774Sraj#define TSEC_REG_MIIMCOM 0x524 /* MII Management command register */ 82176774Sraj#define TSEC_REG_MIIMADD 0x528 /* MII Management address register */ 83176774Sraj#define TSEC_REG_MIIMCON 0x52c /* MII Management control register */ 84176774Sraj#define TSEC_REG_MIIMSTAT 0x530 /* MII Management status register */ 85176774Sraj#define TSEC_REG_MIIMIND 0x534 /* MII Management indicator register */ 86176774Sraj#define TSEC_REG_IFSTAT 0x53c /* Interface status register */ 87176774Sraj#define TSEC_REG_MACSTNADDR1 0x540 /* Station address register, part 1 */ 88176774Sraj#define TSEC_REG_MACSTNADDR2 0x544 /* Station address register, part 2 */ 89176774Sraj 90176774Sraj/* TSEC Transmit and Receive Counters */ 91176774Sraj#define TSEC_REG_MON_TR64 0x680 /* Transmit and receive 64-byte 92176774Sraj * frame counter register */ 93176774Sraj#define TSEC_REG_MON_TR127 0x684 /* Transmit and receive 65-127 byte 94176774Sraj * frame counter register */ 95176774Sraj#define TSEC_REG_MON_TR255 0x688 /* Transmit and receive 128-255 byte 96176774Sraj * frame counter register */ 97176774Sraj#define TSEC_REG_MON_TR511 0x68c /* Transmit and receive 256-511 byte 98176774Sraj * frame counter register */ 99176774Sraj#define TSEC_REG_MON_TR1K 0x690 /* Transmit and receive 512-1023 byte 100176774Sraj * frame counter register */ 101176774Sraj#define TSEC_REG_MON_TRMAX 0x694 /* Transmit and receive 1024-1518 byte 102176774Sraj * frame counter register */ 103176774Sraj#define TSEC_REG_MON_TRMGV 0x698 /* Transmit and receive 1519-1522 byte 104176774Sraj * good VLAN frame counter register */ 105176774Sraj 106176774Sraj/* TSEC Receive Counters */ 107176774Sraj#define TSEC_REG_MON_RBYT 0x69c /* Receive byte counter register */ 108176774Sraj#define TSEC_REG_MON_RPKT 0x6a0 /* Receive packet counter register */ 109176774Sraj#define TSEC_REG_MON_RFCS 0x6a4 /* Receive FCS error counter register */ 110176774Sraj#define TSEC_REG_MON_RMCA 0x6a8 /* Receive multicast packet counter 111176774Sraj * register */ 112176774Sraj#define TSEC_REG_MON_RBCA 0x6ac /* Receive broadcast packet counter 113176774Sraj * register */ 114176774Sraj#define TSEC_REG_MON_RXCF 0x6b0 /* Receive control frame packet counter 115176774Sraj * register */ 116176774Sraj#define TSEC_REG_MON_RXPF 0x6b4 /* Receive pause frame packet counter 117176774Sraj * register */ 118176774Sraj#define TSEC_REG_MON_RXUO 0x6b8 /* Receive unknown OP code counter 119176774Sraj * register */ 120176774Sraj#define TSEC_REG_MON_RALN 0x6bc /* Receive alignment error counter 121176774Sraj * register */ 122176774Sraj#define TSEC_REG_MON_RFLR 0x6c0 /* Receive frame length error counter 123176774Sraj * register */ 124176774Sraj#define TSEC_REG_MON_RCDE 0x6c4 /* Receive code error counter register */ 125176774Sraj#define TSEC_REG_MON_RCSE 0x6c8 /* Receive carrier sense error counter 126176774Sraj * register */ 127176774Sraj#define TSEC_REG_MON_RUND 0x6cc /* Receive undersize packet counter 128176774Sraj * register */ 129176774Sraj#define TSEC_REG_MON_ROVR 0x6d0 /* Receive oversize packet counter 130176774Sraj * register */ 131176774Sraj#define TSEC_REG_MON_RFRG 0x6d4 /* Receive fragments counter register */ 132176774Sraj#define TSEC_REG_MON_RJBR 0x6d8 /* Receive jabber counter register */ 133176774Sraj#define TSEC_REG_MON_RDRP 0x6dc /* Receive drop counter register */ 134176774Sraj 135176774Sraj/* TSEC Transmit Counters */ 136176774Sraj#define TSEC_REG_MON_TBYT 0x6e0 /* Transmit byte counter register */ 137176774Sraj#define TSEC_REG_MON_TPKT 0x6e4 /* Transmit packet counter register */ 138176774Sraj#define TSEC_REG_MON_TMCA 0x6e8 /* Transmit multicast packet counter 139176774Sraj * register */ 140176774Sraj#define TSEC_REG_MON_TBCA 0x6ec /* Transmit broadcast packet counter 141176774Sraj * register */ 142176774Sraj#define TSEC_REG_MON_TXPF 0x6f0 /* Transmit PAUSE control frame counter 143176774Sraj * register */ 144176774Sraj#define TSEC_REG_MON_TDFR 0x6f4 /* Transmit deferral packet counter 145176774Sraj * register */ 146176774Sraj#define TSEC_REG_MON_TEDF 0x6f8 /* Transmit excessive deferral packet 147176774Sraj * counter register */ 148176774Sraj#define TSEC_REG_MON_TSCL 0x6fc /* Transmit single collision packet counter 149176774Sraj * register */ 150176774Sraj#define TSEC_REG_MON_TMCL 0x700 /* Transmit multiple collision packet counter 151176774Sraj * register */ 152176774Sraj#define TSEC_REG_MON_TLCL 0x704 /* Transmit late collision packet counter 153176774Sraj * register */ 154176774Sraj#define TSEC_REG_MON_TXCL 0x708 /* Transmit excessive collision packet 155176774Sraj * counter register */ 156176774Sraj#define TSEC_REG_MON_TNCL 0x70c /* Transmit total collision counter 157176774Sraj * register */ 158176774Sraj#define TSEC_REG_MON_TDRP 0x714 /* Transmit drop frame counter register */ 159176774Sraj#define TSEC_REG_MON_TJBR 0x718 /* Transmit jabber frame counter register */ 160176774Sraj#define TSEC_REG_MON_TFCS 0x71c /* Transmit FCS error counter register */ 161176774Sraj#define TSEC_REG_MON_TXCF 0x720 /* Transmit control frame counter register */ 162176774Sraj#define TSEC_REG_MON_TOVR 0x724 /* Transmit oversize frame counter 163176774Sraj * register */ 164176774Sraj#define TSEC_REG_MON_TUND 0x728 /* Transmit undersize frame counter 165176774Sraj * register */ 166176774Sraj#define TSEC_REG_MON_TFRG 0x72c /* Transmit fragments frame counter 167176774Sraj * register */ 168176774Sraj 169176774Sraj/* TSEC General Registers */ 170176774Sraj#define TSEC_REG_MON_CAR1 0x730 /* Carry register one register */ 171176774Sraj#define TSEC_REG_MON_CAR2 0x734 /* Carry register two register */ 172176774Sraj#define TSEC_REG_MON_CAM1 0x738 /* Carry register one mask register */ 173176774Sraj#define TSEC_REG_MON_CAM2 0x73c /* Carry register two mask register */ 174176774Sraj 175176774Sraj/* TSEC Hash Function Registers */ 176176774Sraj#define TSEC_REG_IADDR0 0x800 /* Indivdual address register 0 */ 177176774Sraj#define TSEC_REG_IADDR1 0x804 /* Indivdual address register 1 */ 178176774Sraj#define TSEC_REG_IADDR2 0x808 /* Indivdual address register 2 */ 179176774Sraj#define TSEC_REG_IADDR3 0x80c /* Indivdual address register 3 */ 180176774Sraj#define TSEC_REG_IADDR4 0x810 /* Indivdual address register 4 */ 181176774Sraj#define TSEC_REG_IADDR5 0x814 /* Indivdual address register 5 */ 182176774Sraj#define TSEC_REG_IADDR6 0x818 /* Indivdual address register 6 */ 183176774Sraj#define TSEC_REG_IADDR7 0x81c /* Indivdual address register 7 */ 184176774Sraj#define TSEC_REG_GADDR0 0x880 /* Group address register 0 */ 185176774Sraj#define TSEC_REG_GADDR1 0x884 /* Group address register 1 */ 186176774Sraj#define TSEC_REG_GADDR2 0x888 /* Group address register 2 */ 187176774Sraj#define TSEC_REG_GADDR3 0x88c /* Group address register 3 */ 188176774Sraj#define TSEC_REG_GADDR4 0x890 /* Group address register 4 */ 189176774Sraj#define TSEC_REG_GADDR5 0x894 /* Group address register 5 */ 190176774Sraj#define TSEC_REG_GADDR6 0x898 /* Group address register 6 */ 191176774Sraj#define TSEC_REG_GADDR7 0x89c /* Group address register 7 */ 192188711Sraj#define TSEC_REG_IADDR(n) (TSEC_REG_IADDR0 + (n << 2)) 193188711Sraj#define TSEC_REG_GADDR(n) (TSEC_REG_GADDR0 + (n << 2)) 194176774Sraj 195176774Sraj/* TSEC attribute registers */ 196176774Sraj#define TSEC_REG_ATTR 0xbf8 /* Attributes Register */ 197176774Sraj#define TSEC_REG_ATTRELI 0xbfc /* Attributes EL & EI register */ 198176774Sraj 199176774Sraj/* Size of TSEC registers area */ 200188711Sraj#define TSEC_IO_SIZE 0x1000 201176774Sraj 202176774Sraj/* reg bits */ 203176774Sraj#define TSEC_FIFO_PAUSE_CTRL_EN 0x0002 204176774Sraj 205176774Sraj#define TSEC_DMACTRL_TDSEN 0x00000080 /* Tx Data snoop enable */ 206176774Sraj#define TSEC_DMACTRL_TBDSEN 0x00000040 /* TxBD snoop enable */ 207176774Sraj#define TSEC_DMACTRL_GRS 0x00000010 /* Graceful receive stop */ 208176774Sraj#define TSEC_DMACTRL_GTS 0x00000008 /* Graceful transmit stop */ 209176774Sraj#define DMACTRL_WWR 0x00000002 /* Write with response */ 210176774Sraj#define DMACTRL_WOP 0x00000001 /* Wait or poll */ 211176774Sraj 212188711Sraj#define TSEC_RCTRL_VLEX 0x00002000 /* Enable automatic VLAN tag 213188711Sraj * extraction and deletion 214188711Sraj * from Ethernet frames */ 215188711Sraj#define TSEC_RCTRL_IPCSEN 0x00000200 /* IP Checksum verification enable */ 216188711Sraj#define TSEC_RCTRL_TUCSEN 0x00000100 /* TCP or UDP Checksum verification enable */ 217188711Sraj#define TSEC_RCTRL_PRSDEP 0x000000C0 /* Parser control */ 218188711Sraj#define TSEC_RCRTL_PRSFM 0x00000020 /* FIFO-mode parsing */ 219176774Sraj#define TSEC_RCTRL_BC_REJ 0x00000010 /* Broadcast frame reject */ 220176774Sraj#define TSEC_RCTRL_PROM 0x00000008 /* Promiscuous mode */ 221176774Sraj#define TSEC_RCTRL_RSF 0x00000004 /* Receive short frame mode */ 222176774Sraj 223188711Sraj#define TSEC_RCTRL_PRSDEP_PARSER_OFF 0x00000000 /* Parser Disabled */ 224188711Sraj#define TSEC_RCTRL_PRSDEP_PARSE_L2 0x00000040 /* Parse L2 */ 225188711Sraj#define TSEC_RCTRL_PRSDEP_PARSE_L23 0x00000080 /* Parse L2 and L3 */ 226188711Sraj#define TSEC_RCTRL_PRSDEP_PARSE_L234 0x000000C0 /* Parse L2, L3 and L4 */ 227188711Sraj 228188711Sraj#define TSEC_TCTRL_IPCSEN 0x00004000 /* IP header checksum generation enable */ 229188711Sraj#define TSEC_TCTRL_TUCSEN 0x00002000 /* TCP/UDP header checksum generation enable */ 230188711Sraj 231176774Sraj#define TSEC_TSTAT_THLT 0x80000000 /* Transmit halt */ 232176774Sraj#define TSEC_RSTAT_QHLT 0x00800000 /* RxBD queue is halted */ 233176774Sraj 234176774Sraj#define TSEC_IEVENT_BABR 0x80000000 /* Babbling receive error */ 235176774Sraj#define TSEC_IEVENT_RXC 0x40000000 /* Receive control interrupt */ 236176774Sraj#define TSEC_IEVENT_BSY 0x20000000 /* Busy condition interrupt */ 237176774Sraj#define TSEC_IEVENT_EBERR 0x10000000 /* Ethernet bus error */ 238176774Sraj#define TSEC_IEVENT_MSRO 0x04000000 /* MSTAT Register Overflow */ 239176774Sraj#define TSEC_IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */ 240176774Sraj#define TSEC_IEVENT_BABT 0x01000000 /* Babbling transmit error */ 241176774Sraj#define TSEC_IEVENT_TXC 0x00800000 /* Transmit control interrupt */ 242176774Sraj#define TSEC_IEVENT_TXE 0x00400000 /* Transmit error */ 243176774Sraj#define TSEC_IEVENT_TXB 0x00200000 /* Transmit buffer */ 244176774Sraj#define TSEC_IEVENT_TXF 0x00100000 /* Transmit frame interrupt */ 245176774Sraj#define TSEC_IEVENT_LC 0x00040000 /* Late collision */ 246176774Sraj#define TSEC_IEVENT_CRL 0x00020000 /* Collision retry limit/excessive 247176774Sraj * defer abort */ 248176774Sraj#define TSEC_IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */ 249176774Sraj#define TSEC_IEVENT_RXB 0x00008000 /* Receive buffer */ 250176774Sraj#define TSEC_IEVENT_MMRD 0x00000400 /* MII management read completion */ 251176774Sraj#define TSEC_IEVENT_MMWR 0x00000200 /* MII management write completion */ 252176774Sraj#define TSEC_IEVENT_GRSC 0x00000100 /* Graceful receive stop complete */ 253176774Sraj#define TSEC_IEVENT_RXF 0x00000080 /* Receive frame interrupt */ 254176774Sraj 255176774Sraj#define TSEC_IMASK_BREN 0x80000000 /* Babbling receiver interrupt */ 256176774Sraj#define TSEC_IMASK_RXCEN 0x40000000 /* Receive control interrupt */ 257176774Sraj#define TSEC_IMASK_BSYEN 0x20000000 /* Busy interrupt */ 258176774Sraj#define TSEC_IMASK_EBERREN 0x10000000 /* Ethernet controller bus error */ 259176774Sraj#define TSEC_IMASK_MSROEN 0x04000000 /* MSTAT register overflow interrupt */ 260176774Sraj#define TSEC_IMASK_GTSCEN 0x02000000 /* Graceful transmit stop complete interrupt */ 261176774Sraj#define TSEC_IMASK_BTEN 0x01000000 /* Babbling transmitter interrupt */ 262176774Sraj#define TSEC_IMASK_TXCEN 0x00800000 /* Transmit control interrupt */ 263176774Sraj#define TSEC_IMASK_TXEEN 0x00400000 /* Transmit error interrupt */ 264176774Sraj#define TSEC_IMASK_TXBEN 0x00200000 /* Transmit buffer interrupt */ 265176774Sraj#define TSEC_IMASK_TXFEN 0x00100000 /* Transmit frame interrupt */ 266176774Sraj#define TSEC_IMASK_LCEN 0x00040000 /* Late collision */ 267176774Sraj#define TSEC_IMASK_CRLEN 0x00020000 /* Collision retry limit/excessive defer */ 268176774Sraj#define TSEC_IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun */ 269176774Sraj#define TSEC_IMASK_RXBEN 0x00008000 /* Receive buffer interrupt */ 270176774Sraj#define TSEC_IMASK_MMRD 0x00000400 /* MII management read completion */ 271176774Sraj#define TSEC_IMASK_MMWR 0x00000200 /* MII management write completion */ 272176774Sraj#define TSEC_IMASK_GRSCEN 0x00000100 /* Graceful receive stop complete interrupt */ 273176774Sraj#define TSEC_IMASK_RXFEN 0x00000080 /* Receive frame interrupt */ 274176774Sraj 275176774Sraj#define TSEC_ATTR_ELCWT 0x00004000 /* Write extracted data to L2 cache */ 276176774Sraj#define TSEC_ATTR_BDLWT 0x00000800 /* Write buffer descriptor to L2 cache */ 277176774Sraj#define TSEC_ATTR_RDSEN 0x00000080 /* Rx data snoop enable */ 278176774Sraj#define TSEC_ATTR_RBDSEN 0x00000040 /* RxBD snoop enable */ 279176774Sraj 280176774Sraj#define TSEC_MACCFG1_SOFT_RESET 0x80000000 /* Soft reset */ 281176774Sraj#define TSEC_MACCFG1_RESET_RX_MC 0x00080000 /* Reset receive MAC control block */ 282176774Sraj#define TSEC_MACCFG1_RESET_TX_MC 0x00040000 /* Reset transmit MAC control block */ 283176774Sraj#define TSEC_MACCFG1_RESET_RX_FUN 0x00020000 /* Reset receive function block */ 284176774Sraj#define TSEC_MACCFG1_RESET_TX_FUN 0x00010000 /* Reset transmit function block */ 285176774Sraj#define TSEC_MACCFG1_LOOPBACK 0x00000100 /* Loopback */ 286176774Sraj#define TSEC_MACCFG1_RX_FLOW 0x00000020 /* Receive flow */ 287176774Sraj#define TSEC_MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */ 288176774Sraj#define TSEC_MACCFG1_SYNCD_RX_EN 0x00000008 /* Receive enable synchronized 289176774Sraj * to the receive stream (Read-only) */ 290176774Sraj#define TSEC_MACCFG1_RX_EN 0x00000004 /* Receive enable */ 291176774Sraj#define TSEC_MACCFG1_SYNCD_TX_EN 0x00000002 /* Transmit enable synchronized 292176774Sraj * to the transmit stream (Read-only) */ 293176774Sraj#define TSEC_MACCFG1_TX_EN 0x00000001 /* Transmit enable */ 294176774Sraj 295176774Sraj#define TSEC_MACCFG2_PRECNT 0x00007000 /* Preamble Length (0x7) */ 296176774Sraj#define TSEC_MACCFG2_IF 0x00000300 /* Determines the type of interface 297176774Sraj * to which the MAC is connected */ 298176774Sraj#define TSEC_MACCFG2_MII 0x00000100 /* Nibble mode (MII) */ 299176774Sraj#define TSEC_MACCFG2_GMII 0x00000200 /* Byte mode (GMII/TBI) */ 300176774Sraj#define TSEC_MACCFG2_HUGEFRAME 0x00000020 /* Huge frame enable */ 301176774Sraj#define TSEC_MACCFG2_LENGTHCHECK 0x00000010 /* Length check */ 302176774Sraj#define TSEC_MACCFG2_PADCRC 0x00000004 /* Pad and append CRC */ 303176774Sraj#define TSEC_MACCFG2_CRCEN 0x00000002 /* CRC enable */ 304176774Sraj#define TSEC_MACCFG2_FULLDUPLEX 0x00000001 /* Full duplex configure */ 305176774Sraj 306176774Sraj#define TSEC_ECNTRL_STEN 0x00001000 /* Statistics enabled */ 307176774Sraj#define TSEC_ECNTRL_GMIIM 0x00000040 /* GMII I/F mode */ 308176774Sraj#define TSEC_ECNTRL_TBIM 0x00000020 /* Ten-bit I/F mode */ 309176774Sraj#define TSEC_ECNTRL_R100M 0x00000008 /* RGMII/RMII 100 mode */ 310176774Sraj#define TSEC_ECNTRL_RMM 0x00000004 /* Reduced-pin mode */ 311176774Sraj#define TSEC_ECNTRL_SGMIIM 0x00000002 /* Serial GMII mode */ 312176774Sraj 313176774Sraj#define TSEC_MIIMCFG_RESETMGMT 0x80000000 /* Reset management */ 314176774Sraj#define TSEC_MIIMCFG_NOPRE 0x00000010 /* Preamble suppress */ 315176774Sraj#define TSEC_MIIMCFG_CLKDIV28 0x00000007 /* source clock divided by 28 */ 316176774Sraj#define TSEC_MIIMCFG_CLKDIV20 0x00000006 /* source clock divided by 20 */ 317176774Sraj#define TSEC_MIIMCFG_CLKDIV14 0x00000005 /* source clock divided by 14 */ 318176774Sraj#define TSEC_MIIMCFG_CLKDIV10 0x00000004 /* source clock divided by 10 */ 319176774Sraj#define TSEC_MIIMCFG_CLKDIV8 0x00000003 /* source clock divided by 8 */ 320176774Sraj#define TSEC_MIIMCFG_CLKDIV6 0x00000002 /* source clock divided by 6 */ 321176774Sraj#define TSEC_MIIMCFG_CLKDIV4 0x00000001 /* source clock divided by 4 */ 322176774Sraj 323176774Sraj#define TSEC_MIIMIND_NOTVALID 0x00000004 /* Not valid */ 324176774Sraj#define TSEC_MIIMIND_SCAN 0x00000002 /* Scan in progress */ 325176774Sraj#define TSEC_MIIMIND_BUSY 0x00000001 /* Busy */ 326176774Sraj 327176774Sraj#define TSEC_MIIMCOM_SCANCYCLE 0x00000002 /* Scan cycle */ 328176774Sraj#define TSEC_MIIMCOM_READCYCLE 0x00000001 /* Read cycle */ 329176774Sraj 330176774Sraj/* Transmit Data Buffer Descriptor (TxBD) Field Descriptions */ 331176774Sraj#define TSEC_TXBD_R 0x8000 /* Ready */ 332176774Sraj#define TSEC_TXBD_PADCRC 0x4000 /* PAD/CRC */ 333176774Sraj#define TSEC_TXBD_W 0x2000 /* Wrap */ 334176774Sraj#define TSEC_TXBD_I 0x1000 /* Interrupt */ 335176774Sraj#define TSEC_TXBD_L 0x0800 /* Last in frame */ 336176774Sraj#define TSEC_TXBD_TC 0x0400 /* Tx CRC */ 337176774Sraj#define TSEC_TXBD_DEF 0x0200 /* Defer indication */ 338176774Sraj#define TSEC_TXBD_TO1 0x0100 /* Transmit software ownership */ 339176774Sraj#define TSEC_TXBD_HFE 0x0080 /* Huge frame enable (written by user) */ 340176774Sraj#define TSEC_TXBD_LC 0x0080 /* Late collision (written by TSEC) */ 341176774Sraj#define TSEC_TXBD_RL 0x0040 /* Retransmission Limit */ 342188711Sraj#define TSEC_TXBD_TOE 0x0002 /* TCP/IP Offload Enable */ 343176774Sraj#define TSEC_TXBD_UN 0x0002 /* Underrun */ 344176774Sraj#define TSEC_TXBD_TXTRUNC 0x0001 /* TX truncation */ 345176774Sraj 346176774Sraj/* Receive Data Buffer Descriptor (RxBD) Field Descriptions */ 347176774Sraj#define TSEC_RXBD_E 0x8000 /* Empty */ 348176774Sraj#define TSEC_RXBD_RO1 0x4000 /* Receive software ownership bit */ 349176774Sraj#define TSEC_RXBD_W 0x2000 /* Wrap */ 350176774Sraj#define TSEC_RXBD_I 0x1000 /* Interrupt */ 351176774Sraj#define TSEC_RXBD_L 0x0800 /* Last in frame */ 352176774Sraj#define TSEC_RXBD_F 0x0400 /* First in frame */ 353176774Sraj#define TSEC_RXBD_M 0x0100 /* Miss - The frame was received because 354176774Sraj * of promiscuous mode. */ 355176774Sraj#define TSEC_RXBD_B 0x0080 /* Broadcast */ 356176774Sraj#define TSEC_RXBD_MC 0x0040 /* Multicast */ 357176774Sraj#define TSEC_RXBD_LG 0x0020 /* Large - Rx frame length violation */ 358176774Sraj#define TSEC_RXBD_NO 0x0010 /* Rx non-octet aligned frame */ 359176774Sraj#define TSEC_RXBD_SH 0x0008 /* Short frame */ 360176774Sraj#define TSEC_RXBD_CR 0x0004 /* Rx CRC error */ 361176774Sraj#define TSEC_RXBD_OV 0x0002 /* Overrun */ 362176774Sraj#define TSEC_RXBD_TR 0x0001 /* Truncation */ 363176774Sraj#define TSEC_RXBD_ZEROONINIT (TSEC_RXBD_TR | TSEC_RXBD_OV | TSEC_RXBD_CR | \ 364176774Sraj TSEC_RXBD_SH | TSEC_RXBD_NO | TSEC_RXBD_LG | TSEC_RXBD_MC | \ 365176774Sraj TSEC_RXBD_B | TSEC_RXBD_M) 366176774Sraj 367176774Sraj#define TSEC_TXBUFFER_ALIGNMENT 64 368176774Sraj#define TSEC_RXBUFFER_ALIGNMENT 64 369188711Sraj 370188711Sraj/* Transmit Path Off-Load Frame Control Block flags */ 371188711Sraj#define TSEC_TX_FCB_VLAN 0x8000 /* VLAN control word valid */ 372188711Sraj#define TSEC_TX_FCB_L3_IS_IP 0x4000 /* Layer 3 header is an IP header */ 373188711Sraj#define TSEC_TX_FCB_L3_IS_IP6 0x2000 /* IP header is IP version 6 */ 374188711Sraj#define TSEC_TX_FCB_L4_IS_TCP_UDP 0x1000 /* Layer 4 header is a TCP or UDP header */ 375188711Sraj#define TSEC_TX_FCB_L4_IS_UDP 0x0800 /* UDP protocol at layer 4 */ 376188711Sraj#define TSEC_TX_FCB_CSUM_IP 0x0400 /* Checksum IP header enable */ 377188711Sraj#define TSEC_TX_FCB_CSUM_TCP_UDP 0x0200 /* Checksum TCP or UDP header enable */ 378188711Sraj#define TSEC_TX_FCB_FLAG_NO_PH_CSUM 0x0100 /* Disable pseudo-header checksum */ 379188711Sraj#define TSEC_TX_FCB_FLAG_PTP 0x0001 /* This is a PTP packet */ 380188711Sraj 381188711Sraj/* Receive Path Off-Load Frame Control Block flags */ 382188711Sraj#define TSEC_RX_FCB_VLAN 0x8000 /* VLAN tag recognized */ 383188711Sraj#define TSEC_RX_FCB_IP_FOUND 0x4000 /* IP header found at layer 3 */ 384188711Sraj#define TSEC_RX_FCB_IP6_FOUND 0x2000 /* IP version 6 header found at layer 3 */ 385188711Sraj#define TSEC_RX_FCB_TCP_UDP_FOUND 0x1000 /* TCP or UDP header found at layer 4 */ 386188711Sraj#define TSEC_RX_FCB_IP_CSUM 0x0800 /* IPv4 header checksum checked */ 387188711Sraj#define TSEC_RX_FCB_TCP_UDP_CSUM 0x0400 /* TCP or UDP header checksum checked */ 388188711Sraj#define TSEC_RX_FCB_IP_CSUM_ERROR 0x0200 /* IPv4 header checksum verification error */ 389188711Sraj#define TSEC_RX_FCB_TCP_UDP_CSUM_ERROR 0x0100 /* TCP or UDP header checksum verification error */ 390188711Sraj#define TSEC_RX_FCB_PARSE_ERROR 0x000C /* Parse error */ 391