1139749Simp/*- 253790Sobrien * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010 353790Sobrien * PCI-SCSI controllers. 453790Sobrien * 586266Sgroudier * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr> 653790Sobrien * 753790Sobrien * This driver also supports the following Symbios/LSI PCI-SCSI chips: 859743Sgroudier * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895, 959743Sgroudier * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode. 1053790Sobrien * 1153790Sobrien * 1253790Sobrien * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver. 1353790Sobrien * Copyright (C) 1998-1999 Gerard Roudier 1453790Sobrien * 1553790Sobrien * The sym53c8xx driver is derived from the ncr53c8xx driver that had been 1653790Sobrien * a port of the FreeBSD ncr driver to Linux-1.2.13. 1753790Sobrien * 1853790Sobrien * The original ncr driver has been written for 386bsd and FreeBSD by 1953790Sobrien * Wolfgang Stanglmeier <wolf@cologne.de> 2053790Sobrien * Stefan Esser <se@mi.Uni-Koeln.de> 2153790Sobrien * Copyright (C) 1994 Wolfgang Stanglmeier 2253790Sobrien * 2353790Sobrien * The initialisation code, and part of the code that addresses 2453790Sobrien * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM 2553790Sobrien * written by Justin T. Gibbs. 2653790Sobrien * 2753790Sobrien * Other major contributions: 2853790Sobrien * 2953790Sobrien * NVRAM detection and reading. 3053790Sobrien * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk> 3153790Sobrien * 3253790Sobrien *----------------------------------------------------------------------------- 3353790Sobrien * 3453790Sobrien * Redistribution and use in source and binary forms, with or without 3553790Sobrien * modification, are permitted provided that the following conditions 3653790Sobrien * are met: 3753790Sobrien * 1. Redistributions of source code must retain the above copyright 3853790Sobrien * notice, this list of conditions and the following disclaimer. 3953790Sobrien * 2. Redistributions in binary form must reproduce the above copyright 4053790Sobrien * notice, this list of conditions and the following disclaimer in the 4153790Sobrien * documentation and/or other materials provided with the distribution. 4253790Sobrien * 3. The name of the author may not be used to endorse or promote products 4353790Sobrien * derived from this software without specific prior written permission. 4453790Sobrien * 4553790Sobrien * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 4653790Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 4753790Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 4853790Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 4953790Sobrien * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 5053790Sobrien * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 5153790Sobrien * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 5253790Sobrien * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 5353790Sobrien * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 5453790Sobrien * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 5553790Sobrien * SUCH DAMAGE. 5653790Sobrien */ 5755258Sobrien 5855258Sobrien/* $FreeBSD$ */ 5955258Sobrien 6053790Sobrien#ifndef SYM_DEFS_H 6153790Sobrien#define SYM_DEFS_H 6253790Sobrien 6353790Sobrien/* 6453790Sobrien * Vendor. 6553790Sobrien */ 6653790Sobrien#define PCI_VENDOR_NCR 0x1000 6753790Sobrien 6853790Sobrien/* 6953790Sobrien * PCI device identifier of SYMBIOS chips. 7053790Sobrien */ 7153790Sobrien#define PCI_ID_SYM53C810 1 7253790Sobrien#define PCI_ID_SYM53C810AP 5 7353790Sobrien#define PCI_ID_SYM53C815 4 7453790Sobrien#define PCI_ID_SYM53C820 2 7553790Sobrien#define PCI_ID_SYM53C825 3 7653790Sobrien#define PCI_ID_SYM53C860 6 7753790Sobrien#define PCI_ID_SYM53C875 0xf 7853790Sobrien#define PCI_ID_SYM53C875_2 0x8f 7953790Sobrien#define PCI_ID_SYM53C885 0xd 8053790Sobrien#define PCI_ID_SYM53C895 0xc 8153790Sobrien#define PCI_ID_SYM53C896 0xb 8253790Sobrien#define PCI_ID_SYM53C895A 0x12 8353790Sobrien#define PCI_ID_LSI53C1010 0x20 8455300Sgroudier#define PCI_ID_LSI53C1010_2 0x21 8553790Sobrien#define PCI_ID_LSI53C1510D 0xa 8653790Sobrien 8753790Sobrien/* 8853790Sobrien * SYM53C8XX device features descriptor. 8953790Sobrien */ 9053790Sobrienstruct sym_pci_chip { 9153790Sobrien u_short device_id; 9253790Sobrien unsigned short revision_id; 93179029Smarius const char *name; 9453790Sobrien u_char burst_max; /* log-base-2 of max burst */ 9553790Sobrien u_char offset_max; 9653790Sobrien u_char nr_divisor; 9754690Sobrien u_char lp_probe_bit; 9853790Sobrien u_int features; 9953790Sobrien#define FE_LED0 (1<<0) 10053790Sobrien#define FE_WIDE (1<<1) /* Wide data transfers */ 10153790Sobrien#define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */ 10253790Sobrien#define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */ 10353790Sobrien#define FE_DBLR (1<<4) /* Clock doubler present */ 10453790Sobrien#define FE_QUAD (1<<5) /* Clock quadrupler present */ 10553790Sobrien#define FE_ERL (1<<6) /* Enable read line */ 10653790Sobrien#define FE_CLSE (1<<7) /* Cache line size enable */ 10753790Sobrien#define FE_WRIE (1<<8) /* Write & Invalidate enable */ 10853790Sobrien#define FE_ERMP (1<<9) /* Enable read multiple */ 10953790Sobrien#define FE_BOF (1<<10) /* Burst opcode fetch */ 11053790Sobrien#define FE_DFS (1<<11) /* DMA fifo size */ 11153790Sobrien#define FE_PFEN (1<<12) /* Prefetch enable */ 11253790Sobrien#define FE_LDSTR (1<<13) /* Load/Store supported */ 11353790Sobrien#define FE_RAM (1<<14) /* On chip RAM present */ 11453790Sobrien#define FE_CLK80 (1<<15) /* Board clock is 80 MHz */ 11553790Sobrien#define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */ 11665404Sgroudier#define FE_64BIT (1<<17) /* 64-bit PCI BUS interface */ 11753790Sobrien#define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */ 11853790Sobrien#define FE_NOPM (1<<19) /* Scripts handles phase mismatch */ 11953790Sobrien#define FE_LEDC (1<<20) /* Hardware control of LED */ 12053790Sobrien#define FE_ULTRA3 (1<<21) /* Ultra 3 - 80 Mtrans/sec DT */ 12165404Sgroudier#define FE_66MHZ (1<<22) /* 66MHz PCI support */ 12253790Sobrien#define FE_CRC (1<<23) /* CRC support */ 12353790Sobrien#define FE_DIFF (1<<24) /* SCSI HVD support */ 12453790Sobrien#define FE_DFBC (1<<25) /* Have DFBC register */ 12553790Sobrien#define FE_LCKFRQ (1<<26) /* Have LCKFRQ */ 12653790Sobrien#define FE_C10 (1<<27) /* Various C10 core (mis)features */ 12753790Sobrien#define FE_U3EN (1<<28) /* U3EN bit usable */ 12865404Sgroudier#define FE_DAC (1<<29) /* Support PCI DAC (64 bit addressing) */ 12953790Sobrien 13053790Sobrien#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP) 13153790Sobrien#define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL) 13253790Sobrien#define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM) 13353790Sobrien}; 13453790Sobrien 13553790Sobrien/* 13653790Sobrien * Symbios NVRAM data format 13753790Sobrien */ 13853790Sobrien#define SYMBIOS_NVRAM_SIZE 368 13953790Sobrien#define SYMBIOS_NVRAM_ADDRESS 0x100 14053790Sobrien 14153790Sobrienstruct Symbios_nvram { 14253790Sobrien/* Header 6 bytes */ 14353790Sobrien u_short type; /* 0x0000 */ 14453790Sobrien u_short byte_count; /* excluding header/trailer */ 14553790Sobrien u_short checksum; 14653790Sobrien 14753790Sobrien/* Controller set up 20 bytes */ 14853790Sobrien u_char v_major; /* 0x00 */ 14953790Sobrien u_char v_minor; /* 0x30 */ 15053790Sobrien u32 boot_crc; 15153790Sobrien u_short flags; 15253790Sobrien#define SYMBIOS_SCAM_ENABLE (1) 15353790Sobrien#define SYMBIOS_PARITY_ENABLE (1<<1) 15453790Sobrien#define SYMBIOS_VERBOSE_MSGS (1<<2) 15553790Sobrien#define SYMBIOS_CHS_MAPPING (1<<3) 15653790Sobrien#define SYMBIOS_NO_NVRAM (1<<3) /* ??? */ 15753790Sobrien u_short flags1; 15853790Sobrien#define SYMBIOS_SCAN_HI_LO (1) 15953790Sobrien u_short term_state; 16053790Sobrien#define SYMBIOS_TERM_CANT_PROGRAM (0) 16153790Sobrien#define SYMBIOS_TERM_ENABLED (1) 16253790Sobrien#define SYMBIOS_TERM_DISABLED (2) 16353790Sobrien u_short rmvbl_flags; 16453790Sobrien#define SYMBIOS_RMVBL_NO_SUPPORT (0) 16553790Sobrien#define SYMBIOS_RMVBL_BOOT_DEVICE (1) 16653790Sobrien#define SYMBIOS_RMVBL_MEDIA_INSTALLED (2) 16753790Sobrien u_char host_id; 16853790Sobrien u_char num_hba; /* 0x04 */ 16953790Sobrien u_char num_devices; /* 0x10 */ 17053790Sobrien u_char max_scam_devices; /* 0x04 */ 17155628Sgroudier u_char num_valid_scam_devices; /* 0x00 */ 17255628Sgroudier u_char flags2; 17355628Sgroudier#define SYMBIOS_AVOID_BUS_RESET (1<<2) 17453790Sobrien 17553790Sobrien/* Boot order 14 bytes * 4 */ 17653790Sobrien struct Symbios_host{ 17753790Sobrien u_short type; /* 4:8xx / 0:nok */ 17853790Sobrien u_short device_id; /* PCI device id */ 17953790Sobrien u_short vendor_id; /* PCI vendor id */ 18053790Sobrien u_char bus_nr; /* PCI bus number */ 18153790Sobrien u_char device_fn; /* PCI device/function number << 3*/ 18253790Sobrien u_short word8; 18353790Sobrien u_short flags; 18453790Sobrien#define SYMBIOS_INIT_SCAN_AT_BOOT (1) 18553790Sobrien u_short io_port; /* PCI io_port address */ 18653790Sobrien } host[4]; 18753790Sobrien 18853790Sobrien/* Targets 8 bytes * 16 */ 18953790Sobrien struct Symbios_target { 19053790Sobrien u_char flags; 19153790Sobrien#define SYMBIOS_DISCONNECT_ENABLE (1) 19253790Sobrien#define SYMBIOS_SCAN_AT_BOOT_TIME (1<<1) 19353790Sobrien#define SYMBIOS_SCAN_LUNS (1<<2) 19453790Sobrien#define SYMBIOS_QUEUE_TAGS_ENABLED (1<<3) 19553790Sobrien u_char rsvd; 19653790Sobrien u_char bus_width; /* 0x08/0x10 */ 19753790Sobrien u_char sync_offset; 19853790Sobrien u_short sync_period; /* 4*period factor */ 19953790Sobrien u_short timeout; 20053790Sobrien } target[16]; 20153790Sobrien/* Scam table 8 bytes * 4 */ 20253790Sobrien struct Symbios_scam { 20353790Sobrien u_short id; 20453790Sobrien u_short method; 20553790Sobrien#define SYMBIOS_SCAM_DEFAULT_METHOD (0) 20653790Sobrien#define SYMBIOS_SCAM_DONT_ASSIGN (1) 20753790Sobrien#define SYMBIOS_SCAM_SET_SPECIFIC_ID (2) 20853790Sobrien#define SYMBIOS_SCAM_USE_ORDER_GIVEN (3) 20953790Sobrien u_short status; 21053790Sobrien#define SYMBIOS_SCAM_UNKNOWN (0) 21153790Sobrien#define SYMBIOS_SCAM_DEVICE_NOT_FOUND (1) 21253790Sobrien#define SYMBIOS_SCAM_ID_NOT_SET (2) 21353790Sobrien#define SYMBIOS_SCAM_ID_VALID (3) 21453790Sobrien u_char target_id; 21553790Sobrien u_char rsvd; 21653790Sobrien } scam[4]; 21753790Sobrien 21853790Sobrien u_char spare_devices[15*8]; 21953790Sobrien u_char trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */ 22053790Sobrien}; 22153790Sobrientypedef struct Symbios_nvram Symbios_nvram; 22253790Sobrientypedef struct Symbios_host Symbios_host; 22353790Sobrientypedef struct Symbios_target Symbios_target; 22453790Sobrientypedef struct Symbios_scam Symbios_scam; 22553790Sobrien 22653790Sobrien/* 22753790Sobrien * Tekram NvRAM data format. 22853790Sobrien */ 22953790Sobrien#define TEKRAM_NVRAM_SIZE 64 23053790Sobrien#define TEKRAM_93C46_NVRAM_ADDRESS 0 23153790Sobrien#define TEKRAM_24C16_NVRAM_ADDRESS 0x40 23253790Sobrien 23353790Sobrienstruct Tekram_nvram { 23453790Sobrien struct Tekram_target { 23553790Sobrien u_char flags; 23653790Sobrien#define TEKRAM_PARITY_CHECK (1) 23753790Sobrien#define TEKRAM_SYNC_NEGO (1<<1) 23853790Sobrien#define TEKRAM_DISCONNECT_ENABLE (1<<2) 23953790Sobrien#define TEKRAM_START_CMD (1<<3) 24053790Sobrien#define TEKRAM_TAGGED_COMMANDS (1<<4) 24153790Sobrien#define TEKRAM_WIDE_NEGO (1<<5) 24253790Sobrien u_char sync_index; 24353790Sobrien u_short word2; 24453790Sobrien } target[16]; 24553790Sobrien u_char host_id; 24653790Sobrien u_char flags; 24753790Sobrien#define TEKRAM_MORE_THAN_2_DRIVES (1) 24853790Sobrien#define TEKRAM_DRIVES_SUP_1GB (1<<1) 24953790Sobrien#define TEKRAM_RESET_ON_POWER_ON (1<<2) 25053790Sobrien#define TEKRAM_ACTIVE_NEGATION (1<<3) 25153790Sobrien#define TEKRAM_IMMEDIATE_SEEK (1<<4) 25253790Sobrien#define TEKRAM_SCAN_LUNS (1<<5) 25353790Sobrien#define TEKRAM_REMOVABLE_FLAGS (3<<6) /* 0: disable; 1: boot device; 2:all */ 25453790Sobrien u_char boot_delay_index; 25553790Sobrien u_char max_tags_index; 25653790Sobrien u_short flags1; 25753790Sobrien#define TEKRAM_F2_F6_ENABLED (1) 25853790Sobrien u_short spare[29]; 25953790Sobrien}; 26053790Sobrientypedef struct Tekram_nvram Tekram_nvram; 26153790Sobrientypedef struct Tekram_target Tekram_target; 26253790Sobrien 26353790Sobrien/* 26453790Sobrien * SYM53C8XX IO register data structure. 26553790Sobrien */ 26653790Sobrienstruct sym_reg { 26753790Sobrien/*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */ 26853790Sobrien 26953790Sobrien/*01*/ u8 nc_scntl1; /* no reset */ 27053790Sobrien #define ISCON 0x10 /* connected to scsi */ 27153790Sobrien #define CRST 0x08 /* force reset */ 27253790Sobrien #define IARB 0x02 /* immediate arbitration */ 27353790Sobrien 27453790Sobrien/*02*/ u8 nc_scntl2; /* no disconnect expected */ 27553790Sobrien #define SDU 0x80 /* cmd: disconnect will raise error */ 27653790Sobrien #define CHM 0x40 /* sta: chained mode */ 27753790Sobrien #define WSS 0x08 /* sta: wide scsi send [W]*/ 27853790Sobrien #define WSR 0x01 /* sta: wide scsi received [W]*/ 27953790Sobrien 28053790Sobrien/*03*/ u8 nc_scntl3; /* cnf system clock dependent */ 28153790Sobrien #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 28253790Sobrien #define ULTRA 0x80 /* cmd: ULTRA enable */ 28353790Sobrien /* bits 0-2, 7 rsvd for C1010 */ 28453790Sobrien 28553790Sobrien/*04*/ u8 nc_scid; /* cnf host adapter scsi address */ 28653790Sobrien #define RRE 0x40 /* r/w:e enable response to resel. */ 28753790Sobrien #define SRE 0x20 /* r/w:e enable response to select */ 28853790Sobrien 28953790Sobrien/*05*/ u8 nc_sxfer; /* ### Sync speed and count */ 29053790Sobrien /* bits 6-7 rsvd for C1010 */ 29153790Sobrien 29253790Sobrien/*06*/ u8 nc_sdid; /* ### Destination-ID */ 29353790Sobrien 29453790Sobrien/*07*/ u8 nc_gpreg; /* ??? IO-Pins */ 29553790Sobrien 29653790Sobrien/*08*/ u8 nc_sfbr; /* ### First byte received */ 29753790Sobrien 29853790Sobrien/*09*/ u8 nc_socl; 29953790Sobrien #define CREQ 0x80 /* r/w: SCSI-REQ */ 30053790Sobrien #define CACK 0x40 /* r/w: SCSI-ACK */ 30153790Sobrien #define CBSY 0x20 /* r/w: SCSI-BSY */ 30253790Sobrien #define CSEL 0x10 /* r/w: SCSI-SEL */ 30353790Sobrien #define CATN 0x08 /* r/w: SCSI-ATN */ 30453790Sobrien #define CMSG 0x04 /* r/w: SCSI-MSG */ 30553790Sobrien #define CC_D 0x02 /* r/w: SCSI-C_D */ 30653790Sobrien #define CI_O 0x01 /* r/w: SCSI-I_O */ 30753790Sobrien 30853790Sobrien/*0a*/ u8 nc_ssid; 30953790Sobrien 31053790Sobrien/*0b*/ u8 nc_sbcl; 31153790Sobrien 31253790Sobrien/*0c*/ u8 nc_dstat; 31353790Sobrien #define DFE 0x80 /* sta: dma fifo empty */ 31453790Sobrien #define MDPE 0x40 /* int: master data parity error */ 31553790Sobrien #define BF 0x20 /* int: script: bus fault */ 31653790Sobrien #define ABRT 0x10 /* int: script: command aborted */ 31753790Sobrien #define SSI 0x08 /* int: script: single step */ 31853790Sobrien #define SIR 0x04 /* int: script: interrupt instruct. */ 31953790Sobrien #define IID 0x01 /* int: script: illegal instruct. */ 32053790Sobrien 32153790Sobrien/*0d*/ u8 nc_sstat0; 32253790Sobrien #define ILF 0x80 /* sta: data in SIDL register lsb */ 32353790Sobrien #define ORF 0x40 /* sta: data in SODR register lsb */ 32453790Sobrien #define OLF 0x20 /* sta: data in SODL register lsb */ 32553790Sobrien #define AIP 0x10 /* sta: arbitration in progress */ 32653790Sobrien #define LOA 0x08 /* sta: arbitration lost */ 32753790Sobrien #define WOA 0x04 /* sta: arbitration won */ 32853790Sobrien #define IRST 0x02 /* sta: scsi reset signal */ 32953790Sobrien #define SDP 0x01 /* sta: scsi parity signal */ 33053790Sobrien 33153790Sobrien/*0e*/ u8 nc_sstat1; 33253790Sobrien #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ 33353790Sobrien 33453790Sobrien/*0f*/ u8 nc_sstat2; 33553790Sobrien #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ 33653790Sobrien #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ 33753790Sobrien #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ 33853790Sobrien #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ 33953790Sobrien #define LDSC 0x02 /* sta: disconnect & reconnect */ 34053790Sobrien 34153790Sobrien/*10*/ u8 nc_dsa; /* --> Base page */ 34253790Sobrien/*11*/ u8 nc_dsa1; 34353790Sobrien/*12*/ u8 nc_dsa2; 34453790Sobrien/*13*/ u8 nc_dsa3; 34553790Sobrien 34653790Sobrien/*14*/ u8 nc_istat; /* --> Main Command and status */ 34753790Sobrien #define CABRT 0x80 /* cmd: abort current operation */ 34853790Sobrien #define SRST 0x40 /* mod: reset chip */ 34953790Sobrien #define SIGP 0x20 /* r/w: message from host to script */ 35053790Sobrien #define SEM 0x10 /* r/w: message between host + script */ 35153790Sobrien #define CON 0x08 /* sta: connected to scsi */ 35253790Sobrien #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ 35353790Sobrien #define SIP 0x02 /* sta: scsi-interrupt */ 35453790Sobrien #define DIP 0x01 /* sta: host/script interrupt */ 35553790Sobrien 35653790Sobrien/*15*/ u8 nc_istat1; /* 896 only */ 35753790Sobrien/*16*/ u8 nc_mbox0; /* 896 only */ 35853790Sobrien/*17*/ u8 nc_mbox1; /* 896 only */ 35953790Sobrien 36053790Sobrien/*18*/ u8 nc_ctest0; 36153790Sobrien/*19*/ u8 nc_ctest1; 36253790Sobrien 36353790Sobrien/*1a*/ u8 nc_ctest2; 36453790Sobrien #define CSIGP 0x40 36553790Sobrien /* bits 0-2,7 rsvd for C1010 */ 36653790Sobrien 36753790Sobrien/*1b*/ u8 nc_ctest3; 36853790Sobrien #define FLF 0x08 /* cmd: flush dma fifo */ 36953790Sobrien #define CLF 0x04 /* cmd: clear dma fifo */ 37053790Sobrien #define FM 0x02 /* mod: fetch pin mode */ 37153790Sobrien #define WRIE 0x01 /* mod: write and invalidate enable */ 37253790Sobrien /* bits 4-7 rsvd for C1010 */ 37353790Sobrien 37453790Sobrien/*1c*/ u32 nc_temp; /* ### Temporary stack */ 37553790Sobrien 37653790Sobrien/*20*/ u8 nc_dfifo; 37753790Sobrien/*21*/ u8 nc_ctest4; 37853790Sobrien #define BDIS 0x80 /* mod: burst disable */ 37953790Sobrien #define MPEE 0x08 /* mod: master parity error enable */ 38053790Sobrien 38153790Sobrien/*22*/ u8 nc_ctest5; 38253790Sobrien #define DFS 0x20 /* mod: dma fifo size */ 38353790Sobrien /* bits 0-1, 3-7 rsvd for C1010 */ 38453790Sobrien 38553790Sobrien/*23*/ u8 nc_ctest6; 38653790Sobrien 38753790Sobrien/*24*/ u32 nc_dbc; /* ### Byte count and command */ 38853790Sobrien/*28*/ u32 nc_dnad; /* ### Next command register */ 38953790Sobrien/*2c*/ u32 nc_dsp; /* --> Script Pointer */ 39053790Sobrien/*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */ 39153790Sobrien 39253790Sobrien/*34*/ u8 nc_scratcha; /* Temporary register a */ 39353790Sobrien/*35*/ u8 nc_scratcha1; 39453790Sobrien/*36*/ u8 nc_scratcha2; 39553790Sobrien/*37*/ u8 nc_scratcha3; 39653790Sobrien 39753790Sobrien/*38*/ u8 nc_dmode; 39853790Sobrien #define BL_2 0x80 /* mod: burst length shift value +2 */ 39953790Sobrien #define BL_1 0x40 /* mod: burst length shift value +1 */ 40053790Sobrien #define ERL 0x08 /* mod: enable read line */ 40153790Sobrien #define ERMP 0x04 /* mod: enable read multiple */ 40253790Sobrien #define BOF 0x02 /* mod: burst op code fetch */ 40353790Sobrien 40453790Sobrien/*39*/ u8 nc_dien; 40553790Sobrien/*3a*/ u8 nc_sbr; 40653790Sobrien 40753790Sobrien/*3b*/ u8 nc_dcntl; /* --> Script execution control */ 40853790Sobrien #define CLSE 0x80 /* mod: cache line size enable */ 40953790Sobrien #define PFF 0x40 /* cmd: pre-fetch flush */ 41053790Sobrien #define PFEN 0x20 /* mod: pre-fetch enable */ 41153790Sobrien #define SSM 0x10 /* mod: single step mode */ 41253790Sobrien #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ 41353790Sobrien #define STD 0x04 /* cmd: start dma mode */ 41453790Sobrien #define IRQD 0x02 /* mod: irq disable */ 41553790Sobrien #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ 41653790Sobrien /* bits 0-1 rsvd for C1010 */ 41753790Sobrien 41853790Sobrien/*3c*/ u32 nc_adder; 41953790Sobrien 42053790Sobrien/*40*/ u16 nc_sien; /* -->: interrupt enable */ 42153790Sobrien/*42*/ u16 nc_sist; /* <--: interrupt status */ 42253790Sobrien #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ 42353790Sobrien #define STO 0x0400/* sta: timeout (select) */ 42453790Sobrien #define GEN 0x0200/* sta: timeout (general) */ 42553790Sobrien #define HTH 0x0100/* sta: timeout (handshake) */ 42653790Sobrien #define MA 0x80 /* sta: phase mismatch */ 42753790Sobrien #define CMP 0x40 /* sta: arbitration complete */ 42853790Sobrien #define SEL 0x20 /* sta: selected by another device */ 42953790Sobrien #define RSL 0x10 /* sta: reselected by another device*/ 43053790Sobrien #define SGE 0x08 /* sta: gross error (over/underflow)*/ 43153790Sobrien #define UDC 0x04 /* sta: unexpected disconnect */ 43253790Sobrien #define RST 0x02 /* sta: scsi bus reset detected */ 43353790Sobrien #define PAR 0x01 /* sta: scsi parity error */ 43453790Sobrien 43553790Sobrien/*44*/ u8 nc_slpar; 43653790Sobrien/*45*/ u8 nc_swide; 43753790Sobrien/*46*/ u8 nc_macntl; 43853790Sobrien/*47*/ u8 nc_gpcntl; 43953790Sobrien/*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/ 44053790Sobrien/*49*/ u8 nc_stime1; /* cmd: timeout user defined */ 44153790Sobrien/*4a*/ u16 nc_respid; /* sta: Reselect-IDs */ 44253790Sobrien 44353790Sobrien/*4c*/ u8 nc_stest0; 44453790Sobrien 44553790Sobrien/*4d*/ u8 nc_stest1; 44653790Sobrien #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ 44753790Sobrien #define DBLEN 0x08 /* clock doubler running */ 44853790Sobrien #define DBLSEL 0x04 /* clock doubler selected */ 44953790Sobrien 45053790Sobrien 45153790Sobrien/*4e*/ u8 nc_stest2; 45253790Sobrien #define ROF 0x40 /* reset scsi offset (after gross error!) */ 45353790Sobrien #define EXT 0x02 /* extended filtering */ 45453790Sobrien 45553790Sobrien/*4f*/ u8 nc_stest3; 45653790Sobrien #define TE 0x80 /* c: tolerAnt enable */ 45753790Sobrien #define HSC 0x20 /* c: Halt SCSI Clock */ 45853790Sobrien #define CSF 0x02 /* c: clear scsi fifo */ 45953790Sobrien 46053790Sobrien/*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */ 46153790Sobrien/*52*/ u8 nc_stest4; 46253790Sobrien #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ 46353790Sobrien #define SMODE_HVD 0x40 /* High Voltage Differential */ 46453790Sobrien #define SMODE_SE 0x80 /* Single Ended */ 46553790Sobrien #define SMODE_LVD 0xc0 /* Low Voltage Differential */ 46653790Sobrien #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ 46753790Sobrien /* bits 0-5 rsvd for C1010 */ 46853790Sobrien 46953790Sobrien/*53*/ u8 nc_53_; 47053790Sobrien/*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */ 47153790Sobrien/*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */ 47253790Sobrien #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */ 47353790Sobrien #define PMJCTL 0x40 /* Phase Mismatch Jump Control */ 47453790Sobrien #define ENNDJ 0x20 /* Enable Non Data PM Jump */ 47553790Sobrien #define DISFC 0x10 /* Disable Auto FIFO Clear */ 47653790Sobrien #define DILS 0x02 /* Disable Internal Load/Store */ 47753790Sobrien #define DPR 0x01 /* Disable Pipe Req */ 47853790Sobrien 47953790Sobrien/*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */ 48053790Sobrien #define ZMOD 0x80 /* High Impedance Mode */ 48153790Sobrien #define DDAC 0x08 /* Disable Dual Address Cycle */ 48253790Sobrien #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */ 48353790Sobrien #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */ 48453790Sobrien #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */ 48553790Sobrien 48653790Sobrien/*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */ 48753790Sobrien/*5a*/ u16 nc_5a_; 48853790Sobrien 48953790Sobrien/*5c*/ u8 nc_scr0; /* Working register B */ 49053790Sobrien/*5d*/ u8 nc_scr1; 49153790Sobrien/*5e*/ u8 nc_scr2; 49253790Sobrien/*5f*/ u8 nc_scr3; 49353790Sobrien 49453790Sobrien/*60*/ u8 nc_scrx[64]; /* Working register C-R */ 49553790Sobrien/*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */ 49653790Sobrien/*a4*/ u32 nc_mmws; /* Memory Move Write Selector */ 49753790Sobrien/*a8*/ u32 nc_sfs; /* Script Fetch Selector */ 49853790Sobrien/*ac*/ u32 nc_drs; /* DSA Relative Selector */ 49953790Sobrien/*b0*/ u32 nc_sbms; /* Static Block Move Selector */ 50053790Sobrien/*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */ 50153790Sobrien/*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */ 50253790Sobrien/*bc*/ u16 nc_scntl4; /* C1010 only */ 50361051Sgroudier #define U3EN 0x80 /* Enable Ultra 3 */ 50461051Sgroudier #define AIPCKEN 0x40 /* AIP checking enable */ 50561051Sgroudier /* Also enable AIP generation on C10-33*/ 50653790Sobrien #define XCLKH_DT 0x08 /* Extra clock of data hold on DT edge */ 50753790Sobrien #define XCLKH_ST 0x04 /* Extra clock of data hold on ST edge */ 50853790Sobrien #define XCLKS_DT 0x02 /* Extra clock of data set on DT edge */ 50953790Sobrien #define XCLKS_ST 0x01 /* Extra clock of data set on ST edge */ 51061051Sgroudier/*be*/ u8 nc_aipcntl0; /* AIP Control 0 C1010 only */ 51161051Sgroudier/*bf*/ u8 nc_aipcntl1; /* AIP Control 1 C1010 only */ 51261051Sgroudier #define DISAIP 0x08 /* Disable AIP generation C10-66 only */ 51353790Sobrien/*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */ 51453790Sobrien/*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */ 51553790Sobrien/*c8*/ u8 nc_rbc; /* Remaining Byte Count */ 51653790Sobrien/*c9*/ u8 nc_rbc1; 51753790Sobrien/*ca*/ u8 nc_rbc2; 51853790Sobrien/*cb*/ u8 nc_rbc3; 51953790Sobrien 52053790Sobrien/*cc*/ u8 nc_ua; /* Updated Address */ 52153790Sobrien/*cd*/ u8 nc_ua1; 52253790Sobrien/*ce*/ u8 nc_ua2; 52353790Sobrien/*cf*/ u8 nc_ua3; 52453790Sobrien/*d0*/ u32 nc_esa; /* Entry Storage Address */ 52553790Sobrien/*d4*/ u8 nc_ia; /* Instruction Address */ 52653790Sobrien/*d5*/ u8 nc_ia1; 52753790Sobrien/*d6*/ u8 nc_ia2; 52853790Sobrien/*d7*/ u8 nc_ia3; 52953790Sobrien/*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */ 53053790Sobrien/*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */ 53153790Sobrien /* Following for C1010 only */ 53253790Sobrien/*e0*/ u16 nc_crcpad; /* CRC Value */ 53353790Sobrien/*e2*/ u8 nc_crccntl0; /* CRC control register */ 53453790Sobrien #define SNDCRC 0x10 /* Send CRC Request */ 53553790Sobrien/*e3*/ u8 nc_crccntl1; /* CRC control register */ 53653790Sobrien/*e4*/ u32 nc_crcdata; /* CRC data register */ 53753790Sobrien/*e8*/ u32 nc_e8_; 53853790Sobrien/*ec*/ u32 nc_ec_; 53953790Sobrien/*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */ 54053790Sobrien}; 54153790Sobrien 54253790Sobrien/*----------------------------------------------------------- 54353790Sobrien * 54453790Sobrien * Utility macros for the script. 54553790Sobrien * 54653790Sobrien *----------------------------------------------------------- 54753790Sobrien */ 54853790Sobrien 54953790Sobrien#define REGJ(p,r) (offsetof(struct sym_reg, p ## r)) 55053790Sobrien#define REG(r) REGJ (nc_, r) 55153790Sobrien 55253790Sobrientypedef u32 symcmd; 55353790Sobrien 55453790Sobrien/*----------------------------------------------------------- 55553790Sobrien * 55653790Sobrien * SCSI phases 55753790Sobrien * 55853790Sobrien *----------------------------------------------------------- 55953790Sobrien */ 56053790Sobrien 56153790Sobrien#define SCR_DATA_OUT 0x00000000 56253790Sobrien#define SCR_DATA_IN 0x01000000 56353790Sobrien#define SCR_COMMAND 0x02000000 56453790Sobrien#define SCR_STATUS 0x03000000 56553790Sobrien#define SCR_DT_DATA_OUT 0x04000000 56653790Sobrien#define SCR_DT_DATA_IN 0x05000000 56753790Sobrien#define SCR_MSG_OUT 0x06000000 56853790Sobrien#define SCR_MSG_IN 0x07000000 56953790Sobrien/* DT phases are illegal for non Ultra3 mode */ 57053790Sobrien#define SCR_ILG_OUT 0x04000000 57153790Sobrien#define SCR_ILG_IN 0x05000000 57253790Sobrien 57353790Sobrien/*----------------------------------------------------------- 57453790Sobrien * 57553790Sobrien * Data transfer via SCSI. 57653790Sobrien * 57753790Sobrien *----------------------------------------------------------- 57853790Sobrien * 57953790Sobrien * MOVE_ABS (LEN) 58053790Sobrien * <<start address>> 58153790Sobrien * 58253790Sobrien * MOVE_IND (LEN) 58353790Sobrien * <<dnad_offset>> 58453790Sobrien * 58553790Sobrien * MOVE_TBL 58653790Sobrien * <<dnad_offset>> 58753790Sobrien * 58853790Sobrien *----------------------------------------------------------- 58953790Sobrien */ 59053790Sobrien 59153790Sobrien#define OPC_MOVE 0x08000000 59253790Sobrien 59353790Sobrien#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) 59453790Sobrien#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) 59553790Sobrien#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) 59653790Sobrien 59753790Sobrien#define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) 59853790Sobrien#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) 59953790Sobrien#define SCR_CHMOV_TBL (0x10000000) 60053790Sobrien 60153790Sobrienstruct sym_tblmove { 60253790Sobrien u32 size; 60353790Sobrien u32 addr; 60453790Sobrien}; 60553790Sobrien 60653790Sobrien/*----------------------------------------------------------- 60753790Sobrien * 60853790Sobrien * Selection 60953790Sobrien * 61053790Sobrien *----------------------------------------------------------- 61153790Sobrien * 61253790Sobrien * SEL_ABS | SCR_ID (0..15) [ | REL_JMP] 61353790Sobrien * <<alternate_address>> 61453790Sobrien * 61553790Sobrien * SEL_TBL | << dnad_offset>> [ | REL_JMP] 61653790Sobrien * <<alternate_address>> 61753790Sobrien * 61853790Sobrien *----------------------------------------------------------- 61953790Sobrien */ 62053790Sobrien 62153790Sobrien#define SCR_SEL_ABS 0x40000000 62253790Sobrien#define SCR_SEL_ABS_ATN 0x41000000 62353790Sobrien#define SCR_SEL_TBL 0x42000000 62453790Sobrien#define SCR_SEL_TBL_ATN 0x43000000 62553790Sobrien 62653790Sobrienstruct sym_tblsel { 62753790Sobrien u_char sel_scntl4; /* C1010 only */ 62853790Sobrien u_char sel_sxfer; 62953790Sobrien u_char sel_id; 63053790Sobrien u_char sel_scntl3; 63153790Sobrien}; 63253790Sobrien 63353790Sobrien#define SCR_JMP_REL 0x04000000 63453790Sobrien#define SCR_ID(id) (((u32)(id)) << 16) 63553790Sobrien 63653790Sobrien/*----------------------------------------------------------- 63753790Sobrien * 63853790Sobrien * Waiting for Disconnect or Reselect 63953790Sobrien * 64053790Sobrien *----------------------------------------------------------- 64153790Sobrien * 64253790Sobrien * WAIT_DISC 64353790Sobrien * dummy: <<alternate_address>> 64453790Sobrien * 64553790Sobrien * WAIT_RESEL 64653790Sobrien * <<alternate_address>> 64753790Sobrien * 64853790Sobrien *----------------------------------------------------------- 64953790Sobrien */ 65053790Sobrien 65153790Sobrien#define SCR_WAIT_DISC 0x48000000 65253790Sobrien#define SCR_WAIT_RESEL 0x50000000 65353790Sobrien 65453790Sobrien/*----------------------------------------------------------- 65553790Sobrien * 65653790Sobrien * Bit Set / Reset 65753790Sobrien * 65853790Sobrien *----------------------------------------------------------- 65953790Sobrien * 66053790Sobrien * SET (flags {|.. }) 66153790Sobrien * 66253790Sobrien * CLR (flags {|.. }) 66353790Sobrien * 66453790Sobrien *----------------------------------------------------------- 66553790Sobrien */ 66653790Sobrien 66753790Sobrien#define SCR_SET(f) (0x58000000 | (f)) 66853790Sobrien#define SCR_CLR(f) (0x60000000 | (f)) 66953790Sobrien 67053790Sobrien#define SCR_CARRY 0x00000400 67153790Sobrien#define SCR_TRG 0x00000200 67253790Sobrien#define SCR_ACK 0x00000040 67353790Sobrien#define SCR_ATN 0x00000008 67453790Sobrien 67553790Sobrien 67653790Sobrien/*----------------------------------------------------------- 67753790Sobrien * 67853790Sobrien * Memory to memory move 67953790Sobrien * 68053790Sobrien *----------------------------------------------------------- 68153790Sobrien * 68253790Sobrien * COPY (bytecount) 68353790Sobrien * << source_address >> 68453790Sobrien * << destination_address >> 68553790Sobrien * 68653790Sobrien * SCR_COPY sets the NO FLUSH option by default. 68753790Sobrien * SCR_COPY_F does not set this option. 68853790Sobrien * 68953790Sobrien * For chips which do not support this option, 69053790Sobrien * sym_copy_and_bind() will remove this bit. 69153790Sobrien * 69253790Sobrien *----------------------------------------------------------- 69353790Sobrien */ 69453790Sobrien 69553790Sobrien#define SCR_NO_FLUSH 0x01000000 69653790Sobrien 69753790Sobrien#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) 69853790Sobrien#define SCR_COPY_F(n) (0xc0000000 | (n)) 69953790Sobrien 70053790Sobrien/*----------------------------------------------------------- 70153790Sobrien * 70253790Sobrien * Register move and binary operations 70353790Sobrien * 70453790Sobrien *----------------------------------------------------------- 70553790Sobrien * 70653790Sobrien * SFBR_REG (reg, op, data) reg = SFBR op data 70753790Sobrien * << 0 >> 70853790Sobrien * 70953790Sobrien * REG_SFBR (reg, op, data) SFBR = reg op data 71053790Sobrien * << 0 >> 71153790Sobrien * 71253790Sobrien * REG_REG (reg, op, data) reg = reg op data 71353790Sobrien * << 0 >> 71453790Sobrien * 71553790Sobrien *----------------------------------------------------------- 71653790Sobrien * 71753790Sobrien * On 825A, 875, 895 and 896 chips the content 71853790Sobrien * of SFBR register can be used as data (SCR_SFBR_DATA). 71953790Sobrien * The 896 has additionnal IO registers starting at 72053790Sobrien * offset 0x80. Bit 7 of register offset is stored in 72153790Sobrien * bit 7 of the SCRIPTS instruction first DWORD. 72253790Sobrien * 72353790Sobrien *----------------------------------------------------------- 72453790Sobrien */ 72553790Sobrien 72653790Sobrien#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80)) 72753790Sobrien 72853790Sobrien#define SCR_SFBR_REG(reg,op,data) \ 72953790Sobrien (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 73053790Sobrien 73153790Sobrien#define SCR_REG_SFBR(reg,op,data) \ 73253790Sobrien (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 73353790Sobrien 73453790Sobrien#define SCR_REG_REG(reg,op,data) \ 73553790Sobrien (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 73653790Sobrien 73753790Sobrien 73853790Sobrien#define SCR_LOAD 0x00000000 73953790Sobrien#define SCR_SHL 0x01000000 74053790Sobrien#define SCR_OR 0x02000000 74153790Sobrien#define SCR_XOR 0x03000000 74253790Sobrien#define SCR_AND 0x04000000 74353790Sobrien#define SCR_SHR 0x05000000 74453790Sobrien#define SCR_ADD 0x06000000 74553790Sobrien#define SCR_ADDC 0x07000000 74653790Sobrien 74753790Sobrien#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ 74853790Sobrien 74953790Sobrien/*----------------------------------------------------------- 75053790Sobrien * 75153790Sobrien * FROM_REG (reg) SFBR = reg 75253790Sobrien * << 0 >> 75353790Sobrien * 75453790Sobrien * TO_REG (reg) reg = SFBR 75553790Sobrien * << 0 >> 75653790Sobrien * 75753790Sobrien * LOAD_REG (reg, data) reg = <data> 75853790Sobrien * << 0 >> 75953790Sobrien * 76053790Sobrien * LOAD_SFBR(data) SFBR = <data> 76153790Sobrien * << 0 >> 76253790Sobrien * 76353790Sobrien *----------------------------------------------------------- 76453790Sobrien */ 76553790Sobrien 76653790Sobrien#define SCR_FROM_REG(reg) \ 76753790Sobrien SCR_REG_SFBR(reg,SCR_OR,0) 76853790Sobrien 76953790Sobrien#define SCR_TO_REG(reg) \ 77053790Sobrien SCR_SFBR_REG(reg,SCR_OR,0) 77153790Sobrien 77253790Sobrien#define SCR_LOAD_REG(reg,data) \ 77353790Sobrien SCR_REG_REG(reg,SCR_LOAD,data) 77453790Sobrien 77553790Sobrien#define SCR_LOAD_SFBR(data) \ 77653790Sobrien (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) 77753790Sobrien 77853790Sobrien/*----------------------------------------------------------- 77953790Sobrien * 78053790Sobrien * LOAD from memory to register. 78153790Sobrien * STORE from register to memory. 78253790Sobrien * 78353790Sobrien * Only supported by 810A, 860, 825A, 875, 895 and 896. 78453790Sobrien * 78553790Sobrien *----------------------------------------------------------- 78653790Sobrien * 78753790Sobrien * LOAD_ABS (LEN) 78853790Sobrien * <<start address>> 78953790Sobrien * 79053790Sobrien * LOAD_REL (LEN) (DSA relative) 79153790Sobrien * <<dsa_offset>> 79253790Sobrien * 79353790Sobrien *----------------------------------------------------------- 79453790Sobrien */ 79553790Sobrien 79653790Sobrien#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) 79753790Sobrien#define SCR_NO_FLUSH2 0x02000000 79853790Sobrien#define SCR_DSA_REL2 0x10000000 79953790Sobrien 80053790Sobrien#define SCR_LOAD_R(reg, how, n) \ 801106696Salfred (0xe1000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n)) 80253790Sobrien 80353790Sobrien#define SCR_STORE_R(reg, how, n) \ 804106696Salfred (0xe0000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n)) 80553790Sobrien 80653790Sobrien#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) 80753790Sobrien#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) 80853790Sobrien#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) 80953790Sobrien#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) 81053790Sobrien 81153790Sobrien#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) 81253790Sobrien#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) 81353790Sobrien#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) 81453790Sobrien#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) 81553790Sobrien 81653790Sobrien 81753790Sobrien/*----------------------------------------------------------- 81853790Sobrien * 81953790Sobrien * Waiting for Disconnect or Reselect 82053790Sobrien * 82153790Sobrien *----------------------------------------------------------- 82253790Sobrien * 82353790Sobrien * JUMP [ | IFTRUE/IFFALSE ( ... ) ] 82453790Sobrien * <<address>> 82553790Sobrien * 82653790Sobrien * JUMPR [ | IFTRUE/IFFALSE ( ... ) ] 82753790Sobrien * <<distance>> 82853790Sobrien * 82953790Sobrien * CALL [ | IFTRUE/IFFALSE ( ... ) ] 83053790Sobrien * <<address>> 83153790Sobrien * 83253790Sobrien * CALLR [ | IFTRUE/IFFALSE ( ... ) ] 83353790Sobrien * <<distance>> 83453790Sobrien * 83553790Sobrien * RETURN [ | IFTRUE/IFFALSE ( ... ) ] 83653790Sobrien * <<dummy>> 83753790Sobrien * 83853790Sobrien * INT [ | IFTRUE/IFFALSE ( ... ) ] 83953790Sobrien * <<ident>> 84053790Sobrien * 84153790Sobrien * INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] 84253790Sobrien * <<ident>> 84353790Sobrien * 84453790Sobrien * Conditions: 84553790Sobrien * WHEN (phase) 84653790Sobrien * IF (phase) 84753790Sobrien * CARRYSET 84853790Sobrien * DATA (data, mask) 84953790Sobrien * 85053790Sobrien *----------------------------------------------------------- 85153790Sobrien */ 85253790Sobrien 85353790Sobrien#define SCR_NO_OP 0x80000000 85453790Sobrien#define SCR_JUMP 0x80080000 85553790Sobrien#define SCR_JUMP64 0x80480000 85653790Sobrien#define SCR_JUMPR 0x80880000 85753790Sobrien#define SCR_CALL 0x88080000 85853790Sobrien#define SCR_CALLR 0x88880000 85953790Sobrien#define SCR_RETURN 0x90080000 86053790Sobrien#define SCR_INT 0x98080000 86153790Sobrien#define SCR_INT_FLY 0x98180000 86253790Sobrien 86353790Sobrien#define IFFALSE(arg) (0x00080000 | (arg)) 86453790Sobrien#define IFTRUE(arg) (0x00000000 | (arg)) 86553790Sobrien 86653790Sobrien#define WHEN(phase) (0x00030000 | (phase)) 86753790Sobrien#define IF(phase) (0x00020000 | (phase)) 86853790Sobrien 86953790Sobrien#define DATA(D) (0x00040000 | ((D) & 0xff)) 87053790Sobrien#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) 87153790Sobrien 87253790Sobrien#define CARRYSET (0x00200000) 87353790Sobrien 87453790Sobrien/*----------------------------------------------------------- 87553790Sobrien * 87653790Sobrien * SCSI constants. 87753790Sobrien * 87853790Sobrien *----------------------------------------------------------- 87953790Sobrien */ 88053790Sobrien 88153790Sobrien/* 88253790Sobrien * Messages 88353790Sobrien */ 88453790Sobrien 88553790Sobrien#define M_COMPLETE (0x00) 88653790Sobrien#define M_EXTENDED (0x01) 88753790Sobrien#define M_SAVE_DP (0x02) 88853790Sobrien#define M_RESTORE_DP (0x03) 88953790Sobrien#define M_DISCONNECT (0x04) 89053790Sobrien#define M_ID_ERROR (0x05) 89153790Sobrien#define M_ABORT (0x06) 89253790Sobrien#define M_REJECT (0x07) 89353790Sobrien#define M_NOOP (0x08) 89453790Sobrien#define M_PARITY (0x09) 89553790Sobrien#define M_LCOMPLETE (0x0a) 89653790Sobrien#define M_FCOMPLETE (0x0b) 89753790Sobrien#define M_RESET (0x0c) 89853790Sobrien#define M_ABORT_TAG (0x0d) 89953790Sobrien#define M_CLEAR_QUEUE (0x0e) 90053790Sobrien#define M_INIT_REC (0x0f) 90153790Sobrien#define M_REL_REC (0x10) 90253790Sobrien#define M_TERMINATE (0x11) 90353790Sobrien#define M_SIMPLE_TAG (0x20) 90453790Sobrien#define M_HEAD_TAG (0x21) 90553790Sobrien#define M_ORDERED_TAG (0x22) 90653790Sobrien#define M_IGN_RESIDUE (0x23) 90753790Sobrien#define M_IDENTIFY (0x80) 90853790Sobrien 90953790Sobrien#define M_X_MODIFY_DP (0x00) 91053790Sobrien#define M_X_SYNC_REQ (0x01) 91153790Sobrien#define M_X_WIDE_REQ (0x03) 91253790Sobrien#define M_X_PPR_REQ (0x04) 91353790Sobrien 91453790Sobrien/* 91553790Sobrien * PPR protocol options 91653790Sobrien */ 91753790Sobrien#define PPR_OPT_IU (0x01) 91853790Sobrien#define PPR_OPT_DT (0x02) 91953790Sobrien#define PPR_OPT_QAS (0x04) 92053790Sobrien#define PPR_OPT_MASK (0x07) 92153790Sobrien 92253790Sobrien/* 92353790Sobrien * Status 92453790Sobrien */ 92553790Sobrien 92653790Sobrien#define S_GOOD (0x00) 92753790Sobrien#define S_CHECK_COND (0x02) 92853790Sobrien#define S_COND_MET (0x04) 92953790Sobrien#define S_BUSY (0x08) 93053790Sobrien#define S_INT (0x10) 93153790Sobrien#define S_INT_COND_MET (0x14) 93253790Sobrien#define S_CONFLICT (0x18) 93353790Sobrien#define S_TERMINATED (0x20) 93453790Sobrien#define S_QUEUE_FULL (0x28) 93553790Sobrien#define S_ILLEGAL (0xff) 93653790Sobrien 93753790Sobrien#endif /* defined SYM_DEFS_H */ 938