if_stereg.h revision 200912
119026Sjulian/*- 267627Sasmodai * Copyright (c) 1997, 1998, 1999 319026Sjulian * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 419026Sjulian * 519026Sjulian * Redistribution and use in source and binary forms, with or without 619026Sjulian * modification, are permitted provided that the following conditions 719026Sjulian * are met: 819026Sjulian * 1. Redistributions of source code must retain the above copyright 919026Sjulian * notice, this list of conditions and the following disclaimer. 1019026Sjulian * 2. Redistributions in binary form must reproduce the above copyright 1119026Sjulian * notice, this list of conditions and the following disclaimer in the 1219026Sjulian * documentation and/or other materials provided with the distribution. 1319026Sjulian * 3. All advertising materials mentioning features or use of this software 1419026Sjulian * must display the following acknowledgement: 1519026Sjulian * This product includes software developed by Bill Paul. 1619026Sjulian * 4. Neither the name of the author nor the names of any co-contributors 1719026Sjulian * may be used to endorse or promote products derived from this software 1819026Sjulian * without specific prior written permission. 1919026Sjulian * 2019026Sjulian * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2119026Sjulian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2219026Sjulian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2319026Sjulian * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2419026Sjulian * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2519026Sjulian * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2660446Sphantom * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27237317Smav * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28204704Smav * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2979538Sru * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 305884Sdg * THE POSSIBILITY OF SUCH DAMAGE. 3140439Sken * 32204704Smav * $FreeBSD: head/sys/dev/ste/if_stereg.h 200912 2009-12-23 19:26:38Z yongari $ 335884Sdg */ 3456467Sasmodai 35204704Smav/* 3656467Sasmodai * Sundance PCI device/vendor ID for the 3756467Sasmodai * ST201 chip. 3856467Sasmodai */ 3956467Sasmodai#define ST_VENDORID 0x13F0 4056467Sasmodai#define ST_DEVICEID_ST201_1 0x0200 4156467Sasmodai#define ST_DEVICEID_ST201_2 0x0201 4270466Sru 4370466Sru/* 4470466Sru * D-Link PCI device/vendor ID for the DL10050[AB] chip 4570466Sru */ 46237317Smav#define DL_VENDORID 0x1186 4770466Sru#define DL_DEVICEID_DL10050 0x1002 4870466Sru 4970466Sru/* 5070466Sru * Register definitions for the Sundance Technologies ST201 PCI 5170466Sru * fast ethernet controller. The register space is 128 bytes long and 525884Sdg * can be accessed using either PCI I/O space or PCI memory mapping. 53204704Smav * There are 32-bit, 16-bit and 8-bit registers. 54204704Smav */ 5540439Sken 5640439Sken#define STE_DMACTL 0x00 5740439Sken#define STE_TX_DMALIST_PTR 0x04 58204704Smav#define STE_TX_DMABURST_THRESH 0x08 59204704Smav#define STE_TX_DMAURG_THRESH 0x09 6040439Sken#define STE_TX_DMAPOLL_PERIOD 0x0A 6140439Sken#define STE_RX_DMASTATUS 0x0C 62204704Smav#define STE_RX_DMALIST_PTR 0x10 63204704Smav#define STE_RX_DMABURST_THRESH 0x14 6457676Ssheldonh#define STE_RX_DMAURG_THRESH 0x15 65204704Smav#define STE_RX_DMAPOLL_PERIOD 0x16 66204704Smav#define STE_COUNTDOWN 0x18 67117011Sru#define STE_DEBUGCTL 0x1A 6840439Sken#define STE_ASICCTL 0x30 69204704Smav#define STE_EEPROM_DATA 0x34 705884Sdg#define STE_EEPROM_CTL 0x36 7140439Sken#define STE_FIFOCTL 0x3A 72204704Smav#define STE_TX_STARTTHRESH 0x3C 7340439Sken#define STE_RX_EARLYTHRESH 0x3E 7440439Sken#define STE_EXT_ROMADDR 0x40 7540439Sken#define STE_EXT_ROMDATA 0x44 76237317Smav#define STE_WAKE_EVENT 0x45 77204704Smav#define STE_TX_STATUS 0x46 78204704Smav#define STE_TX_FRAMEID 0x47 79141846Sru#define STE_ISR_ACK 0x4A 8040439Sken#define STE_IMR 0x4C 81117011Sru#define STE_ISR 0x4E 8240439Sken#define STE_MACCTL0 0x50 8340439Sken#define STE_MACCTL1 0x52 8440439Sken#define STE_PAR0 0x54 85117011Sru#define STE_PAR1 0x56 86204704Smav#define STE_PAR2 0x58 8740439Sken#define STE_MAX_FRAMELEN 0x5A 88117011Sru#define STE_RX_MODE 0x5C 89204704Smav#define STE_TX_RECLAIM_THRESH 0x5D 90204704Smav#define STE_PHYCTL 0x5E 91117011Sru#define STE_MAR0 0x60 9240439Sken#define STE_MAR1 0x62 9340439Sken#define STE_MAR2 0x64 9440439Sken#define STE_MAR3 0x66 9540439Sken 9640439Sken#define STE_STAT_RX_OCTETS_LO 0x68 97117011Sru#define STE_STAT_RX_OCTETS_HI 0x6A 98117011Sru#define STE_STAT_TX_OCTETS_LO 0x6C 9940439Sken#define STE_STAT_TX_OCTETS_HI 0x6E 100117011Sru#define STE_STAT_TX_FRAMES 0x70 101117011Sru#define STE_STAT_RX_FRAMES 0x72 102117011Sru#define STE_STAT_CARRIER_ERR 0x74 103117011Sru#define STE_STAT_LATE_COLLS 0x75 10440439Sken#define STE_STAT_MULTI_COLLS 0x76 10540439Sken#define STE_STAT_SINGLE_COLLS 0x77 106131530Sru#define STE_STAT_TX_DEFER 0x78 107141846Sru#define STE_STAT_RX_LOST 0x79 10840439Sken#define STE_STAT_TX_EXDEFER 0x7A 10940439Sken#define STE_STAT_TX_ABORT 0x7B 11040439Sken#define STE_STAT_TX_BCAST 0x7C 11140439Sken#define STE_STAT_RX_BCAST 0x7D 112117011Sru#define STE_STAT_TX_MCAST 0x7E 113117011Sru#define STE_STAT_RX_MCAST 0x7F 11440439Sken 115141846Sru#define STE_DMACTL_RXDMA_STOPPED 0x00000001 11640439Sken#define STE_DMACTL_TXDMA_CMPREQ 0x00000002 11740439Sken#define STE_DMACTL_TXDMA_STOPPED 0x00000004 11840439Sken#define STE_DMACTL_RXDMA_COMPLETE 0x00000008 11940439Sken#define STE_DMACTL_TXDMA_COMPLETE 0x00000010 12040439Sken#define STE_DMACTL_RXDMA_STALL 0x00000100 12140439Sken#define STE_DMACTL_RXDMA_UNSTALL 0x00000200 122117011Sru#define STE_DMACTL_TXDMA_STALL 0x00000400 123204704Smav#define STE_DMACTL_TXDMA_UNSTALL 0x00000800 124204704Smav#define STE_DMACTL_TXDMA_INPROG 0x00004000 125204704Smav#define STE_DMACTL_DMA_HALTINPROG 0x00008000 12640439Sken#define STE_DMACTL_RXEARLY_ENABLE 0x00020000 12740439Sken#define STE_DMACTL_COUNTDOWN_SPEED 0x00040000 12840439Sken#define STE_DMACTL_COUNTDOWN_MODE 0x00080000 129117011Sru#define STE_DMACTL_MWI_DISABLE 0x00100000 130117011Sru#define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000 13140439Sken#define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000 13240439Sken#define STE_DMACTL_TARGET_ABORT 0x40000000 133117011Sru#define STE_DMACTL_MASTER_ABORT 0x80000000 134117011Sru 13540439Sken/* 136117011Sru * TX DMA burst thresh is the number of 32-byte blocks that 137117011Sru * must be loaded into the TX Fifo before a TXDMA burst request 13840439Sken * will be issued. 13940439Sken */ 14040439Sken#define STE_TXDMABURST_THRESH 0x1F 141141846Sru 142117011Sru/* 14340439Sken * The number of 32-byte blocks in the TX FIFO falls below the 144117011Sru * TX DMA urgent threshold, a TX DMA urgent request will be 145117011Sru * generated. 14640439Sken */ 147117011Sru#define STE_TXDMAURG_THRESH 0x3F 148117011Sru 14940439Sken/* 15040439Sken * Number of 320ns intervals between polls of the TXDMA next 15140439Sken * descriptor pointer (if we're using polling mode). 1526813Sdufault */ 153204704Smav#define STE_TXDMA_POLL_PERIOD 0x7F 1546813Sdufault 155193204Sjmallett#define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF 1566813Sdufault#define STE_RX_DMASTATUS_RXERR 0x00004000 1576813Sdufault#define STE_RX_DMASTATUS_DMADONE 0x00008000 1586813Sdufault#define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000 1596813Sdufault#define STE_RX_DMASTATUS_RUNT 0x00020000 1606813Sdufault#define STE_RX_DMASTATUS_ALIGNERR 0x00040000 1616813Sdufault#define STE_RX_DMASTATUS_CRCERR 0x00080000 1626813Sdufault#define STE_RX_DMASTATUS_GIANT 0x00100000 1636813Sdufault#define STE_RX_DMASTATUS_DRIBBLE 0x00800000 164131026Sscottl#define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000 165131530Sru 166131530Sru/* 167131530Sru * RX DMA burst thresh is the number of 32-byte blocks that 168131026Sscottl * must be present in the RX FIFO before a RXDMA bus master 169131530Sru * request will be issued. 170131530Sru */ 171131026Sscottl#define STE_RXDMABURST_THRESH 0xFF 172131026Sscottl 173131026Sscottl/* 1746813Sdufault * The number of 32-byte blocks in the RX FIFO falls below the 175131530Sru * RX DMA urgent threshold, a RX DMA urgent request will be 176131530Sru * generated. 177131530Sru */ 178131026Sscottl#define STE_RXDMAURG_THRESH 0x1F 179131026Sscottl 180131026Sscottl/* 181131026Sscottl * Number of 320ns intervals between polls of the RXDMA complete 1826813Sdufault * bit in the status field on the current RX descriptor (if we're 183131530Sru * using polling mode). 184131530Sru */ 185131530Sru#define STE_RXDMA_POLL_PERIOD 0x7F 186131026Sscottl 187131026Sscottl#define STE_DEBUGCTL_GPIO0_CTL 0x0001 188131026Sscottl#define STE_DEBUGCTL_GPIO1_CTL 0x0002 189131026Sscottl#define STE_DEBUGCTL_GPIO0_DATA 0x0004 190131026Sscottl#define STE_DEBUGCTL_GPIO1_DATA 0x0008 191131026Sscottl 192131026Sscottl#define STE_ASICCTL_ROMSIZE 0x00000002 193131026Sscottl#define STE_ASICCTL_TX_LARGEPKTS 0x00000004 194131026Sscottl#define STE_ASICCTL_RX_LARGEPKTS 0x00000008 195131530Sru#define STE_ASICCTL_EXTROM_DISABLE 0x00000010 196131530Sru#define STE_ASICCTL_PHYSPEED_10 0x00000020 197131530Sru#define STE_ASICCTL_PHYSPEED_100 0x00000040 198262018Smav#define STE_ASICCTL_PHYMEDIA 0x00000080 199131026Sscottl#define STE_ASICCTL_FORCEDCONFIG 0x00000700 200131026Sscottl#define STE_ASICCTL_D3RESET_DISABLE 0x00000800 201131026Sscottl#define STE_ASICCTL_SPEEDUPMODE 0x00002000 202131026Sscottl#define STE_ASICCTL_LEDMODE 0x00004000 203131026Sscottl#define STE_ASICCTL_RSTOUT_POLARITY 0x00008000 204131026Sscottl#define STE_ASICCTL_GLOBAL_RESET 0x00010000 205131026Sscottl#define STE_ASICCTL_RX_RESET 0x00020000 206131026Sscottl#define STE_ASICCTL_TX_RESET 0x00040000 207131026Sscottl#define STE_ASICCTL_DMA_RESET 0x00080000 208131026Sscottl#define STE_ASICCTL_FIFO_RESET 0x00100000 209204704Smav#define STE_ASICCTL_NETWORK_RESET 0x00200000 210204704Smav#define STE_ASICCTL_HOST_RESET 0x00400000 211204704Smav#define STE_ASICCTL_AUTOINIT_RESET 0x00800000 212131026Sscottl#define STE_ASICCTL_EXTRESET_RESET 0x01000000 213131026Sscottl#define STE_ASICCTL_SOFTINTR 0x02000000 214131026Sscottl#define STE_ASICCTL_RESET_BUSY 0x04000000 215131026Sscottl 2166813Sdufault#define STE_EECTL_ADDR 0x00FF 2176813Sdufault#define STE_EECTL_OPCODE 0x0300 218117011Sru#define STE_EECTL_BUSY 0x1000 219117011Sru 22040439Sken#define STE_EEOPCODE_WRITE 0x0100 2216813Sdufault#define STE_EEOPCODE_READ 0x0200 22240439Sken#define STE_EEOPCODE_ERASE 0x0300 2235884Sdg 2245884Sdg#define STE_FIFOCTL_RAMTESTMODE 0x0001 22557676Ssheldonh#define STE_FIFOCTL_OVERRUNMODE 0x0200 22657676Ssheldonh#define STE_FIFOCTL_RXFIFOFULL 0x0800 22779727Sschweikh#define STE_FIFOCTL_TX_BUSY 0x4000 228204704Smav#define STE_FIFOCTL_RX_BUSY 0x8000 229204704Smav 230204704Smav/* 23157676Ssheldonh * The number of bytes that must in present in the TX FIFO before 23257676Ssheldonh * transmission begins. Value should be in increments of 4 bytes. 23357676Ssheldonh */ 23457676Ssheldonh#define STE_TXSTART_THRESH 0x1FFC 2355884Sdg 2365884Sdg/* 23779727Sschweikh * Number of bytes that must be present in the RX FIFO before 23840439Sken * an RX EARLY interrupt is generated. 2395884Sdg */ 24057676Ssheldonh#define STE_RXEARLY_THRESH 0x1FFC 24157676Ssheldonh 242204704Smav#define STE_WAKEEVENT_WAKEPKT_ENB 0x01 243204704Smav#define STE_WAKEEVENT_MAGICPKT_ENB 0x02 24440439Sken#define STE_WAKEEVENT_LINKEVT_ENB 0x04 24540439Sken#define STE_WAKEEVENT_WAKEPOLARITY 0x08 2465884Sdg#define STE_WAKEEVENT_WAKEPKTEVENT 0x10 247131530Sru#define STE_WAKEEVENT_MAGICPKTEVENT 0x20 248131530Sru#define STE_WAKEEVENT_LINKEVENT 0x40 249131530Sru#define STE_WAKEEVENT_WAKEONLAN_ENB 0x80 2505884Sdg 251237317Smav#define STE_TXSTATUS_RECLAIMERR 0x02 252237317Smav#define STE_TXSTATUS_STATSOFLOW 0x04 253237317Smav#define STE_TXSTATUS_EXCESSCOLLS 0x08 25440439Sken#define STE_TXSTATUS_UNDERRUN 0x10 25540439Sken#define STE_TXSTATUS_TXINTR_REQ 0x40 256237317Smav#define STE_TXSTATUS_TXDONE 0x80 25740439Sken 25840439Sken#define STE_ERR_BITS "\20" \ 259237317Smav "\2RECLAIM\3STSOFLOW" \ 260131530Sru "\4EXCESSCOLLS\5UNDERRUN" \ 26140439Sken "\6INTREQ\7DONE" 26240439Sken 263237317Smav#define STE_ISRACK_INTLATCH 0x0001 26440439Sken#define STE_ISRACK_HOSTERR 0x0002 265237317Smav#define STE_ISRACK_TX_DONE 0x0004 266237317Smav#define STE_ISRACK_MACCTL_FRAME 0x0008 267237317Smav#define STE_ISRACK_RX_DONE 0x0010 26840439Sken#define STE_ISRACK_RX_EARLY 0x0020 26940439Sken#define STE_ISRACK_SOFTINTR 0x0040 270237317Smav#define STE_ISRACK_STATS_OFLOW 0x0080 271237317Smav#define STE_ISRACK_LINKEVENT 0x0100 272237317Smav#define STE_ISRACK_TX_DMADONE 0x0200 273237317Smav#define STE_ISRACK_RX_DMADONE 0x0400 274237317Smav 275237317Smav#define STE_IMR_HOSTERR 0x0002 2765884Sdg#define STE_IMR_TX_DONE 0x0004 27740439Sken#define STE_IMR_MACCTL_FRAME 0x0008 27840439Sken#define STE_IMR_RX_DONE 0x0010 27940439Sken#define STE_IMR_RX_EARLY 0x0020 28040439Sken#define STE_IMR_SOFTINTR 0x0040 281237317Smav#define STE_IMR_STATS_OFLOW 0x0080 282237317Smav#define STE_IMR_LINKEVENT 0x0100 283237317Smav#define STE_IMR_TX_DMADONE 0x0200 284131530Sru#define STE_IMR_RX_DMADONE 0x0400 28540439Sken 286237317Smav#define STE_INTRS \ 28740439Sken (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \ 288237317Smav STE_IMR_TX_DONE|STE_IMR_HOSTERR) 289204704Smav 290204704Smav#define STE_ISR_INTLATCH 0x0001 291237317Smav#define STE_ISR_HOSTERR 0x0002 292237317Smav#define STE_ISR_TX_DONE 0x0004 293237317Smav#define STE_ISR_MACCTL_FRAME 0x0008 294117011Sru#define STE_ISR_RX_DONE 0x0010 29540439Sken#define STE_ISR_RX_EARLY 0x0020 296237317Smav#define STE_ISR_SOFTINTR 0x0040 297237317Smav#define STE_ISR_STATS_OFLOW 0x0080 29840439Sken#define STE_ISR_LINKEVENT 0x0100 299117011Sru#define STE_ISR_TX_DMADONE 0x0200 300117011Sru#define STE_ISR_RX_DMADONE 0x0400 30140439Sken 302117011Sru/* 303117011Sru * Note: the Sundance manual gives the impression that the's 30440439Sken * only one 32-bit MACCTL register. In fact, there are two 305117011Sru * 16-bit registers side by side, and you have to access them 306117011Sru * separately. 30740439Sken */ 30840439Sken#define STE_MACCTL0_IPG 0x0003 309237317Smav#define STE_MACCTL0_FULLDUPLEX 0x0020 31040439Sken#define STE_MACCTL0_RX_GIANTS 0x0040 311237317Smav#define STE_MACCTL0_FLOWCTL_ENABLE 0x0100 312131530Sru#define STE_MACCTL0_RX_FCS 0x0200 31340439Sken#define STE_MACCTL0_FIFOLOOPBK 0x0400 31440439Sken#define STE_MACCTL0_MACLOOPBK 0x0800 3155884Sdg 316204704Smav#define STE_MACCTL1_COLLDETECT 0x0001 31720920Swosch#define STE_MACCTL1_CARRSENSE 0x0002 31820920Swosch#define STE_MACCTL1_TX_BUSY 0x0004 31940439Sken#define STE_MACCTL1_TX_ERROR 0x0008 320204704Smav#define STE_MACCTL1_STATS_ENABLE 0x0020 321204704Smav#define STE_MACCTL1_STATS_DISABLE 0x0040 32220920Swosch#define STE_MACCTL1_STATS_ENABLED 0x0080 32320920Swosch#define STE_MACCTL1_TX_ENABLE 0x0100 32418480Swosch#define STE_MACCTL1_TX_DISABLE 0x0200 32540439Sken#define STE_MACCTL1_TX_ENABLED 0x0400 32640439Sken#define STE_MACCTL1_RX_ENABLE 0x0800 32740439Sken#define STE_MACCTL1_RX_DISABLE 0x1000 32840439Sken#define STE_MACCTL1_RX_ENABLED 0x2000 32940439Sken#define STE_MACCTL1_PAUSED 0x4000 33040439Sken 3315884Sdg#define STE_IPG_96BT 0x00000000 332204704Smav#define STE_IPG_128BT 0x00000001 333204704Smav#define STE_IPG_224BT 0x00000002 33440439Sken#define STE_IPG_544BT 0x00000003 33540439Sken 33640439Sken#define STE_RXMODE_UNICAST 0x01 337204704Smav#define STE_RXMODE_ALLMULTI 0x02 338204704Smav#define STE_RXMODE_BROADCAST 0x04 339204704Smav#define STE_RXMODE_PROMISC 0x08 340204704Smav#define STE_RXMODE_MULTIHASH 0x10 34140439Sken#define STE_RXMODE_ALLIPMULTI 0x20 34269027Sru 343204704Smav#define STE_PHYCTL_MCLK 0x01 344204704Smav#define STE_PHYCTL_MDATA 0x02 34540439Sken#define STE_PHYCTL_MDIR 0x04 34649831Smpp#define STE_PHYCTL_CLK25_DISABLE 0x08 34749831Smpp#define STE_PHYCTL_DUPLEXPOLARITY 0x10 34849831Smpp#define STE_PHYCTL_DUPLEXSTAT 0x20 34949831Smpp#define STE_PHYCTL_SPEEDSTAT 0x40 350204704Smav#define STE_PHYCTL_LINKSTAT 0x80 351204704Smav 352204704Smav/* 353204704Smav * EEPROM offsets. 354204704Smav */ 355#define STE_EEADDR_CONFIGPARM 0x00 356#define STE_EEADDR_ASICCTL 0x02 357#define STE_EEADDR_SUBSYS_ID 0x04 358#define STE_EEADDR_SUBVEN_ID 0x08 359 360#define STE_EEADDR_NODE0 0x10 361#define STE_EEADDR_NODE1 0x12 362#define STE_EEADDR_NODE2 0x14 363 364/* PCI registers */ 365#define STE_PCI_VENDOR_ID 0x00 366#define STE_PCI_DEVICE_ID 0x02 367#define STE_PCI_COMMAND 0x04 368#define STE_PCI_STATUS 0x06 369#define STE_PCI_CLASSCODE 0x09 370#define STE_PCI_LATENCY_TIMER 0x0D 371#define STE_PCI_HEADER_TYPE 0x0E 372#define STE_PCI_LOIO 0x10 373#define STE_PCI_LOMEM 0x14 374#define STE_PCI_BIOSROM 0x30 375#define STE_PCI_INTLINE 0x3C 376#define STE_PCI_INTPIN 0x3D 377#define STE_PCI_MINGNT 0x3E 378#define STE_PCI_MINLAT 0x0F 379 380#define STE_PCI_CAPID 0x50 /* 8 bits */ 381#define STE_PCI_NEXTPTR 0x51 /* 8 bits */ 382#define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 383#define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 384 385#define STE_PSTATE_MASK 0x0003 386#define STE_PSTATE_D0 0x0000 387#define STE_PSTATE_D1 0x0002 388#define STE_PSTATE_D2 0x0002 389#define STE_PSTATE_D3 0x0003 390#define STE_PME_EN 0x0010 391#define STE_PME_STATUS 0x8000 392 393struct ste_hw_stats { 394 uint64_t rx_bytes; 395 uint32_t rx_frames; 396 uint32_t rx_bcast_frames; 397 uint32_t rx_mcast_frames; 398 uint32_t rx_lost_frames; 399 uint64_t tx_bytes; 400 uint32_t tx_frames; 401 uint32_t tx_bcast_frames; 402 uint32_t tx_mcast_frames; 403 uint32_t tx_carrsense_errs; 404 uint32_t tx_single_colls; 405 uint32_t tx_multi_colls; 406 uint32_t tx_late_colls; 407 uint32_t tx_frames_defered; 408 uint32_t tx_excess_defers; 409 uint32_t tx_abort; 410}; 411 412struct ste_frag { 413 uint32_t ste_addr; 414 uint32_t ste_len; 415}; 416 417#define STE_FRAG_LAST 0x80000000 418#define STE_FRAG_LEN 0x00001FFF 419 420/* 421 * A TFD is 16 to 512 bytes in length which means it can have up to 126 422 * fragments for a single Tx frame. Since most frames used in stack have 423 * 3-4 fragments supporting 8 fragments would be enough for normal 424 * operation. If we encounter more than 8 fragments we'll collapse them 425 * into a frame that has less than or equal to 8 fragments. Each buffer 426 * address of a fragment has no alignment limitation. 427 */ 428#define STE_MAXFRAGS 8 429 430struct ste_desc { 431 uint32_t ste_next; 432 uint32_t ste_ctl; 433 struct ste_frag ste_frags[STE_MAXFRAGS]; 434}; 435 436/* 437 * A RFD has the same structure of TFD which in turn means hardware 438 * supports scatter operation in Rx buffer. Since we just allocate Rx 439 * buffer with m_getcl(9) there is no fragmentation at all so use 440 * single fragment for RFD. 441 */ 442struct ste_desc_onefrag { 443 uint32_t ste_next; 444 uint32_t ste_status; 445 struct ste_frag ste_frag; 446}; 447 448#define STE_TXCTL_WORDALIGN 0x00000003 449#define STE_TXCTL_ALIGN_DIS 0x00000001 450#define STE_TXCTL_FRAMEID 0x000003FC 451#define STE_TXCTL_NOCRC 0x00002000 452#define STE_TXCTL_TXINTR 0x00008000 453#define STE_TXCTL_DMADONE 0x00010000 454#define STE_TXCTL_DMAINTR 0x80000000 455 456#define STE_RXSTAT_FRAMELEN 0x00001FFF 457#define STE_RXSTAT_FRAME_ERR 0x00004000 458#define STE_RXSTAT_DMADONE 0x00008000 459#define STE_RXSTAT_FIFO_OFLOW 0x00010000 460#define STE_RXSTAT_RUNT 0x00020000 461#define STE_RXSTAT_ALIGNERR 0x00040000 462#define STE_RXSTAT_CRCERR 0x00080000 463#define STE_RXSTAT_GIANT 0x00100000 464#define STE_RXSTAT_DRIBBLEBITS 0x00800000 465#define STE_RXSTAT_DMA_OFLOW 0x01000000 466#define STE_RXATAT_ONEBUF 0x10000000 467 468#define STE_RX_BYTES(x) ((x) & STE_RXSTAT_FRAMELEN) 469 470/* 471 * register space access macros 472 */ 473#define CSR_WRITE_4(sc, reg, val) \ 474 bus_write_4((sc)->ste_res, reg, val) 475#define CSR_WRITE_2(sc, reg, val) \ 476 bus_write_2((sc)->ste_res, reg, val) 477#define CSR_WRITE_1(sc, reg, val) \ 478 bus_write_1((sc)->ste_res, reg, val) 479 480#define CSR_READ_4(sc, reg) \ 481 bus_read_4((sc)->ste_res, reg) 482#define CSR_READ_2(sc, reg) \ 483 bus_read_2((sc)->ste_res, reg) 484#define CSR_READ_1(sc, reg) \ 485 bus_read_1((sc)->ste_res, reg) 486 487#define STE_DESC_ALIGN 8 488#define STE_RX_LIST_CNT 128 489#define STE_TX_LIST_CNT 128 490#define STE_RX_LIST_SZ \ 491 (sizeof(struct ste_desc_onefrag) * STE_RX_LIST_CNT) 492#define STE_TX_LIST_SZ \ 493 (sizeof(struct ste_desc) * STE_TX_LIST_CNT) 494#define STE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF) 495#define STE_ADDR_HI(x) ((uint64_t)(x) >> 32) 496 497#define STE_TX_TIMEOUT 5 498#define STE_TIMEOUT 1000 499#define STE_MIN_FRAMELEN 60 500#define STE_PACKET_SIZE 1536 501#define STE_INC(x, y) (x) = (x + 1) % y 502#define STE_DEC(x, y) (x) = ((x) + ((y) - 1)) % (y) 503#define STE_NEXT(x, y) (x + 1) % y 504 505struct ste_type { 506 uint16_t ste_vid; 507 uint16_t ste_did; 508 char *ste_name; 509}; 510 511struct ste_list_data { 512 struct ste_desc_onefrag *ste_rx_list; 513 bus_addr_t ste_rx_list_paddr; 514 struct ste_desc *ste_tx_list; 515 bus_addr_t ste_tx_list_paddr; 516}; 517 518struct ste_chain { 519 struct ste_desc *ste_ptr; 520 struct mbuf *ste_mbuf; 521 struct ste_chain *ste_next; 522 uint32_t ste_phys; 523 bus_dmamap_t ste_map; 524}; 525 526struct ste_chain_onefrag { 527 struct ste_desc_onefrag *ste_ptr; 528 struct mbuf *ste_mbuf; 529 struct ste_chain_onefrag *ste_next; 530 bus_dmamap_t ste_map; 531}; 532 533struct ste_chain_data { 534 bus_dma_tag_t ste_parent_tag; 535 bus_dma_tag_t ste_rx_tag; 536 bus_dma_tag_t ste_tx_tag; 537 bus_dma_tag_t ste_rx_list_tag; 538 bus_dmamap_t ste_rx_list_map; 539 bus_dma_tag_t ste_tx_list_tag; 540 bus_dmamap_t ste_tx_list_map; 541 bus_dmamap_t ste_rx_sparemap; 542 struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; 543 struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; 544 struct ste_chain_onefrag *ste_rx_head; 545 struct ste_chain *ste_last_tx; 546 int ste_tx_prod; 547 int ste_tx_cons; 548 int ste_tx_cnt; 549}; 550 551struct ste_softc { 552 struct ifnet *ste_ifp; 553 struct resource *ste_res; 554 int ste_res_id; 555 int ste_res_type; 556 struct resource *ste_irq; 557 void *ste_intrhand; 558 struct ste_type *ste_info; 559 device_t ste_miibus; 560 device_t ste_dev; 561 int ste_tx_thresh; 562 int ste_flags; 563#define STE_FLAG_ONE_PHY 0x0001 564#define STE_FLAG_LINK 0x8000 565 int ste_if_flags; 566 int ste_timer; 567 struct ste_list_data ste_ldata; 568 struct ste_chain_data ste_cdata; 569 struct callout ste_callout; 570 struct ste_hw_stats ste_stats; 571 struct mtx ste_mtx; 572}; 573 574#define STE_LOCK(_sc) mtx_lock(&(_sc)->ste_mtx) 575#define STE_UNLOCK(_sc) mtx_unlock(&(_sc)->ste_mtx) 576#define STE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ste_mtx, MA_OWNED) 577 578struct ste_mii_frame { 579 uint8_t mii_stdelim; 580 uint8_t mii_opcode; 581 uint8_t mii_phyaddr; 582 uint8_t mii_regaddr; 583 uint8_t mii_turnaround; 584 uint16_t mii_data; 585}; 586 587/* 588 * MII constants 589 */ 590#define STE_MII_STARTDELIM 0x01 591#define STE_MII_READOP 0x02 592#define STE_MII_WRITEOP 0x01 593#define STE_MII_TURNAROUND 0x02 594