if_stereg.h revision 200803
1139825Simp/*- 250128Swpaul * Copyright (c) 1997, 1998, 1999 350128Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 450128Swpaul * 550128Swpaul * Redistribution and use in source and binary forms, with or without 650128Swpaul * modification, are permitted provided that the following conditions 750128Swpaul * are met: 850128Swpaul * 1. Redistributions of source code must retain the above copyright 950128Swpaul * notice, this list of conditions and the following disclaimer. 1050128Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1150128Swpaul * notice, this list of conditions and the following disclaimer in the 1250128Swpaul * documentation and/or other materials provided with the distribution. 1350128Swpaul * 3. All advertising materials mentioning features or use of this software 1450128Swpaul * must display the following acknowledgement: 1550128Swpaul * This product includes software developed by Bill Paul. 1650128Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1750128Swpaul * may be used to endorse or promote products derived from this software 1850128Swpaul * without specific prior written permission. 1950128Swpaul * 2050128Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2150128Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250128Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350128Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2450128Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2550128Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2650128Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2750128Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2850128Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2950128Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050128Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3150128Swpaul * 3250477Speter * $FreeBSD: head/sys/dev/ste/if_stereg.h 200803 2009-12-21 20:00:27Z yongari $ 3350128Swpaul */ 3450128Swpaul 3550128Swpaul/* 3650128Swpaul * Sundance PCI device/vendor ID for the 3750128Swpaul * ST201 chip. 3850128Swpaul */ 3950128Swpaul#define ST_VENDORID 0x13F0 40167407Syongari#define ST_DEVICEID_ST201_1 0x0200 41167407Syongari#define ST_DEVICEID_ST201_2 0x0201 4250128Swpaul 4350128Swpaul/* 44108237Sphk * D-Link PCI device/vendor ID for the DL10050[AB] chip 4550128Swpaul */ 4650128Swpaul#define DL_VENDORID 0x1186 47108237Sphk#define DL_DEVICEID_DL10050 0x1002 4850128Swpaul 4950128Swpaul/* 5050128Swpaul * Register definitions for the Sundance Technologies ST201 PCI 5150128Swpaul * fast ethernet controller. The register space is 128 bytes long and 5250128Swpaul * can be accessed using either PCI I/O space or PCI memory mapping. 5350128Swpaul * There are 32-bit, 16-bit and 8-bit registers. 5450128Swpaul */ 5550128Swpaul 5650128Swpaul#define STE_DMACTL 0x00 5750128Swpaul#define STE_TX_DMALIST_PTR 0x04 5850128Swpaul#define STE_TX_DMABURST_THRESH 0x08 5950128Swpaul#define STE_TX_DMAURG_THRESH 0x09 6050128Swpaul#define STE_TX_DMAPOLL_PERIOD 0x0A 6150128Swpaul#define STE_RX_DMASTATUS 0x0C 6250128Swpaul#define STE_RX_DMALIST_PTR 0x10 6350128Swpaul#define STE_RX_DMABURST_THRESH 0x14 6450128Swpaul#define STE_RX_DMAURG_THRESH 0x15 6550128Swpaul#define STE_RX_DMAPOLL_PERIOD 0x16 6650128Swpaul#define STE_DEBUGCTL 0x1A 6750128Swpaul#define STE_ASICCTL 0x30 6850128Swpaul#define STE_EEPROM_DATA 0x34 6950128Swpaul#define STE_EEPROM_CTL 0x36 7050128Swpaul#define STE_FIFOCTL 0x3A 7150128Swpaul#define STE_TX_STARTTHRESH 0x3C 7250128Swpaul#define STE_RX_EARLYTHRESH 0x3E 7350128Swpaul#define STE_EXT_ROMADDR 0x40 7450128Swpaul#define STE_EXT_ROMDATA 0x44 7550128Swpaul#define STE_WAKE_EVENT 0x45 7650128Swpaul#define STE_TX_STATUS 0x46 7750128Swpaul#define STE_TX_FRAMEID 0x47 7850128Swpaul#define STE_COUNTDOWN 0x48 7950128Swpaul#define STE_ISR_ACK 0x4A 8050128Swpaul#define STE_IMR 0x4C 8150128Swpaul#define STE_ISR 0x4E 8250128Swpaul#define STE_MACCTL0 0x50 8350128Swpaul#define STE_MACCTL1 0x52 8450128Swpaul#define STE_PAR0 0x54 8550128Swpaul#define STE_PAR1 0x56 8650128Swpaul#define STE_PAR2 0x58 8750128Swpaul#define STE_MAX_FRAMELEN 0x5A 8850128Swpaul#define STE_RX_MODE 0x5C 8950128Swpaul#define STE_TX_RECLAIM_THRESH 0x5D 9050128Swpaul#define STE_PHYCTL 0x5E 9150128Swpaul#define STE_MAR0 0x60 9282214Swpaul#define STE_MAR1 0x62 9382214Swpaul#define STE_MAR2 0x64 9482214Swpaul#define STE_MAR3 0x66 9550128Swpaul#define STE_STATS 0x68 9650128Swpaul 97101493Sambrisko#define STE_LATE_COLLS 0x75 98101493Sambrisko#define STE_MULTI_COLLS 0x76 99101493Sambrisko#define STE_SINGLE_COLLS 0x77 100101493Sambrisko 10150128Swpaul#define STE_DMACTL_RXDMA_STOPPED 0x00000001 10250128Swpaul#define STE_DMACTL_TXDMA_CMPREQ 0x00000002 10350128Swpaul#define STE_DMACTL_TXDMA_STOPPED 0x00000004 10450128Swpaul#define STE_DMACTL_RXDMA_COMPLETE 0x00000008 10550128Swpaul#define STE_DMACTL_TXDMA_COMPLETE 0x00000010 10650128Swpaul#define STE_DMACTL_RXDMA_STALL 0x00000100 10750128Swpaul#define STE_DMACTL_RXDMA_UNSTALL 0x00000200 10850128Swpaul#define STE_DMACTL_TXDMA_STALL 0x00000400 10950128Swpaul#define STE_DMACTL_TXDMA_UNSTALL 0x00000800 11050128Swpaul#define STE_DMACTL_TXDMA_INPROG 0x00004000 11150128Swpaul#define STE_DMACTL_DMA_HALTINPROG 0x00008000 11250128Swpaul#define STE_DMACTL_RXEARLY_ENABLE 0x00020000 11350128Swpaul#define STE_DMACTL_COUNTDOWN_SPEED 0x00040000 11450128Swpaul#define STE_DMACTL_COUNTDOWN_MODE 0x00080000 11550128Swpaul#define STE_DMACTL_MWI_DISABLE 0x00100000 11650128Swpaul#define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000 11750128Swpaul#define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000 11850128Swpaul#define STE_DMACTL_TARGET_ABORT 0x40000000 11950128Swpaul#define STE_DMACTL_MASTER_ABORT 0x80000000 12050128Swpaul 12150128Swpaul/* 12250128Swpaul * TX DMA burst thresh is the number of 32-byte blocks that 12350128Swpaul * must be loaded into the TX Fifo before a TXDMA burst request 12450128Swpaul * will be issued. 12550128Swpaul */ 12650128Swpaul#define STE_TXDMABURST_THRESH 0x1F 12750128Swpaul 12850128Swpaul/* 12950128Swpaul * The number of 32-byte blocks in the TX FIFO falls below the 13050128Swpaul * TX DMA urgent threshold, a TX DMA urgent request will be 13150128Swpaul * generated. 13250128Swpaul */ 13350128Swpaul#define STE_TXDMAURG_THRESH 0x3F 13450128Swpaul 13550128Swpaul/* 13650128Swpaul * Number of 320ns intervals between polls of the TXDMA next 13750128Swpaul * descriptor pointer (if we're using polling mode). 13850128Swpaul */ 13950128Swpaul#define STE_TXDMA_POLL_PERIOD 0x7F 14050128Swpaul 14150128Swpaul#define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF 14250128Swpaul#define STE_RX_DMASTATUS_RXERR 0x00004000 14350128Swpaul#define STE_RX_DMASTATUS_DMADONE 0x00008000 14450128Swpaul#define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000 14550128Swpaul#define STE_RX_DMASTATUS_RUNT 0x00020000 14650128Swpaul#define STE_RX_DMASTATUS_ALIGNERR 0x00040000 14750128Swpaul#define STE_RX_DMASTATUS_CRCERR 0x00080000 14850128Swpaul#define STE_RX_DMASTATUS_GIANT 0x00100000 14950128Swpaul#define STE_RX_DMASTATUS_DRIBBLE 0x00800000 15050128Swpaul#define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000 15150128Swpaul 15250128Swpaul/* 15350128Swpaul * RX DMA burst thresh is the number of 32-byte blocks that 15450128Swpaul * must be present in the RX FIFO before a RXDMA bus master 15550128Swpaul * request will be issued. 15650128Swpaul */ 15750128Swpaul#define STE_RXDMABURST_THRESH 0xFF 15850128Swpaul 15950128Swpaul/* 16050128Swpaul * The number of 32-byte blocks in the RX FIFO falls below the 16150128Swpaul * RX DMA urgent threshold, a RX DMA urgent request will be 16250128Swpaul * generated. 16350128Swpaul */ 16450128Swpaul#define STE_RXDMAURG_THRESH 0x1F 16550128Swpaul 16650128Swpaul/* 16750128Swpaul * Number of 320ns intervals between polls of the RXDMA complete 16850128Swpaul * bit in the status field on the current RX descriptor (if we're 16950128Swpaul * using polling mode). 17050128Swpaul */ 17150128Swpaul#define STE_RXDMA_POLL_PERIOD 0x7F 17250128Swpaul 17350128Swpaul#define STE_DEBUGCTL_GPIO0_CTL 0x0001 17450128Swpaul#define STE_DEBUGCTL_GPIO1_CTL 0x0002 17550128Swpaul#define STE_DEBUGCTL_GPIO0_DATA 0x0004 17650128Swpaul#define STE_DEBUGCTL_GPIO1_DATA 0x0008 17750128Swpaul 17850128Swpaul#define STE_ASICCTL_ROMSIZE 0x00000002 17950128Swpaul#define STE_ASICCTL_TX_LARGEPKTS 0x00000004 18050128Swpaul#define STE_ASICCTL_RX_LARGEPKTS 0x00000008 18150128Swpaul#define STE_ASICCTL_EXTROM_DISABLE 0x00000010 18250128Swpaul#define STE_ASICCTL_PHYSPEED_10 0x00000020 18350128Swpaul#define STE_ASICCTL_PHYSPEED_100 0x00000040 18450128Swpaul#define STE_ASICCTL_PHYMEDIA 0x00000080 18550128Swpaul#define STE_ASICCTL_FORCEDCONFIG 0x00000700 18650128Swpaul#define STE_ASICCTL_D3RESET_DISABLE 0x00000800 18750128Swpaul#define STE_ASICCTL_SPEEDUPMODE 0x00002000 18850128Swpaul#define STE_ASICCTL_LEDMODE 0x00004000 18950128Swpaul#define STE_ASICCTL_RSTOUT_POLARITY 0x00008000 19050128Swpaul#define STE_ASICCTL_GLOBAL_RESET 0x00010000 19150128Swpaul#define STE_ASICCTL_RX_RESET 0x00020000 19250128Swpaul#define STE_ASICCTL_TX_RESET 0x00040000 19350128Swpaul#define STE_ASICCTL_DMA_RESET 0x00080000 19450128Swpaul#define STE_ASICCTL_FIFO_RESET 0x00100000 19550128Swpaul#define STE_ASICCTL_NETWORK_RESET 0x00200000 19650128Swpaul#define STE_ASICCTL_HOST_RESET 0x00400000 19750128Swpaul#define STE_ASICCTL_AUTOINIT_RESET 0x00800000 19850128Swpaul#define STE_ASICCTL_EXTRESET_RESET 0x01000000 19950128Swpaul#define STE_ASICCTL_SOFTINTR 0x02000000 20050128Swpaul#define STE_ASICCTL_RESET_BUSY 0x04000000 20150128Swpaul 20250128Swpaul#define STE_ASICCTL1_GLOBAL_RESET 0x0001 20350128Swpaul#define STE_ASICCTL1_RX_RESET 0x0002 20450128Swpaul#define STE_ASICCTL1_TX_RESET 0x0004 20550128Swpaul#define STE_ASICCTL1_DMA_RESET 0x0008 20650128Swpaul#define STE_ASICCTL1_FIFO_RESET 0x0010 20750128Swpaul#define STE_ASICCTL1_NETWORK_RESET 0x0020 20850128Swpaul#define STE_ASICCTL1_HOST_RESET 0x0040 20950128Swpaul#define STE_ASICCTL1_AUTOINIT_RESET 0x0080 21050128Swpaul#define STE_ASICCTL1_EXTRESET_RESET 0x0100 21150128Swpaul#define STE_ASICCTL1_SOFTINTR 0x0200 21250128Swpaul#define STE_ASICCTL1_RESET_BUSY 0x0400 21350128Swpaul 21450128Swpaul#define STE_EECTL_ADDR 0x00FF 21550128Swpaul#define STE_EECTL_OPCODE 0x0300 21650128Swpaul#define STE_EECTL_BUSY 0x1000 21750128Swpaul 21850128Swpaul#define STE_EEOPCODE_WRITE 0x0100 21950128Swpaul#define STE_EEOPCODE_READ 0x0200 22050128Swpaul#define STE_EEOPCODE_ERASE 0x0300 22150128Swpaul 22250128Swpaul#define STE_FIFOCTL_RAMTESTMODE 0x0001 22350128Swpaul#define STE_FIFOCTL_OVERRUNMODE 0x0200 22450128Swpaul#define STE_FIFOCTL_RXFIFOFULL 0x0800 22550128Swpaul#define STE_FIFOCTL_TX_BUSY 0x4000 22650128Swpaul#define STE_FIFOCTL_RX_BUSY 0x8000 22750128Swpaul 22850128Swpaul/* 22950128Swpaul * The number of bytes that must in present in the TX FIFO before 23050128Swpaul * transmission begins. Value should be in increments of 4 bytes. 23150128Swpaul */ 232101493Sambrisko#define STE_TXSTART_THRESH 0x1FFC 23350128Swpaul 23450128Swpaul/* 23550128Swpaul * Number of bytes that must be present in the RX FIFO before 23650128Swpaul * an RX EARLY interrupt is generated. 23750128Swpaul */ 238101493Sambrisko#define STE_RXEARLY_THRESH 0x1FFC 23950128Swpaul 24050128Swpaul#define STE_WAKEEVENT_WAKEPKT_ENB 0x01 24150128Swpaul#define STE_WAKEEVENT_MAGICPKT_ENB 0x02 24250128Swpaul#define STE_WAKEEVENT_LINKEVT_ENB 0x04 24350128Swpaul#define STE_WAKEEVENT_WAKEPOLARITY 0x08 24450128Swpaul#define STE_WAKEEVENT_WAKEPKTEVENT 0x10 24550128Swpaul#define STE_WAKEEVENT_MAGICPKTEVENT 0x20 24650128Swpaul#define STE_WAKEEVENT_LINKEVENT 0x40 24750128Swpaul#define STE_WAKEEVENT_WAKEONLAN_ENB 0x80 24850128Swpaul 24950128Swpaul#define STE_TXSTATUS_RECLAIMERR 0x02 25050128Swpaul#define STE_TXSTATUS_STATSOFLOW 0x04 25150128Swpaul#define STE_TXSTATUS_EXCESSCOLLS 0x08 25250128Swpaul#define STE_TXSTATUS_UNDERRUN 0x10 25350128Swpaul#define STE_TXSTATUS_TXINTR_REQ 0x40 25450128Swpaul#define STE_TXSTATUS_TXDONE 0x80 25550128Swpaul 25650128Swpaul#define STE_ISRACK_INTLATCH 0x0001 25750128Swpaul#define STE_ISRACK_HOSTERR 0x0002 25850128Swpaul#define STE_ISRACK_TX_DONE 0x0004 25950128Swpaul#define STE_ISRACK_MACCTL_FRAME 0x0008 26050128Swpaul#define STE_ISRACK_RX_DONE 0x0010 26150128Swpaul#define STE_ISRACK_RX_EARLY 0x0020 26250128Swpaul#define STE_ISRACK_SOFTINTR 0x0040 26350128Swpaul#define STE_ISRACK_STATS_OFLOW 0x0080 26450128Swpaul#define STE_ISRACK_LINKEVENT 0x0100 26550128Swpaul#define STE_ISRACK_TX_DMADONE 0x0200 26650128Swpaul#define STE_ISRACK_RX_DMADONE 0x0400 26750128Swpaul 26850128Swpaul#define STE_IMR_HOSTERR 0x0002 26950128Swpaul#define STE_IMR_TX_DONE 0x0004 27050128Swpaul#define STE_IMR_MACCTL_FRAME 0x0008 27150128Swpaul#define STE_IMR_RX_DONE 0x0010 27250128Swpaul#define STE_IMR_RX_EARLY 0x0020 27350128Swpaul#define STE_IMR_SOFTINTR 0x0040 27450128Swpaul#define STE_IMR_STATS_OFLOW 0x0080 27550128Swpaul#define STE_IMR_LINKEVENT 0x0100 27650128Swpaul#define STE_IMR_TX_DMADONE 0x0200 27750128Swpaul#define STE_IMR_RX_DMADONE 0x0400 27850128Swpaul 27950128Swpaul#define STE_INTRS \ 280101493Sambrisko (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \ 281101493Sambrisko STE_IMR_TX_DONE|STE_IMR_HOSTERR| \ 282101493Sambrisko STE_IMR_LINKEVENT) 28350128Swpaul 28450128Swpaul#define STE_ISR_INTLATCH 0x0001 28550128Swpaul#define STE_ISR_HOSTERR 0x0002 28650128Swpaul#define STE_ISR_TX_DONE 0x0004 28750128Swpaul#define STE_ISR_MACCTL_FRAME 0x0008 28850128Swpaul#define STE_ISR_RX_DONE 0x0010 28950128Swpaul#define STE_ISR_RX_EARLY 0x0020 29050128Swpaul#define STE_ISR_SOFTINTR 0x0040 29150128Swpaul#define STE_ISR_STATS_OFLOW 0x0080 29250128Swpaul#define STE_ISR_LINKEVENT 0x0100 29350128Swpaul#define STE_ISR_TX_DMADONE 0x0200 29450128Swpaul#define STE_ISR_RX_DMADONE 0x0400 29550128Swpaul 29650128Swpaul/* 29750128Swpaul * Note: the Sundance manual gives the impression that the's 29850128Swpaul * only one 32-bit MACCTL register. In fact, there are two 29950128Swpaul * 16-bit registers side by side, and you have to access them 30050128Swpaul * separately. 30150128Swpaul */ 30250128Swpaul#define STE_MACCTL0_IPG 0x0003 30350128Swpaul#define STE_MACCTL0_FULLDUPLEX 0x0020 30450128Swpaul#define STE_MACCTL0_RX_GIANTS 0x0040 30550128Swpaul#define STE_MACCTL0_FLOWCTL_ENABLE 0x0100 30650128Swpaul#define STE_MACCTL0_RX_FCS 0x0200 30750128Swpaul#define STE_MACCTL0_FIFOLOOPBK 0x0400 30850128Swpaul#define STE_MACCTL0_MACLOOPBK 0x0800 30950128Swpaul 31050128Swpaul#define STE_MACCTL1_COLLDETECT 0x0001 31150128Swpaul#define STE_MACCTL1_CARRSENSE 0x0002 31250128Swpaul#define STE_MACCTL1_TX_BUSY 0x0004 31350128Swpaul#define STE_MACCTL1_TX_ERROR 0x0008 31450128Swpaul#define STE_MACCTL1_STATS_ENABLE 0x0020 31550128Swpaul#define STE_MACCTL1_STATS_DISABLE 0x0040 31650128Swpaul#define STE_MACCTL1_STATS_ENABLED 0x0080 31750128Swpaul#define STE_MACCTL1_TX_ENABLE 0x0100 31850128Swpaul#define STE_MACCTL1_TX_DISABLE 0x0200 31950128Swpaul#define STE_MACCTL1_TX_ENABLED 0x0400 32050128Swpaul#define STE_MACCTL1_RX_ENABLE 0x0800 32150128Swpaul#define STE_MACCTL1_RX_DISABLE 0x1000 32250128Swpaul#define STE_MACCTL1_RX_ENABLED 0x2000 32350128Swpaul#define STE_MACCTL1_PAUSED 0x4000 32450128Swpaul 32550128Swpaul#define STE_IPG_96BT 0x00000000 32650128Swpaul#define STE_IPG_128BT 0x00000001 32750128Swpaul#define STE_IPG_224BT 0x00000002 32850128Swpaul#define STE_IPG_544BT 0x00000003 32950128Swpaul 33050128Swpaul#define STE_RXMODE_UNICAST 0x01 33150128Swpaul#define STE_RXMODE_ALLMULTI 0x02 33250128Swpaul#define STE_RXMODE_BROADCAST 0x04 33350128Swpaul#define STE_RXMODE_PROMISC 0x08 33450128Swpaul#define STE_RXMODE_MULTIHASH 0x10 33550128Swpaul#define STE_RXMODE_ALLIPMULTI 0x20 33650128Swpaul 33750128Swpaul#define STE_PHYCTL_MCLK 0x01 33850128Swpaul#define STE_PHYCTL_MDATA 0x02 33950128Swpaul#define STE_PHYCTL_MDIR 0x04 34050128Swpaul#define STE_PHYCTL_CLK25_DISABLE 0x08 34150128Swpaul#define STE_PHYCTL_DUPLEXPOLARITY 0x10 34250128Swpaul#define STE_PHYCTL_DUPLEXSTAT 0x20 34350128Swpaul#define STE_PHYCTL_SPEEDSTAT 0x40 34450128Swpaul#define STE_PHYCTL_LINKSTAT 0x80 34550128Swpaul 34650128Swpaul/* 34750128Swpaul * EEPROM offsets. 34850128Swpaul */ 34950128Swpaul#define STE_EEADDR_CONFIGPARM 0x00 35050128Swpaul#define STE_EEADDR_ASICCTL 0x02 35150128Swpaul#define STE_EEADDR_SUBSYS_ID 0x04 35250128Swpaul#define STE_EEADDR_SUBVEN_ID 0x08 35350128Swpaul 35450128Swpaul#define STE_EEADDR_NODE0 0x10 35550128Swpaul#define STE_EEADDR_NODE1 0x12 35650128Swpaul#define STE_EEADDR_NODE2 0x14 35750128Swpaul 35850128Swpaul/* PCI registers */ 35950128Swpaul#define STE_PCI_VENDOR_ID 0x00 36050128Swpaul#define STE_PCI_DEVICE_ID 0x02 36150128Swpaul#define STE_PCI_COMMAND 0x04 36250128Swpaul#define STE_PCI_STATUS 0x06 36350128Swpaul#define STE_PCI_CLASSCODE 0x09 36450128Swpaul#define STE_PCI_LATENCY_TIMER 0x0D 36550128Swpaul#define STE_PCI_HEADER_TYPE 0x0E 36650128Swpaul#define STE_PCI_LOIO 0x10 36750128Swpaul#define STE_PCI_LOMEM 0x14 36850128Swpaul#define STE_PCI_BIOSROM 0x30 36950128Swpaul#define STE_PCI_INTLINE 0x3C 37050128Swpaul#define STE_PCI_INTPIN 0x3D 37150128Swpaul#define STE_PCI_MINGNT 0x3E 37250128Swpaul#define STE_PCI_MINLAT 0x0F 37350128Swpaul 37450128Swpaul#define STE_PCI_CAPID 0x50 /* 8 bits */ 37550128Swpaul#define STE_PCI_NEXTPTR 0x51 /* 8 bits */ 37650128Swpaul#define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 37750128Swpaul#define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 37850128Swpaul 37950128Swpaul#define STE_PSTATE_MASK 0x0003 38050128Swpaul#define STE_PSTATE_D0 0x0000 38150128Swpaul#define STE_PSTATE_D1 0x0002 38250128Swpaul#define STE_PSTATE_D2 0x0002 38350128Swpaul#define STE_PSTATE_D3 0x0003 38450128Swpaul#define STE_PME_EN 0x0010 38550128Swpaul#define STE_PME_STATUS 0x8000 38650128Swpaul 38750128Swpaul 38850128Swpaulstruct ste_stats { 389200803Syongari uint32_t ste_rx_bytes; 390200803Syongari uint32_t ste_tx_bytes; 391200803Syongari uint16_t ste_tx_frames; 392200803Syongari uint16_t ste_rx_frames; 393200803Syongari uint8_t ste_carrsense_errs; 394200803Syongari uint8_t ste_late_colls; 395200803Syongari uint8_t ste_multi_colls; 396200803Syongari uint8_t ste_single_colls; 397200803Syongari uint8_t ste_tx_frames_defered; 398200803Syongari uint8_t ste_rx_lost_frames; 399200803Syongari uint8_t ste_tx_excess_defers; 400200803Syongari uint8_t ste_tx_abort_excess_colls; 401200803Syongari uint8_t ste_tx_bcast_frames; 402200803Syongari uint8_t ste_rx_bcast_frames; 403200803Syongari uint8_t ste_tx_mcast_frames; 404200803Syongari uint8_t ste_rx_mcast_frames; 40550128Swpaul}; 40650128Swpaul 40750128Swpaulstruct ste_frag { 408200803Syongari uint32_t ste_addr; 409200803Syongari uint32_t ste_len; 41050128Swpaul}; 41150128Swpaul 41250128Swpaul#define STE_FRAG_LAST 0x80000000 41350128Swpaul#define STE_FRAG_LEN 0x00001FFF 41450128Swpaul 415101493Sambrisko#define STE_MAXFRAGS 8 41650128Swpaul 41750128Swpaulstruct ste_desc { 418200803Syongari uint32_t ste_next; 419200803Syongari uint32_t ste_ctl; 42050128Swpaul struct ste_frag ste_frags[STE_MAXFRAGS]; 42150128Swpaul}; 42250128Swpaul 42350128Swpaulstruct ste_desc_onefrag { 424200803Syongari uint32_t ste_next; 425200803Syongari uint32_t ste_status; 42650128Swpaul struct ste_frag ste_frag; 42750128Swpaul}; 42850128Swpaul 42950128Swpaul#define STE_TXCTL_WORDALIGN 0x00000003 43050128Swpaul#define STE_TXCTL_FRAMEID 0x000003FC 43150128Swpaul#define STE_TXCTL_NOCRC 0x00002000 43250128Swpaul#define STE_TXCTL_TXINTR 0x00008000 43350128Swpaul#define STE_TXCTL_DMADONE 0x00010000 43450128Swpaul#define STE_TXCTL_DMAINTR 0x80000000 43550128Swpaul 43650128Swpaul#define STE_RXSTAT_FRAMELEN 0x00001FFF 43750128Swpaul#define STE_RXSTAT_FRAME_ERR 0x00004000 43850128Swpaul#define STE_RXSTAT_DMADONE 0x00008000 43950128Swpaul#define STE_RXSTAT_FIFO_OFLOW 0x00010000 44050128Swpaul#define STE_RXSTAT_RUNT 0x00020000 44150128Swpaul#define STE_RXSTAT_ALIGNERR 0x00040000 44250128Swpaul#define STE_RXSTAT_CRCERR 0x00080000 44350128Swpaul#define STE_RXSTAT_GIANT 0x00100000 44450128Swpaul#define STE_RXSTAT_DRIBBLEBITS 0x00800000 44550128Swpaul#define STE_RXSTAT_DMA_OFLOW 0x01000000 44650128Swpaul#define STE_RXATAT_ONEBUF 0x10000000 44750128Swpaul 44850128Swpaul/* 44950128Swpaul * register space access macros 45050128Swpaul */ 45150128Swpaul#define CSR_WRITE_4(sc, reg, val) \ 45250128Swpaul bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val) 45350128Swpaul#define CSR_WRITE_2(sc, reg, val) \ 45450128Swpaul bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val) 45550128Swpaul#define CSR_WRITE_1(sc, reg, val) \ 45650128Swpaul bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val) 45750128Swpaul 45850128Swpaul#define CSR_READ_4(sc, reg) \ 45950128Swpaul bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg) 46050128Swpaul#define CSR_READ_2(sc, reg) \ 46150128Swpaul bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg) 46250128Swpaul#define CSR_READ_1(sc, reg) \ 46350128Swpaul bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg) 46450128Swpaul 46554268Swpaul#define STE_TIMEOUT 1000 46654268Swpaul#define STE_MIN_FRAMELEN 60 46754268Swpaul#define STE_PACKET_SIZE 1536 46854268Swpaul#define ETHER_ALIGN 2 469101493Sambrisko#define STE_RX_LIST_CNT 64 470127937Sru#define STE_TX_LIST_CNT 128 47154268Swpaul#define STE_INC(x, y) (x) = (x + 1) % y 472101493Sambrisko#define STE_NEXT(x, y) (x + 1) % y 47350128Swpaul 47450128Swpaulstruct ste_type { 475200803Syongari uint16_t ste_vid; 476200803Syongari uint16_t ste_did; 47750128Swpaul char *ste_name; 47850128Swpaul}; 47950128Swpaul 48050128Swpaulstruct ste_list_data { 48150128Swpaul struct ste_desc_onefrag ste_rx_list[STE_RX_LIST_CNT]; 48250128Swpaul struct ste_desc ste_tx_list[STE_TX_LIST_CNT]; 48350128Swpaul}; 48450128Swpaul 48550128Swpaulstruct ste_chain { 48650128Swpaul struct ste_desc *ste_ptr; 48750128Swpaul struct mbuf *ste_mbuf; 48850128Swpaul struct ste_chain *ste_next; 489200803Syongari uint32_t ste_phys; 49050128Swpaul}; 49150128Swpaul 49250128Swpaulstruct ste_chain_onefrag { 49350128Swpaul struct ste_desc_onefrag *ste_ptr; 49450128Swpaul struct mbuf *ste_mbuf; 49550128Swpaul struct ste_chain_onefrag *ste_next; 49650128Swpaul}; 49750128Swpaul 49850128Swpaulstruct ste_chain_data { 49950128Swpaul struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; 50050128Swpaul struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; 50150128Swpaul struct ste_chain_onefrag *ste_rx_head; 50250128Swpaul 50354268Swpaul int ste_tx_prod; 50454268Swpaul int ste_tx_cons; 50550128Swpaul}; 50650128Swpaul 50750128Swpaulstruct ste_softc { 508147256Sbrooks struct ifnet *ste_ifp; 50950128Swpaul bus_space_tag_t ste_btag; 51050128Swpaul bus_space_handle_t ste_bhandle; 51150128Swpaul struct resource *ste_res; 51250128Swpaul struct resource *ste_irq; 51350128Swpaul void *ste_intrhand; 51450128Swpaul struct ste_type *ste_info; 51550128Swpaul device_t ste_miibus; 516101493Sambrisko device_t ste_dev; 51750128Swpaul int ste_tx_thresh; 518200803Syongari uint8_t ste_link; 51954268Swpaul int ste_if_flags; 520199559Sjhb int ste_timer; 521127775Sru struct ste_chain *ste_tx_prev; 52250128Swpaul struct ste_list_data *ste_ldata; 52350128Swpaul struct ste_chain_data ste_cdata; 524149646Sjhb struct callout ste_stat_callout; 52567089Swpaul struct mtx ste_mtx; 526200803Syongari uint8_t ste_one_phy; 527127686Sru#ifdef DEVICE_POLLING 528127686Sru int rxcycles; 529127686Sru#endif 53050128Swpaul}; 53150128Swpaul 53272200Sbmilekic#define STE_LOCK(_sc) mtx_lock(&(_sc)->ste_mtx) 53372200Sbmilekic#define STE_UNLOCK(_sc) mtx_unlock(&(_sc)->ste_mtx) 534122689Ssam#define STE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ste_mtx, MA_OWNED) 53567089Swpaul 53650128Swpaulstruct ste_mii_frame { 537200803Syongari uint8_t mii_stdelim; 538200803Syongari uint8_t mii_opcode; 539200803Syongari uint8_t mii_phyaddr; 540200803Syongari uint8_t mii_regaddr; 541200803Syongari uint8_t mii_turnaround; 542200803Syongari uint16_t mii_data; 54350128Swpaul}; 54450128Swpaul 54550128Swpaul/* 54650128Swpaul * MII constants 54750128Swpaul */ 54850128Swpaul#define STE_MII_STARTDELIM 0x01 54950128Swpaul#define STE_MII_READOP 0x02 55050128Swpaul#define STE_MII_WRITEOP 0x01 55150128Swpaul#define STE_MII_TURNAROUND 0x02 552