if_ste.c revision 92739
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 92739 2002-03-20 02:08:01Z alfred $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48 49#include <net/bpf.h> 50 51#include <vm/vm.h> /* for vtophys */ 52#include <vm/pmap.h> /* for vtophys */ 53#include <machine/bus_memio.h> 54#include <machine/bus_pio.h> 55#include <machine/bus.h> 56#include <machine/resource.h> 57#include <sys/bus.h> 58#include <sys/rman.h> 59 60#include <dev/mii/mii.h> 61#include <dev/mii/miivar.h> 62 63#include <pci/pcireg.h> 64#include <pci/pcivar.h> 65 66/* "controller miibus0" required. See GENERIC if you get errors here. */ 67#include "miibus_if.h" 68 69#define STE_USEIOSPACE 70 71#include <pci/if_stereg.h> 72 73MODULE_DEPEND(ste, miibus, 1, 1, 1); 74 75#if !defined(lint) 76static const char rcsid[] = 77 "$FreeBSD: head/sys/pci/if_ste.c 92739 2002-03-20 02:08:01Z alfred $"; 78#endif 79 80/* 81 * Various supported device vendors/types and their names. 82 */ 83static struct ste_type ste_devs[] = { 84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 85 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 86 { 0, 0, NULL } 87}; 88 89static int ste_probe (device_t); 90static int ste_attach (device_t); 91static int ste_detach (device_t); 92static void ste_init (void *); 93static void ste_intr (void *); 94static void ste_rxeof (struct ste_softc *); 95static void ste_txeoc (struct ste_softc *); 96static void ste_txeof (struct ste_softc *); 97static void ste_stats_update (void *); 98static void ste_stop (struct ste_softc *); 99static void ste_reset (struct ste_softc *); 100static int ste_ioctl (struct ifnet *, u_long, caddr_t); 101static int ste_encap (struct ste_softc *, struct ste_chain *, 102 struct mbuf *); 103static void ste_start (struct ifnet *); 104static void ste_watchdog (struct ifnet *); 105static void ste_shutdown (device_t); 106static int ste_newbuf (struct ste_softc *, 107 struct ste_chain_onefrag *, 108 struct mbuf *); 109static int ste_ifmedia_upd (struct ifnet *); 110static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111 112static void ste_mii_sync (struct ste_softc *); 113static void ste_mii_send (struct ste_softc *, u_int32_t, int); 114static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 115static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 116static int ste_miibus_readreg (device_t, int, int); 117static int ste_miibus_writereg (device_t, int, int, int); 118static void ste_miibus_statchg (device_t); 119 120static int ste_eeprom_wait (struct ste_softc *); 121static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 122static void ste_wait (struct ste_softc *); 123static u_int8_t ste_calchash (caddr_t); 124static void ste_setmulti (struct ste_softc *); 125static int ste_init_rx_list (struct ste_softc *); 126static void ste_init_tx_list (struct ste_softc *); 127 128#ifdef STE_USEIOSPACE 129#define STE_RES SYS_RES_IOPORT 130#define STE_RID STE_PCI_LOIO 131#else 132#define STE_RES SYS_RES_MEMORY 133#define STE_RID STE_PCI_LOMEM 134#endif 135 136static device_method_t ste_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, ste_probe), 139 DEVMETHOD(device_attach, ste_attach), 140 DEVMETHOD(device_detach, ste_detach), 141 DEVMETHOD(device_shutdown, ste_shutdown), 142 143 /* bus interface */ 144 DEVMETHOD(bus_print_child, bus_generic_print_child), 145 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 146 147 /* MII interface */ 148 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 149 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 150 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 151 152 { 0, 0 } 153}; 154 155static driver_t ste_driver = { 156 "ste", 157 ste_methods, 158 sizeof(struct ste_softc) 159}; 160 161static devclass_t ste_devclass; 162 163DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 164DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 165 166#define STE_SETBIT4(sc, reg, x) \ 167 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 168 169#define STE_CLRBIT4(sc, reg, x) \ 170 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 171 172#define STE_SETBIT2(sc, reg, x) \ 173 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 174 175#define STE_CLRBIT2(sc, reg, x) \ 176 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 177 178#define STE_SETBIT1(sc, reg, x) \ 179 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 180 181#define STE_CLRBIT1(sc, reg, x) \ 182 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 183 184 185#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 186#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 187 188/* 189 * Sync the PHYs by setting data bit and strobing the clock 32 times. 190 */ 191static void ste_mii_sync(sc) 192 struct ste_softc *sc; 193{ 194 register int i; 195 196 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 197 198 for (i = 0; i < 32; i++) { 199 MII_SET(STE_PHYCTL_MCLK); 200 DELAY(1); 201 MII_CLR(STE_PHYCTL_MCLK); 202 DELAY(1); 203 } 204 205 return; 206} 207 208/* 209 * Clock a series of bits through the MII. 210 */ 211static void ste_mii_send(sc, bits, cnt) 212 struct ste_softc *sc; 213 u_int32_t bits; 214 int cnt; 215{ 216 int i; 217 218 MII_CLR(STE_PHYCTL_MCLK); 219 220 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 221 if (bits & i) { 222 MII_SET(STE_PHYCTL_MDATA); 223 } else { 224 MII_CLR(STE_PHYCTL_MDATA); 225 } 226 DELAY(1); 227 MII_CLR(STE_PHYCTL_MCLK); 228 DELAY(1); 229 MII_SET(STE_PHYCTL_MCLK); 230 } 231} 232 233/* 234 * Read an PHY register through the MII. 235 */ 236static int ste_mii_readreg(sc, frame) 237 struct ste_softc *sc; 238 struct ste_mii_frame *frame; 239 240{ 241 int i, ack; 242 243 STE_LOCK(sc); 244 245 /* 246 * Set up frame for RX. 247 */ 248 frame->mii_stdelim = STE_MII_STARTDELIM; 249 frame->mii_opcode = STE_MII_READOP; 250 frame->mii_turnaround = 0; 251 frame->mii_data = 0; 252 253 CSR_WRITE_2(sc, STE_PHYCTL, 0); 254 /* 255 * Turn on data xmit. 256 */ 257 MII_SET(STE_PHYCTL_MDIR); 258 259 ste_mii_sync(sc); 260 261 /* 262 * Send command/address info. 263 */ 264 ste_mii_send(sc, frame->mii_stdelim, 2); 265 ste_mii_send(sc, frame->mii_opcode, 2); 266 ste_mii_send(sc, frame->mii_phyaddr, 5); 267 ste_mii_send(sc, frame->mii_regaddr, 5); 268 269 /* Turn off xmit. */ 270 MII_CLR(STE_PHYCTL_MDIR); 271 272 /* Idle bit */ 273 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 274 DELAY(1); 275 MII_SET(STE_PHYCTL_MCLK); 276 DELAY(1); 277 278 /* Check for ack */ 279 MII_CLR(STE_PHYCTL_MCLK); 280 DELAY(1); 281 MII_SET(STE_PHYCTL_MCLK); 282 DELAY(1); 283 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 284 285 /* 286 * Now try reading data bits. If the ack failed, we still 287 * need to clock through 16 cycles to keep the PHY(s) in sync. 288 */ 289 if (ack) { 290 for(i = 0; i < 16; i++) { 291 MII_CLR(STE_PHYCTL_MCLK); 292 DELAY(1); 293 MII_SET(STE_PHYCTL_MCLK); 294 DELAY(1); 295 } 296 goto fail; 297 } 298 299 for (i = 0x8000; i; i >>= 1) { 300 MII_CLR(STE_PHYCTL_MCLK); 301 DELAY(1); 302 if (!ack) { 303 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 304 frame->mii_data |= i; 305 DELAY(1); 306 } 307 MII_SET(STE_PHYCTL_MCLK); 308 DELAY(1); 309 } 310 311fail: 312 313 MII_CLR(STE_PHYCTL_MCLK); 314 DELAY(1); 315 MII_SET(STE_PHYCTL_MCLK); 316 DELAY(1); 317 318 STE_UNLOCK(sc); 319 320 if (ack) 321 return(1); 322 return(0); 323} 324 325/* 326 * Write to a PHY register through the MII. 327 */ 328static int ste_mii_writereg(sc, frame) 329 struct ste_softc *sc; 330 struct ste_mii_frame *frame; 331 332{ 333 STE_LOCK(sc); 334 335 /* 336 * Set up frame for TX. 337 */ 338 339 frame->mii_stdelim = STE_MII_STARTDELIM; 340 frame->mii_opcode = STE_MII_WRITEOP; 341 frame->mii_turnaround = STE_MII_TURNAROUND; 342 343 /* 344 * Turn on data output. 345 */ 346 MII_SET(STE_PHYCTL_MDIR); 347 348 ste_mii_sync(sc); 349 350 ste_mii_send(sc, frame->mii_stdelim, 2); 351 ste_mii_send(sc, frame->mii_opcode, 2); 352 ste_mii_send(sc, frame->mii_phyaddr, 5); 353 ste_mii_send(sc, frame->mii_regaddr, 5); 354 ste_mii_send(sc, frame->mii_turnaround, 2); 355 ste_mii_send(sc, frame->mii_data, 16); 356 357 /* Idle bit. */ 358 MII_SET(STE_PHYCTL_MCLK); 359 DELAY(1); 360 MII_CLR(STE_PHYCTL_MCLK); 361 DELAY(1); 362 363 /* 364 * Turn off xmit. 365 */ 366 MII_CLR(STE_PHYCTL_MDIR); 367 368 STE_UNLOCK(sc); 369 370 return(0); 371} 372 373static int ste_miibus_readreg(dev, phy, reg) 374 device_t dev; 375 int phy, reg; 376{ 377 struct ste_softc *sc; 378 struct ste_mii_frame frame; 379 380 sc = device_get_softc(dev); 381 382 bzero((char *)&frame, sizeof(frame)); 383 384 frame.mii_phyaddr = phy; 385 frame.mii_regaddr = reg; 386 ste_mii_readreg(sc, &frame); 387 388 return(frame.mii_data); 389} 390 391static int ste_miibus_writereg(dev, phy, reg, data) 392 device_t dev; 393 int phy, reg, data; 394{ 395 struct ste_softc *sc; 396 struct ste_mii_frame frame; 397 398 sc = device_get_softc(dev); 399 bzero((char *)&frame, sizeof(frame)); 400 401 frame.mii_phyaddr = phy; 402 frame.mii_regaddr = reg; 403 frame.mii_data = data; 404 405 ste_mii_writereg(sc, &frame); 406 407 return(0); 408} 409 410static void ste_miibus_statchg(dev) 411 device_t dev; 412{ 413 struct ste_softc *sc; 414 struct mii_data *mii; 415 416 sc = device_get_softc(dev); 417 STE_LOCK(sc); 418 mii = device_get_softc(sc->ste_miibus); 419 420 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 421 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 422 } else { 423 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 424 } 425 STE_UNLOCK(sc); 426 427 return; 428} 429 430static int ste_ifmedia_upd(ifp) 431 struct ifnet *ifp; 432{ 433 struct ste_softc *sc; 434 struct mii_data *mii; 435 436 sc = ifp->if_softc; 437 mii = device_get_softc(sc->ste_miibus); 438 sc->ste_link = 0; 439 if (mii->mii_instance) { 440 struct mii_softc *miisc; 441 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 442 mii_phy_reset(miisc); 443 } 444 mii_mediachg(mii); 445 446 return(0); 447} 448 449static void ste_ifmedia_sts(ifp, ifmr) 450 struct ifnet *ifp; 451 struct ifmediareq *ifmr; 452{ 453 struct ste_softc *sc; 454 struct mii_data *mii; 455 456 sc = ifp->if_softc; 457 mii = device_get_softc(sc->ste_miibus); 458 459 mii_pollstat(mii); 460 ifmr->ifm_active = mii->mii_media_active; 461 ifmr->ifm_status = mii->mii_media_status; 462 463 return; 464} 465 466static void ste_wait(sc) 467 struct ste_softc *sc; 468{ 469 register int i; 470 471 for (i = 0; i < STE_TIMEOUT; i++) { 472 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 473 break; 474 } 475 476 if (i == STE_TIMEOUT) 477 printf("ste%d: command never completed!\n", sc->ste_unit); 478 479 return; 480} 481 482/* 483 * The EEPROM is slow: give it time to come ready after issuing 484 * it a command. 485 */ 486static int ste_eeprom_wait(sc) 487 struct ste_softc *sc; 488{ 489 int i; 490 491 DELAY(1000); 492 493 for (i = 0; i < 100; i++) { 494 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 495 DELAY(1000); 496 else 497 break; 498 } 499 500 if (i == 100) { 501 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 502 return(1); 503 } 504 505 return(0); 506} 507 508/* 509 * Read a sequence of words from the EEPROM. Note that ethernet address 510 * data is stored in the EEPROM in network byte order. 511 */ 512static int ste_read_eeprom(sc, dest, off, cnt, swap) 513 struct ste_softc *sc; 514 caddr_t dest; 515 int off; 516 int cnt; 517 int swap; 518{ 519 int err = 0, i; 520 u_int16_t word = 0, *ptr; 521 522 if (ste_eeprom_wait(sc)) 523 return(1); 524 525 for (i = 0; i < cnt; i++) { 526 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 527 err = ste_eeprom_wait(sc); 528 if (err) 529 break; 530 word = CSR_READ_2(sc, STE_EEPROM_DATA); 531 ptr = (u_int16_t *)(dest + (i * 2)); 532 if (swap) 533 *ptr = ntohs(word); 534 else 535 *ptr = word; 536 } 537 538 return(err ? 1 : 0); 539} 540 541static u_int8_t ste_calchash(addr) 542 caddr_t addr; 543{ 544 545 u_int32_t crc, carry; 546 int i, j; 547 u_int8_t c; 548 549 /* Compute CRC for the address value. */ 550 crc = 0xFFFFFFFF; /* initial value */ 551 552 for (i = 0; i < 6; i++) { 553 c = *(addr + i); 554 for (j = 0; j < 8; j++) { 555 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 556 crc <<= 1; 557 c >>= 1; 558 if (carry) 559 crc = (crc ^ 0x04c11db6) | carry; 560 } 561 } 562 563 /* return the filter bit position */ 564 return(crc & 0x0000003F); 565} 566 567static void ste_setmulti(sc) 568 struct ste_softc *sc; 569{ 570 struct ifnet *ifp; 571 int h = 0; 572 u_int32_t hashes[2] = { 0, 0 }; 573 struct ifmultiaddr *ifma; 574 575 ifp = &sc->arpcom.ac_if; 576 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 577 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 578 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 579 return; 580 } 581 582 /* first, zot all the existing hash bits */ 583 CSR_WRITE_2(sc, STE_MAR0, 0); 584 CSR_WRITE_2(sc, STE_MAR1, 0); 585 CSR_WRITE_2(sc, STE_MAR2, 0); 586 CSR_WRITE_2(sc, STE_MAR3, 0); 587 588 /* now program new ones */ 589 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 590 if (ifma->ifma_addr->sa_family != AF_LINK) 591 continue; 592 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 593 if (h < 32) 594 hashes[0] |= (1 << h); 595 else 596 hashes[1] |= (1 << (h - 32)); 597 } 598 599 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 600 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 601 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 602 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 603 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 604 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 605 606 return; 607} 608 609static void ste_intr(xsc) 610 void *xsc; 611{ 612 struct ste_softc *sc; 613 struct ifnet *ifp; 614 u_int16_t status; 615 616 sc = xsc; 617 STE_LOCK(sc); 618 ifp = &sc->arpcom.ac_if; 619 620 /* See if this is really our interrupt. */ 621 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 622 STE_UNLOCK(sc); 623 return; 624 } 625 626 for (;;) { 627 status = CSR_READ_2(sc, STE_ISR_ACK); 628 629 if (!(status & STE_INTRS)) 630 break; 631 632 if (status & STE_ISR_RX_DMADONE) 633 ste_rxeof(sc); 634 635 if (status & STE_ISR_TX_DMADONE) 636 ste_txeof(sc); 637 638 if (status & STE_ISR_TX_DONE) 639 ste_txeoc(sc); 640 641 if (status & STE_ISR_STATS_OFLOW) { 642 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 643 ste_stats_update(sc); 644 } 645 646 if (status & STE_ISR_HOSTERR) { 647 ste_reset(sc); 648 ste_init(sc); 649 } 650 } 651 652 /* Re-enable interrupts */ 653 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 654 655 if (ifp->if_snd.ifq_head != NULL) 656 ste_start(ifp); 657 658 STE_UNLOCK(sc); 659 660 return; 661} 662 663/* 664 * A frame has been uploaded: pass the resulting mbuf chain up to 665 * the higher level protocols. 666 */ 667static void ste_rxeof(sc) 668 struct ste_softc *sc; 669{ 670 struct ether_header *eh; 671 struct mbuf *m; 672 struct ifnet *ifp; 673 struct ste_chain_onefrag *cur_rx; 674 int total_len = 0; 675 u_int32_t rxstat; 676 677 ifp = &sc->arpcom.ac_if; 678 679again: 680 681 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) { 682 cur_rx = sc->ste_cdata.ste_rx_head; 683 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 684 685 /* 686 * If an error occurs, update stats, clear the 687 * status word and leave the mbuf cluster in place: 688 * it should simply get re-used next time this descriptor 689 * comes up in the ring. 690 */ 691 if (rxstat & STE_RXSTAT_FRAME_ERR) { 692 ifp->if_ierrors++; 693 cur_rx->ste_ptr->ste_status = 0; 694 continue; 695 } 696 697 /* 698 * If there error bit was not set, the upload complete 699 * bit should be set which means we have a valid packet. 700 * If not, something truly strange has happened. 701 */ 702 if (!(rxstat & STE_RXSTAT_DMADONE)) { 703 printf("ste%d: bad receive status -- packet dropped", 704 sc->ste_unit); 705 ifp->if_ierrors++; 706 cur_rx->ste_ptr->ste_status = 0; 707 continue; 708 } 709 710 /* No errors; receive the packet. */ 711 m = cur_rx->ste_mbuf; 712 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 713 714 /* 715 * Try to conjure up a new mbuf cluster. If that 716 * fails, it means we have an out of memory condition and 717 * should leave the buffer in place and continue. This will 718 * result in a lost packet, but there's little else we 719 * can do in this situation. 720 */ 721 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 722 ifp->if_ierrors++; 723 cur_rx->ste_ptr->ste_status = 0; 724 continue; 725 } 726 727 ifp->if_ipackets++; 728 eh = mtod(m, struct ether_header *); 729 m->m_pkthdr.rcvif = ifp; 730 m->m_pkthdr.len = m->m_len = total_len; 731 732 /* Remove header from mbuf and pass it on. */ 733 m_adj(m, sizeof(struct ether_header)); 734 ether_input(ifp, eh, m); 735 } 736 737 /* 738 * Handle the 'end of channel' condition. When the upload 739 * engine hits the end of the RX ring, it will stall. This 740 * is our cue to flush the RX ring, reload the uplist pointer 741 * register and unstall the engine. 742 * XXX This is actually a little goofy. With the ThunderLAN 743 * chip, you get an interrupt when the receiver hits the end 744 * of the receive ring, which tells you exactly when you 745 * you need to reload the ring pointer. Here we have to 746 * fake it. I'm mad at myself for not being clever enough 747 * to avoid the use of a goto here. 748 */ 749 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 || 750 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) { 751 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 752 ste_wait(sc); 753 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 754 vtophys(&sc->ste_ldata->ste_rx_list[0])); 755 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0]; 756 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 757 goto again; 758 } 759 760 return; 761} 762 763static void ste_txeoc(sc) 764 struct ste_softc *sc; 765{ 766 u_int8_t txstat; 767 struct ifnet *ifp; 768 769 ifp = &sc->arpcom.ac_if; 770 771 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 772 STE_TXSTATUS_TXDONE) { 773 if (txstat & STE_TXSTATUS_UNDERRUN || 774 txstat & STE_TXSTATUS_EXCESSCOLLS || 775 txstat & STE_TXSTATUS_RECLAIMERR) { 776 ifp->if_oerrors++; 777 printf("ste%d: transmission error: %x\n", 778 sc->ste_unit, txstat); 779 780 ste_reset(sc); 781 ste_init(sc); 782 783 if (txstat & STE_TXSTATUS_UNDERRUN && 784 sc->ste_tx_thresh < STE_PACKET_SIZE) { 785 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 786 printf("ste%d: tx underrun, increasing tx" 787 " start threshold to %d bytes\n", 788 sc->ste_unit, sc->ste_tx_thresh); 789 } 790 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 791 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 792 (STE_PACKET_SIZE >> 4)); 793 } 794 ste_init(sc); 795 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 796 } 797 798 return; 799} 800 801static void ste_txeof(sc) 802 struct ste_softc *sc; 803{ 804 struct ste_chain *cur_tx = NULL; 805 struct ifnet *ifp; 806 int idx; 807 808 ifp = &sc->arpcom.ac_if; 809 810 idx = sc->ste_cdata.ste_tx_cons; 811 while(idx != sc->ste_cdata.ste_tx_prod) { 812 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 813 814 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 815 break; 816 817 if (cur_tx->ste_mbuf != NULL) { 818 m_freem(cur_tx->ste_mbuf); 819 cur_tx->ste_mbuf = NULL; 820 } 821 822 ifp->if_opackets++; 823 824 sc->ste_cdata.ste_tx_cnt--; 825 STE_INC(idx, STE_TX_LIST_CNT); 826 ifp->if_timer = 0; 827 } 828 829 sc->ste_cdata.ste_tx_cons = idx; 830 831 if (cur_tx != NULL) 832 ifp->if_flags &= ~IFF_OACTIVE; 833 834 return; 835} 836 837static void ste_stats_update(xsc) 838 void *xsc; 839{ 840 struct ste_softc *sc; 841 struct ste_stats stats; 842 struct ifnet *ifp; 843 struct mii_data *mii; 844 int i; 845 u_int8_t *p; 846 847 sc = xsc; 848 STE_LOCK(sc); 849 850 ifp = &sc->arpcom.ac_if; 851 mii = device_get_softc(sc->ste_miibus); 852 853 p = (u_int8_t *)&stats; 854 855 for (i = 0; i < sizeof(stats); i++) { 856 *p = CSR_READ_1(sc, STE_STATS + i); 857 p++; 858 } 859 860 ifp->if_collisions += stats.ste_single_colls + 861 stats.ste_multi_colls + stats.ste_late_colls; 862 863 mii_tick(mii); 864 if (!sc->ste_link && mii->mii_media_status & IFM_ACTIVE && 865 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 866 sc->ste_link++; 867 if (ifp->if_snd.ifq_head != NULL) 868 ste_start(ifp); 869 } 870 871 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 872 STE_UNLOCK(sc); 873 874 return; 875} 876 877 878/* 879 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 880 * IDs against our list and return a device name if we find a match. 881 */ 882static int ste_probe(dev) 883 device_t dev; 884{ 885 struct ste_type *t; 886 887 t = ste_devs; 888 889 while(t->ste_name != NULL) { 890 if ((pci_get_vendor(dev) == t->ste_vid) && 891 (pci_get_device(dev) == t->ste_did)) { 892 device_set_desc(dev, t->ste_name); 893 return(0); 894 } 895 t++; 896 } 897 898 return(ENXIO); 899} 900 901/* 902 * Attach the interface. Allocate softc structures, do ifmedia 903 * setup and ethernet/BPF attach. 904 */ 905static int ste_attach(dev) 906 device_t dev; 907{ 908 u_int32_t command; 909 struct ste_softc *sc; 910 struct ifnet *ifp; 911 int unit, error = 0, rid; 912 913 sc = device_get_softc(dev); 914 unit = device_get_unit(dev); 915 bzero(sc, sizeof(struct ste_softc)); 916 917 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 918 STE_LOCK(sc); 919 920 /* 921 * Handle power management nonsense. 922 */ 923 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 924 u_int32_t iobase, membase, irq; 925 926 /* Save important PCI config data. */ 927 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 928 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 929 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 930 931 /* Reset the power state. */ 932 printf("ste%d: chip is in D%d power mode " 933 "-- setting to D0\n", unit, 934 pci_get_powerstate(dev)); 935 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 936 937 /* Restore PCI config data. */ 938 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 939 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 940 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 941 } 942 943 /* 944 * Map control/status registers. 945 */ 946 pci_enable_busmaster(dev); 947 pci_enable_io(dev, SYS_RES_IOPORT); 948 pci_enable_io(dev, SYS_RES_MEMORY); 949 command = pci_read_config(dev, PCIR_COMMAND, 4); 950 951#ifdef STE_USEIOSPACE 952 if (!(command & PCIM_CMD_PORTEN)) { 953 printf("ste%d: failed to enable I/O ports!\n", unit); 954 error = ENXIO; 955 goto fail; 956 } 957#else 958 if (!(command & PCIM_CMD_MEMEN)) { 959 printf("ste%d: failed to enable memory mapping!\n", unit); 960 error = ENXIO; 961 goto fail; 962 } 963#endif 964 965 rid = STE_RID; 966 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 967 0, ~0, 1, RF_ACTIVE); 968 969 if (sc->ste_res == NULL) { 970 printf ("ste%d: couldn't map ports/memory\n", unit); 971 error = ENXIO; 972 goto fail; 973 } 974 975 sc->ste_btag = rman_get_bustag(sc->ste_res); 976 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 977 978 rid = 0; 979 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 980 RF_SHAREABLE | RF_ACTIVE); 981 982 if (sc->ste_irq == NULL) { 983 printf("ste%d: couldn't map interrupt\n", unit); 984 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 985 error = ENXIO; 986 goto fail; 987 } 988 989 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 990 ste_intr, sc, &sc->ste_intrhand); 991 992 if (error) { 993 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 994 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 995 printf("ste%d: couldn't set up irq\n", unit); 996 goto fail; 997 } 998 999 callout_handle_init(&sc->ste_stat_ch); 1000 1001 /* Reset the adapter. */ 1002 ste_reset(sc); 1003 1004 /* 1005 * Get station address from the EEPROM. 1006 */ 1007 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1008 STE_EEADDR_NODE0, 3, 0)) { 1009 printf("ste%d: failed to read station address\n", unit); 1010 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1011 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1012 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1013 error = ENXIO;; 1014 goto fail; 1015 } 1016 1017 /* 1018 * A Sundance chip was detected. Inform the world. 1019 */ 1020 printf("ste%d: Ethernet address: %6D\n", unit, 1021 sc->arpcom.ac_enaddr, ":"); 1022 1023 sc->ste_unit = unit; 1024 1025 /* Allocate the descriptor queues. */ 1026 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1027 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1028 1029 if (sc->ste_ldata == NULL) { 1030 printf("ste%d: no memory for list buffers!\n", unit); 1031 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1032 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1033 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1034 error = ENXIO; 1035 goto fail; 1036 } 1037 1038 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1039 1040 /* Do MII setup. */ 1041 if (mii_phy_probe(dev, &sc->ste_miibus, 1042 ste_ifmedia_upd, ste_ifmedia_sts)) { 1043 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1044 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1045 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1046 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1047 contigfree(sc->ste_ldata, 1048 sizeof(struct ste_list_data), M_DEVBUF); 1049 error = ENXIO; 1050 goto fail; 1051 } 1052 1053 ifp = &sc->arpcom.ac_if; 1054 ifp->if_softc = sc; 1055 ifp->if_unit = unit; 1056 ifp->if_name = "ste"; 1057 ifp->if_mtu = ETHERMTU; 1058 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1059 ifp->if_ioctl = ste_ioctl; 1060 ifp->if_output = ether_output; 1061 ifp->if_start = ste_start; 1062 ifp->if_watchdog = ste_watchdog; 1063 ifp->if_init = ste_init; 1064 ifp->if_baudrate = 10000000; 1065 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1066 1067 /* 1068 * Call MI attach routine. 1069 */ 1070 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1071 STE_UNLOCK(sc); 1072 return(0); 1073 1074fail: 1075 STE_UNLOCK(sc); 1076 mtx_destroy(&sc->ste_mtx); 1077 return(error); 1078} 1079 1080static int ste_detach(dev) 1081 device_t dev; 1082{ 1083 struct ste_softc *sc; 1084 struct ifnet *ifp; 1085 1086 sc = device_get_softc(dev); 1087 STE_LOCK(sc); 1088 ifp = &sc->arpcom.ac_if; 1089 1090 ste_stop(sc); 1091 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1092 1093 bus_generic_detach(dev); 1094 device_delete_child(dev, sc->ste_miibus); 1095 1096 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1097 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1098 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1099 1100 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1101 1102 STE_UNLOCK(sc); 1103 mtx_destroy(&sc->ste_mtx); 1104 1105 return(0); 1106} 1107 1108static int ste_newbuf(sc, c, m) 1109 struct ste_softc *sc; 1110 struct ste_chain_onefrag *c; 1111 struct mbuf *m; 1112{ 1113 struct mbuf *m_new = NULL; 1114 1115 if (m == NULL) { 1116 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1117 if (m_new == NULL) 1118 return(ENOBUFS); 1119 MCLGET(m_new, M_DONTWAIT); 1120 if (!(m_new->m_flags & M_EXT)) { 1121 m_freem(m_new); 1122 return(ENOBUFS); 1123 } 1124 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1125 } else { 1126 m_new = m; 1127 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1128 m_new->m_data = m_new->m_ext.ext_buf; 1129 } 1130 1131 m_adj(m_new, ETHER_ALIGN); 1132 1133 c->ste_mbuf = m_new; 1134 c->ste_ptr->ste_status = 0; 1135 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1136 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; 1137 1138 return(0); 1139} 1140 1141static int ste_init_rx_list(sc) 1142 struct ste_softc *sc; 1143{ 1144 struct ste_chain_data *cd; 1145 struct ste_list_data *ld; 1146 int i; 1147 1148 cd = &sc->ste_cdata; 1149 ld = sc->ste_ldata; 1150 1151 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1152 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1153 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1154 return(ENOBUFS); 1155 if (i == (STE_RX_LIST_CNT - 1)) { 1156 cd->ste_rx_chain[i].ste_next = 1157 &cd->ste_rx_chain[0]; 1158 ld->ste_rx_list[i].ste_next = 1159 vtophys(&ld->ste_rx_list[0]); 1160 } else { 1161 cd->ste_rx_chain[i].ste_next = 1162 &cd->ste_rx_chain[i + 1]; 1163 ld->ste_rx_list[i].ste_next = 1164 vtophys(&ld->ste_rx_list[i + 1]); 1165 } 1166 1167 } 1168 1169 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1170 1171 return(0); 1172} 1173 1174static void ste_init_tx_list(sc) 1175 struct ste_softc *sc; 1176{ 1177 struct ste_chain_data *cd; 1178 struct ste_list_data *ld; 1179 int i; 1180 1181 cd = &sc->ste_cdata; 1182 ld = sc->ste_ldata; 1183 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1184 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1185 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1186 if (i == (STE_TX_LIST_CNT - 1)) 1187 cd->ste_tx_chain[i].ste_next = 1188 &cd->ste_tx_chain[0]; 1189 else 1190 cd->ste_tx_chain[i].ste_next = 1191 &cd->ste_tx_chain[i + 1]; 1192 if (i == 0) 1193 cd->ste_tx_chain[i].ste_prev = 1194 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1195 else 1196 cd->ste_tx_chain[i].ste_prev = 1197 &cd->ste_tx_chain[i - 1]; 1198 } 1199 1200 1201 bzero((char *)ld->ste_tx_list, 1202 sizeof(struct ste_desc) * STE_TX_LIST_CNT); 1203 1204 cd->ste_tx_prod = 0; 1205 cd->ste_tx_cons = 0; 1206 cd->ste_tx_cnt = 0; 1207 1208 return; 1209} 1210 1211static void ste_init(xsc) 1212 void *xsc; 1213{ 1214 struct ste_softc *sc; 1215 int i; 1216 struct ifnet *ifp; 1217 struct mii_data *mii; 1218 1219 sc = xsc; 1220 STE_LOCK(sc); 1221 ifp = &sc->arpcom.ac_if; 1222 mii = device_get_softc(sc->ste_miibus); 1223 1224 ste_stop(sc); 1225 1226 /* Init our MAC address */ 1227 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1228 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1229 } 1230 1231 /* Init RX list */ 1232 if (ste_init_rx_list(sc) == ENOBUFS) { 1233 printf("ste%d: initialization failed: no " 1234 "memory for RX buffers\n", sc->ste_unit); 1235 ste_stop(sc); 1236 STE_UNLOCK(sc); 1237 return; 1238 } 1239 1240 /* Init TX descriptors */ 1241 ste_init_tx_list(sc); 1242 1243 /* Set the TX freethresh value */ 1244 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1245 1246 /* Set the TX start threshold for best performance. */ 1247 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1248 1249 /* Set the TX reclaim threshold. */ 1250 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1251 1252 /* Set up the RX filter. */ 1253 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1254 1255 /* If we want promiscuous mode, set the allframes bit. */ 1256 if (ifp->if_flags & IFF_PROMISC) { 1257 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1258 } else { 1259 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1260 } 1261 1262 /* Set capture broadcast bit to accept broadcast frames. */ 1263 if (ifp->if_flags & IFF_BROADCAST) { 1264 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1265 } else { 1266 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1267 } 1268 1269 ste_setmulti(sc); 1270 1271 /* Load the address of the RX list. */ 1272 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1273 ste_wait(sc); 1274 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1275 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1276 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1277 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1278 1279 /* Set TX polling interval */ 1280 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1281 1282 /* Load address of the TX list */ 1283 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1284 ste_wait(sc); 1285 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1286 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1287 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1288 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1289 ste_wait(sc); 1290 1291 /* Enable receiver and transmitter */ 1292 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1293 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1294 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1295 1296 /* Enable stats counters. */ 1297 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1298 1299 /* Enable interrupts. */ 1300 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1301 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1302 1303 ste_ifmedia_upd(ifp); 1304 1305 ifp->if_flags |= IFF_RUNNING; 1306 ifp->if_flags &= ~IFF_OACTIVE; 1307 1308 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1309 STE_UNLOCK(sc); 1310 1311 return; 1312} 1313 1314static void ste_stop(sc) 1315 struct ste_softc *sc; 1316{ 1317 int i; 1318 struct ifnet *ifp; 1319 1320 STE_LOCK(sc); 1321 ifp = &sc->arpcom.ac_if; 1322 1323 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1324 1325 CSR_WRITE_2(sc, STE_IMR, 0); 1326 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1327 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1328 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1329 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1330 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1331 ste_wait(sc); 1332 1333 sc->ste_link = 0; 1334 1335 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1336 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1337 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1338 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1339 } 1340 } 1341 1342 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1343 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1344 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1345 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1346 } 1347 } 1348 1349 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1350 STE_UNLOCK(sc); 1351 1352 return; 1353} 1354 1355static void ste_reset(sc) 1356 struct ste_softc *sc; 1357{ 1358 int i; 1359 1360 STE_SETBIT4(sc, STE_ASICCTL, 1361 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1362 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1363 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1364 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1365 STE_ASICCTL_EXTRESET_RESET); 1366 1367 DELAY(100000); 1368 1369 for (i = 0; i < STE_TIMEOUT; i++) { 1370 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1371 break; 1372 } 1373 1374 if (i == STE_TIMEOUT) 1375 printf("ste%d: global reset never completed\n", sc->ste_unit); 1376 1377 return; 1378} 1379 1380static int ste_ioctl(ifp, command, data) 1381 struct ifnet *ifp; 1382 u_long command; 1383 caddr_t data; 1384{ 1385 struct ste_softc *sc; 1386 struct ifreq *ifr; 1387 struct mii_data *mii; 1388 int error = 0; 1389 1390 sc = ifp->if_softc; 1391 STE_LOCK(sc); 1392 ifr = (struct ifreq *)data; 1393 1394 switch(command) { 1395 case SIOCSIFADDR: 1396 case SIOCGIFADDR: 1397 case SIOCSIFMTU: 1398 error = ether_ioctl(ifp, command, data); 1399 break; 1400 case SIOCSIFFLAGS: 1401 if (ifp->if_flags & IFF_UP) { 1402 if (ifp->if_flags & IFF_RUNNING && 1403 ifp->if_flags & IFF_PROMISC && 1404 !(sc->ste_if_flags & IFF_PROMISC)) { 1405 STE_SETBIT1(sc, STE_RX_MODE, 1406 STE_RXMODE_PROMISC); 1407 } else if (ifp->if_flags & IFF_RUNNING && 1408 !(ifp->if_flags & IFF_PROMISC) && 1409 sc->ste_if_flags & IFF_PROMISC) { 1410 STE_CLRBIT1(sc, STE_RX_MODE, 1411 STE_RXMODE_PROMISC); 1412 } else if (!(ifp->if_flags & IFF_RUNNING)) { 1413 sc->ste_tx_thresh = STE_MIN_FRAMELEN; 1414 ste_init(sc); 1415 } 1416 } else { 1417 if (ifp->if_flags & IFF_RUNNING) 1418 ste_stop(sc); 1419 } 1420 sc->ste_if_flags = ifp->if_flags; 1421 error = 0; 1422 break; 1423 case SIOCADDMULTI: 1424 case SIOCDELMULTI: 1425 ste_setmulti(sc); 1426 error = 0; 1427 break; 1428 case SIOCGIFMEDIA: 1429 case SIOCSIFMEDIA: 1430 mii = device_get_softc(sc->ste_miibus); 1431 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1432 break; 1433 default: 1434 error = EINVAL; 1435 break; 1436 } 1437 1438 STE_UNLOCK(sc); 1439 1440 return(error); 1441} 1442 1443static int ste_encap(sc, c, m_head) 1444 struct ste_softc *sc; 1445 struct ste_chain *c; 1446 struct mbuf *m_head; 1447{ 1448 int frag = 0; 1449 struct ste_frag *f = NULL; 1450 struct mbuf *m; 1451 struct ste_desc *d; 1452 int total_len = 0; 1453 1454 d = c->ste_ptr; 1455 d->ste_ctl = 0; 1456 d->ste_next = 0; 1457 1458 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1459 if (m->m_len != 0) { 1460 if (frag == STE_MAXFRAGS) 1461 break; 1462 total_len += m->m_len; 1463 f = &c->ste_ptr->ste_frags[frag]; 1464 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1465 f->ste_len = m->m_len; 1466 frag++; 1467 } 1468 } 1469 1470 c->ste_mbuf = m_head; 1471 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1472 c->ste_ptr->ste_ctl = total_len; 1473 1474 return(0); 1475} 1476 1477static void ste_start(ifp) 1478 struct ifnet *ifp; 1479{ 1480 struct ste_softc *sc; 1481 struct mbuf *m_head = NULL; 1482 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1483 int idx; 1484 1485 sc = ifp->if_softc; 1486 STE_LOCK(sc); 1487 1488 if (!sc->ste_link) { 1489 STE_UNLOCK(sc); 1490 return; 1491 } 1492 1493 if (ifp->if_flags & IFF_OACTIVE) { 1494 STE_UNLOCK(sc); 1495 return; 1496 } 1497 1498 idx = sc->ste_cdata.ste_tx_prod; 1499 start_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1500 1501 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1502 1503 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1504 ifp->if_flags |= IFF_OACTIVE; 1505 break; 1506 } 1507 1508 IF_DEQUEUE(&ifp->if_snd, m_head); 1509 if (m_head == NULL) 1510 break; 1511 1512 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1513 1514 ste_encap(sc, cur_tx, m_head); 1515 1516 if (prev != NULL) 1517 prev->ste_ptr->ste_next = cur_tx->ste_phys; 1518 prev = cur_tx; 1519 1520 /* 1521 * If there's a BPF listener, bounce a copy of this frame 1522 * to him. 1523 */ 1524 if (ifp->if_bpf) 1525 bpf_mtap(ifp, cur_tx->ste_mbuf); 1526 1527 STE_INC(idx, STE_TX_LIST_CNT); 1528 sc->ste_cdata.ste_tx_cnt++; 1529 } 1530 1531 if (cur_tx == NULL) { 1532 STE_UNLOCK(sc); 1533 return; 1534 } 1535 1536 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR; 1537 1538 /* Start transmission */ 1539 sc->ste_cdata.ste_tx_prod = idx; 1540 start_tx->ste_prev->ste_ptr->ste_next = start_tx->ste_phys; 1541 1542 ifp->if_timer = 5; 1543 STE_UNLOCK(sc); 1544 1545 return; 1546} 1547 1548static void ste_watchdog(ifp) 1549 struct ifnet *ifp; 1550{ 1551 struct ste_softc *sc; 1552 1553 sc = ifp->if_softc; 1554 STE_LOCK(sc); 1555 1556 ifp->if_oerrors++; 1557 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1558 1559 ste_txeoc(sc); 1560 ste_txeof(sc); 1561 ste_rxeof(sc); 1562 ste_reset(sc); 1563 ste_init(sc); 1564 1565 if (ifp->if_snd.ifq_head != NULL) 1566 ste_start(ifp); 1567 STE_UNLOCK(sc); 1568 1569 return; 1570} 1571 1572static void ste_shutdown(dev) 1573 device_t dev; 1574{ 1575 struct ste_softc *sc; 1576 1577 sc = device_get_softc(dev); 1578 1579 ste_stop(sc); 1580 1581 return; 1582} 1583