if_ste.c revision 84147
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 84147 2001-09-29 19:28:31Z jlemon $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48 49#include <net/bpf.h> 50 51#include <vm/vm.h> /* for vtophys */ 52#include <vm/pmap.h> /* for vtophys */ 53#include <machine/bus_memio.h> 54#include <machine/bus_pio.h> 55#include <machine/bus.h> 56#include <machine/resource.h> 57#include <sys/bus.h> 58#include <sys/rman.h> 59 60#include <dev/mii/mii.h> 61#include <dev/mii/miivar.h> 62 63#include <pci/pcireg.h> 64#include <pci/pcivar.h> 65 66/* "controller miibus0" required. See GENERIC if you get errors here. */ 67#include "miibus_if.h" 68 69#define STE_USEIOSPACE 70 71#include <pci/if_stereg.h> 72 73MODULE_DEPEND(ste, miibus, 1, 1, 1); 74 75#if !defined(lint) 76static const char rcsid[] = 77 "$FreeBSD: head/sys/pci/if_ste.c 84147 2001-09-29 19:28:31Z jlemon $"; 78#endif 79 80/* 81 * Various supported device vendors/types and their names. 82 */ 83static struct ste_type ste_devs[] = { 84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 85 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 86 { 0, 0, NULL } 87}; 88 89static int ste_probe __P((device_t)); 90static int ste_attach __P((device_t)); 91static int ste_detach __P((device_t)); 92static void ste_init __P((void *)); 93static void ste_intr __P((void *)); 94static void ste_rxeof __P((struct ste_softc *)); 95static void ste_txeoc __P((struct ste_softc *)); 96static void ste_txeof __P((struct ste_softc *)); 97static void ste_stats_update __P((void *)); 98static void ste_stop __P((struct ste_softc *)); 99static void ste_reset __P((struct ste_softc *)); 100static int ste_ioctl __P((struct ifnet *, u_long, caddr_t)); 101static int ste_encap __P((struct ste_softc *, struct ste_chain *, 102 struct mbuf *)); 103static void ste_start __P((struct ifnet *)); 104static void ste_watchdog __P((struct ifnet *)); 105static void ste_shutdown __P((device_t)); 106static int ste_newbuf __P((struct ste_softc *, 107 struct ste_chain_onefrag *, 108 struct mbuf *)); 109static int ste_ifmedia_upd __P((struct ifnet *)); 110static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 111 112static void ste_mii_sync __P((struct ste_softc *)); 113static void ste_mii_send __P((struct ste_softc *, u_int32_t, int)); 114static int ste_mii_readreg __P((struct ste_softc *, 115 struct ste_mii_frame *)); 116static int ste_mii_writereg __P((struct ste_softc *, 117 struct ste_mii_frame *)); 118static int ste_miibus_readreg __P((device_t, int, int)); 119static int ste_miibus_writereg __P((device_t, int, int, int)); 120static void ste_miibus_statchg __P((device_t)); 121 122static int ste_eeprom_wait __P((struct ste_softc *)); 123static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int, 124 int, int)); 125static void ste_wait __P((struct ste_softc *)); 126static u_int8_t ste_calchash __P((caddr_t)); 127static void ste_setmulti __P((struct ste_softc *)); 128static int ste_init_rx_list __P((struct ste_softc *)); 129static void ste_init_tx_list __P((struct ste_softc *)); 130 131#ifdef STE_USEIOSPACE 132#define STE_RES SYS_RES_IOPORT 133#define STE_RID STE_PCI_LOIO 134#else 135#define STE_RES SYS_RES_MEMORY 136#define STE_RID STE_PCI_LOMEM 137#endif 138 139static device_method_t ste_methods[] = { 140 /* Device interface */ 141 DEVMETHOD(device_probe, ste_probe), 142 DEVMETHOD(device_attach, ste_attach), 143 DEVMETHOD(device_detach, ste_detach), 144 DEVMETHOD(device_shutdown, ste_shutdown), 145 146 /* bus interface */ 147 DEVMETHOD(bus_print_child, bus_generic_print_child), 148 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 149 150 /* MII interface */ 151 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 152 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 153 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 154 155 { 0, 0 } 156}; 157 158static driver_t ste_driver = { 159 "ste", 160 ste_methods, 161 sizeof(struct ste_softc) 162}; 163 164static devclass_t ste_devclass; 165 166DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 167DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 168 169#define STE_SETBIT4(sc, reg, x) \ 170 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 171 172#define STE_CLRBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 174 175#define STE_SETBIT2(sc, reg, x) \ 176 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 177 178#define STE_CLRBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 180 181#define STE_SETBIT1(sc, reg, x) \ 182 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 183 184#define STE_CLRBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 186 187 188#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 189#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 190 191/* 192 * Sync the PHYs by setting data bit and strobing the clock 32 times. 193 */ 194static void ste_mii_sync(sc) 195 struct ste_softc *sc; 196{ 197 register int i; 198 199 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 200 201 for (i = 0; i < 32; i++) { 202 MII_SET(STE_PHYCTL_MCLK); 203 DELAY(1); 204 MII_CLR(STE_PHYCTL_MCLK); 205 DELAY(1); 206 } 207 208 return; 209} 210 211/* 212 * Clock a series of bits through the MII. 213 */ 214static void ste_mii_send(sc, bits, cnt) 215 struct ste_softc *sc; 216 u_int32_t bits; 217 int cnt; 218{ 219 int i; 220 221 MII_CLR(STE_PHYCTL_MCLK); 222 223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 224 if (bits & i) { 225 MII_SET(STE_PHYCTL_MDATA); 226 } else { 227 MII_CLR(STE_PHYCTL_MDATA); 228 } 229 DELAY(1); 230 MII_CLR(STE_PHYCTL_MCLK); 231 DELAY(1); 232 MII_SET(STE_PHYCTL_MCLK); 233 } 234} 235 236/* 237 * Read an PHY register through the MII. 238 */ 239static int ste_mii_readreg(sc, frame) 240 struct ste_softc *sc; 241 struct ste_mii_frame *frame; 242 243{ 244 int i, ack; 245 246 STE_LOCK(sc); 247 248 /* 249 * Set up frame for RX. 250 */ 251 frame->mii_stdelim = STE_MII_STARTDELIM; 252 frame->mii_opcode = STE_MII_READOP; 253 frame->mii_turnaround = 0; 254 frame->mii_data = 0; 255 256 CSR_WRITE_2(sc, STE_PHYCTL, 0); 257 /* 258 * Turn on data xmit. 259 */ 260 MII_SET(STE_PHYCTL_MDIR); 261 262 ste_mii_sync(sc); 263 264 /* 265 * Send command/address info. 266 */ 267 ste_mii_send(sc, frame->mii_stdelim, 2); 268 ste_mii_send(sc, frame->mii_opcode, 2); 269 ste_mii_send(sc, frame->mii_phyaddr, 5); 270 ste_mii_send(sc, frame->mii_regaddr, 5); 271 272 /* Turn off xmit. */ 273 MII_CLR(STE_PHYCTL_MDIR); 274 275 /* Idle bit */ 276 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 277 DELAY(1); 278 MII_SET(STE_PHYCTL_MCLK); 279 DELAY(1); 280 281 /* Check for ack */ 282 MII_CLR(STE_PHYCTL_MCLK); 283 DELAY(1); 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 287 288 /* 289 * Now try reading data bits. If the ack failed, we still 290 * need to clock through 16 cycles to keep the PHY(s) in sync. 291 */ 292 if (ack) { 293 for(i = 0; i < 16; i++) { 294 MII_CLR(STE_PHYCTL_MCLK); 295 DELAY(1); 296 MII_SET(STE_PHYCTL_MCLK); 297 DELAY(1); 298 } 299 goto fail; 300 } 301 302 for (i = 0x8000; i; i >>= 1) { 303 MII_CLR(STE_PHYCTL_MCLK); 304 DELAY(1); 305 if (!ack) { 306 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 307 frame->mii_data |= i; 308 DELAY(1); 309 } 310 MII_SET(STE_PHYCTL_MCLK); 311 DELAY(1); 312 } 313 314fail: 315 316 MII_CLR(STE_PHYCTL_MCLK); 317 DELAY(1); 318 MII_SET(STE_PHYCTL_MCLK); 319 DELAY(1); 320 321 STE_UNLOCK(sc); 322 323 if (ack) 324 return(1); 325 return(0); 326} 327 328/* 329 * Write to a PHY register through the MII. 330 */ 331static int ste_mii_writereg(sc, frame) 332 struct ste_softc *sc; 333 struct ste_mii_frame *frame; 334 335{ 336 STE_LOCK(sc); 337 338 /* 339 * Set up frame for TX. 340 */ 341 342 frame->mii_stdelim = STE_MII_STARTDELIM; 343 frame->mii_opcode = STE_MII_WRITEOP; 344 frame->mii_turnaround = STE_MII_TURNAROUND; 345 346 /* 347 * Turn on data output. 348 */ 349 MII_SET(STE_PHYCTL_MDIR); 350 351 ste_mii_sync(sc); 352 353 ste_mii_send(sc, frame->mii_stdelim, 2); 354 ste_mii_send(sc, frame->mii_opcode, 2); 355 ste_mii_send(sc, frame->mii_phyaddr, 5); 356 ste_mii_send(sc, frame->mii_regaddr, 5); 357 ste_mii_send(sc, frame->mii_turnaround, 2); 358 ste_mii_send(sc, frame->mii_data, 16); 359 360 /* Idle bit. */ 361 MII_SET(STE_PHYCTL_MCLK); 362 DELAY(1); 363 MII_CLR(STE_PHYCTL_MCLK); 364 DELAY(1); 365 366 /* 367 * Turn off xmit. 368 */ 369 MII_CLR(STE_PHYCTL_MDIR); 370 371 STE_UNLOCK(sc); 372 373 return(0); 374} 375 376static int ste_miibus_readreg(dev, phy, reg) 377 device_t dev; 378 int phy, reg; 379{ 380 struct ste_softc *sc; 381 struct ste_mii_frame frame; 382 383 sc = device_get_softc(dev); 384 385 bzero((char *)&frame, sizeof(frame)); 386 387 frame.mii_phyaddr = phy; 388 frame.mii_regaddr = reg; 389 ste_mii_readreg(sc, &frame); 390 391 return(frame.mii_data); 392} 393 394static int ste_miibus_writereg(dev, phy, reg, data) 395 device_t dev; 396 int phy, reg, data; 397{ 398 struct ste_softc *sc; 399 struct ste_mii_frame frame; 400 401 sc = device_get_softc(dev); 402 bzero((char *)&frame, sizeof(frame)); 403 404 frame.mii_phyaddr = phy; 405 frame.mii_regaddr = reg; 406 frame.mii_data = data; 407 408 ste_mii_writereg(sc, &frame); 409 410 return(0); 411} 412 413static void ste_miibus_statchg(dev) 414 device_t dev; 415{ 416 struct ste_softc *sc; 417 struct mii_data *mii; 418 419 sc = device_get_softc(dev); 420 STE_LOCK(sc); 421 mii = device_get_softc(sc->ste_miibus); 422 423 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 424 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 425 } else { 426 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 427 } 428 STE_UNLOCK(sc); 429 430 return; 431} 432 433static int ste_ifmedia_upd(ifp) 434 struct ifnet *ifp; 435{ 436 struct ste_softc *sc; 437 struct mii_data *mii; 438 439 sc = ifp->if_softc; 440 mii = device_get_softc(sc->ste_miibus); 441 sc->ste_link = 0; 442 if (mii->mii_instance) { 443 struct mii_softc *miisc; 444 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 445 mii_phy_reset(miisc); 446 } 447 mii_mediachg(mii); 448 449 return(0); 450} 451 452static void ste_ifmedia_sts(ifp, ifmr) 453 struct ifnet *ifp; 454 struct ifmediareq *ifmr; 455{ 456 struct ste_softc *sc; 457 struct mii_data *mii; 458 459 sc = ifp->if_softc; 460 mii = device_get_softc(sc->ste_miibus); 461 462 mii_pollstat(mii); 463 ifmr->ifm_active = mii->mii_media_active; 464 ifmr->ifm_status = mii->mii_media_status; 465 466 return; 467} 468 469static void ste_wait(sc) 470 struct ste_softc *sc; 471{ 472 register int i; 473 474 for (i = 0; i < STE_TIMEOUT; i++) { 475 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 476 break; 477 } 478 479 if (i == STE_TIMEOUT) 480 printf("ste%d: command never completed!\n", sc->ste_unit); 481 482 return; 483} 484 485/* 486 * The EEPROM is slow: give it time to come ready after issuing 487 * it a command. 488 */ 489static int ste_eeprom_wait(sc) 490 struct ste_softc *sc; 491{ 492 int i; 493 494 DELAY(1000); 495 496 for (i = 0; i < 100; i++) { 497 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 498 DELAY(1000); 499 else 500 break; 501 } 502 503 if (i == 100) { 504 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 505 return(1); 506 } 507 508 return(0); 509} 510 511/* 512 * Read a sequence of words from the EEPROM. Note that ethernet address 513 * data is stored in the EEPROM in network byte order. 514 */ 515static int ste_read_eeprom(sc, dest, off, cnt, swap) 516 struct ste_softc *sc; 517 caddr_t dest; 518 int off; 519 int cnt; 520 int swap; 521{ 522 int err = 0, i; 523 u_int16_t word = 0, *ptr; 524 525 if (ste_eeprom_wait(sc)) 526 return(1); 527 528 for (i = 0; i < cnt; i++) { 529 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 530 err = ste_eeprom_wait(sc); 531 if (err) 532 break; 533 word = CSR_READ_2(sc, STE_EEPROM_DATA); 534 ptr = (u_int16_t *)(dest + (i * 2)); 535 if (swap) 536 *ptr = ntohs(word); 537 else 538 *ptr = word; 539 } 540 541 return(err ? 1 : 0); 542} 543 544static u_int8_t ste_calchash(addr) 545 caddr_t addr; 546{ 547 548 u_int32_t crc, carry; 549 int i, j; 550 u_int8_t c; 551 552 /* Compute CRC for the address value. */ 553 crc = 0xFFFFFFFF; /* initial value */ 554 555 for (i = 0; i < 6; i++) { 556 c = *(addr + i); 557 for (j = 0; j < 8; j++) { 558 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 559 crc <<= 1; 560 c >>= 1; 561 if (carry) 562 crc = (crc ^ 0x04c11db6) | carry; 563 } 564 } 565 566 /* return the filter bit position */ 567 return(crc & 0x0000003F); 568} 569 570static void ste_setmulti(sc) 571 struct ste_softc *sc; 572{ 573 struct ifnet *ifp; 574 int h = 0; 575 u_int32_t hashes[2] = { 0, 0 }; 576 struct ifmultiaddr *ifma; 577 578 ifp = &sc->arpcom.ac_if; 579 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 580 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 581 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 582 return; 583 } 584 585 /* first, zot all the existing hash bits */ 586 CSR_WRITE_2(sc, STE_MAR0, 0); 587 CSR_WRITE_2(sc, STE_MAR1, 0); 588 CSR_WRITE_2(sc, STE_MAR2, 0); 589 CSR_WRITE_2(sc, STE_MAR3, 0); 590 591 /* now program new ones */ 592 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 593 if (ifma->ifma_addr->sa_family != AF_LINK) 594 continue; 595 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 596 if (h < 32) 597 hashes[0] |= (1 << h); 598 else 599 hashes[1] |= (1 << (h - 32)); 600 } 601 602 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 603 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 604 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 605 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 606 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 607 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 608 609 return; 610} 611 612static void ste_intr(xsc) 613 void *xsc; 614{ 615 struct ste_softc *sc; 616 struct ifnet *ifp; 617 u_int16_t status; 618 619 sc = xsc; 620 STE_LOCK(sc); 621 ifp = &sc->arpcom.ac_if; 622 623 /* See if this is really our interrupt. */ 624 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 625 STE_UNLOCK(sc); 626 return; 627 } 628 629 for (;;) { 630 status = CSR_READ_2(sc, STE_ISR_ACK); 631 632 if (!(status & STE_INTRS)) 633 break; 634 635 if (status & STE_ISR_RX_DMADONE) 636 ste_rxeof(sc); 637 638 if (status & STE_ISR_TX_DMADONE) 639 ste_txeof(sc); 640 641 if (status & STE_ISR_TX_DONE) 642 ste_txeoc(sc); 643 644 if (status & STE_ISR_STATS_OFLOW) { 645 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 646 ste_stats_update(sc); 647 } 648 649 if (status & STE_ISR_HOSTERR) { 650 ste_reset(sc); 651 ste_init(sc); 652 } 653 } 654 655 /* Re-enable interrupts */ 656 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 657 658 if (ifp->if_snd.ifq_head != NULL) 659 ste_start(ifp); 660 661 STE_UNLOCK(sc); 662 663 return; 664} 665 666/* 667 * A frame has been uploaded: pass the resulting mbuf chain up to 668 * the higher level protocols. 669 */ 670static void ste_rxeof(sc) 671 struct ste_softc *sc; 672{ 673 struct ether_header *eh; 674 struct mbuf *m; 675 struct ifnet *ifp; 676 struct ste_chain_onefrag *cur_rx; 677 int total_len = 0; 678 u_int32_t rxstat; 679 680 ifp = &sc->arpcom.ac_if; 681 682again: 683 684 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) { 685 cur_rx = sc->ste_cdata.ste_rx_head; 686 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 687 688 /* 689 * If an error occurs, update stats, clear the 690 * status word and leave the mbuf cluster in place: 691 * it should simply get re-used next time this descriptor 692 * comes up in the ring. 693 */ 694 if (rxstat & STE_RXSTAT_FRAME_ERR) { 695 ifp->if_ierrors++; 696 cur_rx->ste_ptr->ste_status = 0; 697 continue; 698 } 699 700 /* 701 * If there error bit was not set, the upload complete 702 * bit should be set which means we have a valid packet. 703 * If not, something truly strange has happened. 704 */ 705 if (!(rxstat & STE_RXSTAT_DMADONE)) { 706 printf("ste%d: bad receive status -- packet dropped", 707 sc->ste_unit); 708 ifp->if_ierrors++; 709 cur_rx->ste_ptr->ste_status = 0; 710 continue; 711 } 712 713 /* No errors; receive the packet. */ 714 m = cur_rx->ste_mbuf; 715 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 716 717 /* 718 * Try to conjure up a new mbuf cluster. If that 719 * fails, it means we have an out of memory condition and 720 * should leave the buffer in place and continue. This will 721 * result in a lost packet, but there's little else we 722 * can do in this situation. 723 */ 724 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 725 ifp->if_ierrors++; 726 cur_rx->ste_ptr->ste_status = 0; 727 continue; 728 } 729 730 ifp->if_ipackets++; 731 eh = mtod(m, struct ether_header *); 732 m->m_pkthdr.rcvif = ifp; 733 m->m_pkthdr.len = m->m_len = total_len; 734 735 /* Remove header from mbuf and pass it on. */ 736 m_adj(m, sizeof(struct ether_header)); 737 ether_input(ifp, eh, m); 738 } 739 740 /* 741 * Handle the 'end of channel' condition. When the upload 742 * engine hits the end of the RX ring, it will stall. This 743 * is our cue to flush the RX ring, reload the uplist pointer 744 * register and unstall the engine. 745 * XXX This is actually a little goofy. With the ThunderLAN 746 * chip, you get an interrupt when the receiver hits the end 747 * of the receive ring, which tells you exactly when you 748 * you need to reload the ring pointer. Here we have to 749 * fake it. I'm mad at myself for not being clever enough 750 * to avoid the use of a goto here. 751 */ 752 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 || 753 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) { 754 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 755 ste_wait(sc); 756 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 757 vtophys(&sc->ste_ldata->ste_rx_list[0])); 758 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0]; 759 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 760 goto again; 761 } 762 763 return; 764} 765 766static void ste_txeoc(sc) 767 struct ste_softc *sc; 768{ 769 u_int8_t txstat; 770 struct ifnet *ifp; 771 772 ifp = &sc->arpcom.ac_if; 773 774 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 775 STE_TXSTATUS_TXDONE) { 776 if (txstat & STE_TXSTATUS_UNDERRUN || 777 txstat & STE_TXSTATUS_EXCESSCOLLS || 778 txstat & STE_TXSTATUS_RECLAIMERR) { 779 ifp->if_oerrors++; 780 printf("ste%d: transmission error: %x\n", 781 sc->ste_unit, txstat); 782 783 ste_reset(sc); 784 ste_init(sc); 785 786 if (txstat & STE_TXSTATUS_UNDERRUN && 787 sc->ste_tx_thresh < STE_PACKET_SIZE) { 788 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 789 printf("ste%d: tx underrun, increasing tx" 790 " start threshold to %d bytes\n", 791 sc->ste_unit, sc->ste_tx_thresh); 792 } 793 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 794 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 795 (STE_PACKET_SIZE >> 4)); 796 } 797 ste_init(sc); 798 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 799 } 800 801 return; 802} 803 804static void ste_txeof(sc) 805 struct ste_softc *sc; 806{ 807 struct ste_chain *cur_tx = NULL; 808 struct ifnet *ifp; 809 int idx; 810 811 ifp = &sc->arpcom.ac_if; 812 813 idx = sc->ste_cdata.ste_tx_cons; 814 while(idx != sc->ste_cdata.ste_tx_prod) { 815 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 816 817 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 818 break; 819 820 if (cur_tx->ste_mbuf != NULL) { 821 m_freem(cur_tx->ste_mbuf); 822 cur_tx->ste_mbuf = NULL; 823 } 824 825 ifp->if_opackets++; 826 827 sc->ste_cdata.ste_tx_cnt--; 828 STE_INC(idx, STE_TX_LIST_CNT); 829 ifp->if_timer = 0; 830 } 831 832 sc->ste_cdata.ste_tx_cons = idx; 833 834 if (cur_tx != NULL) 835 ifp->if_flags &= ~IFF_OACTIVE; 836 837 return; 838} 839 840static void ste_stats_update(xsc) 841 void *xsc; 842{ 843 struct ste_softc *sc; 844 struct ste_stats stats; 845 struct ifnet *ifp; 846 struct mii_data *mii; 847 int i; 848 u_int8_t *p; 849 850 sc = xsc; 851 STE_LOCK(sc); 852 853 ifp = &sc->arpcom.ac_if; 854 mii = device_get_softc(sc->ste_miibus); 855 856 p = (u_int8_t *)&stats; 857 858 for (i = 0; i < sizeof(stats); i++) { 859 *p = CSR_READ_1(sc, STE_STATS + i); 860 p++; 861 } 862 863 ifp->if_collisions += stats.ste_single_colls + 864 stats.ste_multi_colls + stats.ste_late_colls; 865 866 mii_tick(mii); 867 if (!sc->ste_link && mii->mii_media_status & IFM_ACTIVE && 868 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 869 sc->ste_link++; 870 if (ifp->if_snd.ifq_head != NULL) 871 ste_start(ifp); 872 } 873 874 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 875 STE_UNLOCK(sc); 876 877 return; 878} 879 880 881/* 882 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 883 * IDs against our list and return a device name if we find a match. 884 */ 885static int ste_probe(dev) 886 device_t dev; 887{ 888 struct ste_type *t; 889 890 t = ste_devs; 891 892 while(t->ste_name != NULL) { 893 if ((pci_get_vendor(dev) == t->ste_vid) && 894 (pci_get_device(dev) == t->ste_did)) { 895 device_set_desc(dev, t->ste_name); 896 return(0); 897 } 898 t++; 899 } 900 901 return(ENXIO); 902} 903 904/* 905 * Attach the interface. Allocate softc structures, do ifmedia 906 * setup and ethernet/BPF attach. 907 */ 908static int ste_attach(dev) 909 device_t dev; 910{ 911 u_int32_t command; 912 struct ste_softc *sc; 913 struct ifnet *ifp; 914 int unit, error = 0, rid; 915 916 sc = device_get_softc(dev); 917 unit = device_get_unit(dev); 918 bzero(sc, sizeof(struct ste_softc)); 919 920 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 921 STE_LOCK(sc); 922 923 /* 924 * Handle power management nonsense. 925 */ 926 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 927 u_int32_t iobase, membase, irq; 928 929 /* Save important PCI config data. */ 930 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 931 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 932 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 933 934 /* Reset the power state. */ 935 printf("ste%d: chip is in D%d power mode " 936 "-- setting to D0\n", unit, 937 pci_get_powerstate(dev)); 938 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 939 940 /* Restore PCI config data. */ 941 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 942 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 943 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 944 } 945 946 /* 947 * Map control/status registers. 948 */ 949 pci_enable_busmaster(dev); 950 pci_enable_io(dev, SYS_RES_IOPORT); 951 pci_enable_io(dev, SYS_RES_MEMORY); 952 command = pci_read_config(dev, PCIR_COMMAND, 4); 953 954#ifdef STE_USEIOSPACE 955 if (!(command & PCIM_CMD_PORTEN)) { 956 printf("ste%d: failed to enable I/O ports!\n", unit); 957 error = ENXIO; 958 goto fail; 959 } 960#else 961 if (!(command & PCIM_CMD_MEMEN)) { 962 printf("ste%d: failed to enable memory mapping!\n", unit); 963 error = ENXIO; 964 goto fail; 965 } 966#endif 967 968 rid = STE_RID; 969 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 970 0, ~0, 1, RF_ACTIVE); 971 972 if (sc->ste_res == NULL) { 973 printf ("ste%d: couldn't map ports/memory\n", unit); 974 error = ENXIO; 975 goto fail; 976 } 977 978 sc->ste_btag = rman_get_bustag(sc->ste_res); 979 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 980 981 rid = 0; 982 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 983 RF_SHAREABLE | RF_ACTIVE); 984 985 if (sc->ste_irq == NULL) { 986 printf("ste%d: couldn't map interrupt\n", unit); 987 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 988 error = ENXIO; 989 goto fail; 990 } 991 992 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 993 ste_intr, sc, &sc->ste_intrhand); 994 995 if (error) { 996 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 997 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 998 printf("ste%d: couldn't set up irq\n", unit); 999 goto fail; 1000 } 1001 1002 callout_handle_init(&sc->ste_stat_ch); 1003 1004 /* Reset the adapter. */ 1005 ste_reset(sc); 1006 1007 /* 1008 * Get station address from the EEPROM. 1009 */ 1010 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1011 STE_EEADDR_NODE0, 3, 0)) { 1012 printf("ste%d: failed to read station address\n", unit); 1013 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1014 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1015 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1016 error = ENXIO;; 1017 goto fail; 1018 } 1019 1020 /* 1021 * A Sundance chip was detected. Inform the world. 1022 */ 1023 printf("ste%d: Ethernet address: %6D\n", unit, 1024 sc->arpcom.ac_enaddr, ":"); 1025 1026 sc->ste_unit = unit; 1027 1028 /* Allocate the descriptor queues. */ 1029 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1030 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1031 1032 if (sc->ste_ldata == NULL) { 1033 printf("ste%d: no memory for list buffers!\n", unit); 1034 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1035 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1036 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1037 error = ENXIO; 1038 goto fail; 1039 } 1040 1041 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1042 1043 /* Do MII setup. */ 1044 if (mii_phy_probe(dev, &sc->ste_miibus, 1045 ste_ifmedia_upd, ste_ifmedia_sts)) { 1046 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1047 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1048 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1049 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1050 contigfree(sc->ste_ldata, 1051 sizeof(struct ste_list_data), M_DEVBUF); 1052 error = ENXIO; 1053 goto fail; 1054 } 1055 1056 ifp = &sc->arpcom.ac_if; 1057 ifp->if_softc = sc; 1058 ifp->if_unit = unit; 1059 ifp->if_name = "ste"; 1060 ifp->if_mtu = ETHERMTU; 1061 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1062 ifp->if_ioctl = ste_ioctl; 1063 ifp->if_output = ether_output; 1064 ifp->if_start = ste_start; 1065 ifp->if_watchdog = ste_watchdog; 1066 ifp->if_init = ste_init; 1067 ifp->if_baudrate = 10000000; 1068 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1069 1070 /* 1071 * Call MI attach routine. 1072 */ 1073 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1074 STE_UNLOCK(sc); 1075 return(0); 1076 1077fail: 1078 STE_UNLOCK(sc); 1079 mtx_destroy(&sc->ste_mtx); 1080 return(error); 1081} 1082 1083static int ste_detach(dev) 1084 device_t dev; 1085{ 1086 struct ste_softc *sc; 1087 struct ifnet *ifp; 1088 1089 sc = device_get_softc(dev); 1090 STE_LOCK(sc); 1091 ifp = &sc->arpcom.ac_if; 1092 1093 ste_stop(sc); 1094 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1095 1096 bus_generic_detach(dev); 1097 device_delete_child(dev, sc->ste_miibus); 1098 1099 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1100 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1101 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1102 1103 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1104 1105 STE_UNLOCK(sc); 1106 mtx_destroy(&sc->ste_mtx); 1107 1108 return(0); 1109} 1110 1111static int ste_newbuf(sc, c, m) 1112 struct ste_softc *sc; 1113 struct ste_chain_onefrag *c; 1114 struct mbuf *m; 1115{ 1116 struct mbuf *m_new = NULL; 1117 1118 if (m == NULL) { 1119 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1120 if (m_new == NULL) { 1121 printf("ste%d: no memory for rx list -- " 1122 "packet dropped\n", sc->ste_unit); 1123 return(ENOBUFS); 1124 } 1125 MCLGET(m_new, M_DONTWAIT); 1126 if (!(m_new->m_flags & M_EXT)) { 1127 printf("ste%d: no memory for rx list -- " 1128 "packet dropped\n", sc->ste_unit); 1129 m_freem(m_new); 1130 return(ENOBUFS); 1131 } 1132 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1133 } else { 1134 m_new = m; 1135 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1136 m_new->m_data = m_new->m_ext.ext_buf; 1137 } 1138 1139 m_adj(m_new, ETHER_ALIGN); 1140 1141 c->ste_mbuf = m_new; 1142 c->ste_ptr->ste_status = 0; 1143 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1144 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; 1145 1146 return(0); 1147} 1148 1149static int ste_init_rx_list(sc) 1150 struct ste_softc *sc; 1151{ 1152 struct ste_chain_data *cd; 1153 struct ste_list_data *ld; 1154 int i; 1155 1156 cd = &sc->ste_cdata; 1157 ld = sc->ste_ldata; 1158 1159 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1160 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1161 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1162 return(ENOBUFS); 1163 if (i == (STE_RX_LIST_CNT - 1)) { 1164 cd->ste_rx_chain[i].ste_next = 1165 &cd->ste_rx_chain[0]; 1166 ld->ste_rx_list[i].ste_next = 1167 vtophys(&ld->ste_rx_list[0]); 1168 } else { 1169 cd->ste_rx_chain[i].ste_next = 1170 &cd->ste_rx_chain[i + 1]; 1171 ld->ste_rx_list[i].ste_next = 1172 vtophys(&ld->ste_rx_list[i + 1]); 1173 } 1174 1175 } 1176 1177 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1178 1179 return(0); 1180} 1181 1182static void ste_init_tx_list(sc) 1183 struct ste_softc *sc; 1184{ 1185 struct ste_chain_data *cd; 1186 struct ste_list_data *ld; 1187 int i; 1188 1189 cd = &sc->ste_cdata; 1190 ld = sc->ste_ldata; 1191 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1192 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1193 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1194 if (i == (STE_TX_LIST_CNT - 1)) 1195 cd->ste_tx_chain[i].ste_next = 1196 &cd->ste_tx_chain[0]; 1197 else 1198 cd->ste_tx_chain[i].ste_next = 1199 &cd->ste_tx_chain[i + 1]; 1200 if (i == 0) 1201 cd->ste_tx_chain[i].ste_prev = 1202 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1203 else 1204 cd->ste_tx_chain[i].ste_prev = 1205 &cd->ste_tx_chain[i - 1]; 1206 } 1207 1208 1209 bzero((char *)ld->ste_tx_list, 1210 sizeof(struct ste_desc) * STE_TX_LIST_CNT); 1211 1212 cd->ste_tx_prod = 0; 1213 cd->ste_tx_cons = 0; 1214 cd->ste_tx_cnt = 0; 1215 1216 return; 1217} 1218 1219static void ste_init(xsc) 1220 void *xsc; 1221{ 1222 struct ste_softc *sc; 1223 int i; 1224 struct ifnet *ifp; 1225 struct mii_data *mii; 1226 1227 sc = xsc; 1228 STE_LOCK(sc); 1229 ifp = &sc->arpcom.ac_if; 1230 mii = device_get_softc(sc->ste_miibus); 1231 1232 ste_stop(sc); 1233 1234 /* Init our MAC address */ 1235 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1236 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1237 } 1238 1239 /* Init RX list */ 1240 if (ste_init_rx_list(sc) == ENOBUFS) { 1241 printf("ste%d: initialization failed: no " 1242 "memory for RX buffers\n", sc->ste_unit); 1243 ste_stop(sc); 1244 STE_UNLOCK(sc); 1245 return; 1246 } 1247 1248 /* Init TX descriptors */ 1249 ste_init_tx_list(sc); 1250 1251 /* Set the TX freethresh value */ 1252 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1253 1254 /* Set the TX start threshold for best performance. */ 1255 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1256 1257 /* Set the TX reclaim threshold. */ 1258 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1259 1260 /* Set up the RX filter. */ 1261 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1262 1263 /* If we want promiscuous mode, set the allframes bit. */ 1264 if (ifp->if_flags & IFF_PROMISC) { 1265 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1266 } else { 1267 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1268 } 1269 1270 /* Set capture broadcast bit to accept broadcast frames. */ 1271 if (ifp->if_flags & IFF_BROADCAST) { 1272 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1273 } else { 1274 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1275 } 1276 1277 ste_setmulti(sc); 1278 1279 /* Load the address of the RX list. */ 1280 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1281 ste_wait(sc); 1282 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1283 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1284 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1285 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1286 1287 /* Set TX polling interval */ 1288 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1289 1290 /* Load address of the TX list */ 1291 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1292 ste_wait(sc); 1293 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1294 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1295 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1296 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1297 ste_wait(sc); 1298 1299 /* Enable receiver and transmitter */ 1300 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1301 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1302 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1303 1304 /* Enable stats counters. */ 1305 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1306 1307 /* Enable interrupts. */ 1308 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1309 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1310 1311 ste_ifmedia_upd(ifp); 1312 1313 ifp->if_flags |= IFF_RUNNING; 1314 ifp->if_flags &= ~IFF_OACTIVE; 1315 1316 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1317 STE_UNLOCK(sc); 1318 1319 return; 1320} 1321 1322static void ste_stop(sc) 1323 struct ste_softc *sc; 1324{ 1325 int i; 1326 struct ifnet *ifp; 1327 1328 STE_LOCK(sc); 1329 ifp = &sc->arpcom.ac_if; 1330 1331 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1332 1333 CSR_WRITE_2(sc, STE_IMR, 0); 1334 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1335 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1336 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1337 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1338 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1339 ste_wait(sc); 1340 1341 sc->ste_link = 0; 1342 1343 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1344 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1345 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1346 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1347 } 1348 } 1349 1350 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1351 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1352 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1353 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1354 } 1355 } 1356 1357 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1358 STE_UNLOCK(sc); 1359 1360 return; 1361} 1362 1363static void ste_reset(sc) 1364 struct ste_softc *sc; 1365{ 1366 int i; 1367 1368 STE_SETBIT4(sc, STE_ASICCTL, 1369 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1370 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1371 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1372 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1373 STE_ASICCTL_EXTRESET_RESET); 1374 1375 DELAY(100000); 1376 1377 for (i = 0; i < STE_TIMEOUT; i++) { 1378 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1379 break; 1380 } 1381 1382 if (i == STE_TIMEOUT) 1383 printf("ste%d: global reset never completed\n", sc->ste_unit); 1384 1385 return; 1386} 1387 1388static int ste_ioctl(ifp, command, data) 1389 struct ifnet *ifp; 1390 u_long command; 1391 caddr_t data; 1392{ 1393 struct ste_softc *sc; 1394 struct ifreq *ifr; 1395 struct mii_data *mii; 1396 int error = 0; 1397 1398 sc = ifp->if_softc; 1399 STE_LOCK(sc); 1400 ifr = (struct ifreq *)data; 1401 1402 switch(command) { 1403 case SIOCSIFADDR: 1404 case SIOCGIFADDR: 1405 case SIOCSIFMTU: 1406 error = ether_ioctl(ifp, command, data); 1407 break; 1408 case SIOCSIFFLAGS: 1409 if (ifp->if_flags & IFF_UP) { 1410 if (ifp->if_flags & IFF_RUNNING && 1411 ifp->if_flags & IFF_PROMISC && 1412 !(sc->ste_if_flags & IFF_PROMISC)) { 1413 STE_SETBIT1(sc, STE_RX_MODE, 1414 STE_RXMODE_PROMISC); 1415 } else if (ifp->if_flags & IFF_RUNNING && 1416 !(ifp->if_flags & IFF_PROMISC) && 1417 sc->ste_if_flags & IFF_PROMISC) { 1418 STE_CLRBIT1(sc, STE_RX_MODE, 1419 STE_RXMODE_PROMISC); 1420 } else if (!(ifp->if_flags & IFF_RUNNING)) { 1421 sc->ste_tx_thresh = STE_MIN_FRAMELEN; 1422 ste_init(sc); 1423 } 1424 } else { 1425 if (ifp->if_flags & IFF_RUNNING) 1426 ste_stop(sc); 1427 } 1428 sc->ste_if_flags = ifp->if_flags; 1429 error = 0; 1430 break; 1431 case SIOCADDMULTI: 1432 case SIOCDELMULTI: 1433 ste_setmulti(sc); 1434 error = 0; 1435 break; 1436 case SIOCGIFMEDIA: 1437 case SIOCSIFMEDIA: 1438 mii = device_get_softc(sc->ste_miibus); 1439 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1440 break; 1441 default: 1442 error = EINVAL; 1443 break; 1444 } 1445 1446 STE_UNLOCK(sc); 1447 1448 return(error); 1449} 1450 1451static int ste_encap(sc, c, m_head) 1452 struct ste_softc *sc; 1453 struct ste_chain *c; 1454 struct mbuf *m_head; 1455{ 1456 int frag = 0; 1457 struct ste_frag *f = NULL; 1458 struct mbuf *m; 1459 struct ste_desc *d; 1460 int total_len = 0; 1461 1462 d = c->ste_ptr; 1463 d->ste_ctl = 0; 1464 d->ste_next = 0; 1465 1466 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1467 if (m->m_len != 0) { 1468 if (frag == STE_MAXFRAGS) 1469 break; 1470 total_len += m->m_len; 1471 f = &c->ste_ptr->ste_frags[frag]; 1472 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1473 f->ste_len = m->m_len; 1474 frag++; 1475 } 1476 } 1477 1478 c->ste_mbuf = m_head; 1479 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1480 c->ste_ptr->ste_ctl = total_len; 1481 1482 return(0); 1483} 1484 1485static void ste_start(ifp) 1486 struct ifnet *ifp; 1487{ 1488 struct ste_softc *sc; 1489 struct mbuf *m_head = NULL; 1490 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1491 int idx; 1492 1493 sc = ifp->if_softc; 1494 STE_LOCK(sc); 1495 1496 if (!sc->ste_link) { 1497 STE_UNLOCK(sc); 1498 return; 1499 } 1500 1501 if (ifp->if_flags & IFF_OACTIVE) { 1502 STE_UNLOCK(sc); 1503 return; 1504 } 1505 1506 idx = sc->ste_cdata.ste_tx_prod; 1507 start_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1508 1509 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1510 1511 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1512 ifp->if_flags |= IFF_OACTIVE; 1513 break; 1514 } 1515 1516 IF_DEQUEUE(&ifp->if_snd, m_head); 1517 if (m_head == NULL) 1518 break; 1519 1520 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1521 1522 ste_encap(sc, cur_tx, m_head); 1523 1524 if (prev != NULL) 1525 prev->ste_ptr->ste_next = cur_tx->ste_phys; 1526 prev = cur_tx; 1527 1528 /* 1529 * If there's a BPF listener, bounce a copy of this frame 1530 * to him. 1531 */ 1532 if (ifp->if_bpf) 1533 bpf_mtap(ifp, cur_tx->ste_mbuf); 1534 1535 STE_INC(idx, STE_TX_LIST_CNT); 1536 sc->ste_cdata.ste_tx_cnt++; 1537 } 1538 1539 if (cur_tx == NULL) { 1540 STE_UNLOCK(sc); 1541 return; 1542 } 1543 1544 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR; 1545 1546 /* Start transmission */ 1547 sc->ste_cdata.ste_tx_prod = idx; 1548 start_tx->ste_prev->ste_ptr->ste_next = start_tx->ste_phys; 1549 1550 ifp->if_timer = 5; 1551 STE_UNLOCK(sc); 1552 1553 return; 1554} 1555 1556static void ste_watchdog(ifp) 1557 struct ifnet *ifp; 1558{ 1559 struct ste_softc *sc; 1560 1561 sc = ifp->if_softc; 1562 STE_LOCK(sc); 1563 1564 ifp->if_oerrors++; 1565 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1566 1567 ste_txeoc(sc); 1568 ste_txeof(sc); 1569 ste_rxeof(sc); 1570 ste_reset(sc); 1571 ste_init(sc); 1572 1573 if (ifp->if_snd.ifq_head != NULL) 1574 ste_start(ifp); 1575 STE_UNLOCK(sc); 1576 1577 return; 1578} 1579 1580static void ste_shutdown(dev) 1581 device_t dev; 1582{ 1583 struct ste_softc *sc; 1584 1585 sc = device_get_softc(dev); 1586 1587 ste_stop(sc); 1588 1589 return; 1590} 1591