if_ste.c revision 71228
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 71228 2001-01-19 01:59:14Z bmilekic $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48 49#include <net/bpf.h> 50 51#include <vm/vm.h> /* for vtophys */ 52#include <vm/pmap.h> /* for vtophys */ 53#include <machine/bus_memio.h> 54#include <machine/bus_pio.h> 55#include <machine/bus.h> 56#include <machine/resource.h> 57#include <sys/bus.h> 58#include <sys/rman.h> 59 60#include <dev/mii/mii.h> 61#include <dev/mii/miivar.h> 62 63#include <pci/pcireg.h> 64#include <pci/pcivar.h> 65 66/* "controller miibus0" required. See GENERIC if you get errors here. */ 67#include "miibus_if.h" 68 69#define STE_USEIOSPACE 70 71#include <pci/if_stereg.h> 72 73MODULE_DEPEND(ste, miibus, 1, 1, 1); 74 75#if !defined(lint) 76static const char rcsid[] = 77 "$FreeBSD: head/sys/pci/if_ste.c 71228 2001-01-19 01:59:14Z bmilekic $"; 78#endif 79 80/* 81 * Various supported device vendors/types and their names. 82 */ 83static struct ste_type ste_devs[] = { 84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 85 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 86 { 0, 0, NULL } 87}; 88 89static int ste_probe __P((device_t)); 90static int ste_attach __P((device_t)); 91static int ste_detach __P((device_t)); 92static void ste_init __P((void *)); 93static void ste_intr __P((void *)); 94static void ste_rxeof __P((struct ste_softc *)); 95static void ste_txeoc __P((struct ste_softc *)); 96static void ste_txeof __P((struct ste_softc *)); 97static void ste_stats_update __P((void *)); 98static void ste_stop __P((struct ste_softc *)); 99static void ste_reset __P((struct ste_softc *)); 100static int ste_ioctl __P((struct ifnet *, u_long, caddr_t)); 101static int ste_encap __P((struct ste_softc *, struct ste_chain *, 102 struct mbuf *)); 103static void ste_start __P((struct ifnet *)); 104static void ste_watchdog __P((struct ifnet *)); 105static void ste_shutdown __P((device_t)); 106static int ste_newbuf __P((struct ste_softc *, 107 struct ste_chain_onefrag *, 108 struct mbuf *)); 109static int ste_ifmedia_upd __P((struct ifnet *)); 110static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 111 112static void ste_mii_sync __P((struct ste_softc *)); 113static void ste_mii_send __P((struct ste_softc *, u_int32_t, int)); 114static int ste_mii_readreg __P((struct ste_softc *, 115 struct ste_mii_frame *)); 116static int ste_mii_writereg __P((struct ste_softc *, 117 struct ste_mii_frame *)); 118static int ste_miibus_readreg __P((device_t, int, int)); 119static int ste_miibus_writereg __P((device_t, int, int, int)); 120static void ste_miibus_statchg __P((device_t)); 121 122static int ste_eeprom_wait __P((struct ste_softc *)); 123static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int, 124 int, int)); 125static void ste_wait __P((struct ste_softc *)); 126static u_int8_t ste_calchash __P((caddr_t)); 127static void ste_setmulti __P((struct ste_softc *)); 128static int ste_init_rx_list __P((struct ste_softc *)); 129static void ste_init_tx_list __P((struct ste_softc *)); 130 131#ifdef STE_USEIOSPACE 132#define STE_RES SYS_RES_IOPORT 133#define STE_RID STE_PCI_LOIO 134#else 135#define STE_RES SYS_RES_MEMORY 136#define STE_RID STE_PCI_LOMEM 137#endif 138 139static device_method_t ste_methods[] = { 140 /* Device interface */ 141 DEVMETHOD(device_probe, ste_probe), 142 DEVMETHOD(device_attach, ste_attach), 143 DEVMETHOD(device_detach, ste_detach), 144 DEVMETHOD(device_shutdown, ste_shutdown), 145 146 /* bus interface */ 147 DEVMETHOD(bus_print_child, bus_generic_print_child), 148 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 149 150 /* MII interface */ 151 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 152 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 153 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 154 155 { 0, 0 } 156}; 157 158static driver_t ste_driver = { 159 "ste", 160 ste_methods, 161 sizeof(struct ste_softc) 162}; 163 164static devclass_t ste_devclass; 165 166DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 167DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 168 169#define STE_SETBIT4(sc, reg, x) \ 170 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 171 172#define STE_CLRBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 174 175#define STE_SETBIT2(sc, reg, x) \ 176 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 177 178#define STE_CLRBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 180 181#define STE_SETBIT1(sc, reg, x) \ 182 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 183 184#define STE_CLRBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 186 187 188#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 189#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 190 191/* 192 * Sync the PHYs by setting data bit and strobing the clock 32 times. 193 */ 194static void ste_mii_sync(sc) 195 struct ste_softc *sc; 196{ 197 register int i; 198 199 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 200 201 for (i = 0; i < 32; i++) { 202 MII_SET(STE_PHYCTL_MCLK); 203 DELAY(1); 204 MII_CLR(STE_PHYCTL_MCLK); 205 DELAY(1); 206 } 207 208 return; 209} 210 211/* 212 * Clock a series of bits through the MII. 213 */ 214static void ste_mii_send(sc, bits, cnt) 215 struct ste_softc *sc; 216 u_int32_t bits; 217 int cnt; 218{ 219 int i; 220 221 MII_CLR(STE_PHYCTL_MCLK); 222 223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 224 if (bits & i) { 225 MII_SET(STE_PHYCTL_MDATA); 226 } else { 227 MII_CLR(STE_PHYCTL_MDATA); 228 } 229 DELAY(1); 230 MII_CLR(STE_PHYCTL_MCLK); 231 DELAY(1); 232 MII_SET(STE_PHYCTL_MCLK); 233 } 234} 235 236/* 237 * Read an PHY register through the MII. 238 */ 239static int ste_mii_readreg(sc, frame) 240 struct ste_softc *sc; 241 struct ste_mii_frame *frame; 242 243{ 244 int i, ack; 245 246 STE_LOCK(sc); 247 248 /* 249 * Set up frame for RX. 250 */ 251 frame->mii_stdelim = STE_MII_STARTDELIM; 252 frame->mii_opcode = STE_MII_READOP; 253 frame->mii_turnaround = 0; 254 frame->mii_data = 0; 255 256 CSR_WRITE_2(sc, STE_PHYCTL, 0); 257 /* 258 * Turn on data xmit. 259 */ 260 MII_SET(STE_PHYCTL_MDIR); 261 262 ste_mii_sync(sc); 263 264 /* 265 * Send command/address info. 266 */ 267 ste_mii_send(sc, frame->mii_stdelim, 2); 268 ste_mii_send(sc, frame->mii_opcode, 2); 269 ste_mii_send(sc, frame->mii_phyaddr, 5); 270 ste_mii_send(sc, frame->mii_regaddr, 5); 271 272 /* Turn off xmit. */ 273 MII_CLR(STE_PHYCTL_MDIR); 274 275 /* Idle bit */ 276 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 277 DELAY(1); 278 MII_SET(STE_PHYCTL_MCLK); 279 DELAY(1); 280 281 /* Check for ack */ 282 MII_CLR(STE_PHYCTL_MCLK); 283 DELAY(1); 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 287 288 /* 289 * Now try reading data bits. If the ack failed, we still 290 * need to clock through 16 cycles to keep the PHY(s) in sync. 291 */ 292 if (ack) { 293 for(i = 0; i < 16; i++) { 294 MII_CLR(STE_PHYCTL_MCLK); 295 DELAY(1); 296 MII_SET(STE_PHYCTL_MCLK); 297 DELAY(1); 298 } 299 goto fail; 300 } 301 302 for (i = 0x8000; i; i >>= 1) { 303 MII_CLR(STE_PHYCTL_MCLK); 304 DELAY(1); 305 if (!ack) { 306 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 307 frame->mii_data |= i; 308 DELAY(1); 309 } 310 MII_SET(STE_PHYCTL_MCLK); 311 DELAY(1); 312 } 313 314fail: 315 316 MII_CLR(STE_PHYCTL_MCLK); 317 DELAY(1); 318 MII_SET(STE_PHYCTL_MCLK); 319 DELAY(1); 320 321 STE_UNLOCK(sc); 322 323 if (ack) 324 return(1); 325 return(0); 326} 327 328/* 329 * Write to a PHY register through the MII. 330 */ 331static int ste_mii_writereg(sc, frame) 332 struct ste_softc *sc; 333 struct ste_mii_frame *frame; 334 335{ 336 STE_LOCK(sc); 337 338 /* 339 * Set up frame for TX. 340 */ 341 342 frame->mii_stdelim = STE_MII_STARTDELIM; 343 frame->mii_opcode = STE_MII_WRITEOP; 344 frame->mii_turnaround = STE_MII_TURNAROUND; 345 346 /* 347 * Turn on data output. 348 */ 349 MII_SET(STE_PHYCTL_MDIR); 350 351 ste_mii_sync(sc); 352 353 ste_mii_send(sc, frame->mii_stdelim, 2); 354 ste_mii_send(sc, frame->mii_opcode, 2); 355 ste_mii_send(sc, frame->mii_phyaddr, 5); 356 ste_mii_send(sc, frame->mii_regaddr, 5); 357 ste_mii_send(sc, frame->mii_turnaround, 2); 358 ste_mii_send(sc, frame->mii_data, 16); 359 360 /* Idle bit. */ 361 MII_SET(STE_PHYCTL_MCLK); 362 DELAY(1); 363 MII_CLR(STE_PHYCTL_MCLK); 364 DELAY(1); 365 366 /* 367 * Turn off xmit. 368 */ 369 MII_CLR(STE_PHYCTL_MDIR); 370 371 STE_UNLOCK(sc); 372 373 return(0); 374} 375 376static int ste_miibus_readreg(dev, phy, reg) 377 device_t dev; 378 int phy, reg; 379{ 380 struct ste_softc *sc; 381 struct ste_mii_frame frame; 382 383 sc = device_get_softc(dev); 384 385 bzero((char *)&frame, sizeof(frame)); 386 387 frame.mii_phyaddr = phy; 388 frame.mii_regaddr = reg; 389 ste_mii_readreg(sc, &frame); 390 391 return(frame.mii_data); 392} 393 394static int ste_miibus_writereg(dev, phy, reg, data) 395 device_t dev; 396 int phy, reg, data; 397{ 398 struct ste_softc *sc; 399 struct ste_mii_frame frame; 400 401 sc = device_get_softc(dev); 402 bzero((char *)&frame, sizeof(frame)); 403 404 frame.mii_phyaddr = phy; 405 frame.mii_regaddr = reg; 406 frame.mii_data = data; 407 408 ste_mii_writereg(sc, &frame); 409 410 return(0); 411} 412 413static void ste_miibus_statchg(dev) 414 device_t dev; 415{ 416 struct ste_softc *sc; 417 struct mii_data *mii; 418 419 sc = device_get_softc(dev); 420 STE_LOCK(sc); 421 mii = device_get_softc(sc->ste_miibus); 422 423 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 424 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 425 } else { 426 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 427 } 428 STE_UNLOCK(sc); 429 430 return; 431} 432 433static int ste_ifmedia_upd(ifp) 434 struct ifnet *ifp; 435{ 436 struct ste_softc *sc; 437 struct mii_data *mii; 438 439 sc = ifp->if_softc; 440 mii = device_get_softc(sc->ste_miibus); 441 sc->ste_link = 0; 442 if (mii->mii_instance) { 443 struct mii_softc *miisc; 444 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 445 miisc = LIST_NEXT(miisc, mii_list)) 446 mii_phy_reset(miisc); 447 } 448 mii_mediachg(mii); 449 450 return(0); 451} 452 453static void ste_ifmedia_sts(ifp, ifmr) 454 struct ifnet *ifp; 455 struct ifmediareq *ifmr; 456{ 457 struct ste_softc *sc; 458 struct mii_data *mii; 459 460 sc = ifp->if_softc; 461 mii = device_get_softc(sc->ste_miibus); 462 463 mii_pollstat(mii); 464 ifmr->ifm_active = mii->mii_media_active; 465 ifmr->ifm_status = mii->mii_media_status; 466 467 return; 468} 469 470static void ste_wait(sc) 471 struct ste_softc *sc; 472{ 473 register int i; 474 475 for (i = 0; i < STE_TIMEOUT; i++) { 476 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 477 break; 478 } 479 480 if (i == STE_TIMEOUT) 481 printf("ste%d: command never completed!\n", sc->ste_unit); 482 483 return; 484} 485 486/* 487 * The EEPROM is slow: give it time to come ready after issuing 488 * it a command. 489 */ 490static int ste_eeprom_wait(sc) 491 struct ste_softc *sc; 492{ 493 int i; 494 495 DELAY(1000); 496 497 for (i = 0; i < 100; i++) { 498 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 499 DELAY(1000); 500 else 501 break; 502 } 503 504 if (i == 100) { 505 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 506 return(1); 507 } 508 509 return(0); 510} 511 512/* 513 * Read a sequence of words from the EEPROM. Note that ethernet address 514 * data is stored in the EEPROM in network byte order. 515 */ 516static int ste_read_eeprom(sc, dest, off, cnt, swap) 517 struct ste_softc *sc; 518 caddr_t dest; 519 int off; 520 int cnt; 521 int swap; 522{ 523 int err = 0, i; 524 u_int16_t word = 0, *ptr; 525 526 if (ste_eeprom_wait(sc)) 527 return(1); 528 529 for (i = 0; i < cnt; i++) { 530 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 531 err = ste_eeprom_wait(sc); 532 if (err) 533 break; 534 word = CSR_READ_2(sc, STE_EEPROM_DATA); 535 ptr = (u_int16_t *)(dest + (i * 2)); 536 if (swap) 537 *ptr = ntohs(word); 538 else 539 *ptr = word; 540 } 541 542 return(err ? 1 : 0); 543} 544 545static u_int8_t ste_calchash(addr) 546 caddr_t addr; 547{ 548 549 u_int32_t crc, carry; 550 int i, j; 551 u_int8_t c; 552 553 /* Compute CRC for the address value. */ 554 crc = 0xFFFFFFFF; /* initial value */ 555 556 for (i = 0; i < 6; i++) { 557 c = *(addr + i); 558 for (j = 0; j < 8; j++) { 559 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 560 crc <<= 1; 561 c >>= 1; 562 if (carry) 563 crc = (crc ^ 0x04c11db6) | carry; 564 } 565 } 566 567 /* return the filter bit position */ 568 return(crc & 0x0000003F); 569} 570 571static void ste_setmulti(sc) 572 struct ste_softc *sc; 573{ 574 struct ifnet *ifp; 575 int h = 0; 576 u_int32_t hashes[2] = { 0, 0 }; 577 struct ifmultiaddr *ifma; 578 579 ifp = &sc->arpcom.ac_if; 580 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 581 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 582 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 583 return; 584 } 585 586 /* first, zot all the existing hash bits */ 587 CSR_WRITE_4(sc, STE_MAR0, 0); 588 CSR_WRITE_4(sc, STE_MAR1, 0); 589 590 /* now program new ones */ 591 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 592 ifma = ifma->ifma_link.le_next) { 593 if (ifma->ifma_addr->sa_family != AF_LINK) 594 continue; 595 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 596 if (h < 32) 597 hashes[0] |= (1 << h); 598 else 599 hashes[1] |= (1 << (h - 32)); 600 } 601 602 CSR_WRITE_4(sc, STE_MAR0, hashes[0]); 603 CSR_WRITE_4(sc, STE_MAR1, hashes[1]); 604 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 605 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 606 607 return; 608} 609 610static void ste_intr(xsc) 611 void *xsc; 612{ 613 struct ste_softc *sc; 614 struct ifnet *ifp; 615 u_int16_t status; 616 617 sc = xsc; 618 STE_LOCK(sc); 619 ifp = &sc->arpcom.ac_if; 620 621 /* See if this is really our interrupt. */ 622 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 623 STE_UNLOCK(sc); 624 return; 625 } 626 627 for (;;) { 628 status = CSR_READ_2(sc, STE_ISR_ACK); 629 630 if (!(status & STE_INTRS)) 631 break; 632 633 if (status & STE_ISR_RX_DMADONE) 634 ste_rxeof(sc); 635 636 if (status & STE_ISR_TX_DMADONE) 637 ste_txeof(sc); 638 639 if (status & STE_ISR_TX_DONE) 640 ste_txeoc(sc); 641 642 if (status & STE_ISR_STATS_OFLOW) { 643 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 644 ste_stats_update(sc); 645 } 646 647 if (status & STE_ISR_HOSTERR) { 648 ste_reset(sc); 649 ste_init(sc); 650 } 651 } 652 653 /* Re-enable interrupts */ 654 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 655 656 if (ifp->if_snd.ifq_head != NULL) 657 ste_start(ifp); 658 659 STE_UNLOCK(sc); 660 661 return; 662} 663 664/* 665 * A frame has been uploaded: pass the resulting mbuf chain up to 666 * the higher level protocols. 667 */ 668static void ste_rxeof(sc) 669 struct ste_softc *sc; 670{ 671 struct ether_header *eh; 672 struct mbuf *m; 673 struct ifnet *ifp; 674 struct ste_chain_onefrag *cur_rx; 675 int total_len = 0; 676 u_int32_t rxstat; 677 678 ifp = &sc->arpcom.ac_if; 679 680again: 681 682 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) { 683 cur_rx = sc->ste_cdata.ste_rx_head; 684 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 685 686 /* 687 * If an error occurs, update stats, clear the 688 * status word and leave the mbuf cluster in place: 689 * it should simply get re-used next time this descriptor 690 * comes up in the ring. 691 */ 692 if (rxstat & STE_RXSTAT_FRAME_ERR) { 693 ifp->if_ierrors++; 694 cur_rx->ste_ptr->ste_status = 0; 695 continue; 696 } 697 698 /* 699 * If there error bit was not set, the upload complete 700 * bit should be set which means we have a valid packet. 701 * If not, something truly strange has happened. 702 */ 703 if (!(rxstat & STE_RXSTAT_DMADONE)) { 704 printf("ste%d: bad receive status -- packet dropped", 705 sc->ste_unit); 706 ifp->if_ierrors++; 707 cur_rx->ste_ptr->ste_status = 0; 708 continue; 709 } 710 711 /* No errors; receive the packet. */ 712 m = cur_rx->ste_mbuf; 713 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 714 715 /* 716 * Try to conjure up a new mbuf cluster. If that 717 * fails, it means we have an out of memory condition and 718 * should leave the buffer in place and continue. This will 719 * result in a lost packet, but there's little else we 720 * can do in this situation. 721 */ 722 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 723 ifp->if_ierrors++; 724 cur_rx->ste_ptr->ste_status = 0; 725 continue; 726 } 727 728 ifp->if_ipackets++; 729 eh = mtod(m, struct ether_header *); 730 m->m_pkthdr.rcvif = ifp; 731 m->m_pkthdr.len = m->m_len = total_len; 732 733 /* Remove header from mbuf and pass it on. */ 734 m_adj(m, sizeof(struct ether_header)); 735 ether_input(ifp, eh, m); 736 } 737 738 /* 739 * Handle the 'end of channel' condition. When the upload 740 * engine hits the end of the RX ring, it will stall. This 741 * is our cue to flush the RX ring, reload the uplist pointer 742 * register and unstall the engine. 743 * XXX This is actually a little goofy. With the ThunderLAN 744 * chip, you get an interrupt when the receiver hits the end 745 * of the receive ring, which tells you exactly when you 746 * you need to reload the ring pointer. Here we have to 747 * fake it. I'm mad at myself for not being clever enough 748 * to avoid the use of a goto here. 749 */ 750 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 || 751 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) { 752 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 753 ste_wait(sc); 754 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 755 vtophys(&sc->ste_ldata->ste_rx_list[0])); 756 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0]; 757 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 758 goto again; 759 } 760 761 return; 762} 763 764static void ste_txeoc(sc) 765 struct ste_softc *sc; 766{ 767 u_int8_t txstat; 768 struct ifnet *ifp; 769 770 ifp = &sc->arpcom.ac_if; 771 772 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 773 STE_TXSTATUS_TXDONE) { 774 if (txstat & STE_TXSTATUS_UNDERRUN || 775 txstat & STE_TXSTATUS_EXCESSCOLLS || 776 txstat & STE_TXSTATUS_RECLAIMERR) { 777 ifp->if_oerrors++; 778 printf("ste%d: transmission error: %x\n", 779 sc->ste_unit, txstat); 780 781 ste_reset(sc); 782 ste_init(sc); 783 784 if (txstat & STE_TXSTATUS_UNDERRUN && 785 sc->ste_tx_thresh < STE_PACKET_SIZE) { 786 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 787 printf("ste%d: tx underrun, increasing tx" 788 " start threshold to %d bytes\n", 789 sc->ste_unit, sc->ste_tx_thresh); 790 } 791 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 792 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 793 (STE_PACKET_SIZE >> 4)); 794 } 795 ste_init(sc); 796 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 797 } 798 799 return; 800} 801 802static void ste_txeof(sc) 803 struct ste_softc *sc; 804{ 805 struct ste_chain *cur_tx = NULL; 806 struct ifnet *ifp; 807 int idx; 808 809 ifp = &sc->arpcom.ac_if; 810 811 idx = sc->ste_cdata.ste_tx_cons; 812 while(idx != sc->ste_cdata.ste_tx_prod) { 813 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 814 815 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 816 break; 817 818 if (cur_tx->ste_mbuf != NULL) { 819 m_freem(cur_tx->ste_mbuf); 820 cur_tx->ste_mbuf = NULL; 821 } 822 823 ifp->if_opackets++; 824 825 sc->ste_cdata.ste_tx_cnt--; 826 STE_INC(idx, STE_TX_LIST_CNT); 827 ifp->if_timer = 0; 828 } 829 830 sc->ste_cdata.ste_tx_cons = idx; 831 832 if (cur_tx != NULL) 833 ifp->if_flags &= ~IFF_OACTIVE; 834 835 return; 836} 837 838static void ste_stats_update(xsc) 839 void *xsc; 840{ 841 struct ste_softc *sc; 842 struct ste_stats stats; 843 struct ifnet *ifp; 844 struct mii_data *mii; 845 int i; 846 u_int8_t *p; 847 848 sc = xsc; 849 STE_LOCK(sc); 850 851 ifp = &sc->arpcom.ac_if; 852 mii = device_get_softc(sc->ste_miibus); 853 854 p = (u_int8_t *)&stats; 855 856 for (i = 0; i < sizeof(stats); i++) { 857 *p = CSR_READ_1(sc, STE_STATS + i); 858 p++; 859 } 860 861 ifp->if_collisions += stats.ste_single_colls + 862 stats.ste_multi_colls + stats.ste_late_colls; 863 864 mii_tick(mii); 865 if (!sc->ste_link) { 866 mii_pollstat(mii); 867 if (mii->mii_media_status & IFM_ACTIVE && 868 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 869 sc->ste_link++; 870 if (ifp->if_snd.ifq_head != NULL) 871 ste_start(ifp); 872 } 873 874 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 875 STE_UNLOCK(sc); 876 877 return; 878} 879 880 881/* 882 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 883 * IDs against our list and return a device name if we find a match. 884 */ 885static int ste_probe(dev) 886 device_t dev; 887{ 888 struct ste_type *t; 889 890 t = ste_devs; 891 892 while(t->ste_name != NULL) { 893 if ((pci_get_vendor(dev) == t->ste_vid) && 894 (pci_get_device(dev) == t->ste_did)) { 895 device_set_desc(dev, t->ste_name); 896 return(0); 897 } 898 t++; 899 } 900 901 return(ENXIO); 902} 903 904/* 905 * Attach the interface. Allocate softc structures, do ifmedia 906 * setup and ethernet/BPF attach. 907 */ 908static int ste_attach(dev) 909 device_t dev; 910{ 911 u_int32_t command; 912 struct ste_softc *sc; 913 struct ifnet *ifp; 914 int unit, error = 0, rid; 915 916 sc = device_get_softc(dev); 917 unit = device_get_unit(dev); 918 bzero(sc, sizeof(struct ste_softc)); 919 920 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 921 STE_LOCK(sc); 922 923 /* 924 * Handle power management nonsense. 925 */ 926 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 927 if (command == 0x01) { 928 929 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 930 if (command & STE_PSTATE_MASK) { 931 u_int32_t iobase, membase, irq; 932 933 /* Save important PCI config data. */ 934 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 935 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 936 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 937 938 /* Reset the power state. */ 939 printf("ste%d: chip is in D%d power mode " 940 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 941 command &= 0xFFFFFFFC; 942 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 943 944 /* Restore PCI config data. */ 945 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 946 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 947 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 948 } 949 } 950 951 /* 952 * Map control/status registers. 953 */ 954 command = pci_read_config(dev, PCIR_COMMAND, 4); 955 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 956 pci_write_config(dev, PCIR_COMMAND, command, 4); 957 command = pci_read_config(dev, PCIR_COMMAND, 4); 958 959#ifdef STE_USEIOSPACE 960 if (!(command & PCIM_CMD_PORTEN)) { 961 printf("ste%d: failed to enable I/O ports!\n", unit); 962 error = ENXIO; 963 goto fail; 964 } 965#else 966 if (!(command & PCIM_CMD_MEMEN)) { 967 printf("ste%d: failed to enable memory mapping!\n", unit); 968 error = ENXIO; 969 goto fail; 970 } 971#endif 972 973 rid = STE_RID; 974 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 975 0, ~0, 1, RF_ACTIVE); 976 977 if (sc->ste_res == NULL) { 978 printf ("ste%d: couldn't map ports/memory\n", unit); 979 error = ENXIO; 980 goto fail; 981 } 982 983 sc->ste_btag = rman_get_bustag(sc->ste_res); 984 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 985 986 rid = 0; 987 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 988 RF_SHAREABLE | RF_ACTIVE); 989 990 if (sc->ste_irq == NULL) { 991 printf("ste%d: couldn't map interrupt\n", unit); 992 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 993 error = ENXIO; 994 goto fail; 995 } 996 997 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 998 ste_intr, sc, &sc->ste_intrhand); 999 1000 if (error) { 1001 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1002 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1003 printf("ste%d: couldn't set up irq\n", unit); 1004 goto fail; 1005 } 1006 1007 callout_handle_init(&sc->ste_stat_ch); 1008 1009 /* Reset the adapter. */ 1010 ste_reset(sc); 1011 1012 /* 1013 * Get station address from the EEPROM. 1014 */ 1015 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1016 STE_EEADDR_NODE0, 3, 0)) { 1017 printf("ste%d: failed to read station address\n", unit); 1018 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1019 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1020 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1021 error = ENXIO;; 1022 goto fail; 1023 } 1024 1025 /* 1026 * A Sundance chip was detected. Inform the world. 1027 */ 1028 printf("ste%d: Ethernet address: %6D\n", unit, 1029 sc->arpcom.ac_enaddr, ":"); 1030 1031 sc->ste_unit = unit; 1032 1033 /* Allocate the descriptor queues. */ 1034 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1035 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1036 1037 if (sc->ste_ldata == NULL) { 1038 printf("ste%d: no memory for list buffers!\n", unit); 1039 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1040 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1041 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1042 error = ENXIO; 1043 goto fail; 1044 } 1045 1046 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1047 1048 /* Do MII setup. */ 1049 if (mii_phy_probe(dev, &sc->ste_miibus, 1050 ste_ifmedia_upd, ste_ifmedia_sts)) { 1051 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1052 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1053 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1054 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1055 contigfree(sc->ste_ldata, 1056 sizeof(struct ste_list_data), M_DEVBUF); 1057 error = ENXIO; 1058 goto fail; 1059 } 1060 1061 ifp = &sc->arpcom.ac_if; 1062 ifp->if_softc = sc; 1063 ifp->if_unit = unit; 1064 ifp->if_name = "ste"; 1065 ifp->if_mtu = ETHERMTU; 1066 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1067 ifp->if_ioctl = ste_ioctl; 1068 ifp->if_output = ether_output; 1069 ifp->if_start = ste_start; 1070 ifp->if_watchdog = ste_watchdog; 1071 ifp->if_init = ste_init; 1072 ifp->if_baudrate = 10000000; 1073 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1074 1075 /* 1076 * Call MI attach routine. 1077 */ 1078 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1079 STE_UNLOCK(sc); 1080 return(0); 1081 1082fail: 1083 STE_UNLOCK(sc); 1084 mtx_destroy(&sc->ste_mtx); 1085 return(error); 1086} 1087 1088static int ste_detach(dev) 1089 device_t dev; 1090{ 1091 struct ste_softc *sc; 1092 struct ifnet *ifp; 1093 1094 sc = device_get_softc(dev); 1095 STE_LOCK(sc); 1096 ifp = &sc->arpcom.ac_if; 1097 1098 ste_stop(sc); 1099 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1100 1101 bus_generic_detach(dev); 1102 device_delete_child(dev, sc->ste_miibus); 1103 1104 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1105 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1106 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1107 1108 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1109 1110 STE_UNLOCK(sc); 1111 mtx_destroy(&sc->ste_mtx); 1112 1113 return(0); 1114} 1115 1116static int ste_newbuf(sc, c, m) 1117 struct ste_softc *sc; 1118 struct ste_chain_onefrag *c; 1119 struct mbuf *m; 1120{ 1121 struct mbuf *m_new = NULL; 1122 1123 if (m == NULL) { 1124 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1125 if (m_new == NULL) { 1126 printf("ste%d: no memory for rx list -- " 1127 "packet dropped\n", sc->ste_unit); 1128 return(ENOBUFS); 1129 } 1130 MCLGET(m_new, M_DONTWAIT); 1131 if (!(m_new->m_flags & M_EXT)) { 1132 printf("ste%d: no memory for rx list -- " 1133 "packet dropped\n", sc->ste_unit); 1134 m_freem(m_new); 1135 return(ENOBUFS); 1136 } 1137 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1138 } else { 1139 m_new = m; 1140 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1141 m_new->m_data = m_new->m_ext.ext_buf; 1142 } 1143 1144 m_adj(m_new, ETHER_ALIGN); 1145 1146 c->ste_mbuf = m_new; 1147 c->ste_ptr->ste_status = 0; 1148 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1149 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; 1150 1151 return(0); 1152} 1153 1154static int ste_init_rx_list(sc) 1155 struct ste_softc *sc; 1156{ 1157 struct ste_chain_data *cd; 1158 struct ste_list_data *ld; 1159 int i; 1160 1161 cd = &sc->ste_cdata; 1162 ld = sc->ste_ldata; 1163 1164 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1165 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1166 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1167 return(ENOBUFS); 1168 if (i == (STE_RX_LIST_CNT - 1)) { 1169 cd->ste_rx_chain[i].ste_next = 1170 &cd->ste_rx_chain[0]; 1171 ld->ste_rx_list[i].ste_next = 1172 vtophys(&ld->ste_rx_list[0]); 1173 } else { 1174 cd->ste_rx_chain[i].ste_next = 1175 &cd->ste_rx_chain[i + 1]; 1176 ld->ste_rx_list[i].ste_next = 1177 vtophys(&ld->ste_rx_list[i + 1]); 1178 } 1179 1180 } 1181 1182 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1183 1184 return(0); 1185} 1186 1187static void ste_init_tx_list(sc) 1188 struct ste_softc *sc; 1189{ 1190 struct ste_chain_data *cd; 1191 struct ste_list_data *ld; 1192 int i; 1193 1194 cd = &sc->ste_cdata; 1195 ld = sc->ste_ldata; 1196 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1197 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1198 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1199 if (i == (STE_TX_LIST_CNT - 1)) 1200 cd->ste_tx_chain[i].ste_next = 1201 &cd->ste_tx_chain[0]; 1202 else 1203 cd->ste_tx_chain[i].ste_next = 1204 &cd->ste_tx_chain[i + 1]; 1205 if (i == 0) 1206 cd->ste_tx_chain[i].ste_prev = 1207 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1208 else 1209 cd->ste_tx_chain[i].ste_prev = 1210 &cd->ste_tx_chain[i - 1]; 1211 } 1212 1213 1214 bzero((char *)ld->ste_tx_list, 1215 sizeof(struct ste_desc) * STE_TX_LIST_CNT); 1216 1217 cd->ste_tx_prod = 0; 1218 cd->ste_tx_cons = 0; 1219 cd->ste_tx_cnt = 0; 1220 1221 return; 1222} 1223 1224static void ste_init(xsc) 1225 void *xsc; 1226{ 1227 struct ste_softc *sc; 1228 int i; 1229 struct ifnet *ifp; 1230 struct mii_data *mii; 1231 1232 sc = xsc; 1233 STE_LOCK(sc); 1234 ifp = &sc->arpcom.ac_if; 1235 mii = device_get_softc(sc->ste_miibus); 1236 1237 ste_stop(sc); 1238 1239 /* Init our MAC address */ 1240 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1241 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1242 } 1243 1244 /* Init RX list */ 1245 if (ste_init_rx_list(sc) == ENOBUFS) { 1246 printf("ste%d: initialization failed: no " 1247 "memory for RX buffers\n", sc->ste_unit); 1248 ste_stop(sc); 1249 STE_UNLOCK(sc); 1250 return; 1251 } 1252 1253 /* Init TX descriptors */ 1254 ste_init_tx_list(sc); 1255 1256 /* Set the TX freethresh value */ 1257 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1258 1259 /* Set the TX start threshold for best performance. */ 1260 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1261 1262 /* Set the TX reclaim threshold. */ 1263 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1264 1265 /* Set up the RX filter. */ 1266 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1267 1268 /* If we want promiscuous mode, set the allframes bit. */ 1269 if (ifp->if_flags & IFF_PROMISC) { 1270 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1271 } else { 1272 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1273 } 1274 1275 /* Set capture broadcast bit to accept broadcast frames. */ 1276 if (ifp->if_flags & IFF_BROADCAST) { 1277 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1278 } else { 1279 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1280 } 1281 1282 ste_setmulti(sc); 1283 1284 /* Load the address of the RX list. */ 1285 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1286 ste_wait(sc); 1287 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1288 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1289 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1290 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1291 1292 /* Set TX polling interval */ 1293 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1294 1295 /* Load address of the TX list */ 1296 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1297 ste_wait(sc); 1298 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1299 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1300 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1301 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1302 ste_wait(sc); 1303 1304 /* Enable receiver and transmitter */ 1305 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1306 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1307 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1308 1309 /* Enable stats counters. */ 1310 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1311 1312 /* Enable interrupts. */ 1313 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1314 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1315 1316 ste_ifmedia_upd(ifp); 1317 1318 ifp->if_flags |= IFF_RUNNING; 1319 ifp->if_flags &= ~IFF_OACTIVE; 1320 1321 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1322 STE_UNLOCK(sc); 1323 1324 return; 1325} 1326 1327static void ste_stop(sc) 1328 struct ste_softc *sc; 1329{ 1330 int i; 1331 struct ifnet *ifp; 1332 1333 STE_LOCK(sc); 1334 ifp = &sc->arpcom.ac_if; 1335 1336 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1337 1338 CSR_WRITE_2(sc, STE_IMR, 0); 1339 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1340 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1341 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1342 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1343 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1344 ste_wait(sc); 1345 1346 sc->ste_link = 0; 1347 1348 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1349 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1350 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1351 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1352 } 1353 } 1354 1355 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1356 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1357 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1358 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1359 } 1360 } 1361 1362 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1363 STE_UNLOCK(sc); 1364 1365 return; 1366} 1367 1368static void ste_reset(sc) 1369 struct ste_softc *sc; 1370{ 1371 int i; 1372 1373 STE_SETBIT4(sc, STE_ASICCTL, 1374 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1375 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1376 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1377 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1378 STE_ASICCTL_EXTRESET_RESET); 1379 1380 DELAY(100000); 1381 1382 for (i = 0; i < STE_TIMEOUT; i++) { 1383 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1384 break; 1385 } 1386 1387 if (i == STE_TIMEOUT) 1388 printf("ste%d: global reset never completed\n", sc->ste_unit); 1389 1390 return; 1391} 1392 1393static int ste_ioctl(ifp, command, data) 1394 struct ifnet *ifp; 1395 u_long command; 1396 caddr_t data; 1397{ 1398 struct ste_softc *sc; 1399 struct ifreq *ifr; 1400 struct mii_data *mii; 1401 int error = 0; 1402 1403 sc = ifp->if_softc; 1404 STE_LOCK(sc); 1405 ifr = (struct ifreq *)data; 1406 1407 switch(command) { 1408 case SIOCSIFADDR: 1409 case SIOCGIFADDR: 1410 case SIOCSIFMTU: 1411 error = ether_ioctl(ifp, command, data); 1412 break; 1413 case SIOCSIFFLAGS: 1414 if (ifp->if_flags & IFF_UP) { 1415 if (ifp->if_flags & IFF_RUNNING && 1416 ifp->if_flags & IFF_PROMISC && 1417 !(sc->ste_if_flags & IFF_PROMISC)) { 1418 STE_SETBIT1(sc, STE_RX_MODE, 1419 STE_RXMODE_PROMISC); 1420 } else if (ifp->if_flags & IFF_RUNNING && 1421 !(ifp->if_flags & IFF_PROMISC) && 1422 sc->ste_if_flags & IFF_PROMISC) { 1423 STE_CLRBIT1(sc, STE_RX_MODE, 1424 STE_RXMODE_PROMISC); 1425 } else if (!(ifp->if_flags & IFF_RUNNING)) { 1426 sc->ste_tx_thresh = STE_MIN_FRAMELEN; 1427 ste_init(sc); 1428 } 1429 } else { 1430 if (ifp->if_flags & IFF_RUNNING) 1431 ste_stop(sc); 1432 } 1433 sc->ste_if_flags = ifp->if_flags; 1434 error = 0; 1435 break; 1436 case SIOCADDMULTI: 1437 case SIOCDELMULTI: 1438 ste_setmulti(sc); 1439 error = 0; 1440 break; 1441 case SIOCGIFMEDIA: 1442 case SIOCSIFMEDIA: 1443 mii = device_get_softc(sc->ste_miibus); 1444 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1445 break; 1446 default: 1447 error = EINVAL; 1448 break; 1449 } 1450 1451 STE_UNLOCK(sc); 1452 1453 return(error); 1454} 1455 1456static int ste_encap(sc, c, m_head) 1457 struct ste_softc *sc; 1458 struct ste_chain *c; 1459 struct mbuf *m_head; 1460{ 1461 int frag = 0; 1462 struct ste_frag *f = NULL; 1463 struct mbuf *m; 1464 struct ste_desc *d; 1465 int total_len = 0; 1466 1467 d = c->ste_ptr; 1468 d->ste_ctl = 0; 1469 d->ste_next = 0; 1470 1471 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1472 if (m->m_len != 0) { 1473 if (frag == STE_MAXFRAGS) 1474 break; 1475 total_len += m->m_len; 1476 f = &c->ste_ptr->ste_frags[frag]; 1477 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1478 f->ste_len = m->m_len; 1479 frag++; 1480 } 1481 } 1482 1483 c->ste_mbuf = m_head; 1484 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1485 c->ste_ptr->ste_ctl = total_len; 1486 1487 return(0); 1488} 1489 1490static void ste_start(ifp) 1491 struct ifnet *ifp; 1492{ 1493 struct ste_softc *sc; 1494 struct mbuf *m_head = NULL; 1495 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1496 int idx; 1497 1498 sc = ifp->if_softc; 1499 STE_LOCK(sc); 1500 1501 if (!sc->ste_link) { 1502 STE_UNLOCK(sc); 1503 return; 1504 } 1505 1506 if (ifp->if_flags & IFF_OACTIVE) { 1507 STE_UNLOCK(sc); 1508 return; 1509 } 1510 1511 idx = sc->ste_cdata.ste_tx_prod; 1512 start_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1513 1514 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1515 1516 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1517 ifp->if_flags |= IFF_OACTIVE; 1518 break; 1519 } 1520 1521 IF_DEQUEUE(&ifp->if_snd, m_head); 1522 if (m_head == NULL) 1523 break; 1524 1525 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1526 1527 ste_encap(sc, cur_tx, m_head); 1528 1529 if (prev != NULL) 1530 prev->ste_ptr->ste_next = cur_tx->ste_phys; 1531 prev = cur_tx; 1532 1533 /* 1534 * If there's a BPF listener, bounce a copy of this frame 1535 * to him. 1536 */ 1537 if (ifp->if_bpf) 1538 bpf_mtap(ifp, cur_tx->ste_mbuf); 1539 1540 STE_INC(idx, STE_TX_LIST_CNT); 1541 sc->ste_cdata.ste_tx_cnt++; 1542 } 1543 1544 if (cur_tx == NULL) { 1545 STE_UNLOCK(sc); 1546 return; 1547 } 1548 1549 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR; 1550 1551 /* Start transmission */ 1552 sc->ste_cdata.ste_tx_prod = idx; 1553 start_tx->ste_prev->ste_ptr->ste_next = start_tx->ste_phys; 1554 1555 ifp->if_timer = 5; 1556 STE_UNLOCK(sc); 1557 1558 return; 1559} 1560 1561static void ste_watchdog(ifp) 1562 struct ifnet *ifp; 1563{ 1564 struct ste_softc *sc; 1565 1566 sc = ifp->if_softc; 1567 STE_LOCK(sc); 1568 1569 ifp->if_oerrors++; 1570 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1571 1572 ste_txeoc(sc); 1573 ste_txeof(sc); 1574 ste_rxeof(sc); 1575 ste_reset(sc); 1576 ste_init(sc); 1577 1578 if (ifp->if_snd.ifq_head != NULL) 1579 ste_start(ifp); 1580 STE_UNLOCK(sc); 1581 1582 return; 1583} 1584 1585static void ste_shutdown(dev) 1586 device_t dev; 1587{ 1588 struct ste_softc *sc; 1589 1590 sc = device_get_softc(dev); 1591 1592 ste_stop(sc); 1593 1594 return; 1595} 1596