if_ste.c revision 67089
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 67089 2000-10-13 18:35:49Z wpaul $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48 49#include <net/bpf.h> 50 51#include <vm/vm.h> /* for vtophys */ 52#include <vm/pmap.h> /* for vtophys */ 53#include <machine/clock.h> /* for DELAY */ 54#include <machine/bus_memio.h> 55#include <machine/bus_pio.h> 56#include <machine/bus.h> 57#include <machine/resource.h> 58#include <sys/bus.h> 59#include <sys/rman.h> 60 61#include <dev/mii/mii.h> 62#include <dev/mii/miivar.h> 63 64#include <pci/pcireg.h> 65#include <pci/pcivar.h> 66 67/* "controller miibus0" required. See GENERIC if you get errors here. */ 68#include "miibus_if.h" 69 70#define STE_USEIOSPACE 71 72#include <pci/if_stereg.h> 73 74MODULE_DEPEND(ste, miibus, 1, 1, 1); 75 76#if !defined(lint) 77static const char rcsid[] = 78 "$FreeBSD: head/sys/pci/if_ste.c 67089 2000-10-13 18:35:49Z wpaul $"; 79#endif 80 81/* 82 * Various supported device vendors/types and their names. 83 */ 84static struct ste_type ste_devs[] = { 85 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 86 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 87 { 0, 0, NULL } 88}; 89 90static int ste_probe __P((device_t)); 91static int ste_attach __P((device_t)); 92static int ste_detach __P((device_t)); 93static void ste_init __P((void *)); 94static void ste_intr __P((void *)); 95static void ste_rxeof __P((struct ste_softc *)); 96static void ste_txeoc __P((struct ste_softc *)); 97static void ste_txeof __P((struct ste_softc *)); 98static void ste_stats_update __P((void *)); 99static void ste_stop __P((struct ste_softc *)); 100static void ste_reset __P((struct ste_softc *)); 101static int ste_ioctl __P((struct ifnet *, u_long, caddr_t)); 102static int ste_encap __P((struct ste_softc *, struct ste_chain *, 103 struct mbuf *)); 104static void ste_start __P((struct ifnet *)); 105static void ste_watchdog __P((struct ifnet *)); 106static void ste_shutdown __P((device_t)); 107static int ste_newbuf __P((struct ste_softc *, 108 struct ste_chain_onefrag *, 109 struct mbuf *)); 110static int ste_ifmedia_upd __P((struct ifnet *)); 111static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 112 113static void ste_mii_sync __P((struct ste_softc *)); 114static void ste_mii_send __P((struct ste_softc *, u_int32_t, int)); 115static int ste_mii_readreg __P((struct ste_softc *, 116 struct ste_mii_frame *)); 117static int ste_mii_writereg __P((struct ste_softc *, 118 struct ste_mii_frame *)); 119static int ste_miibus_readreg __P((device_t, int, int)); 120static int ste_miibus_writereg __P((device_t, int, int, int)); 121static void ste_miibus_statchg __P((device_t)); 122 123static int ste_eeprom_wait __P((struct ste_softc *)); 124static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int, 125 int, int)); 126static void ste_wait __P((struct ste_softc *)); 127static u_int8_t ste_calchash __P((caddr_t)); 128static void ste_setmulti __P((struct ste_softc *)); 129static int ste_init_rx_list __P((struct ste_softc *)); 130static void ste_init_tx_list __P((struct ste_softc *)); 131 132#ifdef STE_USEIOSPACE 133#define STE_RES SYS_RES_IOPORT 134#define STE_RID STE_PCI_LOIO 135#else 136#define STE_RES SYS_RES_MEMORY 137#define STE_RID STE_PCI_LOMEM 138#endif 139 140static device_method_t ste_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, ste_probe), 143 DEVMETHOD(device_attach, ste_attach), 144 DEVMETHOD(device_detach, ste_detach), 145 DEVMETHOD(device_shutdown, ste_shutdown), 146 147 /* bus interface */ 148 DEVMETHOD(bus_print_child, bus_generic_print_child), 149 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 150 151 /* MII interface */ 152 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 153 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 154 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 155 156 { 0, 0 } 157}; 158 159static driver_t ste_driver = { 160 "ste", 161 ste_methods, 162 sizeof(struct ste_softc) 163}; 164 165static devclass_t ste_devclass; 166 167DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 168DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 169 170#define STE_SETBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 172 173#define STE_CLRBIT4(sc, reg, x) \ 174 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 175 176#define STE_SETBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 178 179#define STE_CLRBIT2(sc, reg, x) \ 180 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 181 182#define STE_SETBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 184 185#define STE_CLRBIT1(sc, reg, x) \ 186 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 187 188 189#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 190#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 191 192/* 193 * Sync the PHYs by setting data bit and strobing the clock 32 times. 194 */ 195static void ste_mii_sync(sc) 196 struct ste_softc *sc; 197{ 198 register int i; 199 200 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 201 202 for (i = 0; i < 32; i++) { 203 MII_SET(STE_PHYCTL_MCLK); 204 DELAY(1); 205 MII_CLR(STE_PHYCTL_MCLK); 206 DELAY(1); 207 } 208 209 return; 210} 211 212/* 213 * Clock a series of bits through the MII. 214 */ 215static void ste_mii_send(sc, bits, cnt) 216 struct ste_softc *sc; 217 u_int32_t bits; 218 int cnt; 219{ 220 int i; 221 222 MII_CLR(STE_PHYCTL_MCLK); 223 224 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 225 if (bits & i) { 226 MII_SET(STE_PHYCTL_MDATA); 227 } else { 228 MII_CLR(STE_PHYCTL_MDATA); 229 } 230 DELAY(1); 231 MII_CLR(STE_PHYCTL_MCLK); 232 DELAY(1); 233 MII_SET(STE_PHYCTL_MCLK); 234 } 235} 236 237/* 238 * Read an PHY register through the MII. 239 */ 240static int ste_mii_readreg(sc, frame) 241 struct ste_softc *sc; 242 struct ste_mii_frame *frame; 243 244{ 245 int i, ack; 246 247 STE_LOCK(sc); 248 249 /* 250 * Set up frame for RX. 251 */ 252 frame->mii_stdelim = STE_MII_STARTDELIM; 253 frame->mii_opcode = STE_MII_READOP; 254 frame->mii_turnaround = 0; 255 frame->mii_data = 0; 256 257 CSR_WRITE_2(sc, STE_PHYCTL, 0); 258 /* 259 * Turn on data xmit. 260 */ 261 MII_SET(STE_PHYCTL_MDIR); 262 263 ste_mii_sync(sc); 264 265 /* 266 * Send command/address info. 267 */ 268 ste_mii_send(sc, frame->mii_stdelim, 2); 269 ste_mii_send(sc, frame->mii_opcode, 2); 270 ste_mii_send(sc, frame->mii_phyaddr, 5); 271 ste_mii_send(sc, frame->mii_regaddr, 5); 272 273 /* Turn off xmit. */ 274 MII_CLR(STE_PHYCTL_MDIR); 275 276 /* Idle bit */ 277 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 278 DELAY(1); 279 MII_SET(STE_PHYCTL_MCLK); 280 DELAY(1); 281 282 /* Check for ack */ 283 MII_CLR(STE_PHYCTL_MCLK); 284 DELAY(1); 285 MII_SET(STE_PHYCTL_MCLK); 286 DELAY(1); 287 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 288 289 /* 290 * Now try reading data bits. If the ack failed, we still 291 * need to clock through 16 cycles to keep the PHY(s) in sync. 292 */ 293 if (ack) { 294 for(i = 0; i < 16; i++) { 295 MII_CLR(STE_PHYCTL_MCLK); 296 DELAY(1); 297 MII_SET(STE_PHYCTL_MCLK); 298 DELAY(1); 299 } 300 goto fail; 301 } 302 303 for (i = 0x8000; i; i >>= 1) { 304 MII_CLR(STE_PHYCTL_MCLK); 305 DELAY(1); 306 if (!ack) { 307 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 308 frame->mii_data |= i; 309 DELAY(1); 310 } 311 MII_SET(STE_PHYCTL_MCLK); 312 DELAY(1); 313 } 314 315fail: 316 317 MII_CLR(STE_PHYCTL_MCLK); 318 DELAY(1); 319 MII_SET(STE_PHYCTL_MCLK); 320 DELAY(1); 321 322 STE_UNLOCK(sc); 323 324 if (ack) 325 return(1); 326 return(0); 327} 328 329/* 330 * Write to a PHY register through the MII. 331 */ 332static int ste_mii_writereg(sc, frame) 333 struct ste_softc *sc; 334 struct ste_mii_frame *frame; 335 336{ 337 STE_LOCK(sc); 338 339 /* 340 * Set up frame for TX. 341 */ 342 343 frame->mii_stdelim = STE_MII_STARTDELIM; 344 frame->mii_opcode = STE_MII_WRITEOP; 345 frame->mii_turnaround = STE_MII_TURNAROUND; 346 347 /* 348 * Turn on data output. 349 */ 350 MII_SET(STE_PHYCTL_MDIR); 351 352 ste_mii_sync(sc); 353 354 ste_mii_send(sc, frame->mii_stdelim, 2); 355 ste_mii_send(sc, frame->mii_opcode, 2); 356 ste_mii_send(sc, frame->mii_phyaddr, 5); 357 ste_mii_send(sc, frame->mii_regaddr, 5); 358 ste_mii_send(sc, frame->mii_turnaround, 2); 359 ste_mii_send(sc, frame->mii_data, 16); 360 361 /* Idle bit. */ 362 MII_SET(STE_PHYCTL_MCLK); 363 DELAY(1); 364 MII_CLR(STE_PHYCTL_MCLK); 365 DELAY(1); 366 367 /* 368 * Turn off xmit. 369 */ 370 MII_CLR(STE_PHYCTL_MDIR); 371 372 STE_UNLOCK(sc); 373 374 return(0); 375} 376 377static int ste_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380{ 381 struct ste_softc *sc; 382 struct ste_mii_frame frame; 383 384 sc = device_get_softc(dev); 385 386 bzero((char *)&frame, sizeof(frame)); 387 388 frame.mii_phyaddr = phy; 389 frame.mii_regaddr = reg; 390 ste_mii_readreg(sc, &frame); 391 392 return(frame.mii_data); 393} 394 395static int ste_miibus_writereg(dev, phy, reg, data) 396 device_t dev; 397 int phy, reg, data; 398{ 399 struct ste_softc *sc; 400 struct ste_mii_frame frame; 401 402 sc = device_get_softc(dev); 403 bzero((char *)&frame, sizeof(frame)); 404 405 frame.mii_phyaddr = phy; 406 frame.mii_regaddr = reg; 407 frame.mii_data = data; 408 409 ste_mii_writereg(sc, &frame); 410 411 return(0); 412} 413 414static void ste_miibus_statchg(dev) 415 device_t dev; 416{ 417 struct ste_softc *sc; 418 struct mii_data *mii; 419 420 sc = device_get_softc(dev); 421 STE_LOCK(sc); 422 mii = device_get_softc(sc->ste_miibus); 423 424 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 425 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 426 } else { 427 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 428 } 429 STE_UNLOCK(sc); 430 431 return; 432} 433 434static int ste_ifmedia_upd(ifp) 435 struct ifnet *ifp; 436{ 437 struct ste_softc *sc; 438 struct mii_data *mii; 439 440 sc = ifp->if_softc; 441 mii = device_get_softc(sc->ste_miibus); 442 sc->ste_link = 0; 443 if (mii->mii_instance) { 444 struct mii_softc *miisc; 445 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 446 miisc = LIST_NEXT(miisc, mii_list)) 447 mii_phy_reset(miisc); 448 } 449 mii_mediachg(mii); 450 451 return(0); 452} 453 454static void ste_ifmedia_sts(ifp, ifmr) 455 struct ifnet *ifp; 456 struct ifmediareq *ifmr; 457{ 458 struct ste_softc *sc; 459 struct mii_data *mii; 460 461 sc = ifp->if_softc; 462 mii = device_get_softc(sc->ste_miibus); 463 464 mii_pollstat(mii); 465 ifmr->ifm_active = mii->mii_media_active; 466 ifmr->ifm_status = mii->mii_media_status; 467 468 return; 469} 470 471static void ste_wait(sc) 472 struct ste_softc *sc; 473{ 474 register int i; 475 476 for (i = 0; i < STE_TIMEOUT; i++) { 477 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 478 break; 479 } 480 481 if (i == STE_TIMEOUT) 482 printf("ste%d: command never completed!\n", sc->ste_unit); 483 484 return; 485} 486 487/* 488 * The EEPROM is slow: give it time to come ready after issuing 489 * it a command. 490 */ 491static int ste_eeprom_wait(sc) 492 struct ste_softc *sc; 493{ 494 int i; 495 496 DELAY(1000); 497 498 for (i = 0; i < 100; i++) { 499 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 500 DELAY(1000); 501 else 502 break; 503 } 504 505 if (i == 100) { 506 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 507 return(1); 508 } 509 510 return(0); 511} 512 513/* 514 * Read a sequence of words from the EEPROM. Note that ethernet address 515 * data is stored in the EEPROM in network byte order. 516 */ 517static int ste_read_eeprom(sc, dest, off, cnt, swap) 518 struct ste_softc *sc; 519 caddr_t dest; 520 int off; 521 int cnt; 522 int swap; 523{ 524 int err = 0, i; 525 u_int16_t word = 0, *ptr; 526 527 if (ste_eeprom_wait(sc)) 528 return(1); 529 530 for (i = 0; i < cnt; i++) { 531 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 532 err = ste_eeprom_wait(sc); 533 if (err) 534 break; 535 word = CSR_READ_2(sc, STE_EEPROM_DATA); 536 ptr = (u_int16_t *)(dest + (i * 2)); 537 if (swap) 538 *ptr = ntohs(word); 539 else 540 *ptr = word; 541 } 542 543 return(err ? 1 : 0); 544} 545 546static u_int8_t ste_calchash(addr) 547 caddr_t addr; 548{ 549 550 u_int32_t crc, carry; 551 int i, j; 552 u_int8_t c; 553 554 /* Compute CRC for the address value. */ 555 crc = 0xFFFFFFFF; /* initial value */ 556 557 for (i = 0; i < 6; i++) { 558 c = *(addr + i); 559 for (j = 0; j < 8; j++) { 560 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 561 crc <<= 1; 562 c >>= 1; 563 if (carry) 564 crc = (crc ^ 0x04c11db6) | carry; 565 } 566 } 567 568 /* return the filter bit position */ 569 return(crc & 0x0000003F); 570} 571 572static void ste_setmulti(sc) 573 struct ste_softc *sc; 574{ 575 struct ifnet *ifp; 576 int h = 0; 577 u_int32_t hashes[2] = { 0, 0 }; 578 struct ifmultiaddr *ifma; 579 580 ifp = &sc->arpcom.ac_if; 581 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 582 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 583 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 584 return; 585 } 586 587 /* first, zot all the existing hash bits */ 588 CSR_WRITE_4(sc, STE_MAR0, 0); 589 CSR_WRITE_4(sc, STE_MAR1, 0); 590 591 /* now program new ones */ 592 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 593 ifma = ifma->ifma_link.le_next) { 594 if (ifma->ifma_addr->sa_family != AF_LINK) 595 continue; 596 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 597 if (h < 32) 598 hashes[0] |= (1 << h); 599 else 600 hashes[1] |= (1 << (h - 32)); 601 } 602 603 CSR_WRITE_4(sc, STE_MAR0, hashes[0]); 604 CSR_WRITE_4(sc, STE_MAR1, hashes[1]); 605 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 606 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 607 608 return; 609} 610 611static void ste_intr(xsc) 612 void *xsc; 613{ 614 struct ste_softc *sc; 615 struct ifnet *ifp; 616 u_int16_t status; 617 618 sc = xsc; 619 STE_LOCK(sc); 620 ifp = &sc->arpcom.ac_if; 621 622 /* See if this is really our interrupt. */ 623 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 624 STE_UNLOCK(sc); 625 return; 626 } 627 628 for (;;) { 629 status = CSR_READ_2(sc, STE_ISR_ACK); 630 631 if (!(status & STE_INTRS)) 632 break; 633 634 if (status & STE_ISR_RX_DMADONE) 635 ste_rxeof(sc); 636 637 if (status & STE_ISR_TX_DMADONE) 638 ste_txeof(sc); 639 640 if (status & STE_ISR_TX_DONE) 641 ste_txeoc(sc); 642 643 if (status & STE_ISR_STATS_OFLOW) { 644 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 645 ste_stats_update(sc); 646 } 647 648 if (status & STE_ISR_HOSTERR) { 649 ste_reset(sc); 650 ste_init(sc); 651 } 652 } 653 654 /* Re-enable interrupts */ 655 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 656 657 if (ifp->if_snd.ifq_head != NULL) 658 ste_start(ifp); 659 660 STE_UNLOCK(sc); 661 662 return; 663} 664 665/* 666 * A frame has been uploaded: pass the resulting mbuf chain up to 667 * the higher level protocols. 668 */ 669static void ste_rxeof(sc) 670 struct ste_softc *sc; 671{ 672 struct ether_header *eh; 673 struct mbuf *m; 674 struct ifnet *ifp; 675 struct ste_chain_onefrag *cur_rx; 676 int total_len = 0; 677 u_int32_t rxstat; 678 679 ifp = &sc->arpcom.ac_if; 680 681again: 682 683 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) { 684 cur_rx = sc->ste_cdata.ste_rx_head; 685 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 686 687 /* 688 * If an error occurs, update stats, clear the 689 * status word and leave the mbuf cluster in place: 690 * it should simply get re-used next time this descriptor 691 * comes up in the ring. 692 */ 693 if (rxstat & STE_RXSTAT_FRAME_ERR) { 694 ifp->if_ierrors++; 695 cur_rx->ste_ptr->ste_status = 0; 696 continue; 697 } 698 699 /* 700 * If there error bit was not set, the upload complete 701 * bit should be set which means we have a valid packet. 702 * If not, something truly strange has happened. 703 */ 704 if (!(rxstat & STE_RXSTAT_DMADONE)) { 705 printf("ste%d: bad receive status -- packet dropped", 706 sc->ste_unit); 707 ifp->if_ierrors++; 708 cur_rx->ste_ptr->ste_status = 0; 709 continue; 710 } 711 712 /* No errors; receive the packet. */ 713 m = cur_rx->ste_mbuf; 714 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 715 716 /* 717 * Try to conjure up a new mbuf cluster. If that 718 * fails, it means we have an out of memory condition and 719 * should leave the buffer in place and continue. This will 720 * result in a lost packet, but there's little else we 721 * can do in this situation. 722 */ 723 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 724 ifp->if_ierrors++; 725 cur_rx->ste_ptr->ste_status = 0; 726 continue; 727 } 728 729 ifp->if_ipackets++; 730 eh = mtod(m, struct ether_header *); 731 m->m_pkthdr.rcvif = ifp; 732 m->m_pkthdr.len = m->m_len = total_len; 733 734 /* Remove header from mbuf and pass it on. */ 735 m_adj(m, sizeof(struct ether_header)); 736 ether_input(ifp, eh, m); 737 } 738 739 /* 740 * Handle the 'end of channel' condition. When the upload 741 * engine hits the end of the RX ring, it will stall. This 742 * is our cue to flush the RX ring, reload the uplist pointer 743 * register and unstall the engine. 744 * XXX This is actually a little goofy. With the ThunderLAN 745 * chip, you get an interrupt when the receiver hits the end 746 * of the receive ring, which tells you exactly when you 747 * you need to reload the ring pointer. Here we have to 748 * fake it. I'm mad at myself for not being clever enough 749 * to avoid the use of a goto here. 750 */ 751 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 || 752 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) { 753 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 754 ste_wait(sc); 755 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 756 vtophys(&sc->ste_ldata->ste_rx_list[0])); 757 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0]; 758 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 759 goto again; 760 } 761 762 return; 763} 764 765static void ste_txeoc(sc) 766 struct ste_softc *sc; 767{ 768 u_int8_t txstat; 769 struct ifnet *ifp; 770 771 ifp = &sc->arpcom.ac_if; 772 773 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 774 STE_TXSTATUS_TXDONE) { 775 if (txstat & STE_TXSTATUS_UNDERRUN || 776 txstat & STE_TXSTATUS_EXCESSCOLLS || 777 txstat & STE_TXSTATUS_RECLAIMERR) { 778 ifp->if_oerrors++; 779 printf("ste%d: transmission error: %x\n", 780 sc->ste_unit, txstat); 781 782 ste_reset(sc); 783 ste_init(sc); 784 785 if (txstat & STE_TXSTATUS_UNDERRUN && 786 sc->ste_tx_thresh < STE_PACKET_SIZE) { 787 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 788 printf("ste%d: tx underrun, increasing tx" 789 " start threshold to %d bytes\n", 790 sc->ste_unit, sc->ste_tx_thresh); 791 } 792 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 793 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 794 (STE_PACKET_SIZE >> 4)); 795 } 796 ste_init(sc); 797 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 798 } 799 800 return; 801} 802 803static void ste_txeof(sc) 804 struct ste_softc *sc; 805{ 806 struct ste_chain *cur_tx = NULL; 807 struct ifnet *ifp; 808 int idx; 809 810 ifp = &sc->arpcom.ac_if; 811 812 idx = sc->ste_cdata.ste_tx_cons; 813 while(idx != sc->ste_cdata.ste_tx_prod) { 814 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 815 816 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 817 break; 818 819 if (cur_tx->ste_mbuf != NULL) { 820 m_freem(cur_tx->ste_mbuf); 821 cur_tx->ste_mbuf = NULL; 822 } 823 824 ifp->if_opackets++; 825 826 sc->ste_cdata.ste_tx_cnt--; 827 STE_INC(idx, STE_TX_LIST_CNT); 828 ifp->if_timer = 0; 829 } 830 831 sc->ste_cdata.ste_tx_cons = idx; 832 833 if (cur_tx != NULL) 834 ifp->if_flags &= ~IFF_OACTIVE; 835 836 return; 837} 838 839static void ste_stats_update(xsc) 840 void *xsc; 841{ 842 struct ste_softc *sc; 843 struct ste_stats stats; 844 struct ifnet *ifp; 845 struct mii_data *mii; 846 int i; 847 u_int8_t *p; 848 849 sc = xsc; 850 STE_LOCK(sc); 851 852 ifp = &sc->arpcom.ac_if; 853 mii = device_get_softc(sc->ste_miibus); 854 855 p = (u_int8_t *)&stats; 856 857 for (i = 0; i < sizeof(stats); i++) { 858 *p = CSR_READ_1(sc, STE_STATS + i); 859 p++; 860 } 861 862 ifp->if_collisions += stats.ste_single_colls + 863 stats.ste_multi_colls + stats.ste_late_colls; 864 865 mii_tick(mii); 866 if (!sc->ste_link) { 867 mii_pollstat(mii); 868 if (mii->mii_media_status & IFM_ACTIVE && 869 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 870 sc->ste_link++; 871 if (ifp->if_snd.ifq_head != NULL) 872 ste_start(ifp); 873 } 874 875 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 876 STE_UNLOCK(sc); 877 878 return; 879} 880 881 882/* 883 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 884 * IDs against our list and return a device name if we find a match. 885 */ 886static int ste_probe(dev) 887 device_t dev; 888{ 889 struct ste_type *t; 890 891 t = ste_devs; 892 893 while(t->ste_name != NULL) { 894 if ((pci_get_vendor(dev) == t->ste_vid) && 895 (pci_get_device(dev) == t->ste_did)) { 896 device_set_desc(dev, t->ste_name); 897 return(0); 898 } 899 t++; 900 } 901 902 return(ENXIO); 903} 904 905/* 906 * Attach the interface. Allocate softc structures, do ifmedia 907 * setup and ethernet/BPF attach. 908 */ 909static int ste_attach(dev) 910 device_t dev; 911{ 912 u_int32_t command; 913 struct ste_softc *sc; 914 struct ifnet *ifp; 915 int unit, error = 0, rid; 916 917 sc = device_get_softc(dev); 918 unit = device_get_unit(dev); 919 bzero(sc, sizeof(struct ste_softc)); 920 921 /* 922 * Handle power management nonsense. 923 */ 924 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 925 if (command == 0x01) { 926 927 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 928 if (command & STE_PSTATE_MASK) { 929 u_int32_t iobase, membase, irq; 930 931 /* Save important PCI config data. */ 932 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 933 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 934 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 935 936 /* Reset the power state. */ 937 printf("ste%d: chip is in D%d power mode " 938 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 939 command &= 0xFFFFFFFC; 940 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 941 942 /* Restore PCI config data. */ 943 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 944 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 945 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 946 } 947 } 948 949 /* 950 * Map control/status registers. 951 */ 952 command = pci_read_config(dev, PCIR_COMMAND, 4); 953 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 954 pci_write_config(dev, PCIR_COMMAND, command, 4); 955 command = pci_read_config(dev, PCIR_COMMAND, 4); 956 957#ifdef STE_USEIOSPACE 958 if (!(command & PCIM_CMD_PORTEN)) { 959 printf("ste%d: failed to enable I/O ports!\n", unit); 960 error = ENXIO; 961 goto fail; 962 } 963#else 964 if (!(command & PCIM_CMD_MEMEN)) { 965 printf("ste%d: failed to enable memory mapping!\n", unit); 966 error = ENXIO; 967 goto fail; 968 } 969#endif 970 971 rid = STE_RID; 972 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 973 0, ~0, 1, RF_ACTIVE); 974 975 if (sc->ste_res == NULL) { 976 printf ("ste%d: couldn't map ports/memory\n", unit); 977 error = ENXIO; 978 goto fail; 979 } 980 981 sc->ste_btag = rman_get_bustag(sc->ste_res); 982 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 983 984 rid = 0; 985 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 986 RF_SHAREABLE | RF_ACTIVE); 987 988 if (sc->ste_irq == NULL) { 989 printf("ste%d: couldn't map interrupt\n", unit); 990 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 991 error = ENXIO; 992 goto fail; 993 } 994 995 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 996 ste_intr, sc, &sc->ste_intrhand); 997 998 if (error) { 999 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1000 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1001 printf("ste%d: couldn't set up irq\n", unit); 1002 goto fail; 1003 } 1004 1005 callout_handle_init(&sc->ste_stat_ch); 1006 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_DEF); 1007 STE_LOCK(sc); 1008 1009 /* Reset the adapter. */ 1010 ste_reset(sc); 1011 1012 /* 1013 * Get station address from the EEPROM. 1014 */ 1015 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1016 STE_EEADDR_NODE0, 3, 0)) { 1017 printf("ste%d: failed to read station address\n", unit); 1018 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1019 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1020 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1021 error = ENXIO;; 1022 goto fail; 1023 } 1024 1025 /* 1026 * A Sundance chip was detected. Inform the world. 1027 */ 1028 printf("ste%d: Ethernet address: %6D\n", unit, 1029 sc->arpcom.ac_enaddr, ":"); 1030 1031 sc->ste_unit = unit; 1032 1033 /* Allocate the descriptor queues. */ 1034 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1035 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1036 1037 if (sc->ste_ldata == NULL) { 1038 printf("ste%d: no memory for list buffers!\n", unit); 1039 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1040 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1041 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1042 error = ENXIO; 1043 goto fail; 1044 } 1045 1046 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1047 1048 /* Do MII setup. */ 1049 if (mii_phy_probe(dev, &sc->ste_miibus, 1050 ste_ifmedia_upd, ste_ifmedia_sts)) { 1051 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1052 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1053 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1054 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1055 contigfree(sc->ste_ldata, 1056 sizeof(struct ste_list_data), M_DEVBUF); 1057 error = ENXIO; 1058 goto fail; 1059 } 1060 1061 ifp = &sc->arpcom.ac_if; 1062 ifp->if_softc = sc; 1063 ifp->if_unit = unit; 1064 ifp->if_name = "ste"; 1065 ifp->if_mtu = ETHERMTU; 1066 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1067 ifp->if_ioctl = ste_ioctl; 1068 ifp->if_output = ether_output; 1069 ifp->if_start = ste_start; 1070 ifp->if_watchdog = ste_watchdog; 1071 ifp->if_init = ste_init; 1072 ifp->if_baudrate = 10000000; 1073 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1074 1075 /* 1076 * Call MI attach routine. 1077 */ 1078 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1079 STE_UNLOCK(sc); 1080 return(0); 1081 1082fail: 1083 STE_UNLOCK(sc); 1084 mtx_destroy(&sc->ste_mtx); 1085 return(error); 1086} 1087 1088static int ste_detach(dev) 1089 device_t dev; 1090{ 1091 struct ste_softc *sc; 1092 struct ifnet *ifp; 1093 1094 sc = device_get_softc(dev); 1095 STE_LOCK(sc); 1096 ifp = &sc->arpcom.ac_if; 1097 1098 ste_stop(sc); 1099 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1100 1101 bus_generic_detach(dev); 1102 device_delete_child(dev, sc->ste_miibus); 1103 1104 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1105 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1106 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1107 1108 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1109 1110 STE_UNLOCK(sc); 1111 mtx_destroy(&sc->ste_mtx); 1112 1113 return(0); 1114} 1115 1116static int ste_newbuf(sc, c, m) 1117 struct ste_softc *sc; 1118 struct ste_chain_onefrag *c; 1119 struct mbuf *m; 1120{ 1121 struct mbuf *m_new = NULL; 1122 1123 if (m == NULL) { 1124 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1125 if (m_new == NULL) { 1126 printf("ste%d: no memory for rx list -- " 1127 "packet dropped\n", sc->ste_unit); 1128 return(ENOBUFS); 1129 } 1130 MCLGET(m_new, M_DONTWAIT); 1131 if (!(m_new->m_flags & M_EXT)) { 1132 printf("ste%d: no memory for rx list -- " 1133 "packet dropped\n", sc->ste_unit); 1134 m_freem(m_new); 1135 return(ENOBUFS); 1136 } 1137 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1138 } else { 1139 m_new = m; 1140 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1141 m_new->m_data = m_new->m_ext.ext_buf; 1142 } 1143 1144 m_adj(m_new, ETHER_ALIGN); 1145 1146 c->ste_mbuf = m_new; 1147 c->ste_ptr->ste_status = 0; 1148 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1149 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; 1150 1151 return(0); 1152} 1153 1154static int ste_init_rx_list(sc) 1155 struct ste_softc *sc; 1156{ 1157 struct ste_chain_data *cd; 1158 struct ste_list_data *ld; 1159 int i; 1160 1161 cd = &sc->ste_cdata; 1162 ld = sc->ste_ldata; 1163 1164 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1165 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1166 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1167 return(ENOBUFS); 1168 if (i == (STE_RX_LIST_CNT - 1)) { 1169 cd->ste_rx_chain[i].ste_next = 1170 &cd->ste_rx_chain[0]; 1171 ld->ste_rx_list[i].ste_next = 1172 vtophys(&ld->ste_rx_list[0]); 1173 } else { 1174 cd->ste_rx_chain[i].ste_next = 1175 &cd->ste_rx_chain[i + 1]; 1176 ld->ste_rx_list[i].ste_next = 1177 vtophys(&ld->ste_rx_list[i + 1]); 1178 } 1179 1180 } 1181 1182 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1183 1184 return(0); 1185} 1186 1187static void ste_init_tx_list(sc) 1188 struct ste_softc *sc; 1189{ 1190 struct ste_chain_data *cd; 1191 struct ste_list_data *ld; 1192 int i; 1193 1194 cd = &sc->ste_cdata; 1195 ld = sc->ste_ldata; 1196 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1197 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1198 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1199 if (i == (STE_TX_LIST_CNT - 1)) 1200 cd->ste_tx_chain[i].ste_next = 1201 &cd->ste_tx_chain[0]; 1202 else 1203 cd->ste_tx_chain[i].ste_next = 1204 &cd->ste_tx_chain[i + 1]; 1205 if (i == 0) 1206 cd->ste_tx_chain[i].ste_prev = 1207 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1208 else 1209 cd->ste_tx_chain[i].ste_prev = 1210 &cd->ste_tx_chain[i - 1]; 1211 } 1212 1213 1214 bzero((char *)ld->ste_tx_list, 1215 sizeof(struct ste_desc) * STE_TX_LIST_CNT); 1216 1217 cd->ste_tx_prod = 0; 1218 cd->ste_tx_cons = 0; 1219 cd->ste_tx_cnt = 0; 1220 1221 return; 1222} 1223 1224static void ste_init(xsc) 1225 void *xsc; 1226{ 1227 struct ste_softc *sc; 1228 int i; 1229 struct ifnet *ifp; 1230 struct mii_data *mii; 1231 1232 sc = xsc; 1233 STE_LOCK(sc); 1234 ifp = &sc->arpcom.ac_if; 1235 mii = device_get_softc(sc->ste_miibus); 1236 1237 ste_stop(sc); 1238 1239 /* Init our MAC address */ 1240 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1241 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1242 } 1243 1244 /* Init RX list */ 1245 if (ste_init_rx_list(sc) == ENOBUFS) { 1246 printf("ste%d: initialization failed: no " 1247 "memory for RX buffers\n", sc->ste_unit); 1248 ste_stop(sc); 1249 STE_UNLOCK(sc); 1250 return; 1251 } 1252 1253 /* Init TX descriptors */ 1254 ste_init_tx_list(sc); 1255 1256 /* Set the TX freethresh value */ 1257 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1258 1259 /* Set the TX start threshold for best performance. */ 1260 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1261 1262 /* Set the TX reclaim threshold. */ 1263 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1264 1265 /* Set up the RX filter. */ 1266 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1267 1268 /* If we want promiscuous mode, set the allframes bit. */ 1269 if (ifp->if_flags & IFF_PROMISC) { 1270 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1271 } else { 1272 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1273 } 1274 1275 /* Set capture broadcast bit to accept broadcast frames. */ 1276 if (ifp->if_flags & IFF_BROADCAST) { 1277 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1278 } else { 1279 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1280 } 1281 1282 ste_setmulti(sc); 1283 1284 /* Load the address of the RX list. */ 1285 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1286 ste_wait(sc); 1287 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1288 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1289 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1290 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1291 1292 /* Set TX polling interval */ 1293 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1294 1295 /* Load address of the TX list */ 1296 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1297 ste_wait(sc); 1298 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1299 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1300 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1301 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1302 ste_wait(sc); 1303 1304 /* Enable receiver and transmitter */ 1305 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1306 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1307 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1308 1309 /* Enable stats counters. */ 1310 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1311 1312 /* Enable interrupts. */ 1313 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1314 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1315 1316 ste_ifmedia_upd(ifp); 1317 1318 ifp->if_flags |= IFF_RUNNING; 1319 ifp->if_flags &= ~IFF_OACTIVE; 1320 1321 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1322 STE_UNLOCK(sc); 1323 1324 return; 1325} 1326 1327static void ste_stop(sc) 1328 struct ste_softc *sc; 1329{ 1330 int i; 1331 struct ifnet *ifp; 1332 1333 STE_LOCK(sc); 1334 ifp = &sc->arpcom.ac_if; 1335 1336 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1337 1338 CSR_WRITE_2(sc, STE_IMR, 0); 1339 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1340 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1341 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1342 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1343 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1344 ste_wait(sc); 1345 1346 sc->ste_link = 0; 1347 1348 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1349 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1350 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1351 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1352 } 1353 } 1354 1355 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1356 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1357 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1358 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1359 } 1360 } 1361 1362 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1363 STE_UNLOCK(sc); 1364 1365 return; 1366} 1367 1368static void ste_reset(sc) 1369 struct ste_softc *sc; 1370{ 1371 int i; 1372 1373 STE_SETBIT4(sc, STE_ASICCTL, 1374 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1375 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1376 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1377 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1378 STE_ASICCTL_EXTRESET_RESET); 1379 1380 DELAY(100000); 1381 1382 for (i = 0; i < STE_TIMEOUT; i++) { 1383 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1384 break; 1385 } 1386 1387 if (i == STE_TIMEOUT) 1388 printf("ste%d: global reset never completed\n", sc->ste_unit); 1389 1390 return; 1391} 1392 1393static int ste_ioctl(ifp, command, data) 1394 struct ifnet *ifp; 1395 u_long command; 1396 caddr_t data; 1397{ 1398 struct ste_softc *sc; 1399 struct ifreq *ifr; 1400 struct mii_data *mii; 1401 int error = 0; 1402 1403 sc = ifp->if_softc; 1404 STE_LOCK(sc); 1405 ifr = (struct ifreq *)data; 1406 1407 switch(command) { 1408 case SIOCSIFADDR: 1409 case SIOCGIFADDR: 1410 case SIOCSIFMTU: 1411 error = ether_ioctl(ifp, command, data); 1412 break; 1413 case SIOCSIFFLAGS: 1414 if (ifp->if_flags & IFF_UP) { 1415 if (ifp->if_flags & IFF_RUNNING && 1416 ifp->if_flags & IFF_PROMISC && 1417 !(sc->ste_if_flags & IFF_PROMISC)) { 1418 STE_SETBIT1(sc, STE_RX_MODE, 1419 STE_RXMODE_PROMISC); 1420 } else if (ifp->if_flags & IFF_RUNNING && 1421 !(ifp->if_flags & IFF_PROMISC) && 1422 sc->ste_if_flags & IFF_PROMISC) { 1423 STE_CLRBIT1(sc, STE_RX_MODE, 1424 STE_RXMODE_PROMISC); 1425 } else if (!(ifp->if_flags & IFF_RUNNING)) { 1426 sc->ste_tx_thresh = STE_MIN_FRAMELEN; 1427 ste_init(sc); 1428 } 1429 } else { 1430 if (ifp->if_flags & IFF_RUNNING) 1431 ste_stop(sc); 1432 } 1433 sc->ste_if_flags = ifp->if_flags; 1434 error = 0; 1435 break; 1436 case SIOCADDMULTI: 1437 case SIOCDELMULTI: 1438 ste_setmulti(sc); 1439 error = 0; 1440 break; 1441 case SIOCGIFMEDIA: 1442 case SIOCSIFMEDIA: 1443 mii = device_get_softc(sc->ste_miibus); 1444 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1445 break; 1446 default: 1447 error = EINVAL; 1448 break; 1449 } 1450 1451 STE_UNLOCK(sc); 1452 1453 return(error); 1454} 1455 1456static int ste_encap(sc, c, m_head) 1457 struct ste_softc *sc; 1458 struct ste_chain *c; 1459 struct mbuf *m_head; 1460{ 1461 int frag = 0; 1462 struct ste_frag *f = NULL; 1463 struct mbuf *m; 1464 struct ste_desc *d; 1465 int total_len = 0; 1466 1467 d = c->ste_ptr; 1468 d->ste_ctl = 0; 1469 d->ste_next = 0; 1470 1471 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1472 if (m->m_len != 0) { 1473 if (frag == STE_MAXFRAGS) 1474 break; 1475 total_len += m->m_len; 1476 f = &c->ste_ptr->ste_frags[frag]; 1477 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1478 f->ste_len = m->m_len; 1479 frag++; 1480 } 1481 } 1482 1483 c->ste_mbuf = m_head; 1484 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1485 c->ste_ptr->ste_ctl = total_len; 1486 1487 return(0); 1488} 1489 1490static void ste_start(ifp) 1491 struct ifnet *ifp; 1492{ 1493 struct ste_softc *sc; 1494 struct mbuf *m_head = NULL; 1495 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1496 int idx; 1497 1498 sc = ifp->if_softc; 1499 STE_LOCK(sc); 1500 1501 if (!sc->ste_link) { 1502 STE_UNLOCK(sc); 1503 return; 1504 } 1505 1506 if (ifp->if_flags & IFF_OACTIVE) { 1507 STE_UNLOCK(sc); 1508 return; 1509 } 1510 1511 idx = sc->ste_cdata.ste_tx_prod; 1512 start_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1513 1514 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1515 1516 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1517 ifp->if_flags |= IFF_OACTIVE; 1518 break; 1519 } 1520 1521 IF_DEQUEUE(&ifp->if_snd, m_head); 1522 if (m_head == NULL) 1523 break; 1524 1525 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1526 1527 ste_encap(sc, cur_tx, m_head); 1528 1529 if (prev != NULL) 1530 prev->ste_ptr->ste_next = cur_tx->ste_phys; 1531 prev = cur_tx; 1532 1533 /* 1534 * If there's a BPF listener, bounce a copy of this frame 1535 * to him. 1536 */ 1537 if (ifp->if_bpf) 1538 bpf_mtap(ifp, cur_tx->ste_mbuf); 1539 1540 STE_INC(idx, STE_TX_LIST_CNT); 1541 sc->ste_cdata.ste_tx_cnt++; 1542 } 1543 1544 if (cur_tx == NULL) { 1545 STE_UNLOCK(sc); 1546 return; 1547 } 1548 1549 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR; 1550 1551 /* Start transmission */ 1552 sc->ste_cdata.ste_tx_prod = idx; 1553 start_tx->ste_prev->ste_ptr->ste_next = start_tx->ste_phys; 1554 1555 ifp->if_timer = 5; 1556 STE_UNLOCK(sc); 1557 1558 return; 1559} 1560 1561static void ste_watchdog(ifp) 1562 struct ifnet *ifp; 1563{ 1564 struct ste_softc *sc; 1565 1566 sc = ifp->if_softc; 1567 STE_LOCK(sc); 1568 1569 ifp->if_oerrors++; 1570 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1571 1572 ste_txeoc(sc); 1573 ste_txeof(sc); 1574 ste_rxeof(sc); 1575 ste_reset(sc); 1576 ste_init(sc); 1577 1578 if (ifp->if_snd.ifq_head != NULL) 1579 ste_start(ifp); 1580 STE_UNLOCK(sc); 1581 1582 return; 1583} 1584 1585static void ste_shutdown(dev) 1586 device_t dev; 1587{ 1588 struct ste_softc *sc; 1589 1590 sc = device_get_softc(dev); 1591 1592 ste_stop(sc); 1593 1594 return; 1595} 1596