if_ste.c revision 61041
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 61041 2000-05-28 16:13:43Z peter $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48 49#include <net/bpf.h> 50 51#include <vm/vm.h> /* for vtophys */ 52#include <vm/pmap.h> /* for vtophys */ 53#include <machine/clock.h> /* for DELAY */ 54#include <machine/bus_memio.h> 55#include <machine/bus_pio.h> 56#include <machine/bus.h> 57#include <machine/resource.h> 58#include <sys/bus.h> 59#include <sys/rman.h> 60 61#include <dev/mii/mii.h> 62#include <dev/mii/miivar.h> 63 64#include <pci/pcireg.h> 65#include <pci/pcivar.h> 66 67/* "controller miibus0" required. See GENERIC if you get errors here. */ 68#include "miibus_if.h" 69 70#define STE_USEIOSPACE 71 72#include <pci/if_stereg.h> 73 74MODULE_DEPEND(ste, miibus, 1, 1, 1); 75 76#if !defined(lint) 77static const char rcsid[] = 78 "$FreeBSD: head/sys/pci/if_ste.c 61041 2000-05-28 16:13:43Z peter $"; 79#endif 80 81/* 82 * Various supported device vendors/types and their names. 83 */ 84static struct ste_type ste_devs[] = { 85 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 86 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 87 { 0, 0, NULL } 88}; 89 90static int ste_probe __P((device_t)); 91static int ste_attach __P((device_t)); 92static int ste_detach __P((device_t)); 93static void ste_init __P((void *)); 94static void ste_intr __P((void *)); 95static void ste_rxeof __P((struct ste_softc *)); 96static void ste_txeoc __P((struct ste_softc *)); 97static void ste_txeof __P((struct ste_softc *)); 98static void ste_stats_update __P((void *)); 99static void ste_stop __P((struct ste_softc *)); 100static void ste_reset __P((struct ste_softc *)); 101static int ste_ioctl __P((struct ifnet *, u_long, caddr_t)); 102static int ste_encap __P((struct ste_softc *, struct ste_chain *, 103 struct mbuf *)); 104static void ste_start __P((struct ifnet *)); 105static void ste_watchdog __P((struct ifnet *)); 106static void ste_shutdown __P((device_t)); 107static int ste_newbuf __P((struct ste_softc *, 108 struct ste_chain_onefrag *, 109 struct mbuf *)); 110static int ste_ifmedia_upd __P((struct ifnet *)); 111static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 112 113static void ste_mii_sync __P((struct ste_softc *)); 114static void ste_mii_send __P((struct ste_softc *, u_int32_t, int)); 115static int ste_mii_readreg __P((struct ste_softc *, 116 struct ste_mii_frame *)); 117static int ste_mii_writereg __P((struct ste_softc *, 118 struct ste_mii_frame *)); 119static int ste_miibus_readreg __P((device_t, int, int)); 120static int ste_miibus_writereg __P((device_t, int, int, int)); 121static void ste_miibus_statchg __P((device_t)); 122 123static int ste_eeprom_wait __P((struct ste_softc *)); 124static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int, 125 int, int)); 126static void ste_wait __P((struct ste_softc *)); 127static u_int8_t ste_calchash __P((caddr_t)); 128static void ste_setmulti __P((struct ste_softc *)); 129static int ste_init_rx_list __P((struct ste_softc *)); 130static void ste_init_tx_list __P((struct ste_softc *)); 131 132#ifdef STE_USEIOSPACE 133#define STE_RES SYS_RES_IOPORT 134#define STE_RID STE_PCI_LOIO 135#else 136#define STE_RES SYS_RES_MEMORY 137#define STE_RID STE_PCI_LOMEM 138#endif 139 140static device_method_t ste_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, ste_probe), 143 DEVMETHOD(device_attach, ste_attach), 144 DEVMETHOD(device_detach, ste_detach), 145 DEVMETHOD(device_shutdown, ste_shutdown), 146 147 /* bus interface */ 148 DEVMETHOD(bus_print_child, bus_generic_print_child), 149 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 150 151 /* MII interface */ 152 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 153 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 154 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 155 156 { 0, 0 } 157}; 158 159static driver_t ste_driver = { 160 "ste", 161 ste_methods, 162 sizeof(struct ste_softc) 163}; 164 165static devclass_t ste_devclass; 166 167DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 168DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 169 170#define STE_SETBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 172 173#define STE_CLRBIT4(sc, reg, x) \ 174 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 175 176#define STE_SETBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 178 179#define STE_CLRBIT2(sc, reg, x) \ 180 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 181 182#define STE_SETBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 184 185#define STE_CLRBIT1(sc, reg, x) \ 186 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 187 188 189#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 190#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 191 192/* 193 * Sync the PHYs by setting data bit and strobing the clock 32 times. 194 */ 195static void ste_mii_sync(sc) 196 struct ste_softc *sc; 197{ 198 register int i; 199 200 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 201 202 for (i = 0; i < 32; i++) { 203 MII_SET(STE_PHYCTL_MCLK); 204 DELAY(1); 205 MII_CLR(STE_PHYCTL_MCLK); 206 DELAY(1); 207 } 208 209 return; 210} 211 212/* 213 * Clock a series of bits through the MII. 214 */ 215static void ste_mii_send(sc, bits, cnt) 216 struct ste_softc *sc; 217 u_int32_t bits; 218 int cnt; 219{ 220 int i; 221 222 MII_CLR(STE_PHYCTL_MCLK); 223 224 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 225 if (bits & i) { 226 MII_SET(STE_PHYCTL_MDATA); 227 } else { 228 MII_CLR(STE_PHYCTL_MDATA); 229 } 230 DELAY(1); 231 MII_CLR(STE_PHYCTL_MCLK); 232 DELAY(1); 233 MII_SET(STE_PHYCTL_MCLK); 234 } 235} 236 237/* 238 * Read an PHY register through the MII. 239 */ 240static int ste_mii_readreg(sc, frame) 241 struct ste_softc *sc; 242 struct ste_mii_frame *frame; 243 244{ 245 int i, ack, s; 246 247 s = splimp(); 248 249 /* 250 * Set up frame for RX. 251 */ 252 frame->mii_stdelim = STE_MII_STARTDELIM; 253 frame->mii_opcode = STE_MII_READOP; 254 frame->mii_turnaround = 0; 255 frame->mii_data = 0; 256 257 CSR_WRITE_2(sc, STE_PHYCTL, 0); 258 /* 259 * Turn on data xmit. 260 */ 261 MII_SET(STE_PHYCTL_MDIR); 262 263 ste_mii_sync(sc); 264 265 /* 266 * Send command/address info. 267 */ 268 ste_mii_send(sc, frame->mii_stdelim, 2); 269 ste_mii_send(sc, frame->mii_opcode, 2); 270 ste_mii_send(sc, frame->mii_phyaddr, 5); 271 ste_mii_send(sc, frame->mii_regaddr, 5); 272 273 /* Turn off xmit. */ 274 MII_CLR(STE_PHYCTL_MDIR); 275 276 /* Idle bit */ 277 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 278 DELAY(1); 279 MII_SET(STE_PHYCTL_MCLK); 280 DELAY(1); 281 282 /* Check for ack */ 283 MII_CLR(STE_PHYCTL_MCLK); 284 DELAY(1); 285 MII_SET(STE_PHYCTL_MCLK); 286 DELAY(1); 287 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 288 289 /* 290 * Now try reading data bits. If the ack failed, we still 291 * need to clock through 16 cycles to keep the PHY(s) in sync. 292 */ 293 if (ack) { 294 for(i = 0; i < 16; i++) { 295 MII_CLR(STE_PHYCTL_MCLK); 296 DELAY(1); 297 MII_SET(STE_PHYCTL_MCLK); 298 DELAY(1); 299 } 300 goto fail; 301 } 302 303 for (i = 0x8000; i; i >>= 1) { 304 MII_CLR(STE_PHYCTL_MCLK); 305 DELAY(1); 306 if (!ack) { 307 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 308 frame->mii_data |= i; 309 DELAY(1); 310 } 311 MII_SET(STE_PHYCTL_MCLK); 312 DELAY(1); 313 } 314 315fail: 316 317 MII_CLR(STE_PHYCTL_MCLK); 318 DELAY(1); 319 MII_SET(STE_PHYCTL_MCLK); 320 DELAY(1); 321 322 splx(s); 323 324 if (ack) 325 return(1); 326 return(0); 327} 328 329/* 330 * Write to a PHY register through the MII. 331 */ 332static int ste_mii_writereg(sc, frame) 333 struct ste_softc *sc; 334 struct ste_mii_frame *frame; 335 336{ 337 int s; 338 339 s = splimp(); 340 /* 341 * Set up frame for TX. 342 */ 343 344 frame->mii_stdelim = STE_MII_STARTDELIM; 345 frame->mii_opcode = STE_MII_WRITEOP; 346 frame->mii_turnaround = STE_MII_TURNAROUND; 347 348 /* 349 * Turn on data output. 350 */ 351 MII_SET(STE_PHYCTL_MDIR); 352 353 ste_mii_sync(sc); 354 355 ste_mii_send(sc, frame->mii_stdelim, 2); 356 ste_mii_send(sc, frame->mii_opcode, 2); 357 ste_mii_send(sc, frame->mii_phyaddr, 5); 358 ste_mii_send(sc, frame->mii_regaddr, 5); 359 ste_mii_send(sc, frame->mii_turnaround, 2); 360 ste_mii_send(sc, frame->mii_data, 16); 361 362 /* Idle bit. */ 363 MII_SET(STE_PHYCTL_MCLK); 364 DELAY(1); 365 MII_CLR(STE_PHYCTL_MCLK); 366 DELAY(1); 367 368 /* 369 * Turn off xmit. 370 */ 371 MII_CLR(STE_PHYCTL_MDIR); 372 373 splx(s); 374 375 return(0); 376} 377 378static int ste_miibus_readreg(dev, phy, reg) 379 device_t dev; 380 int phy, reg; 381{ 382 struct ste_softc *sc; 383 struct ste_mii_frame frame; 384 385 sc = device_get_softc(dev); 386 387 bzero((char *)&frame, sizeof(frame)); 388 389 frame.mii_phyaddr = phy; 390 frame.mii_regaddr = reg; 391 ste_mii_readreg(sc, &frame); 392 393 return(frame.mii_data); 394} 395 396static int ste_miibus_writereg(dev, phy, reg, data) 397 device_t dev; 398 int phy, reg, data; 399{ 400 struct ste_softc *sc; 401 struct ste_mii_frame frame; 402 403 sc = device_get_softc(dev); 404 bzero((char *)&frame, sizeof(frame)); 405 406 frame.mii_phyaddr = phy; 407 frame.mii_regaddr = reg; 408 frame.mii_data = data; 409 410 ste_mii_writereg(sc, &frame); 411 412 return(0); 413} 414 415static void ste_miibus_statchg(dev) 416 device_t dev; 417{ 418 struct ste_softc *sc; 419 struct mii_data *mii; 420 421 sc = device_get_softc(dev); 422 mii = device_get_softc(sc->ste_miibus); 423 424 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 425 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 426 } else { 427 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 428 } 429 430 return; 431} 432 433static int ste_ifmedia_upd(ifp) 434 struct ifnet *ifp; 435{ 436 struct ste_softc *sc; 437 struct mii_data *mii; 438 439 sc = ifp->if_softc; 440 mii = device_get_softc(sc->ste_miibus); 441 sc->ste_link = 0; 442 if (mii->mii_instance) { 443 struct mii_softc *miisc; 444 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 445 miisc = LIST_NEXT(miisc, mii_list)) 446 mii_phy_reset(miisc); 447 } 448 mii_mediachg(mii); 449 450 return(0); 451} 452 453static void ste_ifmedia_sts(ifp, ifmr) 454 struct ifnet *ifp; 455 struct ifmediareq *ifmr; 456{ 457 struct ste_softc *sc; 458 struct mii_data *mii; 459 460 sc = ifp->if_softc; 461 mii = device_get_softc(sc->ste_miibus); 462 463 mii_pollstat(mii); 464 ifmr->ifm_active = mii->mii_media_active; 465 ifmr->ifm_status = mii->mii_media_status; 466 467 return; 468} 469 470static void ste_wait(sc) 471 struct ste_softc *sc; 472{ 473 register int i; 474 475 for (i = 0; i < STE_TIMEOUT; i++) { 476 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 477 break; 478 } 479 480 if (i == STE_TIMEOUT) 481 printf("ste%d: command never completed!\n", sc->ste_unit); 482 483 return; 484} 485 486/* 487 * The EEPROM is slow: give it time to come ready after issuing 488 * it a command. 489 */ 490static int ste_eeprom_wait(sc) 491 struct ste_softc *sc; 492{ 493 int i; 494 495 DELAY(1000); 496 497 for (i = 0; i < 100; i++) { 498 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 499 DELAY(1000); 500 else 501 break; 502 } 503 504 if (i == 100) { 505 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 506 return(1); 507 } 508 509 return(0); 510} 511 512/* 513 * Read a sequence of words from the EEPROM. Note that ethernet address 514 * data is stored in the EEPROM in network byte order. 515 */ 516static int ste_read_eeprom(sc, dest, off, cnt, swap) 517 struct ste_softc *sc; 518 caddr_t dest; 519 int off; 520 int cnt; 521 int swap; 522{ 523 int err = 0, i; 524 u_int16_t word = 0, *ptr; 525 526 if (ste_eeprom_wait(sc)) 527 return(1); 528 529 for (i = 0; i < cnt; i++) { 530 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 531 err = ste_eeprom_wait(sc); 532 if (err) 533 break; 534 word = CSR_READ_2(sc, STE_EEPROM_DATA); 535 ptr = (u_int16_t *)(dest + (i * 2)); 536 if (swap) 537 *ptr = ntohs(word); 538 else 539 *ptr = word; 540 } 541 542 return(err ? 1 : 0); 543} 544 545static u_int8_t ste_calchash(addr) 546 caddr_t addr; 547{ 548 549 u_int32_t crc, carry; 550 int i, j; 551 u_int8_t c; 552 553 /* Compute CRC for the address value. */ 554 crc = 0xFFFFFFFF; /* initial value */ 555 556 for (i = 0; i < 6; i++) { 557 c = *(addr + i); 558 for (j = 0; j < 8; j++) { 559 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 560 crc <<= 1; 561 c >>= 1; 562 if (carry) 563 crc = (crc ^ 0x04c11db6) | carry; 564 } 565 } 566 567 /* return the filter bit position */ 568 return(crc & 0x0000003F); 569} 570 571static void ste_setmulti(sc) 572 struct ste_softc *sc; 573{ 574 struct ifnet *ifp; 575 int h = 0; 576 u_int32_t hashes[2] = { 0, 0 }; 577 struct ifmultiaddr *ifma; 578 579 ifp = &sc->arpcom.ac_if; 580 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 581 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 582 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 583 return; 584 } 585 586 /* first, zot all the existing hash bits */ 587 CSR_WRITE_4(sc, STE_MAR0, 0); 588 CSR_WRITE_4(sc, STE_MAR1, 0); 589 590 /* now program new ones */ 591 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 592 ifma = ifma->ifma_link.le_next) { 593 if (ifma->ifma_addr->sa_family != AF_LINK) 594 continue; 595 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 596 if (h < 32) 597 hashes[0] |= (1 << h); 598 else 599 hashes[1] |= (1 << (h - 32)); 600 } 601 602 CSR_WRITE_4(sc, STE_MAR0, hashes[0]); 603 CSR_WRITE_4(sc, STE_MAR1, hashes[1]); 604 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 605 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 606 607 return; 608} 609 610static void ste_intr(xsc) 611 void *xsc; 612{ 613 struct ste_softc *sc; 614 struct ifnet *ifp; 615 u_int16_t status; 616 617 sc = xsc; 618 ifp = &sc->arpcom.ac_if; 619 620 /* See if this is really our interrupt. */ 621 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 622 return; 623 624 for (;;) { 625 status = CSR_READ_2(sc, STE_ISR_ACK); 626 627 if (!(status & STE_INTRS)) 628 break; 629 630 if (status & STE_ISR_RX_DMADONE) 631 ste_rxeof(sc); 632 633 if (status & STE_ISR_TX_DMADONE) 634 ste_txeof(sc); 635 636 if (status & STE_ISR_TX_DONE) 637 ste_txeoc(sc); 638 639 if (status & STE_ISR_STATS_OFLOW) { 640 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 641 ste_stats_update(sc); 642 } 643 644 if (status & STE_ISR_HOSTERR) { 645 ste_reset(sc); 646 ste_init(sc); 647 } 648 } 649 650 /* Re-enable interrupts */ 651 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 652 653 if (ifp->if_snd.ifq_head != NULL) 654 ste_start(ifp); 655 656 return; 657} 658 659/* 660 * A frame has been uploaded: pass the resulting mbuf chain up to 661 * the higher level protocols. 662 */ 663static void ste_rxeof(sc) 664 struct ste_softc *sc; 665{ 666 struct ether_header *eh; 667 struct mbuf *m; 668 struct ifnet *ifp; 669 struct ste_chain_onefrag *cur_rx; 670 int total_len = 0; 671 u_int32_t rxstat; 672 673 ifp = &sc->arpcom.ac_if; 674 675again: 676 677 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) { 678 cur_rx = sc->ste_cdata.ste_rx_head; 679 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 680 681 /* 682 * If an error occurs, update stats, clear the 683 * status word and leave the mbuf cluster in place: 684 * it should simply get re-used next time this descriptor 685 * comes up in the ring. 686 */ 687 if (rxstat & STE_RXSTAT_FRAME_ERR) { 688 ifp->if_ierrors++; 689 cur_rx->ste_ptr->ste_status = 0; 690 continue; 691 } 692 693 /* 694 * If there error bit was not set, the upload complete 695 * bit should be set which means we have a valid packet. 696 * If not, something truly strange has happened. 697 */ 698 if (!(rxstat & STE_RXSTAT_DMADONE)) { 699 printf("ste%d: bad receive status -- packet dropped", 700 sc->ste_unit); 701 ifp->if_ierrors++; 702 cur_rx->ste_ptr->ste_status = 0; 703 continue; 704 } 705 706 /* No errors; receive the packet. */ 707 m = cur_rx->ste_mbuf; 708 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 709 710 /* 711 * Try to conjure up a new mbuf cluster. If that 712 * fails, it means we have an out of memory condition and 713 * should leave the buffer in place and continue. This will 714 * result in a lost packet, but there's little else we 715 * can do in this situation. 716 */ 717 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 718 ifp->if_ierrors++; 719 cur_rx->ste_ptr->ste_status = 0; 720 continue; 721 } 722 723 ifp->if_ipackets++; 724 eh = mtod(m, struct ether_header *); 725 m->m_pkthdr.rcvif = ifp; 726 m->m_pkthdr.len = m->m_len = total_len; 727 728 /* Remove header from mbuf and pass it on. */ 729 m_adj(m, sizeof(struct ether_header)); 730 ether_input(ifp, eh, m); 731 } 732 733 /* 734 * Handle the 'end of channel' condition. When the upload 735 * engine hits the end of the RX ring, it will stall. This 736 * is our cue to flush the RX ring, reload the uplist pointer 737 * register and unstall the engine. 738 * XXX This is actually a little goofy. With the ThunderLAN 739 * chip, you get an interrupt when the receiver hits the end 740 * of the receive ring, which tells you exactly when you 741 * you need to reload the ring pointer. Here we have to 742 * fake it. I'm mad at myself for not being clever enough 743 * to avoid the use of a goto here. 744 */ 745 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 || 746 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) { 747 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 748 ste_wait(sc); 749 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 750 vtophys(&sc->ste_ldata->ste_rx_list[0])); 751 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0]; 752 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 753 goto again; 754 } 755 756 return; 757} 758 759static void ste_txeoc(sc) 760 struct ste_softc *sc; 761{ 762 u_int8_t txstat; 763 struct ifnet *ifp; 764 765 ifp = &sc->arpcom.ac_if; 766 767 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 768 STE_TXSTATUS_TXDONE) { 769 if (txstat & STE_TXSTATUS_UNDERRUN || 770 txstat & STE_TXSTATUS_EXCESSCOLLS || 771 txstat & STE_TXSTATUS_RECLAIMERR) { 772 ifp->if_oerrors++; 773 printf("ste%d: transmission error: %x\n", 774 sc->ste_unit, txstat); 775 776 ste_reset(sc); 777 ste_init(sc); 778 779 if (txstat & STE_TXSTATUS_UNDERRUN && 780 sc->ste_tx_thresh < STE_PACKET_SIZE) { 781 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 782 printf("ste%d: tx underrun, increasing tx" 783 " start threshold to %d bytes\n", 784 sc->ste_unit, sc->ste_tx_thresh); 785 } 786 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 787 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 788 (STE_PACKET_SIZE >> 4)); 789 } 790 ste_init(sc); 791 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 792 } 793 794 return; 795} 796 797static void ste_txeof(sc) 798 struct ste_softc *sc; 799{ 800 struct ste_chain *cur_tx = NULL; 801 struct ifnet *ifp; 802 int idx; 803 804 ifp = &sc->arpcom.ac_if; 805 806 idx = sc->ste_cdata.ste_tx_cons; 807 while(idx != sc->ste_cdata.ste_tx_prod) { 808 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 809 810 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 811 break; 812 813 if (cur_tx->ste_mbuf != NULL) { 814 m_freem(cur_tx->ste_mbuf); 815 cur_tx->ste_mbuf = NULL; 816 } 817 818 ifp->if_opackets++; 819 820 sc->ste_cdata.ste_tx_cnt--; 821 STE_INC(idx, STE_TX_LIST_CNT); 822 ifp->if_timer = 0; 823 } 824 825 sc->ste_cdata.ste_tx_cons = idx; 826 827 if (cur_tx != NULL) 828 ifp->if_flags &= ~IFF_OACTIVE; 829 830 return; 831} 832 833static void ste_stats_update(xsc) 834 void *xsc; 835{ 836 struct ste_softc *sc; 837 struct ste_stats stats; 838 struct ifnet *ifp; 839 struct mii_data *mii; 840 int i, s; 841 u_int8_t *p; 842 843 s = splimp(); 844 845 sc = xsc; 846 ifp = &sc->arpcom.ac_if; 847 mii = device_get_softc(sc->ste_miibus); 848 849 p = (u_int8_t *)&stats; 850 851 for (i = 0; i < sizeof(stats); i++) { 852 *p = CSR_READ_1(sc, STE_STATS + i); 853 p++; 854 } 855 856 ifp->if_collisions += stats.ste_single_colls + 857 stats.ste_multi_colls + stats.ste_late_colls; 858 859 mii_tick(mii); 860 if (!sc->ste_link) { 861 mii_pollstat(mii); 862 if (mii->mii_media_status & IFM_ACTIVE && 863 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 864 sc->ste_link++; 865 if (ifp->if_snd.ifq_head != NULL) 866 ste_start(ifp); 867 } 868 869 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 870 splx(s); 871 872 return; 873} 874 875 876/* 877 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 878 * IDs against our list and return a device name if we find a match. 879 */ 880static int ste_probe(dev) 881 device_t dev; 882{ 883 struct ste_type *t; 884 885 t = ste_devs; 886 887 while(t->ste_name != NULL) { 888 if ((pci_get_vendor(dev) == t->ste_vid) && 889 (pci_get_device(dev) == t->ste_did)) { 890 device_set_desc(dev, t->ste_name); 891 return(0); 892 } 893 t++; 894 } 895 896 return(ENXIO); 897} 898 899/* 900 * Attach the interface. Allocate softc structures, do ifmedia 901 * setup and ethernet/BPF attach. 902 */ 903static int ste_attach(dev) 904 device_t dev; 905{ 906 int s; 907 u_int32_t command; 908 struct ste_softc *sc; 909 struct ifnet *ifp; 910 int unit, error = 0, rid; 911 912 s = splimp(); 913 914 sc = device_get_softc(dev); 915 unit = device_get_unit(dev); 916 bzero(sc, sizeof(struct ste_softc)); 917 918 /* 919 * Handle power management nonsense. 920 */ 921 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 922 if (command == 0x01) { 923 924 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 925 if (command & STE_PSTATE_MASK) { 926 u_int32_t iobase, membase, irq; 927 928 /* Save important PCI config data. */ 929 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 930 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 931 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 932 933 /* Reset the power state. */ 934 printf("ste%d: chip is in D%d power mode " 935 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 936 command &= 0xFFFFFFFC; 937 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 938 939 /* Restore PCI config data. */ 940 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 941 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 942 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 943 } 944 } 945 946 /* 947 * Map control/status registers. 948 */ 949 command = pci_read_config(dev, PCIR_COMMAND, 4); 950 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 951 pci_write_config(dev, PCIR_COMMAND, command, 4); 952 command = pci_read_config(dev, PCIR_COMMAND, 4); 953 954#ifdef STE_USEIOSPACE 955 if (!(command & PCIM_CMD_PORTEN)) { 956 printf("ste%d: failed to enable I/O ports!\n", unit); 957 error = ENXIO; 958 goto fail; 959 } 960#else 961 if (!(command & PCIM_CMD_MEMEN)) { 962 printf("ste%d: failed to enable memory mapping!\n", unit); 963 error = ENXIO; 964 goto fail; 965 } 966#endif 967 968 rid = STE_RID; 969 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 970 0, ~0, 1, RF_ACTIVE); 971 972 if (sc->ste_res == NULL) { 973 printf ("ste%d: couldn't map ports/memory\n", unit); 974 error = ENXIO; 975 goto fail; 976 } 977 978 sc->ste_btag = rman_get_bustag(sc->ste_res); 979 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 980 981 rid = 0; 982 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 983 RF_SHAREABLE | RF_ACTIVE); 984 985 if (sc->ste_irq == NULL) { 986 printf("ste%d: couldn't map interrupt\n", unit); 987 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 988 error = ENXIO; 989 goto fail; 990 } 991 992 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 993 ste_intr, sc, &sc->ste_intrhand); 994 995 if (error) { 996 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 997 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 998 printf("ste%d: couldn't set up irq\n", unit); 999 goto fail; 1000 } 1001 1002 callout_handle_init(&sc->ste_stat_ch); 1003 1004 /* Reset the adapter. */ 1005 ste_reset(sc); 1006 1007 /* 1008 * Get station address from the EEPROM. 1009 */ 1010 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1011 STE_EEADDR_NODE0, 3, 0)) { 1012 printf("ste%d: failed to read station address\n", unit); 1013 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1014 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1015 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1016 error = ENXIO;; 1017 goto fail; 1018 } 1019 1020 /* 1021 * A Sundance chip was detected. Inform the world. 1022 */ 1023 printf("ste%d: Ethernet address: %6D\n", unit, 1024 sc->arpcom.ac_enaddr, ":"); 1025 1026 sc->ste_unit = unit; 1027 1028 /* Allocate the descriptor queues. */ 1029 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1030 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1031 1032 if (sc->ste_ldata == NULL) { 1033 printf("ste%d: no memory for list buffers!\n", unit); 1034 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1035 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1036 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1037 error = ENXIO; 1038 goto fail; 1039 } 1040 1041 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1042 1043 /* Do MII setup. */ 1044 if (mii_phy_probe(dev, &sc->ste_miibus, 1045 ste_ifmedia_upd, ste_ifmedia_sts)) { 1046 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1047 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1048 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1049 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1050 contigfree(sc->ste_ldata, 1051 sizeof(struct ste_list_data), M_DEVBUF); 1052 error = ENXIO; 1053 goto fail; 1054 } 1055 1056 ifp = &sc->arpcom.ac_if; 1057 ifp->if_softc = sc; 1058 ifp->if_unit = unit; 1059 ifp->if_name = "ste"; 1060 ifp->if_mtu = ETHERMTU; 1061 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1062 ifp->if_ioctl = ste_ioctl; 1063 ifp->if_output = ether_output; 1064 ifp->if_start = ste_start; 1065 ifp->if_watchdog = ste_watchdog; 1066 ifp->if_init = ste_init; 1067 ifp->if_baudrate = 10000000; 1068 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1069 1070 /* 1071 * Call MI attach routines. 1072 */ 1073 1074 if_attach(ifp); 1075 ether_ifattach(ifp); 1076 1077 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1078 1079fail: 1080 splx(s); 1081 return(error); 1082} 1083 1084static int ste_detach(dev) 1085 device_t dev; 1086{ 1087 struct ste_softc *sc; 1088 struct ifnet *ifp; 1089 int s; 1090 1091 s = splimp(); 1092 1093 sc = device_get_softc(dev); 1094 ifp = &sc->arpcom.ac_if; 1095 1096 ste_stop(sc); 1097 if_detach(ifp); 1098 1099 bus_generic_detach(dev); 1100 device_delete_child(dev, sc->ste_miibus); 1101 1102 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1103 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1104 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1105 1106 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1107 1108 splx(s); 1109 1110 return(0); 1111} 1112 1113static int ste_newbuf(sc, c, m) 1114 struct ste_softc *sc; 1115 struct ste_chain_onefrag *c; 1116 struct mbuf *m; 1117{ 1118 struct mbuf *m_new = NULL; 1119 1120 if (m == NULL) { 1121 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1122 if (m_new == NULL) { 1123 printf("ste%d: no memory for rx list -- " 1124 "packet dropped\n", sc->ste_unit); 1125 return(ENOBUFS); 1126 } 1127 MCLGET(m_new, M_DONTWAIT); 1128 if (!(m_new->m_flags & M_EXT)) { 1129 printf("ste%d: no memory for rx list -- " 1130 "packet dropped\n", sc->ste_unit); 1131 m_freem(m_new); 1132 return(ENOBUFS); 1133 } 1134 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1135 } else { 1136 m_new = m; 1137 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1138 m_new->m_data = m_new->m_ext.ext_buf; 1139 } 1140 1141 m_adj(m_new, ETHER_ALIGN); 1142 1143 c->ste_mbuf = m_new; 1144 c->ste_ptr->ste_status = 0; 1145 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1146 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; 1147 1148 return(0); 1149} 1150 1151static int ste_init_rx_list(sc) 1152 struct ste_softc *sc; 1153{ 1154 struct ste_chain_data *cd; 1155 struct ste_list_data *ld; 1156 int i; 1157 1158 cd = &sc->ste_cdata; 1159 ld = sc->ste_ldata; 1160 1161 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1162 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1163 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1164 return(ENOBUFS); 1165 if (i == (STE_RX_LIST_CNT - 1)) { 1166 cd->ste_rx_chain[i].ste_next = 1167 &cd->ste_rx_chain[0]; 1168 ld->ste_rx_list[i].ste_next = 1169 vtophys(&ld->ste_rx_list[0]); 1170 } else { 1171 cd->ste_rx_chain[i].ste_next = 1172 &cd->ste_rx_chain[i + 1]; 1173 ld->ste_rx_list[i].ste_next = 1174 vtophys(&ld->ste_rx_list[i + 1]); 1175 } 1176 1177 } 1178 1179 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1180 1181 return(0); 1182} 1183 1184static void ste_init_tx_list(sc) 1185 struct ste_softc *sc; 1186{ 1187 struct ste_chain_data *cd; 1188 struct ste_list_data *ld; 1189 int i; 1190 1191 cd = &sc->ste_cdata; 1192 ld = sc->ste_ldata; 1193 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1194 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1195 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1196 if (i == (STE_TX_LIST_CNT - 1)) 1197 cd->ste_tx_chain[i].ste_next = 1198 &cd->ste_tx_chain[0]; 1199 else 1200 cd->ste_tx_chain[i].ste_next = 1201 &cd->ste_tx_chain[i + 1]; 1202 if (i == 0) 1203 cd->ste_tx_chain[i].ste_prev = 1204 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1205 else 1206 cd->ste_tx_chain[i].ste_prev = 1207 &cd->ste_tx_chain[i - 1]; 1208 } 1209 1210 1211 bzero((char *)ld->ste_tx_list, 1212 sizeof(struct ste_desc) * STE_TX_LIST_CNT); 1213 1214 cd->ste_tx_prod = 0; 1215 cd->ste_tx_cons = 0; 1216 cd->ste_tx_cnt = 0; 1217 1218 return; 1219} 1220 1221static void ste_init(xsc) 1222 void *xsc; 1223{ 1224 struct ste_softc *sc; 1225 int i, s; 1226 struct ifnet *ifp; 1227 struct mii_data *mii; 1228 1229 s = splimp(); 1230 1231 sc = xsc; 1232 ifp = &sc->arpcom.ac_if; 1233 mii = device_get_softc(sc->ste_miibus); 1234 1235 ste_stop(sc); 1236 1237 /* Init our MAC address */ 1238 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1239 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1240 } 1241 1242 /* Init RX list */ 1243 if (ste_init_rx_list(sc) == ENOBUFS) { 1244 printf("ste%d: initialization failed: no " 1245 "memory for RX buffers\n", sc->ste_unit); 1246 ste_stop(sc); 1247 splx(s); 1248 return; 1249 } 1250 1251 /* Init TX descriptors */ 1252 ste_init_tx_list(sc); 1253 1254 /* Set the TX freethresh value */ 1255 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1256 1257 /* Set the TX start threshold for best performance. */ 1258 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1259 1260 /* Set the TX reclaim threshold. */ 1261 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1262 1263 /* Set up the RX filter. */ 1264 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1265 1266 /* If we want promiscuous mode, set the allframes bit. */ 1267 if (ifp->if_flags & IFF_PROMISC) { 1268 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1269 } else { 1270 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1271 } 1272 1273 /* Set capture broadcast bit to accept broadcast frames. */ 1274 if (ifp->if_flags & IFF_BROADCAST) { 1275 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1276 } else { 1277 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1278 } 1279 1280 ste_setmulti(sc); 1281 1282 /* Load the address of the RX list. */ 1283 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1284 ste_wait(sc); 1285 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1286 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1287 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1288 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1289 1290 /* Set TX polling interval */ 1291 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1292 1293 /* Load address of the TX list */ 1294 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1295 ste_wait(sc); 1296 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1297 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1298 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1299 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1300 ste_wait(sc); 1301 1302 /* Enable receiver and transmitter */ 1303 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1304 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1305 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1306 1307 /* Enable stats counters. */ 1308 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1309 1310 /* Enable interrupts. */ 1311 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1312 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1313 1314 ste_ifmedia_upd(ifp); 1315 1316 ifp->if_flags |= IFF_RUNNING; 1317 ifp->if_flags &= ~IFF_OACTIVE; 1318 1319 splx(s); 1320 1321 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1322 1323 return; 1324} 1325 1326static void ste_stop(sc) 1327 struct ste_softc *sc; 1328{ 1329 int i; 1330 struct ifnet *ifp; 1331 1332 ifp = &sc->arpcom.ac_if; 1333 1334 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1335 1336 CSR_WRITE_2(sc, STE_IMR, 0); 1337 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1338 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1339 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1340 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1341 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1342 ste_wait(sc); 1343 1344 sc->ste_link = 0; 1345 1346 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1347 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1348 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1349 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1350 } 1351 } 1352 1353 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1354 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1355 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1356 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1357 } 1358 } 1359 1360 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1361 1362 return; 1363} 1364 1365static void ste_reset(sc) 1366 struct ste_softc *sc; 1367{ 1368 int i; 1369 1370 STE_SETBIT4(sc, STE_ASICCTL, 1371 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1372 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1373 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1374 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1375 STE_ASICCTL_EXTRESET_RESET); 1376 1377 DELAY(100000); 1378 1379 for (i = 0; i < STE_TIMEOUT; i++) { 1380 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1381 break; 1382 } 1383 1384 if (i == STE_TIMEOUT) 1385 printf("ste%d: global reset never completed\n", sc->ste_unit); 1386 1387 return; 1388} 1389 1390static int ste_ioctl(ifp, command, data) 1391 struct ifnet *ifp; 1392 u_long command; 1393 caddr_t data; 1394{ 1395 struct ste_softc *sc; 1396 struct ifreq *ifr; 1397 struct mii_data *mii; 1398 int error = 0, s; 1399 1400 s = splimp(); 1401 1402 sc = ifp->if_softc; 1403 ifr = (struct ifreq *)data; 1404 1405 switch(command) { 1406 case SIOCSIFADDR: 1407 case SIOCGIFADDR: 1408 case SIOCSIFMTU: 1409 error = ether_ioctl(ifp, command, data); 1410 break; 1411 case SIOCSIFFLAGS: 1412 if (ifp->if_flags & IFF_UP) { 1413 if (ifp->if_flags & IFF_RUNNING && 1414 ifp->if_flags & IFF_PROMISC && 1415 !(sc->ste_if_flags & IFF_PROMISC)) { 1416 STE_SETBIT1(sc, STE_RX_MODE, 1417 STE_RXMODE_PROMISC); 1418 } else if (ifp->if_flags & IFF_RUNNING && 1419 !(ifp->if_flags & IFF_PROMISC) && 1420 sc->ste_if_flags & IFF_PROMISC) { 1421 STE_CLRBIT1(sc, STE_RX_MODE, 1422 STE_RXMODE_PROMISC); 1423 } else if (!(ifp->if_flags & IFF_RUNNING)) { 1424 sc->ste_tx_thresh = STE_MIN_FRAMELEN; 1425 ste_init(sc); 1426 } 1427 } else { 1428 if (ifp->if_flags & IFF_RUNNING) 1429 ste_stop(sc); 1430 } 1431 sc->ste_if_flags = ifp->if_flags; 1432 error = 0; 1433 break; 1434 case SIOCADDMULTI: 1435 case SIOCDELMULTI: 1436 ste_setmulti(sc); 1437 error = 0; 1438 break; 1439 case SIOCGIFMEDIA: 1440 case SIOCSIFMEDIA: 1441 mii = device_get_softc(sc->ste_miibus); 1442 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1443 break; 1444 default: 1445 error = EINVAL; 1446 break; 1447 } 1448 1449 splx(s); 1450 1451 return(error); 1452} 1453 1454static int ste_encap(sc, c, m_head) 1455 struct ste_softc *sc; 1456 struct ste_chain *c; 1457 struct mbuf *m_head; 1458{ 1459 int frag = 0; 1460 struct ste_frag *f = NULL; 1461 struct mbuf *m; 1462 struct ste_desc *d; 1463 int total_len = 0; 1464 1465 d = c->ste_ptr; 1466 d->ste_ctl = 0; 1467 d->ste_next = 0; 1468 1469 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1470 if (m->m_len != 0) { 1471 if (frag == STE_MAXFRAGS) 1472 break; 1473 total_len += m->m_len; 1474 f = &c->ste_ptr->ste_frags[frag]; 1475 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1476 f->ste_len = m->m_len; 1477 frag++; 1478 } 1479 } 1480 1481 c->ste_mbuf = m_head; 1482 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1483 c->ste_ptr->ste_ctl = total_len; 1484 1485 return(0); 1486} 1487 1488static void ste_start(ifp) 1489 struct ifnet *ifp; 1490{ 1491 struct ste_softc *sc; 1492 struct mbuf *m_head = NULL; 1493 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1494 int idx; 1495 1496 sc = ifp->if_softc; 1497 1498 if (!sc->ste_link) 1499 return; 1500 1501 if (ifp->if_flags & IFF_OACTIVE) 1502 return; 1503 1504 idx = sc->ste_cdata.ste_tx_prod; 1505 start_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1506 1507 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1508 1509 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1510 ifp->if_flags |= IFF_OACTIVE; 1511 break; 1512 } 1513 1514 IF_DEQUEUE(&ifp->if_snd, m_head); 1515 if (m_head == NULL) 1516 break; 1517 1518 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1519 1520 ste_encap(sc, cur_tx, m_head); 1521 1522 if (prev != NULL) 1523 prev->ste_ptr->ste_next = cur_tx->ste_phys; 1524 prev = cur_tx; 1525 1526 /* 1527 * If there's a BPF listener, bounce a copy of this frame 1528 * to him. 1529 */ 1530 if (ifp->if_bpf) 1531 bpf_mtap(ifp, cur_tx->ste_mbuf); 1532 1533 STE_INC(idx, STE_TX_LIST_CNT); 1534 sc->ste_cdata.ste_tx_cnt++; 1535 } 1536 1537 if (cur_tx == NULL) 1538 return; 1539 1540 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR; 1541 1542 /* Start transmission */ 1543 sc->ste_cdata.ste_tx_prod = idx; 1544 start_tx->ste_prev->ste_ptr->ste_next = start_tx->ste_phys; 1545 1546 ifp->if_timer = 5; 1547 1548 return; 1549} 1550 1551static void ste_watchdog(ifp) 1552 struct ifnet *ifp; 1553{ 1554 struct ste_softc *sc; 1555 1556 sc = ifp->if_softc; 1557 1558 ifp->if_oerrors++; 1559 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1560 1561 ste_txeoc(sc); 1562 ste_txeof(sc); 1563 ste_rxeof(sc); 1564 ste_reset(sc); 1565 ste_init(sc); 1566 1567 if (ifp->if_snd.ifq_head != NULL) 1568 ste_start(ifp); 1569 1570 return; 1571} 1572 1573static void ste_shutdown(dev) 1574 device_t dev; 1575{ 1576 struct ste_softc *sc; 1577 1578 sc = device_get_softc(dev); 1579 1580 ste_stop(sc); 1581 1582 return; 1583} 1584