if_ste.c revision 59758
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 59758 2000-04-29 13:41:57Z peter $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48 49#include <net/bpf.h> 50 51#include "opt_bdg.h" 52#ifdef BRIDGE 53#include <net/bridge.h> 54#endif 55 56#include <vm/vm.h> /* for vtophys */ 57#include <vm/pmap.h> /* for vtophys */ 58#include <machine/clock.h> /* for DELAY */ 59#include <machine/bus_memio.h> 60#include <machine/bus_pio.h> 61#include <machine/bus.h> 62#include <machine/resource.h> 63#include <sys/bus.h> 64#include <sys/rman.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <pci/pcireg.h> 70#include <pci/pcivar.h> 71 72/* "controller miibus0" required. See GENERIC if you get errors here. */ 73#include "miibus_if.h" 74 75#define STE_USEIOSPACE 76 77#include <pci/if_stereg.h> 78 79MODULE_DEPEND(ste, miibus, 1, 1, 1); 80 81#if !defined(lint) 82static const char rcsid[] = 83 "$FreeBSD: head/sys/pci/if_ste.c 59758 2000-04-29 13:41:57Z peter $"; 84#endif 85 86/* 87 * Various supported device vendors/types and their names. 88 */ 89static struct ste_type ste_devs[] = { 90 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 91 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 92 { 0, 0, NULL } 93}; 94 95static int ste_probe __P((device_t)); 96static int ste_attach __P((device_t)); 97static int ste_detach __P((device_t)); 98static void ste_init __P((void *)); 99static void ste_intr __P((void *)); 100static void ste_rxeof __P((struct ste_softc *)); 101static void ste_txeoc __P((struct ste_softc *)); 102static void ste_txeof __P((struct ste_softc *)); 103static void ste_stats_update __P((void *)); 104static void ste_stop __P((struct ste_softc *)); 105static void ste_reset __P((struct ste_softc *)); 106static int ste_ioctl __P((struct ifnet *, u_long, caddr_t)); 107static int ste_encap __P((struct ste_softc *, struct ste_chain *, 108 struct mbuf *)); 109static void ste_start __P((struct ifnet *)); 110static void ste_watchdog __P((struct ifnet *)); 111static void ste_shutdown __P((device_t)); 112static int ste_newbuf __P((struct ste_softc *, 113 struct ste_chain_onefrag *, 114 struct mbuf *)); 115static int ste_ifmedia_upd __P((struct ifnet *)); 116static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 117 118static void ste_mii_sync __P((struct ste_softc *)); 119static void ste_mii_send __P((struct ste_softc *, u_int32_t, int)); 120static int ste_mii_readreg __P((struct ste_softc *, 121 struct ste_mii_frame *)); 122static int ste_mii_writereg __P((struct ste_softc *, 123 struct ste_mii_frame *)); 124static int ste_miibus_readreg __P((device_t, int, int)); 125static int ste_miibus_writereg __P((device_t, int, int, int)); 126static void ste_miibus_statchg __P((device_t)); 127 128static int ste_eeprom_wait __P((struct ste_softc *)); 129static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int, 130 int, int)); 131static void ste_wait __P((struct ste_softc *)); 132static u_int8_t ste_calchash __P((caddr_t)); 133static void ste_setmulti __P((struct ste_softc *)); 134static int ste_init_rx_list __P((struct ste_softc *)); 135static void ste_init_tx_list __P((struct ste_softc *)); 136 137#ifdef STE_USEIOSPACE 138#define STE_RES SYS_RES_IOPORT 139#define STE_RID STE_PCI_LOIO 140#else 141#define STE_RES SYS_RES_MEMORY 142#define STE_RID STE_PCI_LOMEM 143#endif 144 145static device_method_t ste_methods[] = { 146 /* Device interface */ 147 DEVMETHOD(device_probe, ste_probe), 148 DEVMETHOD(device_attach, ste_attach), 149 DEVMETHOD(device_detach, ste_detach), 150 DEVMETHOD(device_shutdown, ste_shutdown), 151 152 /* bus interface */ 153 DEVMETHOD(bus_print_child, bus_generic_print_child), 154 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 155 156 /* MII interface */ 157 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 158 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 159 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 160 161 { 0, 0 } 162}; 163 164static driver_t ste_driver = { 165 "ste", 166 ste_methods, 167 sizeof(struct ste_softc) 168}; 169 170static devclass_t ste_devclass; 171 172DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 173DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 174 175#define STE_SETBIT4(sc, reg, x) \ 176 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 177 178#define STE_CLRBIT4(sc, reg, x) \ 179 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 180 181#define STE_SETBIT2(sc, reg, x) \ 182 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 183 184#define STE_CLRBIT2(sc, reg, x) \ 185 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 186 187#define STE_SETBIT1(sc, reg, x) \ 188 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 189 190#define STE_CLRBIT1(sc, reg, x) \ 191 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 192 193 194#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 195#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 196 197/* 198 * Sync the PHYs by setting data bit and strobing the clock 32 times. 199 */ 200static void ste_mii_sync(sc) 201 struct ste_softc *sc; 202{ 203 register int i; 204 205 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 206 207 for (i = 0; i < 32; i++) { 208 MII_SET(STE_PHYCTL_MCLK); 209 DELAY(1); 210 MII_CLR(STE_PHYCTL_MCLK); 211 DELAY(1); 212 } 213 214 return; 215} 216 217/* 218 * Clock a series of bits through the MII. 219 */ 220static void ste_mii_send(sc, bits, cnt) 221 struct ste_softc *sc; 222 u_int32_t bits; 223 int cnt; 224{ 225 int i; 226 227 MII_CLR(STE_PHYCTL_MCLK); 228 229 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 230 if (bits & i) { 231 MII_SET(STE_PHYCTL_MDATA); 232 } else { 233 MII_CLR(STE_PHYCTL_MDATA); 234 } 235 DELAY(1); 236 MII_CLR(STE_PHYCTL_MCLK); 237 DELAY(1); 238 MII_SET(STE_PHYCTL_MCLK); 239 } 240} 241 242/* 243 * Read an PHY register through the MII. 244 */ 245static int ste_mii_readreg(sc, frame) 246 struct ste_softc *sc; 247 struct ste_mii_frame *frame; 248 249{ 250 int i, ack, s; 251 252 s = splimp(); 253 254 /* 255 * Set up frame for RX. 256 */ 257 frame->mii_stdelim = STE_MII_STARTDELIM; 258 frame->mii_opcode = STE_MII_READOP; 259 frame->mii_turnaround = 0; 260 frame->mii_data = 0; 261 262 CSR_WRITE_2(sc, STE_PHYCTL, 0); 263 /* 264 * Turn on data xmit. 265 */ 266 MII_SET(STE_PHYCTL_MDIR); 267 268 ste_mii_sync(sc); 269 270 /* 271 * Send command/address info. 272 */ 273 ste_mii_send(sc, frame->mii_stdelim, 2); 274 ste_mii_send(sc, frame->mii_opcode, 2); 275 ste_mii_send(sc, frame->mii_phyaddr, 5); 276 ste_mii_send(sc, frame->mii_regaddr, 5); 277 278 /* Turn off xmit. */ 279 MII_CLR(STE_PHYCTL_MDIR); 280 281 /* Idle bit */ 282 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 283 DELAY(1); 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* Check for ack */ 288 MII_CLR(STE_PHYCTL_MCLK); 289 DELAY(1); 290 MII_SET(STE_PHYCTL_MCLK); 291 DELAY(1); 292 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 293 294 /* 295 * Now try reading data bits. If the ack failed, we still 296 * need to clock through 16 cycles to keep the PHY(s) in sync. 297 */ 298 if (ack) { 299 for(i = 0; i < 16; i++) { 300 MII_CLR(STE_PHYCTL_MCLK); 301 DELAY(1); 302 MII_SET(STE_PHYCTL_MCLK); 303 DELAY(1); 304 } 305 goto fail; 306 } 307 308 for (i = 0x8000; i; i >>= 1) { 309 MII_CLR(STE_PHYCTL_MCLK); 310 DELAY(1); 311 if (!ack) { 312 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 313 frame->mii_data |= i; 314 DELAY(1); 315 } 316 MII_SET(STE_PHYCTL_MCLK); 317 DELAY(1); 318 } 319 320fail: 321 322 MII_CLR(STE_PHYCTL_MCLK); 323 DELAY(1); 324 MII_SET(STE_PHYCTL_MCLK); 325 DELAY(1); 326 327 splx(s); 328 329 if (ack) 330 return(1); 331 return(0); 332} 333 334/* 335 * Write to a PHY register through the MII. 336 */ 337static int ste_mii_writereg(sc, frame) 338 struct ste_softc *sc; 339 struct ste_mii_frame *frame; 340 341{ 342 int s; 343 344 s = splimp(); 345 /* 346 * Set up frame for TX. 347 */ 348 349 frame->mii_stdelim = STE_MII_STARTDELIM; 350 frame->mii_opcode = STE_MII_WRITEOP; 351 frame->mii_turnaround = STE_MII_TURNAROUND; 352 353 /* 354 * Turn on data output. 355 */ 356 MII_SET(STE_PHYCTL_MDIR); 357 358 ste_mii_sync(sc); 359 360 ste_mii_send(sc, frame->mii_stdelim, 2); 361 ste_mii_send(sc, frame->mii_opcode, 2); 362 ste_mii_send(sc, frame->mii_phyaddr, 5); 363 ste_mii_send(sc, frame->mii_regaddr, 5); 364 ste_mii_send(sc, frame->mii_turnaround, 2); 365 ste_mii_send(sc, frame->mii_data, 16); 366 367 /* Idle bit. */ 368 MII_SET(STE_PHYCTL_MCLK); 369 DELAY(1); 370 MII_CLR(STE_PHYCTL_MCLK); 371 DELAY(1); 372 373 /* 374 * Turn off xmit. 375 */ 376 MII_CLR(STE_PHYCTL_MDIR); 377 378 splx(s); 379 380 return(0); 381} 382 383static int ste_miibus_readreg(dev, phy, reg) 384 device_t dev; 385 int phy, reg; 386{ 387 struct ste_softc *sc; 388 struct ste_mii_frame frame; 389 390 sc = device_get_softc(dev); 391 392 bzero((char *)&frame, sizeof(frame)); 393 394 frame.mii_phyaddr = phy; 395 frame.mii_regaddr = reg; 396 ste_mii_readreg(sc, &frame); 397 398 return(frame.mii_data); 399} 400 401static int ste_miibus_writereg(dev, phy, reg, data) 402 device_t dev; 403 int phy, reg, data; 404{ 405 struct ste_softc *sc; 406 struct ste_mii_frame frame; 407 408 sc = device_get_softc(dev); 409 bzero((char *)&frame, sizeof(frame)); 410 411 frame.mii_phyaddr = phy; 412 frame.mii_regaddr = reg; 413 frame.mii_data = data; 414 415 ste_mii_writereg(sc, &frame); 416 417 return(0); 418} 419 420static void ste_miibus_statchg(dev) 421 device_t dev; 422{ 423 struct ste_softc *sc; 424 struct mii_data *mii; 425 426 sc = device_get_softc(dev); 427 mii = device_get_softc(sc->ste_miibus); 428 429 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 430 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } else { 432 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 433 } 434 435 return; 436} 437 438static int ste_ifmedia_upd(ifp) 439 struct ifnet *ifp; 440{ 441 struct ste_softc *sc; 442 struct mii_data *mii; 443 444 sc = ifp->if_softc; 445 mii = device_get_softc(sc->ste_miibus); 446 sc->ste_link = 0; 447 if (mii->mii_instance) { 448 struct mii_softc *miisc; 449 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 450 miisc = LIST_NEXT(miisc, mii_list)) 451 mii_phy_reset(miisc); 452 } 453 mii_mediachg(mii); 454 455 return(0); 456} 457 458static void ste_ifmedia_sts(ifp, ifmr) 459 struct ifnet *ifp; 460 struct ifmediareq *ifmr; 461{ 462 struct ste_softc *sc; 463 struct mii_data *mii; 464 465 sc = ifp->if_softc; 466 mii = device_get_softc(sc->ste_miibus); 467 468 mii_pollstat(mii); 469 ifmr->ifm_active = mii->mii_media_active; 470 ifmr->ifm_status = mii->mii_media_status; 471 472 return; 473} 474 475static void ste_wait(sc) 476 struct ste_softc *sc; 477{ 478 register int i; 479 480 for (i = 0; i < STE_TIMEOUT; i++) { 481 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 482 break; 483 } 484 485 if (i == STE_TIMEOUT) 486 printf("ste%d: command never completed!\n", sc->ste_unit); 487 488 return; 489} 490 491/* 492 * The EEPROM is slow: give it time to come ready after issuing 493 * it a command. 494 */ 495static int ste_eeprom_wait(sc) 496 struct ste_softc *sc; 497{ 498 int i; 499 500 DELAY(1000); 501 502 for (i = 0; i < 100; i++) { 503 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 504 DELAY(1000); 505 else 506 break; 507 } 508 509 if (i == 100) { 510 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 511 return(1); 512 } 513 514 return(0); 515} 516 517/* 518 * Read a sequence of words from the EEPROM. Note that ethernet address 519 * data is stored in the EEPROM in network byte order. 520 */ 521static int ste_read_eeprom(sc, dest, off, cnt, swap) 522 struct ste_softc *sc; 523 caddr_t dest; 524 int off; 525 int cnt; 526 int swap; 527{ 528 int err = 0, i; 529 u_int16_t word = 0, *ptr; 530 531 if (ste_eeprom_wait(sc)) 532 return(1); 533 534 for (i = 0; i < cnt; i++) { 535 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 536 err = ste_eeprom_wait(sc); 537 if (err) 538 break; 539 word = CSR_READ_2(sc, STE_EEPROM_DATA); 540 ptr = (u_int16_t *)(dest + (i * 2)); 541 if (swap) 542 *ptr = ntohs(word); 543 else 544 *ptr = word; 545 } 546 547 return(err ? 1 : 0); 548} 549 550static u_int8_t ste_calchash(addr) 551 caddr_t addr; 552{ 553 554 u_int32_t crc, carry; 555 int i, j; 556 u_int8_t c; 557 558 /* Compute CRC for the address value. */ 559 crc = 0xFFFFFFFF; /* initial value */ 560 561 for (i = 0; i < 6; i++) { 562 c = *(addr + i); 563 for (j = 0; j < 8; j++) { 564 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 565 crc <<= 1; 566 c >>= 1; 567 if (carry) 568 crc = (crc ^ 0x04c11db6) | carry; 569 } 570 } 571 572 /* return the filter bit position */ 573 return(crc & 0x0000003F); 574} 575 576static void ste_setmulti(sc) 577 struct ste_softc *sc; 578{ 579 struct ifnet *ifp; 580 int h = 0; 581 u_int32_t hashes[2] = { 0, 0 }; 582 struct ifmultiaddr *ifma; 583 584 ifp = &sc->arpcom.ac_if; 585 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 586 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 587 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 588 return; 589 } 590 591 /* first, zot all the existing hash bits */ 592 CSR_WRITE_4(sc, STE_MAR0, 0); 593 CSR_WRITE_4(sc, STE_MAR1, 0); 594 595 /* now program new ones */ 596 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 597 ifma = ifma->ifma_link.le_next) { 598 if (ifma->ifma_addr->sa_family != AF_LINK) 599 continue; 600 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 601 if (h < 32) 602 hashes[0] |= (1 << h); 603 else 604 hashes[1] |= (1 << (h - 32)); 605 } 606 607 CSR_WRITE_4(sc, STE_MAR0, hashes[0]); 608 CSR_WRITE_4(sc, STE_MAR1, hashes[1]); 609 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 610 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 611 612 return; 613} 614 615static void ste_intr(xsc) 616 void *xsc; 617{ 618 struct ste_softc *sc; 619 struct ifnet *ifp; 620 u_int16_t status; 621 622 sc = xsc; 623 ifp = &sc->arpcom.ac_if; 624 625 /* See if this is really our interrupt. */ 626 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 627 return; 628 629 for (;;) { 630 status = CSR_READ_2(sc, STE_ISR_ACK); 631 632 if (!(status & STE_INTRS)) 633 break; 634 635 if (status & STE_ISR_RX_DMADONE) 636 ste_rxeof(sc); 637 638 if (status & STE_ISR_TX_DMADONE) 639 ste_txeof(sc); 640 641 if (status & STE_ISR_TX_DONE) 642 ste_txeoc(sc); 643 644 if (status & STE_ISR_STATS_OFLOW) { 645 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 646 ste_stats_update(sc); 647 } 648 649 if (status & STE_ISR_HOSTERR) { 650 ste_reset(sc); 651 ste_init(sc); 652 } 653 } 654 655 /* Re-enable interrupts */ 656 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 657 658 if (ifp->if_snd.ifq_head != NULL) 659 ste_start(ifp); 660 661 return; 662} 663 664/* 665 * A frame has been uploaded: pass the resulting mbuf chain up to 666 * the higher level protocols. 667 */ 668static void ste_rxeof(sc) 669 struct ste_softc *sc; 670{ 671 struct ether_header *eh; 672 struct mbuf *m; 673 struct ifnet *ifp; 674 struct ste_chain_onefrag *cur_rx; 675 int total_len = 0; 676 u_int32_t rxstat; 677 678 ifp = &sc->arpcom.ac_if; 679 680again: 681 682 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) { 683 cur_rx = sc->ste_cdata.ste_rx_head; 684 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 685 686 /* 687 * If an error occurs, update stats, clear the 688 * status word and leave the mbuf cluster in place: 689 * it should simply get re-used next time this descriptor 690 * comes up in the ring. 691 */ 692 if (rxstat & STE_RXSTAT_FRAME_ERR) { 693 ifp->if_ierrors++; 694 cur_rx->ste_ptr->ste_status = 0; 695 continue; 696 } 697 698 /* 699 * If there error bit was not set, the upload complete 700 * bit should be set which means we have a valid packet. 701 * If not, something truly strange has happened. 702 */ 703 if (!(rxstat & STE_RXSTAT_DMADONE)) { 704 printf("ste%d: bad receive status -- packet dropped", 705 sc->ste_unit); 706 ifp->if_ierrors++; 707 cur_rx->ste_ptr->ste_status = 0; 708 continue; 709 } 710 711 /* No errors; receive the packet. */ 712 m = cur_rx->ste_mbuf; 713 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 714 715 /* 716 * Try to conjure up a new mbuf cluster. If that 717 * fails, it means we have an out of memory condition and 718 * should leave the buffer in place and continue. This will 719 * result in a lost packet, but there's little else we 720 * can do in this situation. 721 */ 722 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 723 ifp->if_ierrors++; 724 cur_rx->ste_ptr->ste_status = 0; 725 continue; 726 } 727 728 ifp->if_ipackets++; 729 eh = mtod(m, struct ether_header *); 730 m->m_pkthdr.rcvif = ifp; 731 m->m_pkthdr.len = m->m_len = total_len; 732 733 /* Handle BPF listeners. Let the BPF user see the packet. */ 734 if (ifp->if_bpf) 735 bpf_mtap(ifp, m); 736 737#ifdef BRIDGE 738 if (do_bridge) { 739 struct ifnet *bdg_ifp ; 740 bdg_ifp = bridge_in(m); 741 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 742 bdg_forward(&m, bdg_ifp); 743 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 744 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 745 m_freem(m); 746 continue; 747 } 748 } 749#endif 750 751 /* 752 * Don't pass packet up to the ether_input() layer unless it's 753 * a broadcast packet, multicast packet, matches our ethernet 754 * address or the interface is in promiscuous mode. 755 */ 756 if (ifp->if_bpf) { 757 if (ifp->if_flags & IFF_PROMISC && 758 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 759 ETHER_ADDR_LEN) && (eh->ether_dhost[0] & 1) == 0)){ 760 m_freem(m); 761 continue; 762 } 763 } 764 765 /* Remove header from mbuf and pass it on. */ 766 m_adj(m, sizeof(struct ether_header)); 767 ether_input(ifp, eh, m); 768 } 769 770 /* 771 * Handle the 'end of channel' condition. When the upload 772 * engine hits the end of the RX ring, it will stall. This 773 * is our cue to flush the RX ring, reload the uplist pointer 774 * register and unstall the engine. 775 * XXX This is actually a little goofy. With the ThunderLAN 776 * chip, you get an interrupt when the receiver hits the end 777 * of the receive ring, which tells you exactly when you 778 * you need to reload the ring pointer. Here we have to 779 * fake it. I'm mad at myself for not being clever enough 780 * to avoid the use of a goto here. 781 */ 782 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 || 783 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) { 784 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 785 ste_wait(sc); 786 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 787 vtophys(&sc->ste_ldata->ste_rx_list[0])); 788 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0]; 789 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 790 goto again; 791 } 792 793 return; 794} 795 796static void ste_txeoc(sc) 797 struct ste_softc *sc; 798{ 799 u_int8_t txstat; 800 struct ifnet *ifp; 801 802 ifp = &sc->arpcom.ac_if; 803 804 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 805 STE_TXSTATUS_TXDONE) { 806 if (txstat & STE_TXSTATUS_UNDERRUN || 807 txstat & STE_TXSTATUS_EXCESSCOLLS || 808 txstat & STE_TXSTATUS_RECLAIMERR) { 809 ifp->if_oerrors++; 810 printf("ste%d: transmission error: %x\n", 811 sc->ste_unit, txstat); 812 813 ste_reset(sc); 814 ste_init(sc); 815 816 if (txstat & STE_TXSTATUS_UNDERRUN && 817 sc->ste_tx_thresh < STE_PACKET_SIZE) { 818 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 819 printf("ste%d: tx underrun, increasing tx" 820 " start threshold to %d bytes\n", 821 sc->ste_unit, sc->ste_tx_thresh); 822 } 823 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 824 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 825 (STE_PACKET_SIZE >> 4)); 826 } 827 ste_init(sc); 828 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 829 } 830 831 return; 832} 833 834static void ste_txeof(sc) 835 struct ste_softc *sc; 836{ 837 struct ste_chain *cur_tx = NULL; 838 struct ifnet *ifp; 839 int idx; 840 841 ifp = &sc->arpcom.ac_if; 842 843 idx = sc->ste_cdata.ste_tx_cons; 844 while(idx != sc->ste_cdata.ste_tx_prod) { 845 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 846 847 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 848 break; 849 850 if (cur_tx->ste_mbuf != NULL) { 851 m_freem(cur_tx->ste_mbuf); 852 cur_tx->ste_mbuf = NULL; 853 } 854 855 ifp->if_opackets++; 856 857 sc->ste_cdata.ste_tx_cnt--; 858 STE_INC(idx, STE_TX_LIST_CNT); 859 ifp->if_timer = 0; 860 } 861 862 sc->ste_cdata.ste_tx_cons = idx; 863 864 if (cur_tx != NULL) 865 ifp->if_flags &= ~IFF_OACTIVE; 866 867 return; 868} 869 870static void ste_stats_update(xsc) 871 void *xsc; 872{ 873 struct ste_softc *sc; 874 struct ste_stats stats; 875 struct ifnet *ifp; 876 struct mii_data *mii; 877 int i, s; 878 u_int8_t *p; 879 880 s = splimp(); 881 882 sc = xsc; 883 ifp = &sc->arpcom.ac_if; 884 mii = device_get_softc(sc->ste_miibus); 885 886 p = (u_int8_t *)&stats; 887 888 for (i = 0; i < sizeof(stats); i++) { 889 *p = CSR_READ_1(sc, STE_STATS + i); 890 p++; 891 } 892 893 ifp->if_collisions += stats.ste_single_colls + 894 stats.ste_multi_colls + stats.ste_late_colls; 895 896 mii_tick(mii); 897 if (!sc->ste_link) { 898 mii_pollstat(mii); 899 if (mii->mii_media_status & IFM_ACTIVE && 900 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 901 sc->ste_link++; 902 if (ifp->if_snd.ifq_head != NULL) 903 ste_start(ifp); 904 } 905 906 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 907 splx(s); 908 909 return; 910} 911 912 913/* 914 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 915 * IDs against our list and return a device name if we find a match. 916 */ 917static int ste_probe(dev) 918 device_t dev; 919{ 920 struct ste_type *t; 921 922 t = ste_devs; 923 924 while(t->ste_name != NULL) { 925 if ((pci_get_vendor(dev) == t->ste_vid) && 926 (pci_get_device(dev) == t->ste_did)) { 927 device_set_desc(dev, t->ste_name); 928 return(0); 929 } 930 t++; 931 } 932 933 return(ENXIO); 934} 935 936/* 937 * Attach the interface. Allocate softc structures, do ifmedia 938 * setup and ethernet/BPF attach. 939 */ 940static int ste_attach(dev) 941 device_t dev; 942{ 943 int s; 944 u_int32_t command; 945 struct ste_softc *sc; 946 struct ifnet *ifp; 947 int unit, error = 0, rid; 948 949 s = splimp(); 950 951 sc = device_get_softc(dev); 952 unit = device_get_unit(dev); 953 bzero(sc, sizeof(struct ste_softc)); 954 955 /* 956 * Handle power management nonsense. 957 */ 958 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 959 if (command == 0x01) { 960 961 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 962 if (command & STE_PSTATE_MASK) { 963 u_int32_t iobase, membase, irq; 964 965 /* Save important PCI config data. */ 966 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 967 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 968 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 969 970 /* Reset the power state. */ 971 printf("ste%d: chip is in D%d power mode " 972 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 973 command &= 0xFFFFFFFC; 974 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 975 976 /* Restore PCI config data. */ 977 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 978 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 979 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 980 } 981 } 982 983 /* 984 * Map control/status registers. 985 */ 986 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 987 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 988 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 989 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 990 991#ifdef STE_USEIOSPACE 992 if (!(command & PCIM_CMD_PORTEN)) { 993 printf("ste%d: failed to enable I/O ports!\n", unit); 994 error = ENXIO; 995 goto fail; 996 } 997#else 998 if (!(command & PCIM_CMD_MEMEN)) { 999 printf("ste%d: failed to enable memory mapping!\n", unit); 1000 error = ENXIO; 1001 goto fail; 1002 } 1003#endif 1004 1005 rid = STE_RID; 1006 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 1007 0, ~0, 1, RF_ACTIVE); 1008 1009 if (sc->ste_res == NULL) { 1010 printf ("ste%d: couldn't map ports/memory\n", unit); 1011 error = ENXIO; 1012 goto fail; 1013 } 1014 1015 sc->ste_btag = rman_get_bustag(sc->ste_res); 1016 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1017 1018 rid = 0; 1019 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1020 RF_SHAREABLE | RF_ACTIVE); 1021 1022 if (sc->ste_irq == NULL) { 1023 printf("ste%d: couldn't map interrupt\n", unit); 1024 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1025 error = ENXIO; 1026 goto fail; 1027 } 1028 1029 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1030 ste_intr, sc, &sc->ste_intrhand); 1031 1032 if (error) { 1033 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1034 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1035 printf("ste%d: couldn't set up irq\n", unit); 1036 goto fail; 1037 } 1038 1039 callout_handle_init(&sc->ste_stat_ch); 1040 1041 /* Reset the adapter. */ 1042 ste_reset(sc); 1043 1044 /* 1045 * Get station address from the EEPROM. 1046 */ 1047 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1048 STE_EEADDR_NODE0, 3, 0)) { 1049 printf("ste%d: failed to read station address\n", unit); 1050 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1051 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1052 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1053 error = ENXIO;; 1054 goto fail; 1055 } 1056 1057 /* 1058 * A Sundance chip was detected. Inform the world. 1059 */ 1060 printf("ste%d: Ethernet address: %6D\n", unit, 1061 sc->arpcom.ac_enaddr, ":"); 1062 1063 sc->ste_unit = unit; 1064 1065 /* Allocate the descriptor queues. */ 1066 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1067 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1068 1069 if (sc->ste_ldata == NULL) { 1070 printf("ste%d: no memory for list buffers!\n", unit); 1071 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1072 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1073 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1074 error = ENXIO; 1075 goto fail; 1076 } 1077 1078 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1079 1080 /* Do MII setup. */ 1081 if (mii_phy_probe(dev, &sc->ste_miibus, 1082 ste_ifmedia_upd, ste_ifmedia_sts)) { 1083 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1084 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1085 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1086 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1087 contigfree(sc->ste_ldata, 1088 sizeof(struct ste_list_data), M_DEVBUF); 1089 error = ENXIO; 1090 goto fail; 1091 } 1092 1093 ifp = &sc->arpcom.ac_if; 1094 ifp->if_softc = sc; 1095 ifp->if_unit = unit; 1096 ifp->if_name = "ste"; 1097 ifp->if_mtu = ETHERMTU; 1098 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1099 ifp->if_ioctl = ste_ioctl; 1100 ifp->if_output = ether_output; 1101 ifp->if_start = ste_start; 1102 ifp->if_watchdog = ste_watchdog; 1103 ifp->if_init = ste_init; 1104 ifp->if_baudrate = 10000000; 1105 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1106 1107 /* 1108 * Call MI attach routines. 1109 */ 1110 1111 if_attach(ifp); 1112 ether_ifattach(ifp); 1113 1114 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1115 1116fail: 1117 splx(s); 1118 return(error); 1119} 1120 1121static int ste_detach(dev) 1122 device_t dev; 1123{ 1124 struct ste_softc *sc; 1125 struct ifnet *ifp; 1126 int s; 1127 1128 s = splimp(); 1129 1130 sc = device_get_softc(dev); 1131 ifp = &sc->arpcom.ac_if; 1132 1133 ste_stop(sc); 1134 if_detach(ifp); 1135 1136 bus_generic_detach(dev); 1137 device_delete_child(dev, sc->ste_miibus); 1138 1139 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1140 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1141 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1142 1143 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1144 1145 splx(s); 1146 1147 return(0); 1148} 1149 1150static int ste_newbuf(sc, c, m) 1151 struct ste_softc *sc; 1152 struct ste_chain_onefrag *c; 1153 struct mbuf *m; 1154{ 1155 struct mbuf *m_new = NULL; 1156 1157 if (m == NULL) { 1158 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1159 if (m_new == NULL) { 1160 printf("ste%d: no memory for rx list -- " 1161 "packet dropped\n", sc->ste_unit); 1162 return(ENOBUFS); 1163 } 1164 MCLGET(m_new, M_DONTWAIT); 1165 if (!(m_new->m_flags & M_EXT)) { 1166 printf("ste%d: no memory for rx list -- " 1167 "packet dropped\n", sc->ste_unit); 1168 m_freem(m_new); 1169 return(ENOBUFS); 1170 } 1171 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1172 } else { 1173 m_new = m; 1174 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1175 m_new->m_data = m_new->m_ext.ext_buf; 1176 } 1177 1178 m_adj(m_new, ETHER_ALIGN); 1179 1180 c->ste_mbuf = m_new; 1181 c->ste_ptr->ste_status = 0; 1182 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1183 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; 1184 1185 return(0); 1186} 1187 1188static int ste_init_rx_list(sc) 1189 struct ste_softc *sc; 1190{ 1191 struct ste_chain_data *cd; 1192 struct ste_list_data *ld; 1193 int i; 1194 1195 cd = &sc->ste_cdata; 1196 ld = sc->ste_ldata; 1197 1198 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1199 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1200 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1201 return(ENOBUFS); 1202 if (i == (STE_RX_LIST_CNT - 1)) { 1203 cd->ste_rx_chain[i].ste_next = 1204 &cd->ste_rx_chain[0]; 1205 ld->ste_rx_list[i].ste_next = 1206 vtophys(&ld->ste_rx_list[0]); 1207 } else { 1208 cd->ste_rx_chain[i].ste_next = 1209 &cd->ste_rx_chain[i + 1]; 1210 ld->ste_rx_list[i].ste_next = 1211 vtophys(&ld->ste_rx_list[i + 1]); 1212 } 1213 1214 } 1215 1216 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1217 1218 return(0); 1219} 1220 1221static void ste_init_tx_list(sc) 1222 struct ste_softc *sc; 1223{ 1224 struct ste_chain_data *cd; 1225 struct ste_list_data *ld; 1226 int i; 1227 1228 cd = &sc->ste_cdata; 1229 ld = sc->ste_ldata; 1230 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1231 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1232 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1233 if (i == (STE_TX_LIST_CNT - 1)) 1234 cd->ste_tx_chain[i].ste_next = 1235 &cd->ste_tx_chain[0]; 1236 else 1237 cd->ste_tx_chain[i].ste_next = 1238 &cd->ste_tx_chain[i + 1]; 1239 if (i == 0) 1240 cd->ste_tx_chain[i].ste_prev = 1241 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1242 else 1243 cd->ste_tx_chain[i].ste_prev = 1244 &cd->ste_tx_chain[i - 1]; 1245 } 1246 1247 1248 bzero((char *)ld->ste_tx_list, 1249 sizeof(struct ste_desc) * STE_TX_LIST_CNT); 1250 1251 cd->ste_tx_prod = 0; 1252 cd->ste_tx_cons = 0; 1253 cd->ste_tx_cnt = 0; 1254 1255 return; 1256} 1257 1258static void ste_init(xsc) 1259 void *xsc; 1260{ 1261 struct ste_softc *sc; 1262 int i, s; 1263 struct ifnet *ifp; 1264 struct mii_data *mii; 1265 1266 s = splimp(); 1267 1268 sc = xsc; 1269 ifp = &sc->arpcom.ac_if; 1270 mii = device_get_softc(sc->ste_miibus); 1271 1272 ste_stop(sc); 1273 1274 /* Init our MAC address */ 1275 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1276 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1277 } 1278 1279 /* Init RX list */ 1280 if (ste_init_rx_list(sc) == ENOBUFS) { 1281 printf("ste%d: initialization failed: no " 1282 "memory for RX buffers\n", sc->ste_unit); 1283 ste_stop(sc); 1284 splx(s); 1285 return; 1286 } 1287 1288 /* Init TX descriptors */ 1289 ste_init_tx_list(sc); 1290 1291 /* Set the TX freethresh value */ 1292 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1293 1294 /* Set the TX start threshold for best performance. */ 1295 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1296 1297 /* Set the TX reclaim threshold. */ 1298 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1299 1300 /* Set up the RX filter. */ 1301 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1302 1303 /* If we want promiscuous mode, set the allframes bit. */ 1304 if (ifp->if_flags & IFF_PROMISC) { 1305 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1306 } else { 1307 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1308 } 1309 1310 /* Set capture broadcast bit to accept broadcast frames. */ 1311 if (ifp->if_flags & IFF_BROADCAST) { 1312 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1313 } else { 1314 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1315 } 1316 1317 ste_setmulti(sc); 1318 1319 /* Load the address of the RX list. */ 1320 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1321 ste_wait(sc); 1322 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1323 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1324 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1325 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1326 1327 /* Set TX polling interval */ 1328 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1329 1330 /* Load address of the TX list */ 1331 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1332 ste_wait(sc); 1333 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1334 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1335 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1336 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1337 ste_wait(sc); 1338 1339 /* Enable receiver and transmitter */ 1340 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1341 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1342 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1343 1344 /* Enable stats counters. */ 1345 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1346 1347 /* Enable interrupts. */ 1348 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1349 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1350 1351 ste_ifmedia_upd(ifp); 1352 1353 ifp->if_flags |= IFF_RUNNING; 1354 ifp->if_flags &= ~IFF_OACTIVE; 1355 1356 splx(s); 1357 1358 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1359 1360 return; 1361} 1362 1363static void ste_stop(sc) 1364 struct ste_softc *sc; 1365{ 1366 int i; 1367 struct ifnet *ifp; 1368 1369 ifp = &sc->arpcom.ac_if; 1370 1371 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1372 1373 CSR_WRITE_2(sc, STE_IMR, 0); 1374 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1375 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1376 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1377 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1378 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1379 ste_wait(sc); 1380 1381 sc->ste_link = 0; 1382 1383 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1384 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1385 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1386 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1387 } 1388 } 1389 1390 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1391 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1392 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1393 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1394 } 1395 } 1396 1397 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1398 1399 return; 1400} 1401 1402static void ste_reset(sc) 1403 struct ste_softc *sc; 1404{ 1405 int i; 1406 1407 STE_SETBIT4(sc, STE_ASICCTL, 1408 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1409 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1410 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1411 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1412 STE_ASICCTL_EXTRESET_RESET); 1413 1414 DELAY(100000); 1415 1416 for (i = 0; i < STE_TIMEOUT; i++) { 1417 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1418 break; 1419 } 1420 1421 if (i == STE_TIMEOUT) 1422 printf("ste%d: global reset never completed\n", sc->ste_unit); 1423 1424 return; 1425} 1426 1427static int ste_ioctl(ifp, command, data) 1428 struct ifnet *ifp; 1429 u_long command; 1430 caddr_t data; 1431{ 1432 struct ste_softc *sc; 1433 struct ifreq *ifr; 1434 struct mii_data *mii; 1435 int error = 0, s; 1436 1437 s = splimp(); 1438 1439 sc = ifp->if_softc; 1440 ifr = (struct ifreq *)data; 1441 1442 switch(command) { 1443 case SIOCSIFADDR: 1444 case SIOCGIFADDR: 1445 case SIOCSIFMTU: 1446 error = ether_ioctl(ifp, command, data); 1447 break; 1448 case SIOCSIFFLAGS: 1449 if (ifp->if_flags & IFF_UP) { 1450 if (ifp->if_flags & IFF_RUNNING && 1451 ifp->if_flags & IFF_PROMISC && 1452 !(sc->ste_if_flags & IFF_PROMISC)) { 1453 STE_SETBIT1(sc, STE_RX_MODE, 1454 STE_RXMODE_PROMISC); 1455 } else if (ifp->if_flags & IFF_RUNNING && 1456 !(ifp->if_flags & IFF_PROMISC) && 1457 sc->ste_if_flags & IFF_PROMISC) { 1458 STE_CLRBIT1(sc, STE_RX_MODE, 1459 STE_RXMODE_PROMISC); 1460 } else if (!(ifp->if_flags & IFF_RUNNING)) { 1461 sc->ste_tx_thresh = STE_MIN_FRAMELEN; 1462 ste_init(sc); 1463 } 1464 } else { 1465 if (ifp->if_flags & IFF_RUNNING) 1466 ste_stop(sc); 1467 } 1468 sc->ste_if_flags = ifp->if_flags; 1469 error = 0; 1470 break; 1471 case SIOCADDMULTI: 1472 case SIOCDELMULTI: 1473 ste_setmulti(sc); 1474 error = 0; 1475 break; 1476 case SIOCGIFMEDIA: 1477 case SIOCSIFMEDIA: 1478 mii = device_get_softc(sc->ste_miibus); 1479 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1480 break; 1481 default: 1482 error = EINVAL; 1483 break; 1484 } 1485 1486 splx(s); 1487 1488 return(error); 1489} 1490 1491static int ste_encap(sc, c, m_head) 1492 struct ste_softc *sc; 1493 struct ste_chain *c; 1494 struct mbuf *m_head; 1495{ 1496 int frag = 0; 1497 struct ste_frag *f = NULL; 1498 struct mbuf *m; 1499 struct ste_desc *d; 1500 int total_len = 0; 1501 1502 d = c->ste_ptr; 1503 d->ste_ctl = 0; 1504 d->ste_next = 0; 1505 1506 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1507 if (m->m_len != 0) { 1508 if (frag == STE_MAXFRAGS) 1509 break; 1510 total_len += m->m_len; 1511 f = &c->ste_ptr->ste_frags[frag]; 1512 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1513 f->ste_len = m->m_len; 1514 frag++; 1515 } 1516 } 1517 1518 c->ste_mbuf = m_head; 1519 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1520 c->ste_ptr->ste_ctl = total_len; 1521 1522 return(0); 1523} 1524 1525static void ste_start(ifp) 1526 struct ifnet *ifp; 1527{ 1528 struct ste_softc *sc; 1529 struct mbuf *m_head = NULL; 1530 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1531 int idx; 1532 1533 sc = ifp->if_softc; 1534 1535 if (!sc->ste_link) 1536 return; 1537 1538 if (ifp->if_flags & IFF_OACTIVE) 1539 return; 1540 1541 idx = sc->ste_cdata.ste_tx_prod; 1542 start_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1543 1544 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1545 1546 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1547 ifp->if_flags |= IFF_OACTIVE; 1548 break; 1549 } 1550 1551 IF_DEQUEUE(&ifp->if_snd, m_head); 1552 if (m_head == NULL) 1553 break; 1554 1555 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1556 1557 ste_encap(sc, cur_tx, m_head); 1558 1559 if (prev != NULL) 1560 prev->ste_ptr->ste_next = cur_tx->ste_phys; 1561 prev = cur_tx; 1562 1563 /* 1564 * If there's a BPF listener, bounce a copy of this frame 1565 * to him. 1566 */ 1567 if (ifp->if_bpf) 1568 bpf_mtap(ifp, cur_tx->ste_mbuf); 1569 1570 STE_INC(idx, STE_TX_LIST_CNT); 1571 sc->ste_cdata.ste_tx_cnt++; 1572 } 1573 1574 if (cur_tx == NULL) 1575 return; 1576 1577 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR; 1578 1579 /* Start transmission */ 1580 sc->ste_cdata.ste_tx_prod = idx; 1581 start_tx->ste_prev->ste_ptr->ste_next = start_tx->ste_phys; 1582 1583 ifp->if_timer = 5; 1584 1585 return; 1586} 1587 1588static void ste_watchdog(ifp) 1589 struct ifnet *ifp; 1590{ 1591 struct ste_softc *sc; 1592 1593 sc = ifp->if_softc; 1594 1595 ifp->if_oerrors++; 1596 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1597 1598 ste_txeoc(sc); 1599 ste_txeof(sc); 1600 ste_rxeof(sc); 1601 ste_reset(sc); 1602 ste_init(sc); 1603 1604 if (ifp->if_snd.ifq_head != NULL) 1605 ste_start(ifp); 1606 1607 return; 1608} 1609 1610static void ste_shutdown(dev) 1611 device_t dev; 1612{ 1613 struct ste_softc *sc; 1614 1615 sc = device_get_softc(dev); 1616 1617 ste_stop(sc); 1618 1619 return; 1620} 1621