if_ste.c revision 54268
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 54268 1999-12-07 20:14:42Z wpaul $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48 49#include <net/bpf.h> 50 51#include "opt_bdg.h" 52#ifdef BRIDGE 53#include <net/bridge.h> 54#endif 55 56#include <vm/vm.h> /* for vtophys */ 57#include <vm/pmap.h> /* for vtophys */ 58#include <machine/clock.h> /* for DELAY */ 59#include <machine/bus_memio.h> 60#include <machine/bus_pio.h> 61#include <machine/bus.h> 62#include <machine/resource.h> 63#include <sys/bus.h> 64#include <sys/rman.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <pci/pcireg.h> 70#include <pci/pcivar.h> 71 72/* "controller miibus0" required. See GENERIC if you get errors here. */ 73#include "miibus_if.h" 74 75#define STE_USEIOSPACE 76 77#include <pci/if_stereg.h> 78 79#if !defined(lint) 80static const char rcsid[] = 81 "$FreeBSD: head/sys/pci/if_ste.c 54268 1999-12-07 20:14:42Z wpaul $"; 82#endif 83 84/* 85 * Various supported device vendors/types and their names. 86 */ 87static struct ste_type ste_devs[] = { 88 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 89 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 90 { 0, 0, NULL } 91}; 92 93static int ste_probe __P((device_t)); 94static int ste_attach __P((device_t)); 95static int ste_detach __P((device_t)); 96static void ste_init __P((void *)); 97static void ste_intr __P((void *)); 98static void ste_rxeof __P((struct ste_softc *)); 99static void ste_txeoc __P((struct ste_softc *)); 100static void ste_txeof __P((struct ste_softc *)); 101static void ste_stats_update __P((void *)); 102static void ste_stop __P((struct ste_softc *)); 103static void ste_reset __P((struct ste_softc *)); 104static int ste_ioctl __P((struct ifnet *, u_long, caddr_t)); 105static int ste_encap __P((struct ste_softc *, struct ste_chain *, 106 struct mbuf *)); 107static void ste_start __P((struct ifnet *)); 108static void ste_watchdog __P((struct ifnet *)); 109static void ste_shutdown __P((device_t)); 110static int ste_newbuf __P((struct ste_softc *, 111 struct ste_chain_onefrag *, 112 struct mbuf *)); 113static int ste_ifmedia_upd __P((struct ifnet *)); 114static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 115 116static void ste_mii_sync __P((struct ste_softc *)); 117static void ste_mii_send __P((struct ste_softc *, u_int32_t, int)); 118static int ste_mii_readreg __P((struct ste_softc *, 119 struct ste_mii_frame *)); 120static int ste_mii_writereg __P((struct ste_softc *, 121 struct ste_mii_frame *)); 122static int ste_miibus_readreg __P((device_t, int, int)); 123static int ste_miibus_writereg __P((device_t, int, int, int)); 124static void ste_miibus_statchg __P((device_t)); 125 126static int ste_eeprom_wait __P((struct ste_softc *)); 127static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int, 128 int, int)); 129static void ste_wait __P((struct ste_softc *)); 130static u_int8_t ste_calchash __P((caddr_t)); 131static void ste_setmulti __P((struct ste_softc *)); 132static int ste_init_rx_list __P((struct ste_softc *)); 133static void ste_init_tx_list __P((struct ste_softc *)); 134 135#ifdef STE_USEIOSPACE 136#define STE_RES SYS_RES_IOPORT 137#define STE_RID STE_PCI_LOIO 138#else 139#define STE_RES SYS_RES_MEMORY 140#define STE_RID STE_PCI_LOMEM 141#endif 142 143static device_method_t ste_methods[] = { 144 /* Device interface */ 145 DEVMETHOD(device_probe, ste_probe), 146 DEVMETHOD(device_attach, ste_attach), 147 DEVMETHOD(device_detach, ste_detach), 148 DEVMETHOD(device_shutdown, ste_shutdown), 149 150 /* bus interface */ 151 DEVMETHOD(bus_print_child, bus_generic_print_child), 152 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 153 154 /* MII interface */ 155 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 156 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 157 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 158 159 { 0, 0 } 160}; 161 162static driver_t ste_driver = { 163 "ste", 164 ste_methods, 165 sizeof(struct ste_softc) 166}; 167 168static devclass_t ste_devclass; 169 170DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 171DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 172 173#define STE_SETBIT4(sc, reg, x) \ 174 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 175 176#define STE_CLRBIT4(sc, reg, x) \ 177 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 178 179#define STE_SETBIT2(sc, reg, x) \ 180 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 181 182#define STE_CLRBIT2(sc, reg, x) \ 183 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 184 185#define STE_SETBIT1(sc, reg, x) \ 186 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 187 188#define STE_CLRBIT1(sc, reg, x) \ 189 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 190 191 192#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 193#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 194 195/* 196 * Sync the PHYs by setting data bit and strobing the clock 32 times. 197 */ 198static void ste_mii_sync(sc) 199 struct ste_softc *sc; 200{ 201 register int i; 202 203 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 204 205 for (i = 0; i < 32; i++) { 206 MII_SET(STE_PHYCTL_MCLK); 207 DELAY(1); 208 MII_CLR(STE_PHYCTL_MCLK); 209 DELAY(1); 210 } 211 212 return; 213} 214 215/* 216 * Clock a series of bits through the MII. 217 */ 218static void ste_mii_send(sc, bits, cnt) 219 struct ste_softc *sc; 220 u_int32_t bits; 221 int cnt; 222{ 223 int i; 224 225 MII_CLR(STE_PHYCTL_MCLK); 226 227 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 228 if (bits & i) { 229 MII_SET(STE_PHYCTL_MDATA); 230 } else { 231 MII_CLR(STE_PHYCTL_MDATA); 232 } 233 DELAY(1); 234 MII_CLR(STE_PHYCTL_MCLK); 235 DELAY(1); 236 MII_SET(STE_PHYCTL_MCLK); 237 } 238} 239 240/* 241 * Read an PHY register through the MII. 242 */ 243static int ste_mii_readreg(sc, frame) 244 struct ste_softc *sc; 245 struct ste_mii_frame *frame; 246 247{ 248 int i, ack, s; 249 250 s = splimp(); 251 252 /* 253 * Set up frame for RX. 254 */ 255 frame->mii_stdelim = STE_MII_STARTDELIM; 256 frame->mii_opcode = STE_MII_READOP; 257 frame->mii_turnaround = 0; 258 frame->mii_data = 0; 259 260 CSR_WRITE_2(sc, STE_PHYCTL, 0); 261 /* 262 * Turn on data xmit. 263 */ 264 MII_SET(STE_PHYCTL_MDIR); 265 266 ste_mii_sync(sc); 267 268 /* 269 * Send command/address info. 270 */ 271 ste_mii_send(sc, frame->mii_stdelim, 2); 272 ste_mii_send(sc, frame->mii_opcode, 2); 273 ste_mii_send(sc, frame->mii_phyaddr, 5); 274 ste_mii_send(sc, frame->mii_regaddr, 5); 275 276 /* Turn off xmit. */ 277 MII_CLR(STE_PHYCTL_MDIR); 278 279 /* Idle bit */ 280 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 281 DELAY(1); 282 MII_SET(STE_PHYCTL_MCLK); 283 DELAY(1); 284 285 /* Check for ack */ 286 MII_CLR(STE_PHYCTL_MCLK); 287 DELAY(1); 288 MII_SET(STE_PHYCTL_MCLK); 289 DELAY(1); 290 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 291 292 /* 293 * Now try reading data bits. If the ack failed, we still 294 * need to clock through 16 cycles to keep the PHY(s) in sync. 295 */ 296 if (ack) { 297 for(i = 0; i < 16; i++) { 298 MII_CLR(STE_PHYCTL_MCLK); 299 DELAY(1); 300 MII_SET(STE_PHYCTL_MCLK); 301 DELAY(1); 302 } 303 goto fail; 304 } 305 306 for (i = 0x8000; i; i >>= 1) { 307 MII_CLR(STE_PHYCTL_MCLK); 308 DELAY(1); 309 if (!ack) { 310 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 311 frame->mii_data |= i; 312 DELAY(1); 313 } 314 MII_SET(STE_PHYCTL_MCLK); 315 DELAY(1); 316 } 317 318fail: 319 320 MII_CLR(STE_PHYCTL_MCLK); 321 DELAY(1); 322 MII_SET(STE_PHYCTL_MCLK); 323 DELAY(1); 324 325 splx(s); 326 327 if (ack) 328 return(1); 329 return(0); 330} 331 332/* 333 * Write to a PHY register through the MII. 334 */ 335static int ste_mii_writereg(sc, frame) 336 struct ste_softc *sc; 337 struct ste_mii_frame *frame; 338 339{ 340 int s; 341 342 s = splimp(); 343 /* 344 * Set up frame for TX. 345 */ 346 347 frame->mii_stdelim = STE_MII_STARTDELIM; 348 frame->mii_opcode = STE_MII_WRITEOP; 349 frame->mii_turnaround = STE_MII_TURNAROUND; 350 351 /* 352 * Turn on data output. 353 */ 354 MII_SET(STE_PHYCTL_MDIR); 355 356 ste_mii_sync(sc); 357 358 ste_mii_send(sc, frame->mii_stdelim, 2); 359 ste_mii_send(sc, frame->mii_opcode, 2); 360 ste_mii_send(sc, frame->mii_phyaddr, 5); 361 ste_mii_send(sc, frame->mii_regaddr, 5); 362 ste_mii_send(sc, frame->mii_turnaround, 2); 363 ste_mii_send(sc, frame->mii_data, 16); 364 365 /* Idle bit. */ 366 MII_SET(STE_PHYCTL_MCLK); 367 DELAY(1); 368 MII_CLR(STE_PHYCTL_MCLK); 369 DELAY(1); 370 371 /* 372 * Turn off xmit. 373 */ 374 MII_CLR(STE_PHYCTL_MDIR); 375 376 splx(s); 377 378 return(0); 379} 380 381static int ste_miibus_readreg(dev, phy, reg) 382 device_t dev; 383 int phy, reg; 384{ 385 struct ste_softc *sc; 386 struct ste_mii_frame frame; 387 388 sc = device_get_softc(dev); 389 390 bzero((char *)&frame, sizeof(frame)); 391 392 frame.mii_phyaddr = phy; 393 frame.mii_regaddr = reg; 394 ste_mii_readreg(sc, &frame); 395 396 return(frame.mii_data); 397} 398 399static int ste_miibus_writereg(dev, phy, reg, data) 400 device_t dev; 401 int phy, reg, data; 402{ 403 struct ste_softc *sc; 404 struct ste_mii_frame frame; 405 406 sc = device_get_softc(dev); 407 bzero((char *)&frame, sizeof(frame)); 408 409 frame.mii_phyaddr = phy; 410 frame.mii_regaddr = reg; 411 frame.mii_data = data; 412 413 ste_mii_writereg(sc, &frame); 414 415 return(0); 416} 417 418static void ste_miibus_statchg(dev) 419 device_t dev; 420{ 421 struct ste_softc *sc; 422 struct mii_data *mii; 423 424 sc = device_get_softc(dev); 425 mii = device_get_softc(sc->ste_miibus); 426 427 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 428 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 429 } else { 430 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } 432 433 return; 434} 435 436static int ste_ifmedia_upd(ifp) 437 struct ifnet *ifp; 438{ 439 struct ste_softc *sc; 440 struct mii_data *mii; 441 442 sc = ifp->if_softc; 443 mii = device_get_softc(sc->ste_miibus); 444 sc->ste_link = 0; 445 if (mii->mii_instance) { 446 struct mii_softc *miisc; 447 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 448 miisc = LIST_NEXT(miisc, mii_list)) 449 mii_phy_reset(miisc); 450 } 451 mii_mediachg(mii); 452 453 return(0); 454} 455 456static void ste_ifmedia_sts(ifp, ifmr) 457 struct ifnet *ifp; 458 struct ifmediareq *ifmr; 459{ 460 struct ste_softc *sc; 461 struct mii_data *mii; 462 463 sc = ifp->if_softc; 464 mii = device_get_softc(sc->ste_miibus); 465 466 mii_pollstat(mii); 467 ifmr->ifm_active = mii->mii_media_active; 468 ifmr->ifm_status = mii->mii_media_status; 469 470 return; 471} 472 473static void ste_wait(sc) 474 struct ste_softc *sc; 475{ 476 register int i; 477 478 for (i = 0; i < STE_TIMEOUT; i++) { 479 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 480 break; 481 } 482 483 if (i == STE_TIMEOUT) 484 printf("ste%d: command never completed!\n", sc->ste_unit); 485 486 return; 487} 488 489/* 490 * The EEPROM is slow: give it time to come ready after issuing 491 * it a command. 492 */ 493static int ste_eeprom_wait(sc) 494 struct ste_softc *sc; 495{ 496 int i; 497 498 DELAY(1000); 499 500 for (i = 0; i < 100; i++) { 501 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 502 DELAY(1000); 503 else 504 break; 505 } 506 507 if (i == 100) { 508 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 509 return(1); 510 } 511 512 return(0); 513} 514 515/* 516 * Read a sequence of words from the EEPROM. Note that ethernet address 517 * data is stored in the EEPROM in network byte order. 518 */ 519static int ste_read_eeprom(sc, dest, off, cnt, swap) 520 struct ste_softc *sc; 521 caddr_t dest; 522 int off; 523 int cnt; 524 int swap; 525{ 526 int err = 0, i; 527 u_int16_t word = 0, *ptr; 528 529 if (ste_eeprom_wait(sc)) 530 return(1); 531 532 for (i = 0; i < cnt; i++) { 533 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 534 err = ste_eeprom_wait(sc); 535 if (err) 536 break; 537 word = CSR_READ_2(sc, STE_EEPROM_DATA); 538 ptr = (u_int16_t *)(dest + (i * 2)); 539 if (swap) 540 *ptr = ntohs(word); 541 else 542 *ptr = word; 543 } 544 545 return(err ? 1 : 0); 546} 547 548static u_int8_t ste_calchash(addr) 549 caddr_t addr; 550{ 551 552 u_int32_t crc, carry; 553 int i, j; 554 u_int8_t c; 555 556 /* Compute CRC for the address value. */ 557 crc = 0xFFFFFFFF; /* initial value */ 558 559 for (i = 0; i < 6; i++) { 560 c = *(addr + i); 561 for (j = 0; j < 8; j++) { 562 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 563 crc <<= 1; 564 c >>= 1; 565 if (carry) 566 crc = (crc ^ 0x04c11db6) | carry; 567 } 568 } 569 570 /* return the filter bit position */ 571 return(crc & 0x0000003F); 572} 573 574static void ste_setmulti(sc) 575 struct ste_softc *sc; 576{ 577 struct ifnet *ifp; 578 int h = 0; 579 u_int32_t hashes[2] = { 0, 0 }; 580 struct ifmultiaddr *ifma; 581 582 ifp = &sc->arpcom.ac_if; 583 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 584 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 585 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 586 return; 587 } 588 589 /* first, zot all the existing hash bits */ 590 CSR_WRITE_4(sc, STE_MAR0, 0); 591 CSR_WRITE_4(sc, STE_MAR1, 0); 592 593 /* now program new ones */ 594 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 595 ifma = ifma->ifma_link.le_next) { 596 if (ifma->ifma_addr->sa_family != AF_LINK) 597 continue; 598 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 599 if (h < 32) 600 hashes[0] |= (1 << h); 601 else 602 hashes[1] |= (1 << (h - 32)); 603 } 604 605 CSR_WRITE_4(sc, STE_MAR0, hashes[0]); 606 CSR_WRITE_4(sc, STE_MAR1, hashes[1]); 607 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 608 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 609 610 return; 611} 612 613static void ste_intr(xsc) 614 void *xsc; 615{ 616 struct ste_softc *sc; 617 struct ifnet *ifp; 618 u_int16_t status; 619 620 sc = xsc; 621 ifp = &sc->arpcom.ac_if; 622 623 /* See if this is really our interrupt. */ 624 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 625 return; 626 627 for (;;) { 628 status = CSR_READ_2(sc, STE_ISR_ACK); 629 630 if (!(status & STE_INTRS)) 631 break; 632 633 if (status & STE_ISR_RX_DMADONE) 634 ste_rxeof(sc); 635 636 if (status & STE_ISR_TX_DMADONE) 637 ste_txeof(sc); 638 639 if (status & STE_ISR_TX_DONE) 640 ste_txeoc(sc); 641 642 if (status & STE_ISR_STATS_OFLOW) { 643 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 644 ste_stats_update(sc); 645 } 646 647 if (status & STE_ISR_HOSTERR) { 648 ste_reset(sc); 649 ste_init(sc); 650 } 651 } 652 653 /* Re-enable interrupts */ 654 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 655 656 if (ifp->if_snd.ifq_head != NULL) 657 ste_start(ifp); 658 659 return; 660} 661 662/* 663 * A frame has been uploaded: pass the resulting mbuf chain up to 664 * the higher level protocols. 665 */ 666static void ste_rxeof(sc) 667 struct ste_softc *sc; 668{ 669 struct ether_header *eh; 670 struct mbuf *m; 671 struct ifnet *ifp; 672 struct ste_chain_onefrag *cur_rx; 673 int total_len = 0; 674 u_int32_t rxstat; 675 676 ifp = &sc->arpcom.ac_if; 677 678again: 679 680 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) { 681 cur_rx = sc->ste_cdata.ste_rx_head; 682 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 683 684 /* 685 * If an error occurs, update stats, clear the 686 * status word and leave the mbuf cluster in place: 687 * it should simply get re-used next time this descriptor 688 * comes up in the ring. 689 */ 690 if (rxstat & STE_RXSTAT_FRAME_ERR) { 691 ifp->if_ierrors++; 692 cur_rx->ste_ptr->ste_status = 0; 693 continue; 694 } 695 696 /* 697 * If there error bit was not set, the upload complete 698 * bit should be set which means we have a valid packet. 699 * If not, something truly strange has happened. 700 */ 701 if (!(rxstat & STE_RXSTAT_DMADONE)) { 702 printf("ste%d: bad receive status -- packet dropped", 703 sc->ste_unit); 704 ifp->if_ierrors++; 705 cur_rx->ste_ptr->ste_status = 0; 706 continue; 707 } 708 709 /* No errors; receive the packet. */ 710 m = cur_rx->ste_mbuf; 711 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 712 713 /* 714 * Try to conjure up a new mbuf cluster. If that 715 * fails, it means we have an out of memory condition and 716 * should leave the buffer in place and continue. This will 717 * result in a lost packet, but there's little else we 718 * can do in this situation. 719 */ 720 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 721 ifp->if_ierrors++; 722 cur_rx->ste_ptr->ste_status = 0; 723 continue; 724 } 725 726 ifp->if_ipackets++; 727 eh = mtod(m, struct ether_header *); 728 m->m_pkthdr.rcvif = ifp; 729 m->m_pkthdr.len = m->m_len = total_len; 730 731 /* Handle BPF listeners. Let the BPF user see the packet. */ 732 if (ifp->if_bpf) 733 bpf_mtap(ifp, m); 734 735#ifdef BRIDGE 736 if (do_bridge) { 737 struct ifnet *bdg_ifp ; 738 bdg_ifp = bridge_in(m); 739 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 740 bdg_forward(&m, bdg_ifp); 741 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 742 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 743 m_freem(m); 744 continue; 745 } 746 } 747#endif 748 749 /* 750 * Don't pass packet up to the ether_input() layer unless it's 751 * a broadcast packet, multicast packet, matches our ethernet 752 * address or the interface is in promiscuous mode. 753 */ 754 if (ifp->if_bpf) { 755 if (ifp->if_flags & IFF_PROMISC && 756 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 757 ETHER_ADDR_LEN) && (eh->ether_dhost[0] & 1) == 0)){ 758 m_freem(m); 759 continue; 760 } 761 } 762 763 /* Remove header from mbuf and pass it on. */ 764 m_adj(m, sizeof(struct ether_header)); 765 ether_input(ifp, eh, m); 766 } 767 768 /* 769 * Handle the 'end of channel' condition. When the upload 770 * engine hits the end of the RX ring, it will stall. This 771 * is our cue to flush the RX ring, reload the uplist pointer 772 * register and unstall the engine. 773 * XXX This is actually a little goofy. With the ThunderLAN 774 * chip, you get an interrupt when the receiver hits the end 775 * of the receive ring, which tells you exactly when you 776 * you need to reload the ring pointer. Here we have to 777 * fake it. I'm mad at myself for not being clever enough 778 * to avoid the use of a goto here. 779 */ 780 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 || 781 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) { 782 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 783 ste_wait(sc); 784 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 785 vtophys(&sc->ste_ldata->ste_rx_list[0])); 786 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0]; 787 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 788 goto again; 789 } 790 791 return; 792} 793 794static void ste_txeoc(sc) 795 struct ste_softc *sc; 796{ 797 u_int8_t txstat; 798 struct ifnet *ifp; 799 800 ifp = &sc->arpcom.ac_if; 801 802 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 803 STE_TXSTATUS_TXDONE) { 804 if (txstat & STE_TXSTATUS_UNDERRUN || 805 txstat & STE_TXSTATUS_EXCESSCOLLS || 806 txstat & STE_TXSTATUS_RECLAIMERR) { 807 ifp->if_oerrors++; 808 printf("ste%d: transmission error: %x\n", 809 sc->ste_unit, txstat); 810 811 ste_reset(sc); 812 ste_init(sc); 813 814 if (txstat & STE_TXSTATUS_UNDERRUN && 815 sc->ste_tx_thresh < STE_PACKET_SIZE) { 816 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 817 printf("ste%d: tx underrun, increasing tx" 818 " start threshold to %d bytes\n", 819 sc->ste_unit, sc->ste_tx_thresh); 820 } 821 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 822 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 823 (STE_PACKET_SIZE >> 4)); 824 } 825 ste_init(sc); 826 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 827 } 828 829 return; 830} 831 832static void ste_txeof(sc) 833 struct ste_softc *sc; 834{ 835 struct ste_chain *cur_tx = NULL; 836 struct ifnet *ifp; 837 int idx; 838 839 ifp = &sc->arpcom.ac_if; 840 841 idx = sc->ste_cdata.ste_tx_cons; 842 while(idx != sc->ste_cdata.ste_tx_prod) { 843 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 844 845 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 846 break; 847 848 if (cur_tx->ste_mbuf != NULL) { 849 m_freem(cur_tx->ste_mbuf); 850 cur_tx->ste_mbuf = NULL; 851 } 852 853 ifp->if_opackets++; 854 855 sc->ste_cdata.ste_tx_cnt--; 856 STE_INC(idx, STE_TX_LIST_CNT); 857 ifp->if_timer = 0; 858 } 859 860 sc->ste_cdata.ste_tx_cons = idx; 861 862 if (cur_tx != NULL) 863 ifp->if_flags &= ~IFF_OACTIVE; 864 865 return; 866} 867 868static void ste_stats_update(xsc) 869 void *xsc; 870{ 871 struct ste_softc *sc; 872 struct ste_stats stats; 873 struct ifnet *ifp; 874 struct mii_data *mii; 875 int i, s; 876 u_int8_t *p; 877 878 s = splimp(); 879 880 sc = xsc; 881 ifp = &sc->arpcom.ac_if; 882 mii = device_get_softc(sc->ste_miibus); 883 884 p = (u_int8_t *)&stats; 885 886 for (i = 0; i < sizeof(stats); i++) { 887 *p = CSR_READ_1(sc, STE_STATS + i); 888 p++; 889 } 890 891 ifp->if_collisions += stats.ste_single_colls + 892 stats.ste_multi_colls + stats.ste_late_colls; 893 894 mii_tick(mii); 895 if (!sc->ste_link) { 896 mii_pollstat(mii); 897 if (mii->mii_media_status & IFM_ACTIVE && 898 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 899 sc->ste_link++; 900 if (ifp->if_snd.ifq_head != NULL) 901 ste_start(ifp); 902 } 903 904 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 905 splx(s); 906 907 return; 908} 909 910 911/* 912 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 913 * IDs against our list and return a device name if we find a match. 914 */ 915static int ste_probe(dev) 916 device_t dev; 917{ 918 struct ste_type *t; 919 920 t = ste_devs; 921 922 while(t->ste_name != NULL) { 923 if ((pci_get_vendor(dev) == t->ste_vid) && 924 (pci_get_device(dev) == t->ste_did)) { 925 device_set_desc(dev, t->ste_name); 926 return(0); 927 } 928 t++; 929 } 930 931 return(ENXIO); 932} 933 934/* 935 * Attach the interface. Allocate softc structures, do ifmedia 936 * setup and ethernet/BPF attach. 937 */ 938static int ste_attach(dev) 939 device_t dev; 940{ 941 int s; 942 u_int32_t command; 943 struct ste_softc *sc; 944 struct ifnet *ifp; 945 int unit, error = 0, rid; 946 947 s = splimp(); 948 949 sc = device_get_softc(dev); 950 unit = device_get_unit(dev); 951 bzero(sc, sizeof(struct ste_softc)); 952 953 /* 954 * Handle power management nonsense. 955 */ 956 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 957 if (command == 0x01) { 958 959 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 960 if (command & STE_PSTATE_MASK) { 961 u_int32_t iobase, membase, irq; 962 963 /* Save important PCI config data. */ 964 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 965 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 966 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 967 968 /* Reset the power state. */ 969 printf("ste%d: chip is in D%d power mode " 970 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 971 command &= 0xFFFFFFFC; 972 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 973 974 /* Restore PCI config data. */ 975 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 976 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 977 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 978 } 979 } 980 981 /* 982 * Map control/status registers. 983 */ 984 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 985 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 986 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 987 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 988 989#ifdef STE_USEIOSPACE 990 if (!(command & PCIM_CMD_PORTEN)) { 991 printf("ste%d: failed to enable I/O ports!\n", unit); 992 error = ENXIO; 993 goto fail; 994 } 995#else 996 if (!(command & PCIM_CMD_MEMEN)) { 997 printf("ste%d: failed to enable memory mapping!\n", unit); 998 error = ENXIO; 999 goto fail; 1000 } 1001#endif 1002 1003 rid = STE_RID; 1004 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 1005 0, ~0, 1, RF_ACTIVE); 1006 1007 if (sc->ste_res == NULL) { 1008 printf ("ste%d: couldn't map ports/memory\n", unit); 1009 error = ENXIO; 1010 goto fail; 1011 } 1012 1013 sc->ste_btag = rman_get_bustag(sc->ste_res); 1014 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1015 1016 rid = 0; 1017 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1018 RF_SHAREABLE | RF_ACTIVE); 1019 1020 if (sc->ste_irq == NULL) { 1021 printf("ste%d: couldn't map interrupt\n", unit); 1022 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1023 error = ENXIO; 1024 goto fail; 1025 } 1026 1027 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1028 ste_intr, sc, &sc->ste_intrhand); 1029 1030 if (error) { 1031 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1032 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1033 printf("ste%d: couldn't set up irq\n", unit); 1034 goto fail; 1035 } 1036 1037 callout_handle_init(&sc->ste_stat_ch); 1038 1039 /* Reset the adapter. */ 1040 ste_reset(sc); 1041 1042 /* 1043 * Get station address from the EEPROM. 1044 */ 1045 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1046 STE_EEADDR_NODE0, 3, 0)) { 1047 printf("ste%d: failed to read station address\n", unit); 1048 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1049 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1050 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1051 error = ENXIO;; 1052 goto fail; 1053 } 1054 1055 /* 1056 * A Sundance chip was detected. Inform the world. 1057 */ 1058 printf("ste%d: Ethernet address: %6D\n", unit, 1059 sc->arpcom.ac_enaddr, ":"); 1060 1061 sc->ste_unit = unit; 1062 1063 /* Allocate the descriptor queues. */ 1064 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1065 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1066 1067 if (sc->ste_ldata == NULL) { 1068 printf("ste%d: no memory for list buffers!\n", unit); 1069 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1070 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1071 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1072 error = ENXIO; 1073 goto fail; 1074 } 1075 1076 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1077 1078 /* Do MII setup. */ 1079 if (mii_phy_probe(dev, &sc->ste_miibus, 1080 ste_ifmedia_upd, ste_ifmedia_sts)) { 1081 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1082 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1083 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1084 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1085 contigfree(sc->ste_ldata, 1086 sizeof(struct ste_list_data), M_DEVBUF); 1087 error = ENXIO; 1088 goto fail; 1089 } 1090 1091 ifp = &sc->arpcom.ac_if; 1092 ifp->if_softc = sc; 1093 ifp->if_unit = unit; 1094 ifp->if_name = "ste"; 1095 ifp->if_mtu = ETHERMTU; 1096 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1097 ifp->if_ioctl = ste_ioctl; 1098 ifp->if_output = ether_output; 1099 ifp->if_start = ste_start; 1100 ifp->if_watchdog = ste_watchdog; 1101 ifp->if_init = ste_init; 1102 ifp->if_baudrate = 10000000; 1103 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1104 1105 /* 1106 * Call MI attach routines. 1107 */ 1108 1109 if_attach(ifp); 1110 ether_ifattach(ifp); 1111 1112 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1113 1114fail: 1115 splx(s); 1116 return(error); 1117} 1118 1119static int ste_detach(dev) 1120 device_t dev; 1121{ 1122 struct ste_softc *sc; 1123 struct ifnet *ifp; 1124 int s; 1125 1126 s = splimp(); 1127 1128 sc = device_get_softc(dev); 1129 ifp = &sc->arpcom.ac_if; 1130 1131 ste_stop(sc); 1132 if_detach(ifp); 1133 1134 bus_generic_detach(dev); 1135 device_delete_child(dev, sc->ste_miibus); 1136 1137 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1138 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1139 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1140 1141 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF); 1142 1143 splx(s); 1144 1145 return(0); 1146} 1147 1148static int ste_newbuf(sc, c, m) 1149 struct ste_softc *sc; 1150 struct ste_chain_onefrag *c; 1151 struct mbuf *m; 1152{ 1153 struct mbuf *m_new = NULL; 1154 1155 if (m == NULL) { 1156 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1157 if (m_new == NULL) { 1158 printf("ste%d: no memory for rx list -- " 1159 "packet dropped\n", sc->ste_unit); 1160 return(ENOBUFS); 1161 } 1162 MCLGET(m_new, M_DONTWAIT); 1163 if (!(m_new->m_flags & M_EXT)) { 1164 printf("ste%d: no memory for rx list -- " 1165 "packet dropped\n", sc->ste_unit); 1166 m_freem(m_new); 1167 return(ENOBUFS); 1168 } 1169 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1170 } else { 1171 m_new = m; 1172 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1173 m_new->m_data = m_new->m_ext.ext_buf; 1174 } 1175 1176 m_adj(m_new, ETHER_ALIGN); 1177 1178 c->ste_mbuf = m_new; 1179 c->ste_ptr->ste_status = 0; 1180 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1181 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; 1182 1183 return(0); 1184} 1185 1186static int ste_init_rx_list(sc) 1187 struct ste_softc *sc; 1188{ 1189 struct ste_chain_data *cd; 1190 struct ste_list_data *ld; 1191 int i; 1192 1193 cd = &sc->ste_cdata; 1194 ld = sc->ste_ldata; 1195 1196 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1197 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1198 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1199 return(ENOBUFS); 1200 if (i == (STE_RX_LIST_CNT - 1)) { 1201 cd->ste_rx_chain[i].ste_next = 1202 &cd->ste_rx_chain[0]; 1203 ld->ste_rx_list[i].ste_next = 1204 vtophys(&ld->ste_rx_list[0]); 1205 } else { 1206 cd->ste_rx_chain[i].ste_next = 1207 &cd->ste_rx_chain[i + 1]; 1208 ld->ste_rx_list[i].ste_next = 1209 vtophys(&ld->ste_rx_list[i + 1]); 1210 } 1211 1212 } 1213 1214 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1215 1216 return(0); 1217} 1218 1219static void ste_init_tx_list(sc) 1220 struct ste_softc *sc; 1221{ 1222 struct ste_chain_data *cd; 1223 struct ste_list_data *ld; 1224 int i; 1225 1226 cd = &sc->ste_cdata; 1227 ld = sc->ste_ldata; 1228 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1229 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1230 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1231 if (i == (STE_TX_LIST_CNT - 1)) 1232 cd->ste_tx_chain[i].ste_next = 1233 &cd->ste_tx_chain[0]; 1234 else 1235 cd->ste_tx_chain[i].ste_next = 1236 &cd->ste_tx_chain[i + 1]; 1237 if (i == 0) 1238 cd->ste_tx_chain[i].ste_prev = 1239 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1240 else 1241 cd->ste_tx_chain[i].ste_prev = 1242 &cd->ste_tx_chain[i - 1]; 1243 } 1244 1245 1246 bzero((char *)ld->ste_tx_list, 1247 sizeof(struct ste_desc) * STE_TX_LIST_CNT); 1248 1249 cd->ste_tx_prod = 0; 1250 cd->ste_tx_cons = 0; 1251 cd->ste_tx_cnt = 0; 1252 1253 return; 1254} 1255 1256static void ste_init(xsc) 1257 void *xsc; 1258{ 1259 struct ste_softc *sc; 1260 int i, s; 1261 struct ifnet *ifp; 1262 struct mii_data *mii; 1263 1264 s = splimp(); 1265 1266 sc = xsc; 1267 ifp = &sc->arpcom.ac_if; 1268 mii = device_get_softc(sc->ste_miibus); 1269 1270 ste_stop(sc); 1271 1272 /* Init our MAC address */ 1273 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1274 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1275 } 1276 1277 /* Init RX list */ 1278 if (ste_init_rx_list(sc) == ENOBUFS) { 1279 printf("ste%d: initialization failed: no " 1280 "memory for RX buffers\n", sc->ste_unit); 1281 ste_stop(sc); 1282 splx(s); 1283 return; 1284 } 1285 1286 /* Init TX descriptors */ 1287 ste_init_tx_list(sc); 1288 1289 /* Set the TX freethresh value */ 1290 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1291 1292 /* Set the TX start threshold for best performance. */ 1293 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1294 1295 /* Set the TX reclaim threshold. */ 1296 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1297 1298 /* Set up the RX filter. */ 1299 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1300 1301 /* If we want promiscuous mode, set the allframes bit. */ 1302 if (ifp->if_flags & IFF_PROMISC) { 1303 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1304 } else { 1305 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1306 } 1307 1308 /* Set capture broadcast bit to accept broadcast frames. */ 1309 if (ifp->if_flags & IFF_BROADCAST) { 1310 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1311 } else { 1312 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1313 } 1314 1315 ste_setmulti(sc); 1316 1317 /* Load the address of the RX list. */ 1318 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1319 ste_wait(sc); 1320 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1321 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1322 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1323 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1324 1325 /* Set TX polling interval */ 1326 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1327 1328 /* Load address of the TX list */ 1329 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1330 ste_wait(sc); 1331 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1332 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1333 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1334 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1335 ste_wait(sc); 1336 1337 /* Enable receiver and transmitter */ 1338 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1339 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1340 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1341 1342 /* Enable stats counters. */ 1343 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1344 1345 /* Enable interrupts. */ 1346 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1347 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1348 1349 ste_ifmedia_upd(ifp); 1350 1351 ifp->if_flags |= IFF_RUNNING; 1352 ifp->if_flags &= ~IFF_OACTIVE; 1353 1354 splx(s); 1355 1356 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1357 1358 return; 1359} 1360 1361static void ste_stop(sc) 1362 struct ste_softc *sc; 1363{ 1364 int i; 1365 struct ifnet *ifp; 1366 1367 ifp = &sc->arpcom.ac_if; 1368 1369 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1370 1371 CSR_WRITE_2(sc, STE_IMR, 0); 1372 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1373 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1374 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1375 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1376 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1377 ste_wait(sc); 1378 1379 sc->ste_link = 0; 1380 1381 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1382 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1383 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1384 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1385 } 1386 } 1387 1388 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1389 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1390 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1391 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1392 } 1393 } 1394 1395 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1396 1397 return; 1398} 1399 1400static void ste_reset(sc) 1401 struct ste_softc *sc; 1402{ 1403 int i; 1404 1405 STE_SETBIT4(sc, STE_ASICCTL, 1406 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1407 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1408 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1409 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1410 STE_ASICCTL_EXTRESET_RESET); 1411 1412 DELAY(100000); 1413 1414 for (i = 0; i < STE_TIMEOUT; i++) { 1415 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1416 break; 1417 } 1418 1419 if (i == STE_TIMEOUT) 1420 printf("ste%d: global reset never completed\n", sc->ste_unit); 1421 1422 return; 1423} 1424 1425static int ste_ioctl(ifp, command, data) 1426 struct ifnet *ifp; 1427 u_long command; 1428 caddr_t data; 1429{ 1430 struct ste_softc *sc; 1431 struct ifreq *ifr; 1432 struct mii_data *mii; 1433 int error = 0, s; 1434 1435 s = splimp(); 1436 1437 sc = ifp->if_softc; 1438 ifr = (struct ifreq *)data; 1439 1440 switch(command) { 1441 case SIOCSIFADDR: 1442 case SIOCGIFADDR: 1443 case SIOCSIFMTU: 1444 error = ether_ioctl(ifp, command, data); 1445 break; 1446 case SIOCSIFFLAGS: 1447 if (ifp->if_flags & IFF_UP) { 1448 if (ifp->if_flags & IFF_RUNNING && 1449 ifp->if_flags & IFF_PROMISC && 1450 !(sc->ste_if_flags & IFF_PROMISC)) { 1451 STE_SETBIT1(sc, STE_RX_MODE, 1452 STE_RXMODE_PROMISC); 1453 } else if (ifp->if_flags & IFF_RUNNING && 1454 !(ifp->if_flags & IFF_PROMISC) && 1455 sc->ste_if_flags & IFF_PROMISC) { 1456 STE_CLRBIT1(sc, STE_RX_MODE, 1457 STE_RXMODE_PROMISC); 1458 } else if (!(ifp->if_flags & IFF_RUNNING)) { 1459 sc->ste_tx_thresh = STE_MIN_FRAMELEN; 1460 ste_init(sc); 1461 } 1462 } else { 1463 if (ifp->if_flags & IFF_RUNNING) 1464 ste_stop(sc); 1465 } 1466 sc->ste_if_flags = ifp->if_flags; 1467 error = 0; 1468 break; 1469 case SIOCADDMULTI: 1470 case SIOCDELMULTI: 1471 ste_setmulti(sc); 1472 error = 0; 1473 break; 1474 case SIOCGIFMEDIA: 1475 case SIOCSIFMEDIA: 1476 mii = device_get_softc(sc->ste_miibus); 1477 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1478 break; 1479 default: 1480 error = EINVAL; 1481 break; 1482 } 1483 1484 splx(s); 1485 1486 return(error); 1487} 1488 1489static int ste_encap(sc, c, m_head) 1490 struct ste_softc *sc; 1491 struct ste_chain *c; 1492 struct mbuf *m_head; 1493{ 1494 int frag = 0; 1495 struct ste_frag *f = NULL; 1496 struct mbuf *m; 1497 struct ste_desc *d; 1498 int total_len = 0; 1499 1500 d = c->ste_ptr; 1501 d->ste_ctl = 0; 1502 d->ste_next = 0; 1503 1504 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1505 if (m->m_len != 0) { 1506 if (frag == STE_MAXFRAGS) 1507 break; 1508 total_len += m->m_len; 1509 f = &c->ste_ptr->ste_frags[frag]; 1510 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1511 f->ste_len = m->m_len; 1512 frag++; 1513 } 1514 } 1515 1516 c->ste_mbuf = m_head; 1517 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1518 c->ste_ptr->ste_ctl = total_len; 1519 1520 return(0); 1521} 1522 1523static void ste_start(ifp) 1524 struct ifnet *ifp; 1525{ 1526 struct ste_softc *sc; 1527 struct mbuf *m_head = NULL; 1528 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1529 int idx; 1530 1531 sc = ifp->if_softc; 1532 1533 if (!sc->ste_link) 1534 return; 1535 1536 if (ifp->if_flags & IFF_OACTIVE) 1537 return; 1538 1539 idx = sc->ste_cdata.ste_tx_prod; 1540 start_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1541 1542 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1543 1544 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1545 ifp->if_flags |= IFF_OACTIVE; 1546 break; 1547 } 1548 1549 IF_DEQUEUE(&ifp->if_snd, m_head); 1550 if (m_head == NULL) 1551 break; 1552 1553 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1554 1555 ste_encap(sc, cur_tx, m_head); 1556 1557 if (prev != NULL) 1558 prev->ste_ptr->ste_next = cur_tx->ste_phys; 1559 prev = cur_tx; 1560 1561 /* 1562 * If there's a BPF listener, bounce a copy of this frame 1563 * to him. 1564 */ 1565 if (ifp->if_bpf) 1566 bpf_mtap(ifp, cur_tx->ste_mbuf); 1567 1568 STE_INC(idx, STE_TX_LIST_CNT); 1569 sc->ste_cdata.ste_tx_cnt++; 1570 } 1571 1572 if (cur_tx == NULL) 1573 return; 1574 1575 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR; 1576 1577 /* Start transmission */ 1578 sc->ste_cdata.ste_tx_prod = idx; 1579 start_tx->ste_prev->ste_ptr->ste_next = start_tx->ste_phys; 1580 1581 ifp->if_timer = 5; 1582 1583 return; 1584} 1585 1586static void ste_watchdog(ifp) 1587 struct ifnet *ifp; 1588{ 1589 struct ste_softc *sc; 1590 1591 sc = ifp->if_softc; 1592 1593 ifp->if_oerrors++; 1594 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1595 1596 ste_txeoc(sc); 1597 ste_txeof(sc); 1598 ste_rxeof(sc); 1599 ste_reset(sc); 1600 ste_init(sc); 1601 1602 if (ifp->if_snd.ifq_head != NULL) 1603 ste_start(ifp); 1604 1605 return; 1606} 1607 1608static void ste_shutdown(dev) 1609 device_t dev; 1610{ 1611 struct ste_softc *sc; 1612 1613 sc = device_get_softc(dev); 1614 1615 ste_stop(sc); 1616 1617 return; 1618} 1619