if_ste.c revision 51583
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 51583 1999-09-23 03:32:57Z wpaul $ 33 */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/sockio.h> 38#include <sys/mbuf.h> 39#include <sys/malloc.h> 40#include <sys/kernel.h> 41#include <sys/socket.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48 49#include <net/bpf.h> 50 51#include "opt_bdg.h" 52#ifdef BRIDGE 53#include <net/bridge.h> 54#endif 55 56#include <vm/vm.h> /* for vtophys */ 57#include <vm/pmap.h> /* for vtophys */ 58#include <machine/clock.h> /* for DELAY */ 59#include <machine/bus_memio.h> 60#include <machine/bus_pio.h> 61#include <machine/bus.h> 62#include <machine/resource.h> 63#include <sys/bus.h> 64#include <sys/rman.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <pci/pcireg.h> 70#include <pci/pcivar.h> 71 72/* "controller miibus0" required. See GENERIC if you get errors here. */ 73#include "miibus_if.h" 74 75#define STE_USEIOSPACE 76 77#include <pci/if_stereg.h> 78 79#if !defined(lint) 80static const char rcsid[] = 81 "$FreeBSD: head/sys/pci/if_ste.c 51583 1999-09-23 03:32:57Z wpaul $"; 82#endif 83 84/* 85 * Various supported device vendors/types and their names. 86 */ 87static struct ste_type ste_devs[] = { 88 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 89 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 90 { 0, 0, NULL } 91}; 92 93static int ste_probe __P((device_t)); 94static int ste_attach __P((device_t)); 95static int ste_detach __P((device_t)); 96static void ste_init __P((void *)); 97static void ste_intr __P((void *)); 98static void ste_rxeof __P((struct ste_softc *)); 99static void ste_txeoc __P((struct ste_softc *)); 100static void ste_txeof __P((struct ste_softc *)); 101static void ste_stats_update __P((void *)); 102static void ste_stop __P((struct ste_softc *)); 103static void ste_reset __P((struct ste_softc *)); 104static int ste_ioctl __P((struct ifnet *, u_long, caddr_t)); 105static int ste_encap __P((struct ste_softc *, struct ste_chain *, 106 struct mbuf *)); 107static void ste_start __P((struct ifnet *)); 108static void ste_watchdog __P((struct ifnet *)); 109static void ste_shutdown __P((device_t)); 110static int ste_newbuf __P((struct ste_softc *, 111 struct ste_chain_onefrag *, 112 struct mbuf *)); 113static int ste_ifmedia_upd __P((struct ifnet *)); 114static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 115 116static void ste_mii_sync __P((struct ste_softc *)); 117static void ste_mii_send __P((struct ste_softc *, u_int32_t, int)); 118static int ste_mii_readreg __P((struct ste_softc *, 119 struct ste_mii_frame *)); 120static int ste_mii_writereg __P((struct ste_softc *, 121 struct ste_mii_frame *)); 122static int ste_miibus_readreg __P((device_t, int, int)); 123static int ste_miibus_writereg __P((device_t, int, int, int)); 124static void ste_miibus_statchg __P((device_t)); 125 126static int ste_eeprom_wait __P((struct ste_softc *)); 127static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int, 128 int, int)); 129static void ste_wait __P((struct ste_softc *)); 130static u_int8_t ste_calchash __P((caddr_t)); 131static void ste_setmulti __P((struct ste_softc *)); 132static int ste_init_rx_list __P((struct ste_softc *)); 133static void ste_init_tx_list __P((struct ste_softc *)); 134 135#ifdef STE_USEIOSPACE 136#define STE_RES SYS_RES_IOPORT 137#define STE_RID STE_PCI_LOIO 138#else 139#define STE_RES SYS_RES_MEMORY 140#define STE_RID STE_PCI_LOMEM 141#endif 142 143static device_method_t ste_methods[] = { 144 /* Device interface */ 145 DEVMETHOD(device_probe, ste_probe), 146 DEVMETHOD(device_attach, ste_attach), 147 DEVMETHOD(device_detach, ste_detach), 148 DEVMETHOD(device_shutdown, ste_shutdown), 149 150 /* bus interface */ 151 DEVMETHOD(bus_print_child, bus_generic_print_child), 152 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 153 154 /* MII interface */ 155 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 156 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 157 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 158 159 { 0, 0 } 160}; 161 162static driver_t ste_driver = { 163 "ste", 164 ste_methods, 165 sizeof(struct ste_softc) 166}; 167 168static devclass_t ste_devclass; 169 170DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0); 171DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 172 173#define STE_SETBIT4(sc, reg, x) \ 174 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 175 176#define STE_CLRBIT4(sc, reg, x) \ 177 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 178 179#define STE_SETBIT2(sc, reg, x) \ 180 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 181 182#define STE_CLRBIT2(sc, reg, x) \ 183 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 184 185#define STE_SETBIT1(sc, reg, x) \ 186 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 187 188#define STE_CLRBIT1(sc, reg, x) \ 189 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 190 191 192#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 193#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 194 195/* 196 * Sync the PHYs by setting data bit and strobing the clock 32 times. 197 */ 198static void ste_mii_sync(sc) 199 struct ste_softc *sc; 200{ 201 register int i; 202 203 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 204 205 for (i = 0; i < 32; i++) { 206 MII_SET(STE_PHYCTL_MCLK); 207 DELAY(1); 208 MII_CLR(STE_PHYCTL_MCLK); 209 DELAY(1); 210 } 211 212 return; 213} 214 215/* 216 * Clock a series of bits through the MII. 217 */ 218static void ste_mii_send(sc, bits, cnt) 219 struct ste_softc *sc; 220 u_int32_t bits; 221 int cnt; 222{ 223 int i; 224 225 MII_CLR(STE_PHYCTL_MCLK); 226 227 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 228 if (bits & i) { 229 MII_SET(STE_PHYCTL_MDATA); 230 } else { 231 MII_CLR(STE_PHYCTL_MDATA); 232 } 233 DELAY(1); 234 MII_CLR(STE_PHYCTL_MCLK); 235 DELAY(1); 236 MII_SET(STE_PHYCTL_MCLK); 237 } 238} 239 240/* 241 * Read an PHY register through the MII. 242 */ 243static int ste_mii_readreg(sc, frame) 244 struct ste_softc *sc; 245 struct ste_mii_frame *frame; 246 247{ 248 int i, ack, s; 249 250 s = splimp(); 251 252 /* 253 * Set up frame for RX. 254 */ 255 frame->mii_stdelim = STE_MII_STARTDELIM; 256 frame->mii_opcode = STE_MII_READOP; 257 frame->mii_turnaround = 0; 258 frame->mii_data = 0; 259 260 CSR_WRITE_2(sc, STE_PHYCTL, 0); 261 /* 262 * Turn on data xmit. 263 */ 264 MII_SET(STE_PHYCTL_MDIR); 265 266 ste_mii_sync(sc); 267 268 /* 269 * Send command/address info. 270 */ 271 ste_mii_send(sc, frame->mii_stdelim, 2); 272 ste_mii_send(sc, frame->mii_opcode, 2); 273 ste_mii_send(sc, frame->mii_phyaddr, 5); 274 ste_mii_send(sc, frame->mii_regaddr, 5); 275 276 /* Turn off xmit. */ 277 MII_CLR(STE_PHYCTL_MDIR); 278 279 /* Idle bit */ 280 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 281 DELAY(1); 282 MII_SET(STE_PHYCTL_MCLK); 283 DELAY(1); 284 285 /* Check for ack */ 286 MII_CLR(STE_PHYCTL_MCLK); 287 DELAY(1); 288 MII_SET(STE_PHYCTL_MCLK); 289 DELAY(1); 290 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 291 292 /* 293 * Now try reading data bits. If the ack failed, we still 294 * need to clock through 16 cycles to keep the PHY(s) in sync. 295 */ 296 if (ack) { 297 for(i = 0; i < 16; i++) { 298 MII_CLR(STE_PHYCTL_MCLK); 299 DELAY(1); 300 MII_SET(STE_PHYCTL_MCLK); 301 DELAY(1); 302 } 303 goto fail; 304 } 305 306 for (i = 0x8000; i; i >>= 1) { 307 MII_CLR(STE_PHYCTL_MCLK); 308 DELAY(1); 309 if (!ack) { 310 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 311 frame->mii_data |= i; 312 DELAY(1); 313 } 314 MII_SET(STE_PHYCTL_MCLK); 315 DELAY(1); 316 } 317 318fail: 319 320 MII_CLR(STE_PHYCTL_MCLK); 321 DELAY(1); 322 MII_SET(STE_PHYCTL_MCLK); 323 DELAY(1); 324 325 splx(s); 326 327 if (ack) 328 return(1); 329 return(0); 330} 331 332/* 333 * Write to a PHY register through the MII. 334 */ 335static int ste_mii_writereg(sc, frame) 336 struct ste_softc *sc; 337 struct ste_mii_frame *frame; 338 339{ 340 int s; 341 342 s = splimp(); 343 /* 344 * Set up frame for TX. 345 */ 346 347 frame->mii_stdelim = STE_MII_STARTDELIM; 348 frame->mii_opcode = STE_MII_WRITEOP; 349 frame->mii_turnaround = STE_MII_TURNAROUND; 350 351 /* 352 * Turn on data output. 353 */ 354 MII_SET(STE_PHYCTL_MDIR); 355 356 ste_mii_sync(sc); 357 358 ste_mii_send(sc, frame->mii_stdelim, 2); 359 ste_mii_send(sc, frame->mii_opcode, 2); 360 ste_mii_send(sc, frame->mii_phyaddr, 5); 361 ste_mii_send(sc, frame->mii_regaddr, 5); 362 ste_mii_send(sc, frame->mii_turnaround, 2); 363 ste_mii_send(sc, frame->mii_data, 16); 364 365 /* Idle bit. */ 366 MII_SET(STE_PHYCTL_MCLK); 367 DELAY(1); 368 MII_CLR(STE_PHYCTL_MCLK); 369 DELAY(1); 370 371 /* 372 * Turn off xmit. 373 */ 374 MII_CLR(STE_PHYCTL_MDIR); 375 376 splx(s); 377 378 return(0); 379} 380 381static int ste_miibus_readreg(dev, phy, reg) 382 device_t dev; 383 int phy, reg; 384{ 385 struct ste_softc *sc; 386 struct ste_mii_frame frame; 387 388 sc = device_get_softc(dev); 389 390 bzero((char *)&frame, sizeof(frame)); 391 392 frame.mii_phyaddr = phy; 393 frame.mii_regaddr = reg; 394 ste_mii_readreg(sc, &frame); 395 396 return(frame.mii_data); 397} 398 399static int ste_miibus_writereg(dev, phy, reg, data) 400 device_t dev; 401 int phy, reg, data; 402{ 403 struct ste_softc *sc; 404 struct ste_mii_frame frame; 405 406 sc = device_get_softc(dev); 407 bzero((char *)&frame, sizeof(frame)); 408 409 frame.mii_phyaddr = phy; 410 frame.mii_regaddr = reg; 411 frame.mii_data = data; 412 413 ste_mii_writereg(sc, &frame); 414 415 return(0); 416} 417 418static void ste_miibus_statchg(dev) 419 device_t dev; 420{ 421 struct ste_softc *sc; 422 struct mii_data *mii; 423 424 sc = device_get_softc(dev); 425 mii = device_get_softc(sc->ste_miibus); 426 427 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 428 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 429 } else { 430 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } 432 433 return; 434} 435 436static int ste_ifmedia_upd(ifp) 437 struct ifnet *ifp; 438{ 439 struct ste_softc *sc; 440 struct mii_data *mii; 441 442 sc = ifp->if_softc; 443 mii = device_get_softc(sc->ste_miibus); 444 mii_mediachg(mii); 445 446 return(0); 447} 448 449static void ste_ifmedia_sts(ifp, ifmr) 450 struct ifnet *ifp; 451 struct ifmediareq *ifmr; 452{ 453 struct ste_softc *sc; 454 struct mii_data *mii; 455 456 sc = ifp->if_softc; 457 mii = device_get_softc(sc->ste_miibus); 458 459 mii_pollstat(mii); 460 ifmr->ifm_active = mii->mii_media_active; 461 ifmr->ifm_status = mii->mii_media_status; 462 463 return; 464} 465 466static void ste_wait(sc) 467 struct ste_softc *sc; 468{ 469 register int i; 470 471 for (i = 0; i < STE_TIMEOUT; i++) { 472 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 473 break; 474 } 475 476 if (i == STE_TIMEOUT) 477 printf("ste%d: command never completed!\n", sc->ste_unit); 478 479 return; 480} 481 482/* 483 * The EEPROM is slow: give it time to come ready after issuing 484 * it a command. 485 */ 486static int ste_eeprom_wait(sc) 487 struct ste_softc *sc; 488{ 489 int i; 490 491 DELAY(1000); 492 493 for (i = 0; i < 100; i++) { 494 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 495 DELAY(1000); 496 else 497 break; 498 } 499 500 if (i == 100) { 501 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 502 return(1); 503 } 504 505 return(0); 506} 507 508/* 509 * Read a sequence of words from the EEPROM. Note that ethernet address 510 * data is stored in the EEPROM in network byte order. 511 */ 512static int ste_read_eeprom(sc, dest, off, cnt, swap) 513 struct ste_softc *sc; 514 caddr_t dest; 515 int off; 516 int cnt; 517 int swap; 518{ 519 int err = 0, i; 520 u_int16_t word = 0, *ptr; 521 522 if (ste_eeprom_wait(sc)) 523 return(1); 524 525 for (i = 0; i < cnt; i++) { 526 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 527 err = ste_eeprom_wait(sc); 528 if (err) 529 break; 530 word = CSR_READ_2(sc, STE_EEPROM_DATA); 531 ptr = (u_int16_t *)(dest + (i * 2)); 532 if (swap) 533 *ptr = ntohs(word); 534 else 535 *ptr = word; 536 } 537 538 return(err ? 1 : 0); 539} 540 541static u_int8_t ste_calchash(addr) 542 caddr_t addr; 543{ 544 545 u_int32_t crc, carry; 546 int i, j; 547 u_int8_t c; 548 549 /* Compute CRC for the address value. */ 550 crc = 0xFFFFFFFF; /* initial value */ 551 552 for (i = 0; i < 6; i++) { 553 c = *(addr + i); 554 for (j = 0; j < 8; j++) { 555 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 556 crc <<= 1; 557 c >>= 1; 558 if (carry) 559 crc = (crc ^ 0x04c11db6) | carry; 560 } 561 } 562 563 /* return the filter bit position */ 564 return(crc & 0x0000003F); 565} 566 567static void ste_setmulti(sc) 568 struct ste_softc *sc; 569{ 570 struct ifnet *ifp; 571 int h = 0; 572 u_int32_t hashes[2] = { 0, 0 }; 573 struct ifmultiaddr *ifma; 574 575 ifp = &sc->arpcom.ac_if; 576 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 577 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 578 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 579 return; 580 } 581 582 /* first, zot all the existing hash bits */ 583 CSR_WRITE_4(sc, STE_MAR0, 0); 584 CSR_WRITE_4(sc, STE_MAR1, 0); 585 586 /* now program new ones */ 587 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 588 ifma = ifma->ifma_link.le_next) { 589 if (ifma->ifma_addr->sa_family != AF_LINK) 590 continue; 591 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 592 if (h < 32) 593 hashes[0] |= (1 << h); 594 else 595 hashes[1] |= (1 << (h - 32)); 596 } 597 598 CSR_WRITE_4(sc, STE_MAR0, hashes[0]); 599 CSR_WRITE_4(sc, STE_MAR1, hashes[1]); 600 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 601 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 602 603 return; 604} 605 606static void ste_intr(xsc) 607 void *xsc; 608{ 609 struct ste_softc *sc; 610 struct ifnet *ifp; 611 u_int16_t status; 612 613 sc = xsc; 614 ifp = &sc->arpcom.ac_if; 615 616 /* See if this is really our interrupt. */ 617 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 618 return; 619 620 for (;;) { 621 status = CSR_READ_2(sc, STE_ISR_ACK); 622 623 if (!(status & STE_INTRS)) 624 break; 625 626 if (status & STE_ISR_RX_DMADONE) 627 ste_rxeof(sc); 628 629 if (status & STE_ISR_TX_DMADONE) 630 ste_txeof(sc); 631 632 if (status & STE_ISR_TX_DONE) 633 ste_txeoc(sc); 634 635 if (status & STE_ISR_STATS_OFLOW) { 636 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 637 ste_stats_update(sc); 638 } 639 640 if (status & STE_ISR_HOSTERR) { 641 ste_reset(sc); 642 ste_init(sc); 643 } 644 } 645 646 /* Re-enable interrupts */ 647 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 648 649 if (ifp->if_snd.ifq_head != NULL) 650 ste_start(ifp); 651 652 return; 653} 654 655/* 656 * A frame has been uploaded: pass the resulting mbuf chain up to 657 * the higher level protocols. 658 */ 659static void ste_rxeof(sc) 660 struct ste_softc *sc; 661{ 662 struct ether_header *eh; 663 struct mbuf *m; 664 struct ifnet *ifp; 665 struct ste_chain_onefrag *cur_rx; 666 int total_len = 0; 667 u_int32_t rxstat; 668 669 ifp = &sc->arpcom.ac_if; 670 671again: 672 673 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) { 674 cur_rx = sc->ste_cdata.ste_rx_head; 675 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 676 677 /* 678 * If an error occurs, update stats, clear the 679 * status word and leave the mbuf cluster in place: 680 * it should simply get re-used next time this descriptor 681 * comes up in the ring. 682 */ 683 if (rxstat & STE_RXSTAT_FRAME_ERR) { 684 ifp->if_ierrors++; 685 cur_rx->ste_ptr->ste_status = 0; 686 continue; 687 } 688 689 /* 690 * If there error bit was not set, the upload complete 691 * bit should be set which means we have a valid packet. 692 * If not, something truly strange has happened. 693 */ 694 if (!(rxstat & STE_RXSTAT_DMADONE)) { 695 printf("ste%d: bad receive status -- packet dropped", 696 sc->ste_unit); 697 ifp->if_ierrors++; 698 cur_rx->ste_ptr->ste_status = 0; 699 continue; 700 } 701 702 /* No errors; receive the packet. */ 703 m = cur_rx->ste_mbuf; 704 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 705 706 /* 707 * Try to conjure up a new mbuf cluster. If that 708 * fails, it means we have an out of memory condition and 709 * should leave the buffer in place and continue. This will 710 * result in a lost packet, but there's little else we 711 * can do in this situation. 712 */ 713 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 714 ifp->if_ierrors++; 715 cur_rx->ste_ptr->ste_status = 0; 716 continue; 717 } 718 719 ifp->if_ipackets++; 720 eh = mtod(m, struct ether_header *); 721 m->m_pkthdr.rcvif = ifp; 722 m->m_pkthdr.len = m->m_len = total_len; 723 724 /* Handle BPF listeners. Let the BPF user see the packet. */ 725 if (ifp->if_bpf) 726 bpf_mtap(ifp, m); 727 728#ifdef BRIDGE 729 if (do_bridge) { 730 struct ifnet *bdg_ifp ; 731 bdg_ifp = bridge_in(m); 732 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 733 bdg_forward(&m, bdg_ifp); 734 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 735 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 736 m_freem(m); 737 continue; 738 } 739 } 740#endif 741 742 /* 743 * Don't pass packet up to the ether_input() layer unless it's 744 * a broadcast packet, multicast packet, matches our ethernet 745 * address or the interface is in promiscuous mode. 746 */ 747 if (ifp->if_bpf) { 748 if (ifp->if_flags & IFF_PROMISC && 749 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 750 ETHER_ADDR_LEN) && (eh->ether_dhost[0] & 1) == 0)){ 751 m_freem(m); 752 continue; 753 } 754 } 755 756 /* Remove header from mbuf and pass it on. */ 757 m_adj(m, sizeof(struct ether_header)); 758 ether_input(ifp, eh, m); 759 } 760 761 /* 762 * Handle the 'end of channel' condition. When the upload 763 * engine hits the end of the RX ring, it will stall. This 764 * is our cue to flush the RX ring, reload the uplist pointer 765 * register and unstall the engine. 766 * XXX This is actually a little goofy. With the ThunderLAN 767 * chip, you get an interrupt when the receiver hits the end 768 * of the receive ring, which tells you exactly when you 769 * you need to reload the ring pointer. Here we have to 770 * fake it. I'm mad at myself for not being clever enough 771 * to avoid the use of a goto here. 772 */ 773 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 || 774 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) { 775 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 776 ste_wait(sc); 777 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 778 vtophys(&sc->ste_ldata->ste_rx_list[0])); 779 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0]; 780 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 781 goto again; 782 } 783 784 return; 785} 786 787static void ste_txeoc(sc) 788 struct ste_softc *sc; 789{ 790 u_int8_t txstat; 791 struct ifnet *ifp; 792 793 ifp = &sc->arpcom.ac_if; 794 795 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 796 STE_TXSTATUS_TXDONE) { 797 if (txstat & STE_TXSTATUS_UNDERRUN || 798 txstat & STE_TXSTATUS_EXCESSCOLLS || 799 txstat & STE_TXSTATUS_RECLAIMERR) { 800 ifp->if_oerrors++; 801 printf("ste%d: transmission error: %x\n", 802 sc->ste_unit, txstat); 803 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_TX_RESET); 804 805 if (sc->ste_cdata.ste_tx_head != NULL) 806 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 807 vtophys(sc->ste_cdata.ste_tx_head->ste_ptr)); 808 if (txstat & STE_TXSTATUS_UNDERRUN && 809 sc->ste_tx_thresh < STE_PACKET_SIZE) { 810 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 811 printf("ste%d: tx underrun, increasing tx" 812 " start threshold to %d bytes\n", 813 sc->ste_unit, sc->ste_tx_thresh); 814 } 815 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 816 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 817 (STE_PACKET_SIZE >> 4)); 818 } 819 ste_init(sc); 820 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 821 } 822 823 return; 824} 825 826static void ste_txeof(sc) 827 struct ste_softc *sc; 828{ 829 struct ste_chain *cur_tx; 830 struct ifnet *ifp; 831 832 ifp = &sc->arpcom.ac_if; 833 834 /* Clear the timeout timer. */ 835 ifp->if_timer = 0; 836 837 while(sc->ste_cdata.ste_tx_head != NULL) { 838 cur_tx = sc->ste_cdata.ste_tx_head; 839 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 840 break; 841 sc->ste_cdata.ste_tx_head = cur_tx->ste_next; 842 843 m_freem(cur_tx->ste_mbuf); 844 cur_tx->ste_mbuf = NULL; 845 ifp->if_opackets++; 846 847 cur_tx->ste_next = sc->ste_cdata.ste_tx_free; 848 sc->ste_cdata.ste_tx_free = cur_tx; 849 } 850 851 if (sc->ste_cdata.ste_tx_head == NULL) { 852 ifp->if_flags &= ~IFF_OACTIVE; 853 sc->ste_cdata.ste_tx_tail = NULL; 854 } else { 855 if (CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_TXDMA_STOPPED || 856 !CSR_READ_4(sc, STE_TX_DMALIST_PTR)) { 857 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 858 vtophys(sc->ste_cdata.ste_tx_head->ste_ptr)); 859 CSR_WRITE_4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 860 } 861 } 862 863 return; 864} 865 866static void ste_stats_update(xsc) 867 void *xsc; 868{ 869 struct ste_softc *sc; 870 struct ste_stats stats; 871 struct ifnet *ifp; 872 struct mii_data *mii; 873 int i, s; 874 u_int8_t *p; 875 876 s = splimp(); 877 878 sc = xsc; 879 ifp = &sc->arpcom.ac_if; 880 mii = device_get_softc(sc->ste_miibus); 881 882 p = (u_int8_t *)&stats; 883 884 for (i = 0; i < sizeof(stats); i++) { 885 *p = CSR_READ_1(sc, STE_STATS + i); 886 p++; 887 } 888 889 ifp->if_collisions += stats.ste_single_colls + 890 stats.ste_multi_colls + stats.ste_late_colls; 891 892 mii_tick(mii); 893 894 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 895 splx(s); 896 897 return; 898} 899 900 901/* 902 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 903 * IDs against our list and return a device name if we find a match. 904 */ 905static int ste_probe(dev) 906 device_t dev; 907{ 908 struct ste_type *t; 909 910 t = ste_devs; 911 912 while(t->ste_name != NULL) { 913 if ((pci_get_vendor(dev) == t->ste_vid) && 914 (pci_get_device(dev) == t->ste_did)) { 915 device_set_desc(dev, t->ste_name); 916 return(0); 917 } 918 t++; 919 } 920 921 return(ENXIO); 922} 923 924/* 925 * Attach the interface. Allocate softc structures, do ifmedia 926 * setup and ethernet/BPF attach. 927 */ 928static int ste_attach(dev) 929 device_t dev; 930{ 931 int s; 932 u_int32_t command; 933 struct ste_softc *sc; 934 struct ifnet *ifp; 935 int unit, error = 0, rid; 936 937 s = splimp(); 938 939 sc = device_get_softc(dev); 940 unit = device_get_unit(dev); 941 bzero(sc, sizeof(struct ste_softc)); 942 943 /* 944 * Handle power management nonsense. 945 */ 946 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 947 if (command == 0x01) { 948 949 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 950 if (command & STE_PSTATE_MASK) { 951 u_int32_t iobase, membase, irq; 952 953 /* Save important PCI config data. */ 954 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 955 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 956 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 957 958 /* Reset the power state. */ 959 printf("ste%d: chip is in D%d power mode " 960 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 961 command &= 0xFFFFFFFC; 962 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 963 964 /* Restore PCI config data. */ 965 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 966 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 967 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 968 } 969 } 970 971 /* 972 * Map control/status registers. 973 */ 974 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 975 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 976 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 977 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 978 979#ifdef STE_USEIOSPACE 980 if (!(command & PCIM_CMD_PORTEN)) { 981 printf("ste%d: failed to enable I/O ports!\n", unit); 982 error = ENXIO; 983 goto fail; 984 } 985#else 986 if (!(command & PCIM_CMD_MEMEN)) { 987 printf("ste%d: failed to enable memory mapping!\n", unit); 988 error = ENXIO; 989 goto fail; 990 } 991#endif 992 993 rid = STE_RID; 994 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 995 0, ~0, 1, RF_ACTIVE); 996 997 if (sc->ste_res == NULL) { 998 printf ("ste%d: couldn't map ports/memory\n", unit); 999 error = ENXIO; 1000 goto fail; 1001 } 1002 1003 sc->ste_btag = rman_get_bustag(sc->ste_res); 1004 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1005 1006 rid = 0; 1007 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1008 RF_SHAREABLE | RF_ACTIVE); 1009 1010 if (sc->ste_irq == NULL) { 1011 printf("ste%d: couldn't map interrupt\n", unit); 1012 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1013 error = ENXIO; 1014 goto fail; 1015 } 1016 1017 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1018 ste_intr, sc, &sc->ste_intrhand); 1019 1020 if (error) { 1021 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1022 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1023 printf("ste%d: couldn't set up irq\n", unit); 1024 goto fail; 1025 } 1026 1027 callout_handle_init(&sc->ste_stat_ch); 1028 1029 /* Reset the adapter. */ 1030 ste_reset(sc); 1031 1032 /* 1033 * Get station address from the EEPROM. 1034 */ 1035 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1036 STE_EEADDR_NODE0, 3, 0)) { 1037 printf("ste%d: failed to read station address\n", unit); 1038 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1039 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1040 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1041 error = ENXIO;; 1042 goto fail; 1043 } 1044 1045 /* 1046 * A Sundance chip was detected. Inform the world. 1047 */ 1048 printf("ste%d: Ethernet address: %6D\n", unit, 1049 sc->arpcom.ac_enaddr, ":"); 1050 1051 sc->ste_unit = unit; 1052 1053 /* Allocate the descriptor queues. */ 1054 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1055 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1056 1057 if (sc->ste_ldata == NULL) { 1058 printf("ste%d: no memory for list buffers!\n", unit); 1059 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1060 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1061 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1062 error = ENXIO; 1063 goto fail; 1064 } 1065 1066 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1067 1068 /* Do MII setup. */ 1069 if (mii_phy_probe(dev, &sc->ste_miibus, 1070 ste_ifmedia_upd, ste_ifmedia_sts)) { 1071 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1072 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1073 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1074 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1075 free(sc->ste_ldata, M_DEVBUF); 1076 error = ENXIO; 1077 goto fail; 1078 } 1079 1080 ifp = &sc->arpcom.ac_if; 1081 ifp->if_softc = sc; 1082 ifp->if_unit = unit; 1083 ifp->if_name = "ste"; 1084 ifp->if_mtu = ETHERMTU; 1085 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1086 ifp->if_ioctl = ste_ioctl; 1087 ifp->if_output = ether_output; 1088 ifp->if_start = ste_start; 1089 ifp->if_watchdog = ste_watchdog; 1090 ifp->if_init = ste_init; 1091 ifp->if_baudrate = 10000000; 1092 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1093 1094 /* 1095 * Call MI attach routines. 1096 */ 1097 1098 if_attach(ifp); 1099 ether_ifattach(ifp); 1100 1101 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1102 1103fail: 1104 splx(s); 1105 return(error); 1106} 1107 1108static int ste_detach(dev) 1109 device_t dev; 1110{ 1111 struct ste_softc *sc; 1112 struct ifnet *ifp; 1113 int s; 1114 1115 s = splimp(); 1116 1117 sc = device_get_softc(dev); 1118 ifp = &sc->arpcom.ac_if; 1119 1120 ste_stop(sc); 1121 if_detach(ifp); 1122 1123 bus_generic_detach(dev); 1124 device_delete_child(dev, sc->ste_miibus); 1125 1126 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1127 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1128 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1129 1130 free(sc->ste_ldata, M_DEVBUF); 1131 1132 splx(s); 1133 1134 return(0); 1135} 1136 1137static int ste_newbuf(sc, c, m) 1138 struct ste_softc *sc; 1139 struct ste_chain_onefrag *c; 1140 struct mbuf *m; 1141{ 1142 struct mbuf *m_new = NULL; 1143 1144 if (m == NULL) { 1145 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1146 if (m_new == NULL) { 1147 printf("ste%d: no memory for rx list -- " 1148 "packet dropped\n", sc->ste_unit); 1149 return(ENOBUFS); 1150 } 1151 MCLGET(m_new, M_DONTWAIT); 1152 if (!(m_new->m_flags & M_EXT)) { 1153 printf("ste%d: no memory for rx list -- " 1154 "packet dropped\n", sc->ste_unit); 1155 m_freem(m_new); 1156 return(ENOBUFS); 1157 } 1158 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1159 } else { 1160 m_new = m; 1161 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1162 m_new->m_data = m_new->m_ext.ext_buf; 1163 } 1164 1165 m_adj(m_new, ETHER_ALIGN); 1166 1167 c->ste_mbuf = m_new; 1168 c->ste_ptr->ste_status = 0; 1169 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1170 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; 1171 1172 return(0); 1173} 1174 1175static int ste_init_rx_list(sc) 1176 struct ste_softc *sc; 1177{ 1178 struct ste_chain_data *cd; 1179 struct ste_list_data *ld; 1180 int i; 1181 1182 cd = &sc->ste_cdata; 1183 ld = sc->ste_ldata; 1184 1185 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1186 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1187 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1188 return(ENOBUFS); 1189 if (i == (STE_RX_LIST_CNT - 1)) { 1190 cd->ste_rx_chain[i].ste_next = 1191 &cd->ste_rx_chain[0]; 1192 ld->ste_rx_list[i].ste_next = 1193 vtophys(&ld->ste_rx_list[0]); 1194 } else { 1195 cd->ste_rx_chain[i].ste_next = 1196 &cd->ste_rx_chain[i + 1]; 1197 ld->ste_rx_list[i].ste_next = 1198 vtophys(&ld->ste_rx_list[i + 1]); 1199 } 1200 1201 } 1202 1203 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1204 1205 return(0); 1206} 1207 1208static void ste_init_tx_list(sc) 1209 struct ste_softc *sc; 1210{ 1211 struct ste_chain_data *cd; 1212 struct ste_list_data *ld; 1213 int i; 1214 1215 cd = &sc->ste_cdata; 1216 ld = sc->ste_ldata; 1217 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1218 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1219 if (i == (STE_TX_LIST_CNT - 1)) 1220 cd->ste_tx_chain[i].ste_next = NULL; 1221 else 1222 cd->ste_tx_chain[i].ste_next = 1223 &cd->ste_tx_chain[i + 1]; 1224 } 1225 1226 cd->ste_tx_free = &cd->ste_tx_chain[0]; 1227 cd->ste_tx_tail = cd->ste_tx_head = NULL; 1228 1229 return; 1230} 1231 1232static void ste_init(xsc) 1233 void *xsc; 1234{ 1235 struct ste_softc *sc; 1236 int i, s; 1237 struct ifnet *ifp; 1238 struct mii_data *mii; 1239 1240 s = splimp(); 1241 1242 sc = xsc; 1243 ifp = &sc->arpcom.ac_if; 1244 mii = device_get_softc(sc->ste_miibus); 1245 1246 ste_stop(sc); 1247 1248 /* Init our MAC address */ 1249 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1250 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1251 } 1252 1253 /* Init RX list */ 1254 if (ste_init_rx_list(sc) == ENOBUFS) { 1255 printf("ste%d: initialization failed: no " 1256 "memory for RX buffers\n", sc->ste_unit); 1257 ste_stop(sc); 1258 splx(s); 1259 return; 1260 } 1261 1262 /* Init TX descriptors */ 1263 ste_init_tx_list(sc); 1264 1265 /* Set the TX freethresh value */ 1266 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1267 1268 /* Set the TX start threshold for best performance. */ 1269 sc->ste_tx_thresh = STE_MIN_FRAMELEN; 1270 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1271 1272 /* Set the TX reclaim threshold. */ 1273 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1274 1275 /* Set up the RX filter. */ 1276 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1277 1278 /* If we want promiscuous mode, set the allframes bit. */ 1279 if (ifp->if_flags & IFF_PROMISC) { 1280 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1281 } else { 1282 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1283 } 1284 1285 /* Set capture broadcast bit to accept broadcast frames. */ 1286 if (ifp->if_flags & IFF_BROADCAST) { 1287 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1288 } else { 1289 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1290 } 1291 1292 ste_setmulti(sc); 1293 1294 /* Load the address of the RX list. */ 1295 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1296 ste_wait(sc); 1297 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1298 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1299 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1300 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1301 1302 /* Enable receiver and transmitter */ 1303 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1304 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1305 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1306 1307 /* Enable stats counters. */ 1308 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1309 1310 /* Enable interrupts. */ 1311 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1312 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1313 1314 mii_mediachg(mii); 1315 1316 ifp->if_flags |= IFF_RUNNING; 1317 ifp->if_flags &= ~IFF_OACTIVE; 1318 1319 splx(s); 1320 1321 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1322 1323 return; 1324} 1325 1326static void ste_stop(sc) 1327 struct ste_softc *sc; 1328{ 1329 int i; 1330 struct ifnet *ifp; 1331 1332 ifp = &sc->arpcom.ac_if; 1333 1334 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1335 1336 CSR_WRITE_2(sc, STE_IMR, 0); 1337 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1338 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1339 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1340 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1341 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1342 ste_wait(sc); 1343 1344 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1345 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1346 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1347 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1348 } 1349 } 1350 1351 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1352 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1353 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1354 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1355 } 1356 } 1357 1358 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1359 1360 return; 1361} 1362 1363static void ste_reset(sc) 1364 struct ste_softc *sc; 1365{ 1366 int i; 1367 1368 STE_SETBIT4(sc, STE_ASICCTL, 1369 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1370 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1371 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1372 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1373 STE_ASICCTL_EXTRESET_RESET); 1374 1375 DELAY(100000); 1376 1377 for (i = 0; i < STE_TIMEOUT; i++) { 1378 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1379 break; 1380 } 1381 1382 if (i == STE_TIMEOUT) 1383 printf("ste%d: global reset never completed\n", sc->ste_unit); 1384 1385#ifdef foo 1386 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_RX_RESET); 1387 for (i = 0; i < STE_TIMEOUT; i++) { 1388 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RX_RESET)) 1389 break; 1390 } 1391 1392 if (i == STE_TIMEOUT) 1393 printf("ste%d: RX reset never completed\n", sc->ste_unit); 1394 1395 DELAY(100000); 1396 1397 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_TX_RESET); 1398 for (i = 0; i < STE_TIMEOUT; i++) { 1399 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_TX_RESET)) 1400 break; 1401 } 1402 1403 if (i == STE_TIMEOUT) 1404 printf("ste%d: TX reset never completed\n", sc->ste_unit); 1405 1406 DELAY(100000); 1407#endif 1408 1409 return; 1410} 1411 1412static int ste_ioctl(ifp, command, data) 1413 struct ifnet *ifp; 1414 u_long command; 1415 caddr_t data; 1416{ 1417 struct ste_softc *sc; 1418 struct ifreq *ifr; 1419 struct mii_data *mii; 1420 int error = 0, s; 1421 1422 s = splimp(); 1423 1424 sc = ifp->if_softc; 1425 ifr = (struct ifreq *)data; 1426 1427 switch(command) { 1428 case SIOCSIFADDR: 1429 case SIOCGIFADDR: 1430 case SIOCSIFMTU: 1431 error = ether_ioctl(ifp, command, data); 1432 break; 1433 case SIOCSIFFLAGS: 1434 if (ifp->if_flags & IFF_UP) { 1435 ste_init(sc); 1436 } else { 1437 if (ifp->if_flags & IFF_RUNNING) 1438 ste_stop(sc); 1439 } 1440 error = 0; 1441 break; 1442 case SIOCADDMULTI: 1443 case SIOCDELMULTI: 1444 ste_setmulti(sc); 1445 error = 0; 1446 break; 1447 case SIOCGIFMEDIA: 1448 case SIOCSIFMEDIA: 1449 mii = device_get_softc(sc->ste_miibus); 1450 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1451 break; 1452 default: 1453 error = EINVAL; 1454 break; 1455 } 1456 1457 splx(s); 1458 1459 return(error); 1460} 1461 1462static int ste_encap(sc, c, m_head) 1463 struct ste_softc *sc; 1464 struct ste_chain *c; 1465 struct mbuf *m_head; 1466{ 1467 int frag = 0; 1468 struct ste_frag *f = NULL; 1469 int total_len; 1470 struct mbuf *m; 1471 1472 m = m_head; 1473 total_len = 0; 1474 1475 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1476 if (m->m_len != 0) { 1477 if (frag == STE_MAXFRAGS) 1478 break; 1479 total_len += m->m_len; 1480 f = &c->ste_ptr->ste_frags[frag]; 1481 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1482 f->ste_len = m->m_len; 1483 frag++; 1484 } 1485 } 1486 1487 if (m != NULL) { 1488 struct mbuf *m_new = NULL; 1489 1490 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1491 if (m_new == NULL) { 1492 printf("ste%d: no memory for " 1493 "tx list", sc->ste_unit); 1494 return(1); 1495 } 1496 if (m_head->m_pkthdr.len > MHLEN) { 1497 MCLGET(m_new, M_DONTWAIT); 1498 if (!(m_new->m_flags & M_EXT)) { 1499 m_freem(m_new); 1500 printf("ste%d: no memory for " 1501 "tx list", sc->ste_unit); 1502 return(1); 1503 } 1504 } 1505 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1506 mtod(m_new, caddr_t)); 1507 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1508 m_freem(m_head); 1509 m_head = m_new; 1510 f = &c->ste_ptr->ste_frags[0]; 1511 f->ste_addr = vtophys(mtod(m_new, caddr_t)); 1512 f->ste_len = total_len = m_new->m_len; 1513 frag = 1; 1514 } 1515 1516 c->ste_mbuf = m_head; 1517 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1518 c->ste_ptr->ste_ctl = total_len; 1519 c->ste_ptr->ste_next = 0; 1520 1521 return(0); 1522} 1523 1524static void ste_start(ifp) 1525 struct ifnet *ifp; 1526{ 1527 struct ste_softc *sc; 1528 struct mbuf *m_head = NULL; 1529 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1530 1531 sc = ifp->if_softc; 1532 1533 if (sc->ste_cdata.ste_tx_free == NULL) { 1534 ifp->if_flags |= IFF_OACTIVE; 1535 return; 1536 } 1537 1538 start_tx = sc->ste_cdata.ste_tx_free; 1539 1540 while(sc->ste_cdata.ste_tx_free != NULL) { 1541 IF_DEQUEUE(&ifp->if_snd, m_head); 1542 if (m_head == NULL) 1543 break; 1544 1545 cur_tx = sc->ste_cdata.ste_tx_free; 1546 sc->ste_cdata.ste_tx_free = cur_tx->ste_next; 1547 1548 cur_tx->ste_next = NULL; 1549 1550 ste_encap(sc, cur_tx, m_head); 1551 1552 if (prev != NULL) { 1553 prev->ste_next = cur_tx; 1554 prev->ste_ptr->ste_next = vtophys(cur_tx->ste_ptr); 1555 } 1556 prev = cur_tx; 1557 1558 /* 1559 * If there's a BPF listener, bounce a copt of this frame 1560 * to him. 1561 */ 1562 if (ifp->if_bpf) 1563 bpf_mtap(ifp, cur_tx->ste_mbuf); 1564 } 1565 1566 if (cur_tx == NULL) 1567 return; 1568 1569 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR; 1570 1571 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1572 ste_wait(sc); 1573 1574 if (sc->ste_cdata.ste_tx_head != NULL) { 1575 sc->ste_cdata.ste_tx_tail->ste_next = start_tx; 1576 sc->ste_cdata.ste_tx_tail->ste_ptr->ste_next = 1577 vtophys(start_tx->ste_ptr); 1578 sc->ste_cdata.ste_tx_tail->ste_ptr->ste_ctl &= 1579 ~STE_TXCTL_DMAINTR; 1580 sc->ste_cdata.ste_tx_tail = cur_tx; 1581 } else { 1582 sc->ste_cdata.ste_tx_head = start_tx; 1583 sc->ste_cdata.ste_tx_tail = cur_tx; 1584 } 1585 1586 if (!CSR_READ_4(sc, STE_TX_DMALIST_PTR)) 1587 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1588 vtophys(start_tx->ste_ptr)); 1589 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1590 1591 ifp->if_timer = 5; 1592 1593 return; 1594} 1595 1596static void ste_watchdog(ifp) 1597 struct ifnet *ifp; 1598{ 1599 struct ste_softc *sc; 1600 1601 sc = ifp->if_softc; 1602 1603 ifp->if_oerrors++; 1604 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1605 1606#ifdef foo 1607 if (sc->ste_pinfo != NULL) { 1608 if (!(ste_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1609 printf("ste%d: no carrier - transceiver " 1610 "cable problem?\n", sc->ste_unit); 1611 } 1612#endif 1613 1614 ste_txeoc(sc); 1615 ste_txeof(sc); 1616 ste_rxeof(sc); 1617 ste_reset(sc); 1618 ste_init(sc); 1619 1620 if (ifp->if_snd.ifq_head != NULL) 1621 ste_start(ifp); 1622 1623 return; 1624} 1625 1626static void ste_shutdown(dev) 1627 device_t dev; 1628{ 1629 struct ste_softc *sc; 1630 1631 sc = device_get_softc(dev); 1632 1633 ste_stop(sc); 1634 1635 return; 1636} 1637