if_ste.c revision 51473
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_ste.c 51473 1999-09-20 19:06:45Z wpaul $ 33 */ 34 35 36#include "bpf.h" 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/sockio.h> 41#include <sys/mbuf.h> 42#include <sys/malloc.h> 43#include <sys/kernel.h> 44#include <sys/socket.h> 45 46#include <net/if.h> 47#include <net/if_arp.h> 48#include <net/ethernet.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51 52#if NBPF > 0 53#include <net/bpf.h> 54#endif 55 56#include "opt_bdg.h" 57#ifdef BRIDGE 58#include <net/bridge.h> 59#endif 60 61#include <vm/vm.h> /* for vtophys */ 62#include <vm/pmap.h> /* for vtophys */ 63#include <machine/clock.h> /* for DELAY */ 64#include <machine/bus_memio.h> 65#include <machine/bus_pio.h> 66#include <machine/bus.h> 67#include <machine/resource.h> 68#include <sys/bus.h> 69#include <sys/rman.h> 70 71#include <dev/mii/mii.h> 72#include <dev/mii/miivar.h> 73 74#include <pci/pcireg.h> 75#include <pci/pcivar.h> 76 77/* "controller miibus0" required. See GENERIC if you get errors here. */ 78#include "miibus_if.h" 79 80#define STE_USEIOSPACE 81 82#include <pci/if_stereg.h> 83 84#if !defined(lint) 85static const char rcsid[] = 86 "$FreeBSD: head/sys/pci/if_ste.c 51473 1999-09-20 19:06:45Z wpaul $"; 87#endif 88 89/* 90 * Various supported device vendors/types and their names. 91 */ 92static struct ste_type ste_devs[] = { 93 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 94 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 95 { 0, 0, NULL } 96}; 97 98static int ste_probe __P((device_t)); 99static int ste_attach __P((device_t)); 100static int ste_detach __P((device_t)); 101static void ste_init __P((void *)); 102static void ste_intr __P((void *)); 103static void ste_rxeof __P((struct ste_softc *)); 104static void ste_txeoc __P((struct ste_softc *)); 105static void ste_txeof __P((struct ste_softc *)); 106static void ste_stats_update __P((void *)); 107static void ste_stop __P((struct ste_softc *)); 108static void ste_reset __P((struct ste_softc *)); 109static int ste_ioctl __P((struct ifnet *, u_long, caddr_t)); 110static int ste_encap __P((struct ste_softc *, struct ste_chain *, 111 struct mbuf *)); 112static void ste_start __P((struct ifnet *)); 113static void ste_watchdog __P((struct ifnet *)); 114static void ste_shutdown __P((device_t)); 115static int ste_newbuf __P((struct ste_softc *, 116 struct ste_chain_onefrag *, 117 struct mbuf *)); 118static int ste_ifmedia_upd __P((struct ifnet *)); 119static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 120 121static void ste_mii_sync __P((struct ste_softc *)); 122static void ste_mii_send __P((struct ste_softc *, u_int32_t, int)); 123static int ste_mii_readreg __P((struct ste_softc *, 124 struct ste_mii_frame *)); 125static int ste_mii_writereg __P((struct ste_softc *, 126 struct ste_mii_frame *)); 127static int ste_miibus_readreg __P((device_t, int, int)); 128static int ste_miibus_writereg __P((device_t, int, int, int)); 129static void ste_miibus_statchg __P((device_t)); 130 131static int ste_eeprom_wait __P((struct ste_softc *)); 132static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int, 133 int, int)); 134static void ste_wait __P((struct ste_softc *)); 135static u_int8_t ste_calchash __P((caddr_t)); 136static void ste_setmulti __P((struct ste_softc *)); 137static int ste_init_rx_list __P((struct ste_softc *)); 138static void ste_init_tx_list __P((struct ste_softc *)); 139 140#ifdef STE_USEIOSPACE 141#define STE_RES SYS_RES_IOPORT 142#define STE_RID STE_PCI_LOIO 143#else 144#define STE_RES SYS_RES_MEMORY 145#define STE_RID STE_PCI_LOMEM 146#endif 147 148static device_method_t ste_methods[] = { 149 /* Device interface */ 150 DEVMETHOD(device_probe, ste_probe), 151 DEVMETHOD(device_attach, ste_attach), 152 DEVMETHOD(device_detach, ste_detach), 153 DEVMETHOD(device_shutdown, ste_shutdown), 154 155 /* bus interface */ 156 DEVMETHOD(bus_print_child, bus_generic_print_child), 157 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 158 159 /* MII interface */ 160 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 161 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 162 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 163 164 { 0, 0 } 165}; 166 167static driver_t ste_driver = { 168 "ste", 169 ste_methods, 170 sizeof(struct ste_softc) 171}; 172 173static devclass_t ste_devclass; 174 175DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 176DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 177 178#define STE_SETBIT4(sc, reg, x) \ 179 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 180 181#define STE_CLRBIT4(sc, reg, x) \ 182 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 183 184#define STE_SETBIT2(sc, reg, x) \ 185 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 186 187#define STE_CLRBIT2(sc, reg, x) \ 188 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 189 190#define STE_SETBIT1(sc, reg, x) \ 191 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 192 193#define STE_CLRBIT1(sc, reg, x) \ 194 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 195 196 197#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 198#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 199 200/* 201 * Sync the PHYs by setting data bit and strobing the clock 32 times. 202 */ 203static void ste_mii_sync(sc) 204 struct ste_softc *sc; 205{ 206 register int i; 207 208 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 209 210 for (i = 0; i < 32; i++) { 211 MII_SET(STE_PHYCTL_MCLK); 212 DELAY(1); 213 MII_CLR(STE_PHYCTL_MCLK); 214 DELAY(1); 215 } 216 217 return; 218} 219 220/* 221 * Clock a series of bits through the MII. 222 */ 223static void ste_mii_send(sc, bits, cnt) 224 struct ste_softc *sc; 225 u_int32_t bits; 226 int cnt; 227{ 228 int i; 229 230 MII_CLR(STE_PHYCTL_MCLK); 231 232 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 233 if (bits & i) { 234 MII_SET(STE_PHYCTL_MDATA); 235 } else { 236 MII_CLR(STE_PHYCTL_MDATA); 237 } 238 DELAY(1); 239 MII_CLR(STE_PHYCTL_MCLK); 240 DELAY(1); 241 MII_SET(STE_PHYCTL_MCLK); 242 } 243} 244 245/* 246 * Read an PHY register through the MII. 247 */ 248static int ste_mii_readreg(sc, frame) 249 struct ste_softc *sc; 250 struct ste_mii_frame *frame; 251 252{ 253 int i, ack, s; 254 255 s = splimp(); 256 257 /* 258 * Set up frame for RX. 259 */ 260 frame->mii_stdelim = STE_MII_STARTDELIM; 261 frame->mii_opcode = STE_MII_READOP; 262 frame->mii_turnaround = 0; 263 frame->mii_data = 0; 264 265 CSR_WRITE_2(sc, STE_PHYCTL, 0); 266 /* 267 * Turn on data xmit. 268 */ 269 MII_SET(STE_PHYCTL_MDIR); 270 271 ste_mii_sync(sc); 272 273 /* 274 * Send command/address info. 275 */ 276 ste_mii_send(sc, frame->mii_stdelim, 2); 277 ste_mii_send(sc, frame->mii_opcode, 2); 278 ste_mii_send(sc, frame->mii_phyaddr, 5); 279 ste_mii_send(sc, frame->mii_regaddr, 5); 280 281 /* Turn off xmit. */ 282 MII_CLR(STE_PHYCTL_MDIR); 283 284 /* Idle bit */ 285 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 286 DELAY(1); 287 MII_SET(STE_PHYCTL_MCLK); 288 DELAY(1); 289 290 /* Check for ack */ 291 MII_CLR(STE_PHYCTL_MCLK); 292 DELAY(1); 293 MII_SET(STE_PHYCTL_MCLK); 294 DELAY(1); 295 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 296 297 /* 298 * Now try reading data bits. If the ack failed, we still 299 * need to clock through 16 cycles to keep the PHY(s) in sync. 300 */ 301 if (ack) { 302 for(i = 0; i < 16; i++) { 303 MII_CLR(STE_PHYCTL_MCLK); 304 DELAY(1); 305 MII_SET(STE_PHYCTL_MCLK); 306 DELAY(1); 307 } 308 goto fail; 309 } 310 311 for (i = 0x8000; i; i >>= 1) { 312 MII_CLR(STE_PHYCTL_MCLK); 313 DELAY(1); 314 if (!ack) { 315 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 316 frame->mii_data |= i; 317 DELAY(1); 318 } 319 MII_SET(STE_PHYCTL_MCLK); 320 DELAY(1); 321 } 322 323fail: 324 325 MII_CLR(STE_PHYCTL_MCLK); 326 DELAY(1); 327 MII_SET(STE_PHYCTL_MCLK); 328 DELAY(1); 329 330 splx(s); 331 332 if (ack) 333 return(1); 334 return(0); 335} 336 337/* 338 * Write to a PHY register through the MII. 339 */ 340static int ste_mii_writereg(sc, frame) 341 struct ste_softc *sc; 342 struct ste_mii_frame *frame; 343 344{ 345 int s; 346 347 s = splimp(); 348 /* 349 * Set up frame for TX. 350 */ 351 352 frame->mii_stdelim = STE_MII_STARTDELIM; 353 frame->mii_opcode = STE_MII_WRITEOP; 354 frame->mii_turnaround = STE_MII_TURNAROUND; 355 356 /* 357 * Turn on data output. 358 */ 359 MII_SET(STE_PHYCTL_MDIR); 360 361 ste_mii_sync(sc); 362 363 ste_mii_send(sc, frame->mii_stdelim, 2); 364 ste_mii_send(sc, frame->mii_opcode, 2); 365 ste_mii_send(sc, frame->mii_phyaddr, 5); 366 ste_mii_send(sc, frame->mii_regaddr, 5); 367 ste_mii_send(sc, frame->mii_turnaround, 2); 368 ste_mii_send(sc, frame->mii_data, 16); 369 370 /* Idle bit. */ 371 MII_SET(STE_PHYCTL_MCLK); 372 DELAY(1); 373 MII_CLR(STE_PHYCTL_MCLK); 374 DELAY(1); 375 376 /* 377 * Turn off xmit. 378 */ 379 MII_CLR(STE_PHYCTL_MDIR); 380 381 splx(s); 382 383 return(0); 384} 385 386static int ste_miibus_readreg(dev, phy, reg) 387 device_t dev; 388 int phy, reg; 389{ 390 struct ste_softc *sc; 391 struct ste_mii_frame frame; 392 393 sc = device_get_softc(dev); 394 395 bzero((char *)&frame, sizeof(frame)); 396 397 frame.mii_phyaddr = phy; 398 frame.mii_regaddr = reg; 399 ste_mii_readreg(sc, &frame); 400 401 return(frame.mii_data); 402} 403 404static int ste_miibus_writereg(dev, phy, reg, data) 405 device_t dev; 406 int phy, reg, data; 407{ 408 struct ste_softc *sc; 409 struct ste_mii_frame frame; 410 411 sc = device_get_softc(dev); 412 bzero((char *)&frame, sizeof(frame)); 413 414 frame.mii_phyaddr = phy; 415 frame.mii_regaddr = reg; 416 frame.mii_data = data; 417 418 ste_mii_writereg(sc, &frame); 419 420 return(0); 421} 422 423static void ste_miibus_statchg(dev) 424 device_t dev; 425{ 426 struct ste_softc *sc; 427 struct mii_data *mii; 428 429 sc = device_get_softc(dev); 430 mii = device_get_softc(sc->ste_miibus); 431 432 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 433 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 434 } else { 435 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 436 } 437 438 return; 439} 440 441static int ste_ifmedia_upd(ifp) 442 struct ifnet *ifp; 443{ 444 struct ste_softc *sc; 445 struct mii_data *mii; 446 447 sc = ifp->if_softc; 448 mii = device_get_softc(sc->ste_miibus); 449 mii_mediachg(mii); 450 451 return(0); 452} 453 454static void ste_ifmedia_sts(ifp, ifmr) 455 struct ifnet *ifp; 456 struct ifmediareq *ifmr; 457{ 458 struct ste_softc *sc; 459 struct mii_data *mii; 460 461 sc = ifp->if_softc; 462 mii = device_get_softc(sc->ste_miibus); 463 464 mii_pollstat(mii); 465 ifmr->ifm_active = mii->mii_media_active; 466 ifmr->ifm_status = mii->mii_media_status; 467 468 return; 469} 470 471static void ste_wait(sc) 472 struct ste_softc *sc; 473{ 474 register int i; 475 476 for (i = 0; i < STE_TIMEOUT; i++) { 477 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 478 break; 479 } 480 481 if (i == STE_TIMEOUT) 482 printf("ste%d: command never completed!\n", sc->ste_unit); 483 484 return; 485} 486 487/* 488 * The EEPROM is slow: give it time to come ready after issuing 489 * it a command. 490 */ 491static int ste_eeprom_wait(sc) 492 struct ste_softc *sc; 493{ 494 int i; 495 496 DELAY(1000); 497 498 for (i = 0; i < 100; i++) { 499 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 500 DELAY(1000); 501 else 502 break; 503 } 504 505 if (i == 100) { 506 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 507 return(1); 508 } 509 510 return(0); 511} 512 513/* 514 * Read a sequence of words from the EEPROM. Note that ethernet address 515 * data is stored in the EEPROM in network byte order. 516 */ 517static int ste_read_eeprom(sc, dest, off, cnt, swap) 518 struct ste_softc *sc; 519 caddr_t dest; 520 int off; 521 int cnt; 522 int swap; 523{ 524 int err = 0, i; 525 u_int16_t word = 0, *ptr; 526 527 if (ste_eeprom_wait(sc)) 528 return(1); 529 530 for (i = 0; i < cnt; i++) { 531 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 532 err = ste_eeprom_wait(sc); 533 if (err) 534 break; 535 word = CSR_READ_2(sc, STE_EEPROM_DATA); 536 ptr = (u_int16_t *)(dest + (i * 2)); 537 if (swap) 538 *ptr = ntohs(word); 539 else 540 *ptr = word; 541 } 542 543 return(err ? 1 : 0); 544} 545 546static u_int8_t ste_calchash(addr) 547 caddr_t addr; 548{ 549 550 u_int32_t crc, carry; 551 int i, j; 552 u_int8_t c; 553 554 /* Compute CRC for the address value. */ 555 crc = 0xFFFFFFFF; /* initial value */ 556 557 for (i = 0; i < 6; i++) { 558 c = *(addr + i); 559 for (j = 0; j < 8; j++) { 560 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 561 crc <<= 1; 562 c >>= 1; 563 if (carry) 564 crc = (crc ^ 0x04c11db6) | carry; 565 } 566 } 567 568 /* return the filter bit position */ 569 return(crc & 0x0000003F); 570} 571 572static void ste_setmulti(sc) 573 struct ste_softc *sc; 574{ 575 struct ifnet *ifp; 576 int h = 0; 577 u_int32_t hashes[2] = { 0, 0 }; 578 struct ifmultiaddr *ifma; 579 580 ifp = &sc->arpcom.ac_if; 581 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 582 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 583 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 584 return; 585 } 586 587 /* first, zot all the existing hash bits */ 588 CSR_WRITE_4(sc, STE_MAR0, 0); 589 CSR_WRITE_4(sc, STE_MAR1, 0); 590 591 /* now program new ones */ 592 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 593 ifma = ifma->ifma_link.le_next) { 594 if (ifma->ifma_addr->sa_family != AF_LINK) 595 continue; 596 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 597 if (h < 32) 598 hashes[0] |= (1 << h); 599 else 600 hashes[1] |= (1 << (h - 32)); 601 } 602 603 CSR_WRITE_4(sc, STE_MAR0, hashes[0]); 604 CSR_WRITE_4(sc, STE_MAR1, hashes[1]); 605 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 606 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 607 608 return; 609} 610 611static void ste_intr(xsc) 612 void *xsc; 613{ 614 struct ste_softc *sc; 615 struct ifnet *ifp; 616 u_int16_t status; 617 618 sc = xsc; 619 ifp = &sc->arpcom.ac_if; 620 621 /* See if this is really our interrupt. */ 622 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 623 return; 624 625 for (;;) { 626 status = CSR_READ_2(sc, STE_ISR_ACK); 627 628 if (!(status & STE_INTRS)) 629 break; 630 631 if (status & STE_ISR_RX_DMADONE) 632 ste_rxeof(sc); 633 634 if (status & STE_ISR_TX_DMADONE) 635 ste_txeof(sc); 636 637 if (status & STE_ISR_TX_DONE) 638 ste_txeoc(sc); 639 640 if (status & STE_ISR_STATS_OFLOW) { 641 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 642 ste_stats_update(sc); 643 } 644 645 if (status & STE_ISR_HOSTERR) { 646 ste_reset(sc); 647 ste_init(sc); 648 } 649 } 650 651 /* Re-enable interrupts */ 652 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 653 654 if (ifp->if_snd.ifq_head != NULL) 655 ste_start(ifp); 656 657 return; 658} 659 660/* 661 * A frame has been uploaded: pass the resulting mbuf chain up to 662 * the higher level protocols. 663 */ 664static void ste_rxeof(sc) 665 struct ste_softc *sc; 666{ 667 struct ether_header *eh; 668 struct mbuf *m; 669 struct ifnet *ifp; 670 struct ste_chain_onefrag *cur_rx; 671 int total_len = 0; 672 u_int32_t rxstat; 673 674 ifp = &sc->arpcom.ac_if; 675 676again: 677 678 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) { 679 cur_rx = sc->ste_cdata.ste_rx_head; 680 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 681 682 /* 683 * If an error occurs, update stats, clear the 684 * status word and leave the mbuf cluster in place: 685 * it should simply get re-used next time this descriptor 686 * comes up in the ring. 687 */ 688 if (rxstat & STE_RXSTAT_FRAME_ERR) { 689 ifp->if_ierrors++; 690 cur_rx->ste_ptr->ste_status = 0; 691 continue; 692 } 693 694 /* 695 * If there error bit was not set, the upload complete 696 * bit should be set which means we have a valid packet. 697 * If not, something truly strange has happened. 698 */ 699 if (!(rxstat & STE_RXSTAT_DMADONE)) { 700 printf("ste%d: bad receive status -- packet dropped", 701 sc->ste_unit); 702 ifp->if_ierrors++; 703 cur_rx->ste_ptr->ste_status = 0; 704 continue; 705 } 706 707 /* No errors; receive the packet. */ 708 m = cur_rx->ste_mbuf; 709 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 710 711 /* 712 * Try to conjure up a new mbuf cluster. If that 713 * fails, it means we have an out of memory condition and 714 * should leave the buffer in place and continue. This will 715 * result in a lost packet, but there's little else we 716 * can do in this situation. 717 */ 718 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 719 ifp->if_ierrors++; 720 cur_rx->ste_ptr->ste_status = 0; 721 continue; 722 } 723 724 ifp->if_ipackets++; 725 eh = mtod(m, struct ether_header *); 726 m->m_pkthdr.rcvif = ifp; 727 m->m_pkthdr.len = m->m_len = total_len; 728 729#if NBPF > 0 730 /* Handle BPF listeners. Let the BPF user see the packet. */ 731 if (ifp->if_bpf) 732 bpf_mtap(ifp, m); 733#endif 734 735#ifdef BRIDGE 736 if (do_bridge) { 737 struct ifnet *bdg_ifp ; 738 bdg_ifp = bridge_in(m); 739 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 740 bdg_forward(&m, bdg_ifp); 741 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 742 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 743 m_freem(m); 744 continue; 745 } 746 } 747#endif 748 749#if NBPF > 0 750 /* 751 * Don't pass packet up to the ether_input() layer unless it's 752 * a broadcast packet, multicast packet, matches our ethernet 753 * address or the interface is in promiscuous mode. 754 */ 755 if (ifp->if_bpf) { 756 if (ifp->if_flags & IFF_PROMISC && 757 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 758 ETHER_ADDR_LEN) && (eh->ether_dhost[0] & 1) == 0)){ 759 m_freem(m); 760 continue; 761 } 762 } 763#endif 764 765 /* Remove header from mbuf and pass it on. */ 766 m_adj(m, sizeof(struct ether_header)); 767 ether_input(ifp, eh, m); 768 } 769 770 /* 771 * Handle the 'end of channel' condition. When the upload 772 * engine hits the end of the RX ring, it will stall. This 773 * is our cue to flush the RX ring, reload the uplist pointer 774 * register and unstall the engine. 775 * XXX This is actually a little goofy. With the ThunderLAN 776 * chip, you get an interrupt when the receiver hits the end 777 * of the receive ring, which tells you exactly when you 778 * you need to reload the ring pointer. Here we have to 779 * fake it. I'm mad at myself for not being clever enough 780 * to avoid the use of a goto here. 781 */ 782 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 || 783 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) { 784 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 785 ste_wait(sc); 786 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 787 vtophys(&sc->ste_ldata->ste_rx_list[0])); 788 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0]; 789 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 790 goto again; 791 } 792 793 return; 794} 795 796static void ste_txeoc(sc) 797 struct ste_softc *sc; 798{ 799 u_int8_t txstat; 800 struct ifnet *ifp; 801 802 ifp = &sc->arpcom.ac_if; 803 804 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 805 STE_TXSTATUS_TXDONE) { 806 if (txstat & STE_TXSTATUS_UNDERRUN || 807 txstat & STE_TXSTATUS_EXCESSCOLLS || 808 txstat & STE_TXSTATUS_RECLAIMERR) { 809 ifp->if_oerrors++; 810 printf("ste%d: transmission error: %x\n", 811 sc->ste_unit, txstat); 812 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_TX_RESET); 813 814 if (sc->ste_cdata.ste_tx_head != NULL) 815 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 816 vtophys(sc->ste_cdata.ste_tx_head->ste_ptr)); 817 if (txstat & STE_TXSTATUS_UNDERRUN && 818 sc->ste_tx_thresh < STE_PACKET_SIZE) { 819 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 820 printf("ste%d: tx underrun, increasing tx" 821 " start threshold to %d bytes\n", 822 sc->ste_unit, sc->ste_tx_thresh); 823 } 824 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 825 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 826 (STE_PACKET_SIZE >> 4)); 827 } 828 ste_init(sc); 829 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 830 } 831 832 return; 833} 834 835static void ste_txeof(sc) 836 struct ste_softc *sc; 837{ 838 struct ste_chain *cur_tx; 839 struct ifnet *ifp; 840 841 ifp = &sc->arpcom.ac_if; 842 843 /* Clear the timeout timer. */ 844 ifp->if_timer = 0; 845 846 while(sc->ste_cdata.ste_tx_head != NULL) { 847 cur_tx = sc->ste_cdata.ste_tx_head; 848 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 849 break; 850 sc->ste_cdata.ste_tx_head = cur_tx->ste_next; 851 852 m_freem(cur_tx->ste_mbuf); 853 cur_tx->ste_mbuf = NULL; 854 ifp->if_opackets++; 855 856 cur_tx->ste_next = sc->ste_cdata.ste_tx_free; 857 sc->ste_cdata.ste_tx_free = cur_tx; 858 } 859 860 if (sc->ste_cdata.ste_tx_head == NULL) { 861 ifp->if_flags &= ~IFF_OACTIVE; 862 sc->ste_cdata.ste_tx_tail = NULL; 863 } else { 864 if (CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_TXDMA_STOPPED || 865 !CSR_READ_4(sc, STE_TX_DMALIST_PTR)) { 866 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 867 vtophys(sc->ste_cdata.ste_tx_head->ste_ptr)); 868 CSR_WRITE_4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 869 } 870 } 871 872 return; 873} 874 875static void ste_stats_update(xsc) 876 void *xsc; 877{ 878 struct ste_softc *sc; 879 struct ste_stats stats; 880 struct ifnet *ifp; 881 struct mii_data *mii; 882 int i, s; 883 u_int8_t *p; 884 885 s = splimp(); 886 887 sc = xsc; 888 ifp = &sc->arpcom.ac_if; 889 mii = device_get_softc(sc->ste_miibus); 890 891 p = (u_int8_t *)&stats; 892 893 for (i = 0; i < sizeof(stats); i++) { 894 *p = CSR_READ_1(sc, STE_STATS + i); 895 p++; 896 } 897 898 ifp->if_collisions += stats.ste_single_colls + 899 stats.ste_multi_colls + stats.ste_late_colls; 900 901 mii_tick(mii); 902 903 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 904 splx(s); 905 906 return; 907} 908 909 910/* 911 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 912 * IDs against our list and return a device name if we find a match. 913 */ 914static int ste_probe(dev) 915 device_t dev; 916{ 917 struct ste_type *t; 918 919 t = ste_devs; 920 921 while(t->ste_name != NULL) { 922 if ((pci_get_vendor(dev) == t->ste_vid) && 923 (pci_get_device(dev) == t->ste_did)) { 924 device_set_desc(dev, t->ste_name); 925 return(0); 926 } 927 t++; 928 } 929 930 return(ENXIO); 931} 932 933/* 934 * Attach the interface. Allocate softc structures, do ifmedia 935 * setup and ethernet/BPF attach. 936 */ 937static int ste_attach(dev) 938 device_t dev; 939{ 940 int s; 941 u_int32_t command; 942 struct ste_softc *sc; 943 struct ifnet *ifp; 944 int unit, error = 0, rid; 945 946 s = splimp(); 947 948 sc = device_get_softc(dev); 949 unit = device_get_unit(dev); 950 bzero(sc, sizeof(struct ste_softc)); 951 952 /* 953 * Handle power management nonsense. 954 */ 955 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 956 if (command == 0x01) { 957 958 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 959 if (command & STE_PSTATE_MASK) { 960 u_int32_t iobase, membase, irq; 961 962 /* Save important PCI config data. */ 963 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 964 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 965 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 966 967 /* Reset the power state. */ 968 printf("ste%d: chip is in D%d power mode " 969 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 970 command &= 0xFFFFFFFC; 971 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 972 973 /* Restore PCI config data. */ 974 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 975 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 976 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 977 } 978 } 979 980 /* 981 * Map control/status registers. 982 */ 983 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 984 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 985 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 986 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 987 988#ifdef STE_USEIOSPACE 989 if (!(command & PCIM_CMD_PORTEN)) { 990 printf("ste%d: failed to enable I/O ports!\n", unit); 991 error = ENXIO; 992 goto fail; 993 } 994#else 995 if (!(command & PCIM_CMD_MEMEN)) { 996 printf("ste%d: failed to enable memory mapping!\n", unit); 997 error = ENXIO; 998 goto fail; 999 } 1000#endif 1001 1002 rid = STE_RID; 1003 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 1004 0, ~0, 1, RF_ACTIVE); 1005 1006 if (sc->ste_res == NULL) { 1007 printf ("ste%d: couldn't map ports/memory\n", unit); 1008 error = ENXIO; 1009 goto fail; 1010 } 1011 1012 sc->ste_btag = rman_get_bustag(sc->ste_res); 1013 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1014 1015 rid = 0; 1016 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1017 RF_SHAREABLE | RF_ACTIVE); 1018 1019 if (sc->ste_irq == NULL) { 1020 printf("ste%d: couldn't map interrupt\n", unit); 1021 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1022 error = ENXIO; 1023 goto fail; 1024 } 1025 1026 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1027 ste_intr, sc, &sc->ste_intrhand); 1028 1029 if (error) { 1030 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1031 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1032 printf("ste%d: couldn't set up irq\n", unit); 1033 goto fail; 1034 } 1035 1036 callout_handle_init(&sc->ste_stat_ch); 1037 1038 /* Reset the adapter. */ 1039 ste_reset(sc); 1040 1041 /* 1042 * Get station address from the EEPROM. 1043 */ 1044 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1045 STE_EEADDR_NODE0, 3, 0)) { 1046 printf("ste%d: failed to read station address\n", unit); 1047 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1048 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1049 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1050 error = ENXIO;; 1051 goto fail; 1052 } 1053 1054 /* 1055 * A Sundance chip was detected. Inform the world. 1056 */ 1057 printf("ste%d: Ethernet address: %6D\n", unit, 1058 sc->arpcom.ac_enaddr, ":"); 1059 1060 sc->ste_unit = unit; 1061 1062 /* Allocate the descriptor queues. */ 1063 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1064 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1065 1066 if (sc->ste_ldata == NULL) { 1067 printf("ste%d: no memory for list buffers!\n", unit); 1068 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1069 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1070 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1071 error = ENXIO; 1072 goto fail; 1073 } 1074 1075 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1076 1077 /* Do MII setup. */ 1078 if (mii_phy_probe(dev, &sc->ste_miibus, 1079 ste_ifmedia_upd, ste_ifmedia_sts)) { 1080 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1081 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1082 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1083 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1084 free(sc->ste_ldata, M_DEVBUF); 1085 error = ENXIO; 1086 goto fail; 1087 } 1088 1089 ifp = &sc->arpcom.ac_if; 1090 ifp->if_softc = sc; 1091 ifp->if_unit = unit; 1092 ifp->if_name = "ste"; 1093 ifp->if_mtu = ETHERMTU; 1094 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1095 ifp->if_ioctl = ste_ioctl; 1096 ifp->if_output = ether_output; 1097 ifp->if_start = ste_start; 1098 ifp->if_watchdog = ste_watchdog; 1099 ifp->if_init = ste_init; 1100 ifp->if_baudrate = 10000000; 1101 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1102 1103 /* 1104 * Call MI attach routines. 1105 */ 1106 1107 if_attach(ifp); 1108 ether_ifattach(ifp); 1109 1110#if NBPF > 0 1111 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1112#endif 1113 1114fail: 1115 splx(s); 1116 return(error); 1117} 1118 1119static int ste_detach(dev) 1120 device_t dev; 1121{ 1122 struct ste_softc *sc; 1123 struct ifnet *ifp; 1124 int s; 1125 1126 s = splimp(); 1127 1128 sc = device_get_softc(dev); 1129 ifp = &sc->arpcom.ac_if; 1130 1131 ste_stop(sc); 1132 if_detach(ifp); 1133 1134 bus_generic_detach(dev); 1135 device_delete_child(dev, sc->ste_miibus); 1136 1137 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1138 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1139 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1140 1141 free(sc->ste_ldata, M_DEVBUF); 1142 1143 splx(s); 1144 1145 return(0); 1146} 1147 1148static int ste_newbuf(sc, c, m) 1149 struct ste_softc *sc; 1150 struct ste_chain_onefrag *c; 1151 struct mbuf *m; 1152{ 1153 struct mbuf *m_new = NULL; 1154 1155 if (m == NULL) { 1156 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1157 if (m_new == NULL) { 1158 printf("ste%d: no memory for rx list -- " 1159 "packet dropped\n", sc->ste_unit); 1160 return(ENOBUFS); 1161 } 1162 MCLGET(m_new, M_DONTWAIT); 1163 if (!(m_new->m_flags & M_EXT)) { 1164 printf("ste%d: no memory for rx list -- " 1165 "packet dropped\n", sc->ste_unit); 1166 m_freem(m_new); 1167 return(ENOBUFS); 1168 } 1169 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1170 } else { 1171 m_new = m; 1172 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1173 m_new->m_data = m_new->m_ext.ext_buf; 1174 } 1175 1176 m_adj(m_new, ETHER_ALIGN); 1177 1178 c->ste_mbuf = m_new; 1179 c->ste_ptr->ste_status = 0; 1180 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1181 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; 1182 1183 return(0); 1184} 1185 1186static int ste_init_rx_list(sc) 1187 struct ste_softc *sc; 1188{ 1189 struct ste_chain_data *cd; 1190 struct ste_list_data *ld; 1191 int i; 1192 1193 cd = &sc->ste_cdata; 1194 ld = sc->ste_ldata; 1195 1196 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1197 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1198 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1199 return(ENOBUFS); 1200 if (i == (STE_RX_LIST_CNT - 1)) { 1201 cd->ste_rx_chain[i].ste_next = 1202 &cd->ste_rx_chain[0]; 1203 ld->ste_rx_list[i].ste_next = 1204 vtophys(&ld->ste_rx_list[0]); 1205 } else { 1206 cd->ste_rx_chain[i].ste_next = 1207 &cd->ste_rx_chain[i + 1]; 1208 ld->ste_rx_list[i].ste_next = 1209 vtophys(&ld->ste_rx_list[i + 1]); 1210 } 1211 1212 } 1213 1214 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1215 1216 return(0); 1217} 1218 1219static void ste_init_tx_list(sc) 1220 struct ste_softc *sc; 1221{ 1222 struct ste_chain_data *cd; 1223 struct ste_list_data *ld; 1224 int i; 1225 1226 cd = &sc->ste_cdata; 1227 ld = sc->ste_ldata; 1228 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1229 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1230 if (i == (STE_TX_LIST_CNT - 1)) 1231 cd->ste_tx_chain[i].ste_next = NULL; 1232 else 1233 cd->ste_tx_chain[i].ste_next = 1234 &cd->ste_tx_chain[i + 1]; 1235 } 1236 1237 cd->ste_tx_free = &cd->ste_tx_chain[0]; 1238 cd->ste_tx_tail = cd->ste_tx_head = NULL; 1239 1240 return; 1241} 1242 1243static void ste_init(xsc) 1244 void *xsc; 1245{ 1246 struct ste_softc *sc; 1247 int i, s; 1248 struct ifnet *ifp; 1249 struct mii_data *mii; 1250 1251 s = splimp(); 1252 1253 sc = xsc; 1254 ifp = &sc->arpcom.ac_if; 1255 mii = device_get_softc(sc->ste_miibus); 1256 1257 ste_stop(sc); 1258 1259 /* Init our MAC address */ 1260 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1261 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1262 } 1263 1264 /* Init RX list */ 1265 if (ste_init_rx_list(sc) == ENOBUFS) { 1266 printf("ste%d: initialization failed: no " 1267 "memory for RX buffers\n", sc->ste_unit); 1268 ste_stop(sc); 1269 splx(s); 1270 return; 1271 } 1272 1273 /* Init TX descriptors */ 1274 ste_init_tx_list(sc); 1275 1276 /* Set the TX freethresh value */ 1277 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1278 1279 /* Set the TX start threshold for best performance. */ 1280 sc->ste_tx_thresh = STE_MIN_FRAMELEN; 1281 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1282 1283 /* Set the TX reclaim threshold. */ 1284 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1285 1286 /* Set up the RX filter. */ 1287 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1288 1289 /* If we want promiscuous mode, set the allframes bit. */ 1290 if (ifp->if_flags & IFF_PROMISC) { 1291 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1292 } else { 1293 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1294 } 1295 1296 /* Set capture broadcast bit to accept broadcast frames. */ 1297 if (ifp->if_flags & IFF_BROADCAST) { 1298 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1299 } else { 1300 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1301 } 1302 1303 ste_setmulti(sc); 1304 1305 /* Load the address of the RX list. */ 1306 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1307 ste_wait(sc); 1308 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1309 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1310 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1311 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1312 1313 /* Enable receiver and transmitter */ 1314 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1315 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1316 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1317 1318 /* Enable stats counters. */ 1319 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1320 1321 /* Enable interrupts. */ 1322 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1323 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1324 1325 mii_mediachg(mii); 1326 1327 ifp->if_flags |= IFF_RUNNING; 1328 ifp->if_flags &= ~IFF_OACTIVE; 1329 1330 splx(s); 1331 1332 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1333 1334 return; 1335} 1336 1337static void ste_stop(sc) 1338 struct ste_softc *sc; 1339{ 1340 int i; 1341 struct ifnet *ifp; 1342 1343 ifp = &sc->arpcom.ac_if; 1344 1345 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1346 1347 CSR_WRITE_2(sc, STE_IMR, 0); 1348 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1349 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1350 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1351 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1352 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1353 ste_wait(sc); 1354 1355 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1356 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1357 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1358 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1359 } 1360 } 1361 1362 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1363 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1364 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1365 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1366 } 1367 } 1368 1369 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1370 1371 return; 1372} 1373 1374static void ste_reset(sc) 1375 struct ste_softc *sc; 1376{ 1377 int i; 1378 1379 STE_SETBIT4(sc, STE_ASICCTL, 1380 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1381 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1382 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1383 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1384 STE_ASICCTL_EXTRESET_RESET); 1385 1386 DELAY(100000); 1387 1388 for (i = 0; i < STE_TIMEOUT; i++) { 1389 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1390 break; 1391 } 1392 1393 if (i == STE_TIMEOUT) 1394 printf("ste%d: global reset never completed\n", sc->ste_unit); 1395 1396#ifdef foo 1397 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_RX_RESET); 1398 for (i = 0; i < STE_TIMEOUT; i++) { 1399 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RX_RESET)) 1400 break; 1401 } 1402 1403 if (i == STE_TIMEOUT) 1404 printf("ste%d: RX reset never completed\n", sc->ste_unit); 1405 1406 DELAY(100000); 1407 1408 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_TX_RESET); 1409 for (i = 0; i < STE_TIMEOUT; i++) { 1410 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_TX_RESET)) 1411 break; 1412 } 1413 1414 if (i == STE_TIMEOUT) 1415 printf("ste%d: TX reset never completed\n", sc->ste_unit); 1416 1417 DELAY(100000); 1418#endif 1419 1420 return; 1421} 1422 1423static int ste_ioctl(ifp, command, data) 1424 struct ifnet *ifp; 1425 u_long command; 1426 caddr_t data; 1427{ 1428 struct ste_softc *sc; 1429 struct ifreq *ifr; 1430 struct mii_data *mii; 1431 int error = 0, s; 1432 1433 s = splimp(); 1434 1435 sc = ifp->if_softc; 1436 ifr = (struct ifreq *)data; 1437 1438 switch(command) { 1439 case SIOCSIFADDR: 1440 case SIOCGIFADDR: 1441 case SIOCSIFMTU: 1442 error = ether_ioctl(ifp, command, data); 1443 break; 1444 case SIOCSIFFLAGS: 1445 if (ifp->if_flags & IFF_UP) { 1446 ste_init(sc); 1447 } else { 1448 if (ifp->if_flags & IFF_RUNNING) 1449 ste_stop(sc); 1450 } 1451 error = 0; 1452 break; 1453 case SIOCADDMULTI: 1454 case SIOCDELMULTI: 1455 ste_setmulti(sc); 1456 error = 0; 1457 break; 1458 case SIOCGIFMEDIA: 1459 case SIOCSIFMEDIA: 1460 mii = device_get_softc(sc->ste_miibus); 1461 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1462 break; 1463 default: 1464 error = EINVAL; 1465 break; 1466 } 1467 1468 splx(s); 1469 1470 return(error); 1471} 1472 1473static int ste_encap(sc, c, m_head) 1474 struct ste_softc *sc; 1475 struct ste_chain *c; 1476 struct mbuf *m_head; 1477{ 1478 int frag = 0; 1479 struct ste_frag *f = NULL; 1480 int total_len; 1481 struct mbuf *m; 1482 1483 m = m_head; 1484 total_len = 0; 1485 1486 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1487 if (m->m_len != 0) { 1488 if (frag == STE_MAXFRAGS) 1489 break; 1490 total_len += m->m_len; 1491 f = &c->ste_ptr->ste_frags[frag]; 1492 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1493 f->ste_len = m->m_len; 1494 frag++; 1495 } 1496 } 1497 1498 if (m != NULL) { 1499 struct mbuf *m_new = NULL; 1500 1501 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1502 if (m_new == NULL) { 1503 printf("ste%d: no memory for " 1504 "tx list", sc->ste_unit); 1505 return(1); 1506 } 1507 if (m_head->m_pkthdr.len > MHLEN) { 1508 MCLGET(m_new, M_DONTWAIT); 1509 if (!(m_new->m_flags & M_EXT)) { 1510 m_freem(m_new); 1511 printf("ste%d: no memory for " 1512 "tx list", sc->ste_unit); 1513 return(1); 1514 } 1515 } 1516 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1517 mtod(m_new, caddr_t)); 1518 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1519 m_freem(m_head); 1520 m_head = m_new; 1521 f = &c->ste_ptr->ste_frags[0]; 1522 f->ste_addr = vtophys(mtod(m_new, caddr_t)); 1523 f->ste_len = total_len = m_new->m_len; 1524 frag = 1; 1525 } 1526 1527 c->ste_mbuf = m_head; 1528 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1529 c->ste_ptr->ste_ctl = total_len; 1530 c->ste_ptr->ste_next = 0; 1531 1532 return(0); 1533} 1534 1535static void ste_start(ifp) 1536 struct ifnet *ifp; 1537{ 1538 struct ste_softc *sc; 1539 struct mbuf *m_head = NULL; 1540 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1541 1542 sc = ifp->if_softc; 1543 1544 if (sc->ste_cdata.ste_tx_free == NULL) { 1545 ifp->if_flags |= IFF_OACTIVE; 1546 return; 1547 } 1548 1549 start_tx = sc->ste_cdata.ste_tx_free; 1550 1551 while(sc->ste_cdata.ste_tx_free != NULL) { 1552 IF_DEQUEUE(&ifp->if_snd, m_head); 1553 if (m_head == NULL) 1554 break; 1555 1556 cur_tx = sc->ste_cdata.ste_tx_free; 1557 sc->ste_cdata.ste_tx_free = cur_tx->ste_next; 1558 1559 cur_tx->ste_next = NULL; 1560 1561 ste_encap(sc, cur_tx, m_head); 1562 1563 if (prev != NULL) { 1564 prev->ste_next = cur_tx; 1565 prev->ste_ptr->ste_next = vtophys(cur_tx->ste_ptr); 1566 } 1567 prev = cur_tx; 1568 1569#if NBPF > 0 1570 /* 1571 * If there's a BPF listener, bounce a copt of this frame 1572 * to him. 1573 */ 1574 if (ifp->if_bpf) 1575 bpf_mtap(ifp, cur_tx->ste_mbuf); 1576#endif 1577 } 1578 1579 if (cur_tx == NULL) 1580 return; 1581 1582 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR; 1583 1584 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1585 ste_wait(sc); 1586 1587 if (sc->ste_cdata.ste_tx_head != NULL) { 1588 sc->ste_cdata.ste_tx_tail->ste_next = start_tx; 1589 sc->ste_cdata.ste_tx_tail->ste_ptr->ste_next = 1590 vtophys(start_tx->ste_ptr); 1591 sc->ste_cdata.ste_tx_tail->ste_ptr->ste_ctl &= 1592 ~STE_TXCTL_DMAINTR; 1593 sc->ste_cdata.ste_tx_tail = cur_tx; 1594 } else { 1595 sc->ste_cdata.ste_tx_head = start_tx; 1596 sc->ste_cdata.ste_tx_tail = cur_tx; 1597 } 1598 1599 if (!CSR_READ_4(sc, STE_TX_DMALIST_PTR)) 1600 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1601 vtophys(start_tx->ste_ptr)); 1602 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1603 1604 ifp->if_timer = 5; 1605 1606 return; 1607} 1608 1609static void ste_watchdog(ifp) 1610 struct ifnet *ifp; 1611{ 1612 struct ste_softc *sc; 1613 1614 sc = ifp->if_softc; 1615 1616 ifp->if_oerrors++; 1617 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1618 1619#ifdef foo 1620 if (sc->ste_pinfo != NULL) { 1621 if (!(ste_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1622 printf("ste%d: no carrier - transceiver " 1623 "cable problem?\n", sc->ste_unit); 1624 } 1625#endif 1626 1627 ste_txeoc(sc); 1628 ste_txeof(sc); 1629 ste_rxeof(sc); 1630 ste_reset(sc); 1631 ste_init(sc); 1632 1633 if (ifp->if_snd.ifq_head != NULL) 1634 ste_start(ifp); 1635 1636 return; 1637} 1638 1639static void ste_shutdown(dev) 1640 device_t dev; 1641{ 1642 struct ste_softc *sc; 1643 1644 sc = device_get_softc(dev); 1645 1646 ste_stop(sc); 1647 1648 return; 1649} 1650