if_ste.c revision 50128
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_ste.c,v 1.6 1999/08/20 15:20:08 wpaul Exp $ 33 */ 34 35 36#include "bpf.h" 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/sockio.h> 41#include <sys/mbuf.h> 42#include <sys/malloc.h> 43#include <sys/kernel.h> 44#include <sys/socket.h> 45 46#include <net/if.h> 47#include <net/if_arp.h> 48#include <net/ethernet.h> 49#include <net/if_dl.h> 50#include <net/if_media.h> 51 52#if NBPF > 0 53#include <net/bpf.h> 54#endif 55 56#include "opt_bdg.h" 57#ifdef BRIDGE 58#include <net/bridge.h> 59#endif 60 61#include <vm/vm.h> /* for vtophys */ 62#include <vm/pmap.h> /* for vtophys */ 63#include <machine/clock.h> /* for DELAY */ 64#include <machine/bus_memio.h> 65#include <machine/bus_pio.h> 66#include <machine/bus.h> 67#include <machine/resource.h> 68#include <sys/bus.h> 69#include <sys/rman.h> 70 71#include <dev/mii/mii.h> 72#include <dev/mii/miivar.h> 73 74#include <pci/pcireg.h> 75#include <pci/pcivar.h> 76 77#include "miibus_if.h" 78 79#define STE_USEIOSPACE 80 81#include <pci/if_stereg.h> 82 83#if !defined(lint) 84static const char rcsid[] = 85 "$Id: if_ste.c,v 1.6 1999/08/20 15:20:08 wpaul Exp $"; 86#endif 87 88/* 89 * Various supported device vendors/types and their names. 90 */ 91static struct ste_type ste_devs[] = { 92 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 93 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" }, 94 { 0, 0, NULL } 95}; 96 97static int ste_probe __P((device_t)); 98static int ste_attach __P((device_t)); 99static int ste_detach __P((device_t)); 100static void ste_init __P((void *)); 101static void ste_intr __P((void *)); 102static void ste_rxeof __P((struct ste_softc *)); 103static void ste_txeoc __P((struct ste_softc *)); 104static void ste_txeof __P((struct ste_softc *)); 105static void ste_stats_update __P((void *)); 106static void ste_stop __P((struct ste_softc *)); 107static void ste_reset __P((struct ste_softc *)); 108static int ste_ioctl __P((struct ifnet *, u_long, caddr_t)); 109static int ste_encap __P((struct ste_softc *, struct ste_chain *, 110 struct mbuf *)); 111static void ste_start __P((struct ifnet *)); 112static void ste_watchdog __P((struct ifnet *)); 113static void ste_shutdown __P((device_t)); 114static int ste_newbuf __P((struct ste_softc *, 115 struct ste_chain_onefrag *, 116 struct mbuf *)); 117static int ste_ifmedia_upd __P((struct ifnet *)); 118static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 119 120static void ste_mii_sync __P((struct ste_softc *)); 121static void ste_mii_send __P((struct ste_softc *, u_int32_t, int)); 122static int ste_mii_readreg __P((struct ste_softc *, 123 struct ste_mii_frame *)); 124static int ste_mii_writereg __P((struct ste_softc *, 125 struct ste_mii_frame *)); 126static int ste_miibus_readreg __P((device_t, int, int)); 127static int ste_miibus_writereg __P((device_t, int, int, int)); 128static void ste_miibus_statchg __P((device_t)); 129 130static int ste_eeprom_wait __P((struct ste_softc *)); 131static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int, 132 int, int)); 133static void ste_wait __P((struct ste_softc *)); 134static u_int8_t ste_calchash __P((caddr_t)); 135static void ste_setmulti __P((struct ste_softc *)); 136static int ste_init_rx_list __P((struct ste_softc *)); 137static void ste_init_tx_list __P((struct ste_softc *)); 138 139#ifdef STE_USEIOSPACE 140#define STE_RES SYS_RES_IOPORT 141#define STE_RID STE_PCI_LOIO 142#else 143#define STE_RES SYS_RES_MEMORY 144#define STE_RID STE_PCI_LOMEM 145#endif 146 147static device_method_t ste_methods[] = { 148 /* Device interface */ 149 DEVMETHOD(device_probe, ste_probe), 150 DEVMETHOD(device_attach, ste_attach), 151 DEVMETHOD(device_detach, ste_detach), 152 DEVMETHOD(device_shutdown, ste_shutdown), 153 154 /* bus interface */ 155 DEVMETHOD(bus_print_child, bus_generic_print_child), 156 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 157 158 /* MII interface */ 159 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 160 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 161 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 162 163 { 0, 0 } 164}; 165 166static driver_t ste_driver = { 167 "ste", 168 ste_methods, 169 sizeof(struct ste_softc) 170}; 171 172static devclass_t ste_devclass; 173 174DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 175DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 176 177#define STE_SETBIT4(sc, reg, x) \ 178 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x) 179 180#define STE_CLRBIT4(sc, reg, x) \ 181 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x) 182 183#define STE_SETBIT2(sc, reg, x) \ 184 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) 185 186#define STE_CLRBIT2(sc, reg, x) \ 187 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) 188 189#define STE_SETBIT1(sc, reg, x) \ 190 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x) 191 192#define STE_CLRBIT1(sc, reg, x) \ 193 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x) 194 195 196#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 197#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 198 199/* 200 * Sync the PHYs by setting data bit and strobing the clock 32 times. 201 */ 202static void ste_mii_sync(sc) 203 struct ste_softc *sc; 204{ 205 register int i; 206 207 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 208 209 for (i = 0; i < 32; i++) { 210 MII_SET(STE_PHYCTL_MCLK); 211 DELAY(1); 212 MII_CLR(STE_PHYCTL_MCLK); 213 DELAY(1); 214 } 215 216 return; 217} 218 219/* 220 * Clock a series of bits through the MII. 221 */ 222static void ste_mii_send(sc, bits, cnt) 223 struct ste_softc *sc; 224 u_int32_t bits; 225 int cnt; 226{ 227 int i; 228 229 MII_CLR(STE_PHYCTL_MCLK); 230 231 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 232 if (bits & i) { 233 MII_SET(STE_PHYCTL_MDATA); 234 } else { 235 MII_CLR(STE_PHYCTL_MDATA); 236 } 237 DELAY(1); 238 MII_CLR(STE_PHYCTL_MCLK); 239 DELAY(1); 240 MII_SET(STE_PHYCTL_MCLK); 241 } 242} 243 244/* 245 * Read an PHY register through the MII. 246 */ 247static int ste_mii_readreg(sc, frame) 248 struct ste_softc *sc; 249 struct ste_mii_frame *frame; 250 251{ 252 int i, ack, s; 253 254 s = splimp(); 255 256 /* 257 * Set up frame for RX. 258 */ 259 frame->mii_stdelim = STE_MII_STARTDELIM; 260 frame->mii_opcode = STE_MII_READOP; 261 frame->mii_turnaround = 0; 262 frame->mii_data = 0; 263 264 CSR_WRITE_2(sc, STE_PHYCTL, 0); 265 /* 266 * Turn on data xmit. 267 */ 268 MII_SET(STE_PHYCTL_MDIR); 269 270 ste_mii_sync(sc); 271 272 /* 273 * Send command/address info. 274 */ 275 ste_mii_send(sc, frame->mii_stdelim, 2); 276 ste_mii_send(sc, frame->mii_opcode, 2); 277 ste_mii_send(sc, frame->mii_phyaddr, 5); 278 ste_mii_send(sc, frame->mii_regaddr, 5); 279 280 /* Turn off xmit. */ 281 MII_CLR(STE_PHYCTL_MDIR); 282 283 /* Idle bit */ 284 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 285 DELAY(1); 286 MII_SET(STE_PHYCTL_MCLK); 287 DELAY(1); 288 289 /* Check for ack */ 290 MII_CLR(STE_PHYCTL_MCLK); 291 DELAY(1); 292 MII_SET(STE_PHYCTL_MCLK); 293 DELAY(1); 294 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 295 296 /* 297 * Now try reading data bits. If the ack failed, we still 298 * need to clock through 16 cycles to keep the PHY(s) in sync. 299 */ 300 if (ack) { 301 for(i = 0; i < 16; i++) { 302 MII_CLR(STE_PHYCTL_MCLK); 303 DELAY(1); 304 MII_SET(STE_PHYCTL_MCLK); 305 DELAY(1); 306 } 307 goto fail; 308 } 309 310 for (i = 0x8000; i; i >>= 1) { 311 MII_CLR(STE_PHYCTL_MCLK); 312 DELAY(1); 313 if (!ack) { 314 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 315 frame->mii_data |= i; 316 DELAY(1); 317 } 318 MII_SET(STE_PHYCTL_MCLK); 319 DELAY(1); 320 } 321 322fail: 323 324 MII_CLR(STE_PHYCTL_MCLK); 325 DELAY(1); 326 MII_SET(STE_PHYCTL_MCLK); 327 DELAY(1); 328 329 splx(s); 330 331 if (ack) 332 return(1); 333 return(0); 334} 335 336/* 337 * Write to a PHY register through the MII. 338 */ 339static int ste_mii_writereg(sc, frame) 340 struct ste_softc *sc; 341 struct ste_mii_frame *frame; 342 343{ 344 int s; 345 346 s = splimp(); 347 /* 348 * Set up frame for TX. 349 */ 350 351 frame->mii_stdelim = STE_MII_STARTDELIM; 352 frame->mii_opcode = STE_MII_WRITEOP; 353 frame->mii_turnaround = STE_MII_TURNAROUND; 354 355 /* 356 * Turn on data output. 357 */ 358 MII_SET(STE_PHYCTL_MDIR); 359 360 ste_mii_sync(sc); 361 362 ste_mii_send(sc, frame->mii_stdelim, 2); 363 ste_mii_send(sc, frame->mii_opcode, 2); 364 ste_mii_send(sc, frame->mii_phyaddr, 5); 365 ste_mii_send(sc, frame->mii_regaddr, 5); 366 ste_mii_send(sc, frame->mii_turnaround, 2); 367 ste_mii_send(sc, frame->mii_data, 16); 368 369 /* Idle bit. */ 370 MII_SET(STE_PHYCTL_MCLK); 371 DELAY(1); 372 MII_CLR(STE_PHYCTL_MCLK); 373 DELAY(1); 374 375 /* 376 * Turn off xmit. 377 */ 378 MII_CLR(STE_PHYCTL_MDIR); 379 380 splx(s); 381 382 return(0); 383} 384 385static int ste_miibus_readreg(dev, phy, reg) 386 device_t dev; 387 int phy, reg; 388{ 389 struct ste_softc *sc; 390 struct ste_mii_frame frame; 391 392 sc = device_get_softc(dev); 393 394 bzero((char *)&frame, sizeof(frame)); 395 396 frame.mii_phyaddr = phy; 397 frame.mii_regaddr = reg; 398 ste_mii_readreg(sc, &frame); 399 400 return(frame.mii_data); 401} 402 403static int ste_miibus_writereg(dev, phy, reg, data) 404 device_t dev; 405 int phy, reg, data; 406{ 407 struct ste_softc *sc; 408 struct ste_mii_frame frame; 409 410 sc = device_get_softc(dev); 411 bzero((char *)&frame, sizeof(frame)); 412 413 frame.mii_phyaddr = phy; 414 frame.mii_regaddr = reg; 415 frame.mii_data = data; 416 417 ste_mii_writereg(sc, &frame); 418 419 return(0); 420} 421 422static void ste_miibus_statchg(dev) 423 device_t dev; 424{ 425 struct ste_softc *sc; 426 struct mii_data *mii; 427 428 sc = device_get_softc(dev); 429 mii = device_get_softc(sc->ste_miibus); 430 431 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 432 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 433 } else { 434 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 435 } 436 437 return; 438} 439 440static int ste_ifmedia_upd(ifp) 441 struct ifnet *ifp; 442{ 443 struct ste_softc *sc; 444 struct mii_data *mii; 445 446 sc = ifp->if_softc; 447 mii = device_get_softc(sc->ste_miibus); 448 mii_mediachg(mii); 449 450 return(0); 451} 452 453static void ste_ifmedia_sts(ifp, ifmr) 454 struct ifnet *ifp; 455 struct ifmediareq *ifmr; 456{ 457 struct ste_softc *sc; 458 struct mii_data *mii; 459 460 sc = ifp->if_softc; 461 mii = device_get_softc(sc->ste_miibus); 462 463 mii_pollstat(mii); 464 ifmr->ifm_active = mii->mii_media_active; 465 ifmr->ifm_status = mii->mii_media_status; 466 467 return; 468} 469 470static void ste_wait(sc) 471 struct ste_softc *sc; 472{ 473 register int i; 474 475 for (i = 0; i < STE_TIMEOUT; i++) { 476 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 477 break; 478 } 479 480 if (i == STE_TIMEOUT) 481 printf("ste%d: command never completed!\n", sc->ste_unit); 482 483 return; 484} 485 486/* 487 * The EEPROM is slow: give it time to come ready after issuing 488 * it a command. 489 */ 490static int ste_eeprom_wait(sc) 491 struct ste_softc *sc; 492{ 493 int i; 494 495 DELAY(1000); 496 497 for (i = 0; i < 100; i++) { 498 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 499 DELAY(1000); 500 else 501 break; 502 } 503 504 if (i == 100) { 505 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 506 return(1); 507 } 508 509 return(0); 510} 511 512/* 513 * Read a sequence of words from the EEPROM. Note that ethernet address 514 * data is stored in the EEPROM in network byte order. 515 */ 516static int ste_read_eeprom(sc, dest, off, cnt, swap) 517 struct ste_softc *sc; 518 caddr_t dest; 519 int off; 520 int cnt; 521 int swap; 522{ 523 int err = 0, i; 524 u_int16_t word = 0, *ptr; 525 526 if (ste_eeprom_wait(sc)) 527 return(1); 528 529 for (i = 0; i < cnt; i++) { 530 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 531 err = ste_eeprom_wait(sc); 532 if (err) 533 break; 534 word = CSR_READ_2(sc, STE_EEPROM_DATA); 535 ptr = (u_int16_t *)(dest + (i * 2)); 536 if (swap) 537 *ptr = ntohs(word); 538 else 539 *ptr = word; 540 } 541 542 return(err ? 1 : 0); 543} 544 545static u_int8_t ste_calchash(addr) 546 caddr_t addr; 547{ 548 549 u_int32_t crc, carry; 550 int i, j; 551 u_int8_t c; 552 553 /* Compute CRC for the address value. */ 554 crc = 0xFFFFFFFF; /* initial value */ 555 556 for (i = 0; i < 6; i++) { 557 c = *(addr + i); 558 for (j = 0; j < 8; j++) { 559 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 560 crc <<= 1; 561 c >>= 1; 562 if (carry) 563 crc = (crc ^ 0x04c11db6) | carry; 564 } 565 } 566 567 /* return the filter bit position */ 568 return(crc & 0x0000003F); 569} 570 571static void ste_setmulti(sc) 572 struct ste_softc *sc; 573{ 574 struct ifnet *ifp; 575 int h = 0; 576 u_int32_t hashes[2] = { 0, 0 }; 577 struct ifmultiaddr *ifma; 578 579 ifp = &sc->arpcom.ac_if; 580 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 581 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 582 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 583 return; 584 } 585 586 /* first, zot all the existing hash bits */ 587 CSR_WRITE_4(sc, STE_MAR0, 0); 588 CSR_WRITE_4(sc, STE_MAR1, 0); 589 590 /* now program new ones */ 591 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 592 ifma = ifma->ifma_link.le_next) { 593 if (ifma->ifma_addr->sa_family != AF_LINK) 594 continue; 595 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 596 if (h < 32) 597 hashes[0] |= (1 << h); 598 else 599 hashes[1] |= (1 << (h - 32)); 600 } 601 602 CSR_WRITE_4(sc, STE_MAR0, hashes[0]); 603 CSR_WRITE_4(sc, STE_MAR1, hashes[1]); 604 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 605 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 606 607 return; 608} 609 610static void ste_intr(xsc) 611 void *xsc; 612{ 613 struct ste_softc *sc; 614 struct ifnet *ifp; 615 u_int16_t status; 616 617 sc = xsc; 618 ifp = &sc->arpcom.ac_if; 619 620 /* See if this is really our interrupt. */ 621 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) 622 return; 623 624 for (;;) { 625 status = CSR_READ_2(sc, STE_ISR_ACK); 626 627 if (!(status & STE_INTRS)) 628 break; 629 630 if (status & STE_ISR_RX_DMADONE) 631 ste_rxeof(sc); 632 633 if (status & STE_ISR_TX_DMADONE) 634 ste_txeof(sc); 635 636 if (status & STE_ISR_TX_DONE) 637 ste_txeoc(sc); 638 639 if (status & STE_ISR_STATS_OFLOW) { 640 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 641 ste_stats_update(sc); 642 } 643 644 if (status & STE_ISR_HOSTERR) { 645 ste_reset(sc); 646 ste_init(sc); 647 } 648 } 649 650 /* Re-enable interrupts */ 651 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 652 653 if (ifp->if_snd.ifq_head != NULL) 654 ste_start(ifp); 655 656 return; 657} 658 659/* 660 * A frame has been uploaded: pass the resulting mbuf chain up to 661 * the higher level protocols. 662 */ 663static void ste_rxeof(sc) 664 struct ste_softc *sc; 665{ 666 struct ether_header *eh; 667 struct mbuf *m; 668 struct ifnet *ifp; 669 struct ste_chain_onefrag *cur_rx; 670 int total_len = 0; 671 u_int32_t rxstat; 672 673 ifp = &sc->arpcom.ac_if; 674 675again: 676 677 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)) { 678 cur_rx = sc->ste_cdata.ste_rx_head; 679 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 680 681 /* 682 * If an error occurs, update stats, clear the 683 * status word and leave the mbuf cluster in place: 684 * it should simply get re-used next time this descriptor 685 * comes up in the ring. 686 */ 687 if (rxstat & STE_RXSTAT_FRAME_ERR) { 688 ifp->if_ierrors++; 689 cur_rx->ste_ptr->ste_status = 0; 690 continue; 691 } 692 693 /* 694 * If there error bit was not set, the upload complete 695 * bit should be set which means we have a valid packet. 696 * If not, something truly strange has happened. 697 */ 698 if (!(rxstat & STE_RXSTAT_DMADONE)) { 699 printf("ste%d: bad receive status -- packet dropped", 700 sc->ste_unit); 701 ifp->if_ierrors++; 702 cur_rx->ste_ptr->ste_status = 0; 703 continue; 704 } 705 706 /* No errors; receive the packet. */ 707 m = cur_rx->ste_mbuf; 708 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 709 710 /* 711 * Try to conjure up a new mbuf cluster. If that 712 * fails, it means we have an out of memory condition and 713 * should leave the buffer in place and continue. This will 714 * result in a lost packet, but there's little else we 715 * can do in this situation. 716 */ 717 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 718 ifp->if_ierrors++; 719 cur_rx->ste_ptr->ste_status = 0; 720 continue; 721 } 722 723 ifp->if_ipackets++; 724 eh = mtod(m, struct ether_header *); 725 m->m_pkthdr.rcvif = ifp; 726 m->m_pkthdr.len = m->m_len = total_len; 727 728#if NBPF > 0 729 /* Handle BPF listeners. Let the BPF user see the packet. */ 730 if (ifp->if_bpf) 731 bpf_mtap(ifp, m); 732#endif 733 734#ifdef BRIDGE 735 if (do_bridge) { 736 struct ifnet *bdg_ifp ; 737 bdg_ifp = bridge_in(m); 738 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 739 bdg_forward(&m, bdg_ifp); 740 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 741 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 742 m_freem(m); 743 continue; 744 } 745 } 746#endif 747 748#if NBPF > 0 749 /* 750 * Don't pass packet up to the ether_input() layer unless it's 751 * a broadcast packet, multicast packet, matches our ethernet 752 * address or the interface is in promiscuous mode. 753 */ 754 if (ifp->if_bpf) { 755 if (ifp->if_flags & IFF_PROMISC && 756 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 757 ETHER_ADDR_LEN) && (eh->ether_dhost[0] & 1) == 0)){ 758 m_freem(m); 759 continue; 760 } 761 } 762#endif 763 764 /* Remove header from mbuf and pass it on. */ 765 m_adj(m, sizeof(struct ether_header)); 766 ether_input(ifp, eh, m); 767 } 768 769 /* 770 * Handle the 'end of channel' condition. When the upload 771 * engine hits the end of the RX ring, it will stall. This 772 * is our cue to flush the RX ring, reload the uplist pointer 773 * register and unstall the engine. 774 * XXX This is actually a little goofy. With the ThunderLAN 775 * chip, you get an interrupt when the receiver hits the end 776 * of the receive ring, which tells you exactly when you 777 * you need to reload the ring pointer. Here we have to 778 * fake it. I'm mad at myself for not being clever enough 779 * to avoid the use of a goto here. 780 */ 781 if (CSR_READ_4(sc, STE_RX_DMALIST_PTR) == 0 || 782 CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_RXDMA_STOPPED) { 783 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 784 ste_wait(sc); 785 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 786 vtophys(&sc->ste_ldata->ste_rx_list[0])); 787 sc->ste_cdata.ste_rx_head = &sc->ste_cdata.ste_rx_chain[0]; 788 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 789 goto again; 790 } 791 792 return; 793} 794 795static void ste_txeoc(sc) 796 struct ste_softc *sc; 797{ 798 u_int8_t txstat; 799 struct ifnet *ifp; 800 801 ifp = &sc->arpcom.ac_if; 802 803 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 804 STE_TXSTATUS_TXDONE) { 805 if (txstat & STE_TXSTATUS_UNDERRUN || 806 txstat & STE_TXSTATUS_EXCESSCOLLS || 807 txstat & STE_TXSTATUS_RECLAIMERR) { 808 ifp->if_oerrors++; 809 printf("ste%d: transmission error: %x\n", 810 sc->ste_unit, txstat); 811 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_TX_RESET); 812 813 if (sc->ste_cdata.ste_tx_head != NULL) 814 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 815 vtophys(sc->ste_cdata.ste_tx_head->ste_ptr)); 816 if (txstat & STE_TXSTATUS_UNDERRUN && 817 sc->ste_tx_thresh < STE_PACKET_SIZE) { 818 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 819 printf("ste%d: tx underrun, increasing tx" 820 " start threshold to %d bytes\n", 821 sc->ste_unit, sc->ste_tx_thresh); 822 } 823 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 824 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 825 (STE_PACKET_SIZE >> 4)); 826 } 827 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 828 if (CSR_READ_4(sc, STE_TX_DMALIST_PTR)) 829 CSR_WRITE_4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 830 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 831 } 832 833 return; 834} 835 836static void ste_txeof(sc) 837 struct ste_softc *sc; 838{ 839 struct ste_chain *cur_tx; 840 struct ifnet *ifp; 841 842 ifp = &sc->arpcom.ac_if; 843 844 /* Clear the timeout timer. */ 845 ifp->if_timer = 0; 846 847 while(sc->ste_cdata.ste_tx_head != NULL) { 848 cur_tx = sc->ste_cdata.ste_tx_head; 849 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 850 break; 851 sc->ste_cdata.ste_tx_head = cur_tx->ste_next; 852 853 m_freem(cur_tx->ste_mbuf); 854 cur_tx->ste_mbuf = NULL; 855 ifp->if_opackets++; 856 857 cur_tx->ste_next = sc->ste_cdata.ste_tx_free; 858 sc->ste_cdata.ste_tx_free = cur_tx; 859 } 860 861 if (sc->ste_cdata.ste_tx_head == NULL) { 862 ifp->if_flags &= ~IFF_OACTIVE; 863 sc->ste_cdata.ste_tx_tail = NULL; 864 } else { 865 if (CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_TXDMA_STOPPED || 866 !CSR_READ_4(sc, STE_TX_DMALIST_PTR)) { 867 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 868 vtophys(sc->ste_cdata.ste_tx_head->ste_ptr)); 869 CSR_WRITE_4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 870 } 871 } 872 873 return; 874} 875 876static void ste_stats_update(xsc) 877 void *xsc; 878{ 879 struct ste_softc *sc; 880 struct ste_stats stats; 881 struct ifnet *ifp; 882 struct mii_data *mii; 883 int i, s; 884 u_int8_t *p; 885 886 s = splimp(); 887 888 sc = xsc; 889 ifp = &sc->arpcom.ac_if; 890 mii = device_get_softc(sc->ste_miibus); 891 892 p = (u_int8_t *)&stats; 893 894 for (i = 0; i < sizeof(stats); i++) { 895 *p = CSR_READ_1(sc, STE_STATS + i); 896 p++; 897 } 898 899 ifp->if_collisions += stats.ste_single_colls + 900 stats.ste_multi_colls + stats.ste_late_colls; 901 902 mii_tick(mii); 903 904 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 905 splx(s); 906 907 return; 908} 909 910 911/* 912 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 913 * IDs against our list and return a device name if we find a match. 914 */ 915static int ste_probe(dev) 916 device_t dev; 917{ 918 struct ste_type *t; 919 920 t = ste_devs; 921 922 while(t->ste_name != NULL) { 923 if ((pci_get_vendor(dev) == t->ste_vid) && 924 (pci_get_device(dev) == t->ste_did)) { 925 device_set_desc(dev, t->ste_name); 926 return(0); 927 } 928 t++; 929 } 930 931 return(ENXIO); 932} 933 934/* 935 * Attach the interface. Allocate softc structures, do ifmedia 936 * setup and ethernet/BPF attach. 937 */ 938static int ste_attach(dev) 939 device_t dev; 940{ 941 int s; 942 u_int32_t command; 943 struct ste_softc *sc; 944 struct ifnet *ifp; 945 int unit, error = 0, rid; 946 947 s = splimp(); 948 949 sc = device_get_softc(dev); 950 unit = device_get_unit(dev); 951 bzero(sc, sizeof(struct ste_softc)); 952 953 /* 954 * Handle power management nonsense. 955 */ 956 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF; 957 if (command == 0x01) { 958 959 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4); 960 if (command & STE_PSTATE_MASK) { 961 u_int32_t iobase, membase, irq; 962 963 /* Save important PCI config data. */ 964 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 965 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 966 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 967 968 /* Reset the power state. */ 969 printf("ste%d: chip is in D%d power mode " 970 "-- setting to D0\n", unit, command & STE_PSTATE_MASK); 971 command &= 0xFFFFFFFC; 972 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4); 973 974 /* Restore PCI config data. */ 975 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 976 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 977 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 978 } 979 } 980 981 /* 982 * Map control/status registers. 983 */ 984 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 985 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 986 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 987 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 988 989#ifdef STE_USEIOSPACE 990 if (!(command & PCIM_CMD_PORTEN)) { 991 printf("ste%d: failed to enable I/O ports!\n", unit); 992 error = ENXIO; 993 goto fail; 994 } 995#else 996 if (!(command & PCIM_CMD_MEMEN)) { 997 printf("ste%d: failed to enable memory mapping!\n", unit); 998 error = ENXIO; 999 goto fail; 1000 } 1001#endif 1002 1003 rid = STE_RID; 1004 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid, 1005 0, ~0, 1, RF_ACTIVE); 1006 1007 if (sc->ste_res == NULL) { 1008 printf ("ste%d: couldn't map ports/memory\n", unit); 1009 error = ENXIO; 1010 goto fail; 1011 } 1012 1013 sc->ste_btag = rman_get_bustag(sc->ste_res); 1014 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 1015 1016 rid = 0; 1017 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1018 RF_SHAREABLE | RF_ACTIVE); 1019 1020 if (sc->ste_irq == NULL) { 1021 printf("ste%d: couldn't map interrupt\n", unit); 1022 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1023 error = ENXIO; 1024 goto fail; 1025 } 1026 1027 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1028 ste_intr, sc, &sc->ste_intrhand); 1029 1030 if (error) { 1031 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1032 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1033 printf("ste%d: couldn't set up irq\n", unit); 1034 goto fail; 1035 } 1036 1037 callout_handle_init(&sc->ste_stat_ch); 1038 1039 /* Reset the adapter. */ 1040 ste_reset(sc); 1041 1042 /* 1043 * Get station address from the EEPROM. 1044 */ 1045 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1046 STE_EEADDR_NODE0, 3, 0)) { 1047 printf("ste%d: failed to read station address\n", unit); 1048 free(sc, M_DEVBUF); 1049 goto fail; 1050 } 1051 1052 /* 1053 * A Sundance chip was detected. Inform the world. 1054 */ 1055 printf("ste%d: Ethernet address: %6D\n", unit, 1056 sc->arpcom.ac_enaddr, ":"); 1057 1058 sc->ste_unit = unit; 1059 1060 /* Allocate the descriptor queues. */ 1061 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1062 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1063 1064 if (sc->ste_ldata == NULL) { 1065 free(sc, M_DEVBUF); 1066 printf("ste%d: no memory for list buffers!\n", unit); 1067 goto fail; 1068 } 1069 1070 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1071 1072 /* Do MII setup. */ 1073 if (mii_phy_probe(dev, &sc->ste_miibus, 1074 ste_ifmedia_upd, ste_ifmedia_sts)) { 1075 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1076 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1077 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1078 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1079 free(sc->ste_ldata, M_DEVBUF); 1080 error = ENXIO; 1081 goto fail; 1082 } 1083 1084 ifp = &sc->arpcom.ac_if; 1085 ifp->if_softc = sc; 1086 ifp->if_unit = unit; 1087 ifp->if_name = "ste"; 1088 ifp->if_mtu = ETHERMTU; 1089 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1090 ifp->if_ioctl = ste_ioctl; 1091 ifp->if_output = ether_output; 1092 ifp->if_start = ste_start; 1093 ifp->if_watchdog = ste_watchdog; 1094 ifp->if_init = ste_init; 1095 ifp->if_baudrate = 10000000; 1096 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1097 1098 /* 1099 * Call MI attach routines. 1100 */ 1101 1102 if_attach(ifp); 1103 ether_ifattach(ifp); 1104 1105#if NBPF > 0 1106 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1107#endif 1108 1109fail: 1110 splx(s); 1111 return(error); 1112} 1113 1114static int ste_detach(dev) 1115 device_t dev; 1116{ 1117 struct ste_softc *sc; 1118 struct ifnet *ifp; 1119 int s; 1120 1121 s = splimp(); 1122 1123 sc = device_get_softc(dev); 1124 ifp = &sc->arpcom.ac_if; 1125 1126 ste_stop(sc); 1127 if_detach(ifp); 1128 1129 bus_generic_detach(dev); 1130 device_delete_child(dev, sc->ste_miibus); 1131 1132 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1133 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1134 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1135 1136 free(sc->ste_ldata, M_DEVBUF); 1137 1138 splx(s); 1139 1140 return(0); 1141} 1142 1143static int ste_newbuf(sc, c, m) 1144 struct ste_softc *sc; 1145 struct ste_chain_onefrag *c; 1146 struct mbuf *m; 1147{ 1148 struct mbuf *m_new = NULL; 1149 1150 if (m == NULL) { 1151 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1152 if (m_new == NULL) { 1153 printf("ste%d: no memory for rx list -- " 1154 "packet dropped\n", sc->ste_unit); 1155 return(ENOBUFS); 1156 } 1157 MCLGET(m_new, M_DONTWAIT); 1158 if (!(m_new->m_flags & M_EXT)) { 1159 printf("ste%d: no memory for rx list -- " 1160 "packet dropped\n", sc->ste_unit); 1161 m_freem(m_new); 1162 return(ENOBUFS); 1163 } 1164 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1165 } else { 1166 m_new = m; 1167 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1168 m_new->m_data = m_new->m_ext.ext_buf; 1169 } 1170 1171 m_adj(m_new, ETHER_ALIGN); 1172 1173 c->ste_mbuf = m_new; 1174 c->ste_ptr->ste_status = 0; 1175 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1176 c->ste_ptr->ste_frag.ste_len = 1536 | STE_FRAG_LAST; 1177 1178 return(0); 1179} 1180 1181static int ste_init_rx_list(sc) 1182 struct ste_softc *sc; 1183{ 1184 struct ste_chain_data *cd; 1185 struct ste_list_data *ld; 1186 int i; 1187 1188 cd = &sc->ste_cdata; 1189 ld = sc->ste_ldata; 1190 1191 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1192 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1193 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1194 return(ENOBUFS); 1195 if (i == (STE_RX_LIST_CNT - 1)) { 1196 cd->ste_rx_chain[i].ste_next = 1197 &cd->ste_rx_chain[0]; 1198 ld->ste_rx_list[i].ste_next = 1199 vtophys(&ld->ste_rx_list[0]); 1200 } else { 1201 cd->ste_rx_chain[i].ste_next = 1202 &cd->ste_rx_chain[i + 1]; 1203 ld->ste_rx_list[i].ste_next = 1204 vtophys(&ld->ste_rx_list[i + 1]); 1205 } 1206 1207 } 1208 1209 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1210 1211 return(0); 1212} 1213 1214static void ste_init_tx_list(sc) 1215 struct ste_softc *sc; 1216{ 1217 struct ste_chain_data *cd; 1218 struct ste_list_data *ld; 1219 int i; 1220 1221 cd = &sc->ste_cdata; 1222 ld = sc->ste_ldata; 1223 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1224 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1225 if (i == (STE_TX_LIST_CNT - 1)) 1226 cd->ste_tx_chain[i].ste_next = NULL; 1227 else 1228 cd->ste_tx_chain[i].ste_next = 1229 &cd->ste_tx_chain[i + 1]; 1230 } 1231 1232 cd->ste_tx_free = &cd->ste_tx_chain[0]; 1233 cd->ste_tx_tail = cd->ste_tx_head = NULL; 1234 1235 return; 1236} 1237 1238static void ste_init(xsc) 1239 void *xsc; 1240{ 1241 struct ste_softc *sc; 1242 int i, s; 1243 struct ifnet *ifp; 1244 struct mii_data *mii; 1245 1246 s = splimp(); 1247 1248 sc = xsc; 1249 ifp = &sc->arpcom.ac_if; 1250 mii = device_get_softc(sc->ste_miibus); 1251 1252 ste_stop(sc); 1253 1254 /* Init our MAC address */ 1255 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1256 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1257 } 1258 1259 /* Init RX list */ 1260 if (ste_init_rx_list(sc) == ENOBUFS) { 1261 printf("ste%d: initialization failed: no " 1262 "memory for RX buffers\n", sc->ste_unit); 1263 ste_stop(sc); 1264 splx(s); 1265 return; 1266 } 1267 1268 /* Init TX descriptors */ 1269 ste_init_tx_list(sc); 1270 1271 /* Set the TX freethresh value */ 1272 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1273 1274 /* Set the TX start threshold for best performance. */ 1275 sc->ste_tx_thresh = STE_MIN_FRAMELEN; 1276 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1277 1278 /* Set the TX reclaim threshold. */ 1279 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1280 1281 /* Set up the RX filter. */ 1282 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1283 1284 /* If we want promiscuous mode, set the allframes bit. */ 1285 if (ifp->if_flags & IFF_PROMISC) { 1286 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1287 } else { 1288 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1289 } 1290 1291 /* Set capture broadcast bit to accept broadcast frames. */ 1292 if (ifp->if_flags & IFF_BROADCAST) { 1293 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1294 } else { 1295 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1296 } 1297 1298 ste_setmulti(sc); 1299 1300 /* Load the address of the RX list. */ 1301 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1302 ste_wait(sc); 1303 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1304 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1305 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1306 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1307 1308 /* Enable receiver and transmitter */ 1309 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1310 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1311 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1312 1313 /* Enable stats counters. */ 1314 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1315 1316 /* Enable interrupts. */ 1317 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1318 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1319 1320 mii_mediachg(mii); 1321 1322 ifp->if_flags |= IFF_RUNNING; 1323 ifp->if_flags &= ~IFF_OACTIVE; 1324 1325 splx(s); 1326 1327 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1328 1329 return; 1330} 1331 1332static void ste_stop(sc) 1333 struct ste_softc *sc; 1334{ 1335 int i; 1336 struct ifnet *ifp; 1337 1338 ifp = &sc->arpcom.ac_if; 1339 1340 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1341 1342 CSR_WRITE_2(sc, STE_IMR, 0); 1343 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1344 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1345 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1346 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1347 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1348 ste_wait(sc); 1349 1350 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1351 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1352 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1353 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1354 } 1355 } 1356 1357 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1358 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1359 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1360 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1361 } 1362 } 1363 1364 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1365 1366 return; 1367} 1368 1369static void ste_reset(sc) 1370 struct ste_softc *sc; 1371{ 1372 int i; 1373 1374 STE_SETBIT4(sc, STE_ASICCTL, 1375 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1376 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1377 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1378 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1379 STE_ASICCTL_EXTRESET_RESET); 1380 1381 DELAY(100000); 1382 1383 for (i = 0; i < STE_TIMEOUT; i++) { 1384 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1385 break; 1386 } 1387 1388 if (i == STE_TIMEOUT) 1389 printf("ste%d: global reset never completed\n", sc->ste_unit); 1390 1391#ifdef foo 1392 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_RX_RESET); 1393 for (i = 0; i < STE_TIMEOUT; i++) { 1394 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RX_RESET)) 1395 break; 1396 } 1397 1398 if (i == STE_TIMEOUT) 1399 printf("ste%d: RX reset never completed\n", sc->ste_unit); 1400 1401 DELAY(100000); 1402 1403 STE_SETBIT4(sc, STE_ASICCTL, STE_ASICCTL_TX_RESET); 1404 for (i = 0; i < STE_TIMEOUT; i++) { 1405 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_TX_RESET)) 1406 break; 1407 } 1408 1409 if (i == STE_TIMEOUT) 1410 printf("ste%d: TX reset never completed\n", sc->ste_unit); 1411 1412 DELAY(100000); 1413#endif 1414 1415 return; 1416} 1417 1418static int ste_ioctl(ifp, command, data) 1419 struct ifnet *ifp; 1420 u_long command; 1421 caddr_t data; 1422{ 1423 struct ste_softc *sc; 1424 struct ifreq *ifr; 1425 struct mii_data *mii; 1426 int error = 0, s; 1427 1428 s = splimp(); 1429 1430 sc = ifp->if_softc; 1431 ifr = (struct ifreq *)data; 1432 1433 switch(command) { 1434 case SIOCSIFADDR: 1435 case SIOCGIFADDR: 1436 case SIOCSIFMTU: 1437 error = ether_ioctl(ifp, command, data); 1438 break; 1439 case SIOCSIFFLAGS: 1440 if (ifp->if_flags & IFF_UP) { 1441 ste_init(sc); 1442 } else { 1443 if (ifp->if_flags & IFF_RUNNING) 1444 ste_stop(sc); 1445 } 1446 error = 0; 1447 break; 1448 case SIOCADDMULTI: 1449 case SIOCDELMULTI: 1450 ste_setmulti(sc); 1451 error = 0; 1452 break; 1453 case SIOCGIFMEDIA: 1454 case SIOCSIFMEDIA: 1455 mii = device_get_softc(sc->ste_miibus); 1456 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1457 break; 1458 default: 1459 error = EINVAL; 1460 break; 1461 } 1462 1463 splx(s); 1464 1465 return(error); 1466} 1467 1468static int ste_encap(sc, c, m_head) 1469 struct ste_softc *sc; 1470 struct ste_chain *c; 1471 struct mbuf *m_head; 1472{ 1473 int frag = 0; 1474 struct ste_frag *f = NULL; 1475 int total_len; 1476 struct mbuf *m; 1477 1478 m = m_head; 1479 total_len = 0; 1480 1481 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1482 if (m->m_len != 0) { 1483 if (frag == STE_MAXFRAGS) 1484 break; 1485 total_len += m->m_len; 1486 f = &c->ste_ptr->ste_frags[frag]; 1487 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1488 f->ste_len = m->m_len; 1489 frag++; 1490 } 1491 } 1492 1493 if (m != NULL) { 1494 struct mbuf *m_new = NULL; 1495 1496 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1497 if (m_new == NULL) { 1498 printf("ste%d: no memory for " 1499 "tx list", sc->ste_unit); 1500 return(1); 1501 } 1502 if (m_head->m_pkthdr.len > MHLEN) { 1503 MCLGET(m_new, M_DONTWAIT); 1504 if (!(m_new->m_flags & M_EXT)) { 1505 m_freem(m_new); 1506 printf("ste%d: no memory for " 1507 "tx list", sc->ste_unit); 1508 return(1); 1509 } 1510 } 1511 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1512 mtod(m_new, caddr_t)); 1513 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1514 m_freem(m_head); 1515 m_head = m_new; 1516 f = &c->ste_ptr->ste_frags[0]; 1517 f->ste_addr = vtophys(mtod(m_new, caddr_t)); 1518 f->ste_len = total_len = m_new->m_len; 1519 frag = 1; 1520 } 1521 1522 c->ste_mbuf = m_head; 1523 c->ste_ptr->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1524 c->ste_ptr->ste_ctl = total_len; 1525 c->ste_ptr->ste_next = 0; 1526 1527 return(0); 1528} 1529 1530static void ste_start(ifp) 1531 struct ifnet *ifp; 1532{ 1533 struct ste_softc *sc; 1534 struct mbuf *m_head = NULL; 1535 struct ste_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1536 1537 sc = ifp->if_softc; 1538 1539 if (sc->ste_cdata.ste_tx_free == NULL) { 1540 ifp->if_flags |= IFF_OACTIVE; 1541 return; 1542 } 1543 1544 start_tx = sc->ste_cdata.ste_tx_free; 1545 1546 while(sc->ste_cdata.ste_tx_free != NULL) { 1547 IF_DEQUEUE(&ifp->if_snd, m_head); 1548 if (m_head == NULL) 1549 break; 1550 1551 cur_tx = sc->ste_cdata.ste_tx_free; 1552 sc->ste_cdata.ste_tx_free = cur_tx->ste_next; 1553 1554 cur_tx->ste_next = NULL; 1555 1556 ste_encap(sc, cur_tx, m_head); 1557 1558 if (prev != NULL) { 1559 prev->ste_next = cur_tx; 1560 prev->ste_ptr->ste_next = vtophys(cur_tx->ste_ptr); 1561 } 1562 prev = cur_tx; 1563 1564#if NBPF > 0 1565 /* 1566 * If there's a BPF listener, bounce a copt of this frame 1567 * to him. 1568 */ 1569 if (ifp->if_bpf) 1570 bpf_mtap(ifp, cur_tx->ste_mbuf); 1571#endif 1572 } 1573 1574 if (cur_tx == NULL) 1575 return; 1576 1577 cur_tx->ste_ptr->ste_ctl |= STE_TXCTL_DMAINTR; 1578 1579 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1580 ste_wait(sc); 1581 1582 if (sc->ste_cdata.ste_tx_head != NULL) { 1583 sc->ste_cdata.ste_tx_tail->ste_next = start_tx; 1584 sc->ste_cdata.ste_tx_tail->ste_ptr->ste_next = 1585 vtophys(start_tx->ste_ptr); 1586 sc->ste_cdata.ste_tx_tail->ste_ptr->ste_ctl &= 1587 ~STE_TXCTL_DMAINTR; 1588 sc->ste_cdata.ste_tx_tail = cur_tx; 1589 } else { 1590 sc->ste_cdata.ste_tx_head = start_tx; 1591 sc->ste_cdata.ste_tx_tail = cur_tx; 1592 } 1593 1594 if (!CSR_READ_4(sc, STE_TX_DMALIST_PTR)) 1595 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1596 vtophys(start_tx->ste_ptr)); 1597 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1598 1599 ifp->if_timer = 5; 1600 1601 return; 1602} 1603 1604static void ste_watchdog(ifp) 1605 struct ifnet *ifp; 1606{ 1607 struct ste_softc *sc; 1608 1609 sc = ifp->if_softc; 1610 1611 ifp->if_oerrors++; 1612 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1613 1614#ifdef foo 1615 if (sc->ste_pinfo != NULL) { 1616 if (!(ste_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1617 printf("ste%d: no carrier - transceiver " 1618 "cable problem?\n", sc->ste_unit); 1619 } 1620#endif 1621 1622 ste_txeoc(sc); 1623 ste_txeof(sc); 1624 ste_rxeof(sc); 1625 ste_reset(sc); 1626 ste_init(sc); 1627 1628 if (ifp->if_snd.ifq_head != NULL) 1629 ste_start(ifp); 1630 1631 return; 1632} 1633 1634static void ste_shutdown(dev) 1635 device_t dev; 1636{ 1637 struct ste_softc *sc; 1638 1639 sc = device_get_softc(dev); 1640 1641 ste_stop(sc); 1642 1643 return; 1644} 1645