if_ste.c revision 200966
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 200966 2009-12-24 20:45:33Z yongari $"); 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53 54#include <net/bpf.h> 55#include <net/if.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61#include <net/if_vlan_var.h> 62 63#include <machine/bus.h> 64#include <machine/resource.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <dev/ste/if_stereg.h> 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77MODULE_DEPEND(ste, pci, 1, 1, 1); 78MODULE_DEPEND(ste, ether, 1, 1, 1); 79MODULE_DEPEND(ste, miibus, 1, 1, 1); 80 81/* Define to show Tx error status. */ 82#define STE_SHOW_TXERRORS 83 84/* 85 * Various supported device vendors/types and their names. 86 */ 87static struct ste_type ste_devs[] = { 88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 91 { 0, 0, NULL } 92}; 93 94static int ste_attach(device_t); 95static int ste_detach(device_t); 96static int ste_probe(device_t); 97static int ste_resume(device_t); 98static int ste_shutdown(device_t); 99static int ste_suspend(device_t); 100 101static int ste_dma_alloc(struct ste_softc *); 102static void ste_dma_free(struct ste_softc *); 103static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 104static int ste_eeprom_wait(struct ste_softc *); 105static int ste_encap(struct ste_softc *, struct mbuf **, 106 struct ste_chain *); 107static int ste_ifmedia_upd(struct ifnet *); 108static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109static void ste_init(void *); 110static void ste_init_locked(struct ste_softc *); 111static int ste_init_rx_list(struct ste_softc *); 112static void ste_init_tx_list(struct ste_softc *); 113static void ste_intr(void *); 114static int ste_ioctl(struct ifnet *, u_long, caddr_t); 115static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 116static void ste_mii_send(struct ste_softc *, uint32_t, int); 117static void ste_mii_sync(struct ste_softc *); 118static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 119static int ste_miibus_readreg(device_t, int, int); 120static void ste_miibus_statchg(device_t); 121static int ste_miibus_writereg(device_t, int, int, int); 122static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 123static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 124static void ste_reset(struct ste_softc *); 125static void ste_restart_tx(struct ste_softc *); 126static int ste_rxeof(struct ste_softc *, int); 127static void ste_rxfilter(struct ste_softc *); 128static void ste_setwol(struct ste_softc *); 129static void ste_start(struct ifnet *); 130static void ste_start_locked(struct ifnet *); 131static void ste_stats_clear(struct ste_softc *); 132static void ste_stats_update(struct ste_softc *); 133static void ste_stop(struct ste_softc *); 134static void ste_sysctl_node(struct ste_softc *); 135static void ste_tick(void *); 136static void ste_txeoc(struct ste_softc *); 137static void ste_txeof(struct ste_softc *); 138static void ste_wait(struct ste_softc *); 139static void ste_watchdog(struct ste_softc *); 140 141static device_method_t ste_methods[] = { 142 /* Device interface */ 143 DEVMETHOD(device_probe, ste_probe), 144 DEVMETHOD(device_attach, ste_attach), 145 DEVMETHOD(device_detach, ste_detach), 146 DEVMETHOD(device_shutdown, ste_shutdown), 147 DEVMETHOD(device_suspend, ste_suspend), 148 DEVMETHOD(device_resume, ste_resume), 149 150 /* bus interface */ 151 DEVMETHOD(bus_print_child, bus_generic_print_child), 152 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 153 154 /* MII interface */ 155 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 156 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 157 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 158 159 { 0, 0 } 160}; 161 162static driver_t ste_driver = { 163 "ste", 164 ste_methods, 165 sizeof(struct ste_softc) 166}; 167 168static devclass_t ste_devclass; 169 170DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 171DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 172 173#define STE_SETBIT4(sc, reg, x) \ 174 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 175 176#define STE_CLRBIT4(sc, reg, x) \ 177 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 178 179#define STE_SETBIT2(sc, reg, x) \ 180 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 181 182#define STE_CLRBIT2(sc, reg, x) \ 183 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 184 185#define STE_SETBIT1(sc, reg, x) \ 186 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 187 188#define STE_CLRBIT1(sc, reg, x) \ 189 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 190 191 192#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 193#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 194 195/* 196 * Sync the PHYs by setting data bit and strobing the clock 32 times. 197 */ 198static void 199ste_mii_sync(struct ste_softc *sc) 200{ 201 int i; 202 203 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 204 205 for (i = 0; i < 32; i++) { 206 MII_SET(STE_PHYCTL_MCLK); 207 DELAY(1); 208 MII_CLR(STE_PHYCTL_MCLK); 209 DELAY(1); 210 } 211} 212 213/* 214 * Clock a series of bits through the MII. 215 */ 216static void 217ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt) 218{ 219 int i; 220 221 MII_CLR(STE_PHYCTL_MCLK); 222 223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 224 if (bits & i) { 225 MII_SET(STE_PHYCTL_MDATA); 226 } else { 227 MII_CLR(STE_PHYCTL_MDATA); 228 } 229 DELAY(1); 230 MII_CLR(STE_PHYCTL_MCLK); 231 DELAY(1); 232 MII_SET(STE_PHYCTL_MCLK); 233 } 234} 235 236/* 237 * Read an PHY register through the MII. 238 */ 239static int 240ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 241{ 242 int i, ack; 243 244 /* 245 * Set up frame for RX. 246 */ 247 frame->mii_stdelim = STE_MII_STARTDELIM; 248 frame->mii_opcode = STE_MII_READOP; 249 frame->mii_turnaround = 0; 250 frame->mii_data = 0; 251 252 CSR_WRITE_2(sc, STE_PHYCTL, 0); 253 /* 254 * Turn on data xmit. 255 */ 256 MII_SET(STE_PHYCTL_MDIR); 257 258 ste_mii_sync(sc); 259 260 /* 261 * Send command/address info. 262 */ 263 ste_mii_send(sc, frame->mii_stdelim, 2); 264 ste_mii_send(sc, frame->mii_opcode, 2); 265 ste_mii_send(sc, frame->mii_phyaddr, 5); 266 ste_mii_send(sc, frame->mii_regaddr, 5); 267 268 /* Turn off xmit. */ 269 MII_CLR(STE_PHYCTL_MDIR); 270 271 /* Idle bit */ 272 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 273 DELAY(1); 274 MII_SET(STE_PHYCTL_MCLK); 275 DELAY(1); 276 277 /* Check for ack */ 278 MII_CLR(STE_PHYCTL_MCLK); 279 DELAY(1); 280 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 281 MII_SET(STE_PHYCTL_MCLK); 282 DELAY(1); 283 284 /* 285 * Now try reading data bits. If the ack failed, we still 286 * need to clock through 16 cycles to keep the PHY(s) in sync. 287 */ 288 if (ack) { 289 for (i = 0; i < 16; i++) { 290 MII_CLR(STE_PHYCTL_MCLK); 291 DELAY(1); 292 MII_SET(STE_PHYCTL_MCLK); 293 DELAY(1); 294 } 295 goto fail; 296 } 297 298 for (i = 0x8000; i; i >>= 1) { 299 MII_CLR(STE_PHYCTL_MCLK); 300 DELAY(1); 301 if (!ack) { 302 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 303 frame->mii_data |= i; 304 DELAY(1); 305 } 306 MII_SET(STE_PHYCTL_MCLK); 307 DELAY(1); 308 } 309 310fail: 311 312 MII_CLR(STE_PHYCTL_MCLK); 313 DELAY(1); 314 MII_SET(STE_PHYCTL_MCLK); 315 DELAY(1); 316 317 if (ack) 318 return (1); 319 return (0); 320} 321 322/* 323 * Write to a PHY register through the MII. 324 */ 325static int 326ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 327{ 328 329 /* 330 * Set up frame for TX. 331 */ 332 333 frame->mii_stdelim = STE_MII_STARTDELIM; 334 frame->mii_opcode = STE_MII_WRITEOP; 335 frame->mii_turnaround = STE_MII_TURNAROUND; 336 337 /* 338 * Turn on data output. 339 */ 340 MII_SET(STE_PHYCTL_MDIR); 341 342 ste_mii_sync(sc); 343 344 ste_mii_send(sc, frame->mii_stdelim, 2); 345 ste_mii_send(sc, frame->mii_opcode, 2); 346 ste_mii_send(sc, frame->mii_phyaddr, 5); 347 ste_mii_send(sc, frame->mii_regaddr, 5); 348 ste_mii_send(sc, frame->mii_turnaround, 2); 349 ste_mii_send(sc, frame->mii_data, 16); 350 351 /* Idle bit. */ 352 MII_SET(STE_PHYCTL_MCLK); 353 DELAY(1); 354 MII_CLR(STE_PHYCTL_MCLK); 355 DELAY(1); 356 357 /* 358 * Turn off xmit. 359 */ 360 MII_CLR(STE_PHYCTL_MDIR); 361 362 return (0); 363} 364 365static int 366ste_miibus_readreg(device_t dev, int phy, int reg) 367{ 368 struct ste_softc *sc; 369 struct ste_mii_frame frame; 370 371 sc = device_get_softc(dev); 372 373 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0 && phy != 0) 374 return (0); 375 376 bzero((char *)&frame, sizeof(frame)); 377 378 frame.mii_phyaddr = phy; 379 frame.mii_regaddr = reg; 380 ste_mii_readreg(sc, &frame); 381 382 return (frame.mii_data); 383} 384 385static int 386ste_miibus_writereg(device_t dev, int phy, int reg, int data) 387{ 388 struct ste_softc *sc; 389 struct ste_mii_frame frame; 390 391 sc = device_get_softc(dev); 392 bzero((char *)&frame, sizeof(frame)); 393 394 frame.mii_phyaddr = phy; 395 frame.mii_regaddr = reg; 396 frame.mii_data = data; 397 398 ste_mii_writereg(sc, &frame); 399 400 return (0); 401} 402 403static void 404ste_miibus_statchg(device_t dev) 405{ 406 struct ste_softc *sc; 407 struct mii_data *mii; 408 struct ifnet *ifp; 409 uint16_t cfg; 410 411 sc = device_get_softc(dev); 412 413 mii = device_get_softc(sc->ste_miibus); 414 ifp = sc->ste_ifp; 415 if (mii == NULL || ifp == NULL || 416 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 417 return; 418 419 sc->ste_flags &= ~STE_FLAG_LINK; 420 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 421 (IFM_ACTIVE | IFM_AVALID)) { 422 switch (IFM_SUBTYPE(mii->mii_media_active)) { 423 case IFM_10_T: 424 case IFM_100_TX: 425 case IFM_100_FX: 426 case IFM_100_T4: 427 sc->ste_flags |= STE_FLAG_LINK; 428 default: 429 break; 430 } 431 } 432 433 /* Program MACs with resolved speed/duplex/flow-control. */ 434 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 435 cfg = CSR_READ_2(sc, STE_MACCTL0); 436 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 437 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 438 /* 439 * ST201 data sheet says driver should enable receiving 440 * MAC control frames bit of receive mode register to 441 * receive flow-control frames but the register has no 442 * such bits. In addition the controller has no ability 443 * to send pause frames so it should be handled in 444 * driver. Implementing pause timer handling in driver 445 * layer is not trivial, so don't enable flow-control 446 * here. 447 */ 448 cfg |= STE_MACCTL0_FULLDUPLEX; 449 } 450 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 451 } 452} 453 454static int 455ste_ifmedia_upd(struct ifnet *ifp) 456{ 457 struct ste_softc *sc; 458 struct mii_data *mii; 459 struct mii_softc *miisc; 460 int error; 461 462 sc = ifp->if_softc; 463 STE_LOCK(sc); 464 mii = device_get_softc(sc->ste_miibus); 465 if (mii->mii_instance) { 466 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 467 mii_phy_reset(miisc); 468 } 469 error = mii_mediachg(mii); 470 STE_UNLOCK(sc); 471 472 return (error); 473} 474 475static void 476ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 477{ 478 struct ste_softc *sc; 479 struct mii_data *mii; 480 481 sc = ifp->if_softc; 482 mii = device_get_softc(sc->ste_miibus); 483 484 STE_LOCK(sc); 485 if ((ifp->if_flags & IFF_UP) == 0) { 486 STE_UNLOCK(sc); 487 return; 488 } 489 mii_pollstat(mii); 490 ifmr->ifm_active = mii->mii_media_active; 491 ifmr->ifm_status = mii->mii_media_status; 492 STE_UNLOCK(sc); 493} 494 495static void 496ste_wait(struct ste_softc *sc) 497{ 498 int i; 499 500 for (i = 0; i < STE_TIMEOUT; i++) { 501 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 502 break; 503 DELAY(1); 504 } 505 506 if (i == STE_TIMEOUT) 507 device_printf(sc->ste_dev, "command never completed!\n"); 508} 509 510/* 511 * The EEPROM is slow: give it time to come ready after issuing 512 * it a command. 513 */ 514static int 515ste_eeprom_wait(struct ste_softc *sc) 516{ 517 int i; 518 519 DELAY(1000); 520 521 for (i = 0; i < 100; i++) { 522 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 523 DELAY(1000); 524 else 525 break; 526 } 527 528 if (i == 100) { 529 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 530 return (1); 531 } 532 533 return (0); 534} 535 536/* 537 * Read a sequence of words from the EEPROM. Note that ethernet address 538 * data is stored in the EEPROM in network byte order. 539 */ 540static int 541ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 542{ 543 uint16_t word, *ptr; 544 int err = 0, i; 545 546 if (ste_eeprom_wait(sc)) 547 return (1); 548 549 for (i = 0; i < cnt; i++) { 550 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 551 err = ste_eeprom_wait(sc); 552 if (err) 553 break; 554 word = CSR_READ_2(sc, STE_EEPROM_DATA); 555 ptr = (uint16_t *)(dest + (i * 2)); 556 if (swap) 557 *ptr = ntohs(word); 558 else 559 *ptr = word; 560 } 561 562 return (err ? 1 : 0); 563} 564 565static void 566ste_rxfilter(struct ste_softc *sc) 567{ 568 struct ifnet *ifp; 569 struct ifmultiaddr *ifma; 570 uint32_t hashes[2] = { 0, 0 }; 571 uint8_t rxcfg; 572 int h; 573 574 STE_LOCK_ASSERT(sc); 575 576 ifp = sc->ste_ifp; 577 rxcfg = CSR_READ_1(sc, STE_RX_MODE); 578 rxcfg |= STE_RXMODE_UNICAST; 579 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH | 580 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC); 581 if (ifp->if_flags & IFF_BROADCAST) 582 rxcfg |= STE_RXMODE_BROADCAST; 583 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 584 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 585 rxcfg |= STE_RXMODE_ALLMULTI; 586 if ((ifp->if_flags & IFF_PROMISC) != 0) 587 rxcfg |= STE_RXMODE_PROMISC; 588 goto chipit; 589 } 590 591 rxcfg |= STE_RXMODE_MULTIHASH; 592 /* Now program new ones. */ 593 if_maddr_rlock(ifp); 594 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 595 if (ifma->ifma_addr->sa_family != AF_LINK) 596 continue; 597 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 598 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 599 if (h < 32) 600 hashes[0] |= (1 << h); 601 else 602 hashes[1] |= (1 << (h - 32)); 603 } 604 if_maddr_runlock(ifp); 605 606chipit: 607 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 608 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 609 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 610 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 611 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg); 612 CSR_READ_1(sc, STE_RX_MODE); 613} 614 615#ifdef DEVICE_POLLING 616static poll_handler_t ste_poll, ste_poll_locked; 617 618static int 619ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 620{ 621 struct ste_softc *sc = ifp->if_softc; 622 int rx_npkts = 0; 623 624 STE_LOCK(sc); 625 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 626 rx_npkts = ste_poll_locked(ifp, cmd, count); 627 STE_UNLOCK(sc); 628 return (rx_npkts); 629} 630 631static int 632ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 633{ 634 struct ste_softc *sc = ifp->if_softc; 635 int rx_npkts; 636 637 STE_LOCK_ASSERT(sc); 638 639 rx_npkts = ste_rxeof(sc, count); 640 ste_txeof(sc); 641 ste_txeoc(sc); 642 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 643 ste_start_locked(ifp); 644 645 if (cmd == POLL_AND_CHECK_STATUS) { 646 uint16_t status; 647 648 status = CSR_READ_2(sc, STE_ISR_ACK); 649 650 if (status & STE_ISR_STATS_OFLOW) 651 ste_stats_update(sc); 652 653 if (status & STE_ISR_HOSTERR) { 654 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 655 ste_init_locked(sc); 656 } 657 } 658 return (rx_npkts); 659} 660#endif /* DEVICE_POLLING */ 661 662static void 663ste_intr(void *xsc) 664{ 665 struct ste_softc *sc; 666 struct ifnet *ifp; 667 uint16_t intrs, status; 668 669 sc = xsc; 670 STE_LOCK(sc); 671 ifp = sc->ste_ifp; 672 673#ifdef DEVICE_POLLING 674 if (ifp->if_capenable & IFCAP_POLLING) { 675 STE_UNLOCK(sc); 676 return; 677 } 678#endif 679 /* Reading STE_ISR_ACK clears STE_IMR register. */ 680 status = CSR_READ_2(sc, STE_ISR_ACK); 681 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 682 STE_UNLOCK(sc); 683 return; 684 } 685 686 intrs = STE_INTRS; 687 if (status == 0xFFFF || (status & intrs) == 0) 688 goto done; 689 690 if (sc->ste_int_rx_act > 0) { 691 status &= ~STE_ISR_RX_DMADONE; 692 intrs &= ~STE_IMR_RX_DMADONE; 693 } 694 695 if ((status & (STE_ISR_SOFTINTR | STE_ISR_RX_DMADONE)) != 0) { 696 ste_rxeof(sc, -1); 697 /* 698 * The controller has no ability to Rx interrupt 699 * moderation feature. Receiving 64 bytes frames 700 * from wire generates too many interrupts which in 701 * turn make system useless to process other useful 702 * things. Fortunately ST201 supports single shot 703 * timer so use the timer to implement Rx interrupt 704 * moderation in driver. This adds more register 705 * access but it greatly reduces number of Rx 706 * interrupts under high network load. 707 */ 708 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 709 (sc->ste_int_rx_mod != 0)) { 710 if ((status & STE_ISR_RX_DMADONE) != 0) { 711 CSR_WRITE_2(sc, STE_COUNTDOWN, 712 STE_TIMER_USECS(sc->ste_int_rx_mod)); 713 intrs &= ~STE_IMR_RX_DMADONE; 714 sc->ste_int_rx_act = 1; 715 } else { 716 intrs |= STE_IMR_RX_DMADONE; 717 sc->ste_int_rx_act = 0; 718 } 719 } 720 } 721 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 722 if ((status & STE_ISR_TX_DMADONE) != 0) 723 ste_txeof(sc); 724 if ((status & STE_ISR_TX_DONE) != 0) 725 ste_txeoc(sc); 726 if ((status & STE_ISR_STATS_OFLOW) != 0) 727 ste_stats_update(sc); 728 if ((status & STE_ISR_HOSTERR) != 0) { 729 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 730 ste_init_locked(sc); 731 STE_UNLOCK(sc); 732 return; 733 } 734 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 735 ste_start_locked(ifp); 736done: 737 /* Re-enable interrupts */ 738 CSR_WRITE_2(sc, STE_IMR, intrs); 739 } 740 STE_UNLOCK(sc); 741} 742 743/* 744 * A frame has been uploaded: pass the resulting mbuf chain up to 745 * the higher level protocols. 746 */ 747static int 748ste_rxeof(struct ste_softc *sc, int count) 749{ 750 struct mbuf *m; 751 struct ifnet *ifp; 752 struct ste_chain_onefrag *cur_rx; 753 uint32_t rxstat; 754 int total_len, rx_npkts; 755 756 ifp = sc->ste_ifp; 757 758 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 759 sc->ste_cdata.ste_rx_list_map, 760 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 761 762 cur_rx = sc->ste_cdata.ste_rx_head; 763 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 764 cur_rx = cur_rx->ste_next) { 765 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 766 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 767 break; 768#ifdef DEVICE_POLLING 769 if (ifp->if_capenable & IFCAP_POLLING) { 770 if (count == 0) 771 break; 772 count--; 773 } 774#endif 775 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 776 break; 777 /* 778 * If an error occurs, update stats, clear the 779 * status word and leave the mbuf cluster in place: 780 * it should simply get re-used next time this descriptor 781 * comes up in the ring. 782 */ 783 if (rxstat & STE_RXSTAT_FRAME_ERR) { 784 ifp->if_ierrors++; 785 cur_rx->ste_ptr->ste_status = 0; 786 continue; 787 } 788 789 /* No errors; receive the packet. */ 790 m = cur_rx->ste_mbuf; 791 total_len = STE_RX_BYTES(rxstat); 792 793 /* 794 * Try to conjure up a new mbuf cluster. If that 795 * fails, it means we have an out of memory condition and 796 * should leave the buffer in place and continue. This will 797 * result in a lost packet, but there's little else we 798 * can do in this situation. 799 */ 800 if (ste_newbuf(sc, cur_rx) != 0) { 801 ifp->if_iqdrops++; 802 cur_rx->ste_ptr->ste_status = 0; 803 continue; 804 } 805 806 m->m_pkthdr.rcvif = ifp; 807 m->m_pkthdr.len = m->m_len = total_len; 808 809 ifp->if_ipackets++; 810 STE_UNLOCK(sc); 811 (*ifp->if_input)(ifp, m); 812 STE_LOCK(sc); 813 } 814 815 if (rx_npkts > 0) { 816 sc->ste_cdata.ste_rx_head = cur_rx; 817 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 818 sc->ste_cdata.ste_rx_list_map, 819 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 820 } 821 822 return (rx_npkts); 823} 824 825static void 826ste_txeoc(struct ste_softc *sc) 827{ 828 uint16_t txstat; 829 struct ifnet *ifp; 830 831 STE_LOCK_ASSERT(sc); 832 833 ifp = sc->ste_ifp; 834 835 /* 836 * STE_TX_STATUS register implements a queue of up to 31 837 * transmit status byte. Writing an arbitrary value to the 838 * register will advance the queue to the next transmit 839 * status byte. This means if driver does not read 840 * STE_TX_STATUS register after completing sending more 841 * than 31 frames the controller would be stalled so driver 842 * should re-wake the Tx MAC. This is the most severe 843 * limitation of ST201 based controller. 844 */ 845 for (;;) { 846 txstat = CSR_READ_2(sc, STE_TX_STATUS); 847 if ((txstat & STE_TXSTATUS_TXDONE) == 0) 848 break; 849 if ((txstat & (STE_TXSTATUS_UNDERRUN | 850 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR | 851 STE_TXSTATUS_STATSOFLOW)) != 0) { 852 ifp->if_oerrors++; 853#ifdef STE_SHOW_TXERRORS 854 device_printf(sc->ste_dev, "TX error : 0x%b\n", 855 txstat & 0xFF, STE_ERR_BITS); 856#endif 857 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 && 858 sc->ste_tx_thresh < STE_PACKET_SIZE) { 859 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 860 if (sc->ste_tx_thresh > STE_PACKET_SIZE) 861 sc->ste_tx_thresh = STE_PACKET_SIZE; 862 device_printf(sc->ste_dev, 863 "TX underrun, increasing TX" 864 " start threshold to %d bytes\n", 865 sc->ste_tx_thresh); 866 /* Make sure to disable active DMA cycles. */ 867 STE_SETBIT4(sc, STE_DMACTL, 868 STE_DMACTL_TXDMA_STALL); 869 ste_wait(sc); 870 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 871 ste_init_locked(sc); 872 break; 873 } 874 /* Restart Tx. */ 875 ste_restart_tx(sc); 876 } 877 /* 878 * Advance to next status and ACK TxComplete 879 * interrupt. ST201 data sheet was wrong here, to 880 * get next Tx status, we have to write both 881 * STE_TX_STATUS and STE_TX_FRAMEID register. 882 * Otherwise controller returns the same status 883 * as well as not acknowledge Tx completion 884 * interrupt. 885 */ 886 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 887 } 888} 889 890static void 891ste_tick(void *arg) 892{ 893 struct ste_softc *sc; 894 struct mii_data *mii; 895 896 sc = (struct ste_softc *)arg; 897 898 STE_LOCK_ASSERT(sc); 899 900 mii = device_get_softc(sc->ste_miibus); 901 mii_tick(mii); 902 /* 903 * ukphy(4) does not seem to generate CB that reports 904 * resolved link state so if we know we lost a link, 905 * explicitly check the link state. 906 */ 907 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 908 ste_miibus_statchg(sc->ste_dev); 909 /* 910 * Because we are not generating Tx completion 911 * interrupt for every frame, reclaim transmitted 912 * buffers here. 913 */ 914 ste_txeof(sc); 915 ste_txeoc(sc); 916 ste_stats_update(sc); 917 ste_watchdog(sc); 918 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 919} 920 921static void 922ste_txeof(struct ste_softc *sc) 923{ 924 struct ifnet *ifp; 925 struct ste_chain *cur_tx; 926 uint32_t txstat; 927 int idx; 928 929 STE_LOCK_ASSERT(sc); 930 931 ifp = sc->ste_ifp; 932 idx = sc->ste_cdata.ste_tx_cons; 933 if (idx == sc->ste_cdata.ste_tx_prod) 934 return; 935 936 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 937 sc->ste_cdata.ste_tx_list_map, 938 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 939 940 while (idx != sc->ste_cdata.ste_tx_prod) { 941 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 942 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 943 if ((txstat & STE_TXCTL_DMADONE) == 0) 944 break; 945 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 946 BUS_DMASYNC_POSTWRITE); 947 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 948 KASSERT(cur_tx->ste_mbuf != NULL, 949 ("%s: freeing NULL mbuf!\n", __func__)); 950 m_freem(cur_tx->ste_mbuf); 951 cur_tx->ste_mbuf = NULL; 952 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 953 ifp->if_opackets++; 954 sc->ste_cdata.ste_tx_cnt--; 955 STE_INC(idx, STE_TX_LIST_CNT); 956 } 957 958 sc->ste_cdata.ste_tx_cons = idx; 959 if (sc->ste_cdata.ste_tx_cnt == 0) 960 sc->ste_timer = 0; 961} 962 963static void 964ste_stats_clear(struct ste_softc *sc) 965{ 966 967 STE_LOCK_ASSERT(sc); 968 969 /* Rx stats. */ 970 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO); 971 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI); 972 CSR_READ_2(sc, STE_STAT_RX_FRAMES); 973 CSR_READ_1(sc, STE_STAT_RX_BCAST); 974 CSR_READ_1(sc, STE_STAT_RX_MCAST); 975 CSR_READ_1(sc, STE_STAT_RX_LOST); 976 /* Tx stats. */ 977 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO); 978 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI); 979 CSR_READ_2(sc, STE_STAT_TX_FRAMES); 980 CSR_READ_1(sc, STE_STAT_TX_BCAST); 981 CSR_READ_1(sc, STE_STAT_TX_MCAST); 982 CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 983 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 984 CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 985 CSR_READ_1(sc, STE_STAT_LATE_COLLS); 986 CSR_READ_1(sc, STE_STAT_TX_DEFER); 987 CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 988 CSR_READ_1(sc, STE_STAT_TX_ABORT); 989} 990 991static void 992ste_stats_update(struct ste_softc *sc) 993{ 994 struct ifnet *ifp; 995 struct ste_hw_stats *stats; 996 uint32_t val; 997 998 STE_LOCK_ASSERT(sc); 999 1000 ifp = sc->ste_ifp; 1001 stats = &sc->ste_stats; 1002 /* Rx stats. */ 1003 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) | 1004 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16; 1005 val &= 0x000FFFFF; 1006 stats->rx_bytes += val; 1007 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES); 1008 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST); 1009 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST); 1010 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST); 1011 /* Tx stats. */ 1012 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) | 1013 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16; 1014 val &= 0x000FFFFF; 1015 stats->tx_bytes += val; 1016 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES); 1017 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST); 1018 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST); 1019 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 1020 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 1021 stats->tx_single_colls += val; 1022 ifp->if_collisions += val; 1023 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 1024 stats->tx_multi_colls += val; 1025 ifp->if_collisions += val; 1026 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS); 1027 stats->tx_late_colls += val; 1028 ifp->if_collisions += val; 1029 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER); 1030 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 1031 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT); 1032} 1033 1034/* 1035 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 1036 * IDs against our list and return a device name if we find a match. 1037 */ 1038static int 1039ste_probe(device_t dev) 1040{ 1041 struct ste_type *t; 1042 1043 t = ste_devs; 1044 1045 while (t->ste_name != NULL) { 1046 if ((pci_get_vendor(dev) == t->ste_vid) && 1047 (pci_get_device(dev) == t->ste_did)) { 1048 device_set_desc(dev, t->ste_name); 1049 return (BUS_PROBE_DEFAULT); 1050 } 1051 t++; 1052 } 1053 1054 return (ENXIO); 1055} 1056 1057/* 1058 * Attach the interface. Allocate softc structures, do ifmedia 1059 * setup and ethernet/BPF attach. 1060 */ 1061static int 1062ste_attach(device_t dev) 1063{ 1064 struct ste_softc *sc; 1065 struct ifnet *ifp; 1066 u_char eaddr[6]; 1067 int error = 0, pmc, rid; 1068 1069 sc = device_get_softc(dev); 1070 sc->ste_dev = dev; 1071 1072 /* 1073 * Only use one PHY since this chip reports multiple 1074 * Note on the DFE-550 the PHY is at 1 on the DFE-580 1075 * it is at 0 & 1. It is rev 0x12. 1076 */ 1077 if (pci_get_vendor(dev) == DL_VENDORID && 1078 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1079 pci_get_revid(dev) == 0x12 ) 1080 sc->ste_flags |= STE_FLAG_ONE_PHY; 1081 1082 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1083 MTX_DEF); 1084 /* 1085 * Map control/status registers. 1086 */ 1087 pci_enable_busmaster(dev); 1088 1089 /* Prefer memory space register mapping over IO space. */ 1090 sc->ste_res_id = PCIR_BAR(1); 1091 sc->ste_res_type = SYS_RES_MEMORY; 1092 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 1093 &sc->ste_res_id, RF_ACTIVE); 1094 if (sc->ste_res == NULL) { 1095 sc->ste_res_id = PCIR_BAR(0); 1096 sc->ste_res_type = SYS_RES_IOPORT; 1097 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 1098 &sc->ste_res_id, RF_ACTIVE); 1099 } 1100 if (sc->ste_res == NULL) { 1101 device_printf(dev, "couldn't map ports/memory\n"); 1102 error = ENXIO; 1103 goto fail; 1104 } 1105 1106 /* Allocate interrupt */ 1107 rid = 0; 1108 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1109 RF_SHAREABLE | RF_ACTIVE); 1110 1111 if (sc->ste_irq == NULL) { 1112 device_printf(dev, "couldn't map interrupt\n"); 1113 error = ENXIO; 1114 goto fail; 1115 } 1116 1117 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 1118 1119 /* Reset the adapter. */ 1120 ste_reset(sc); 1121 1122 /* 1123 * Get station address from the EEPROM. 1124 */ 1125 if (ste_read_eeprom(sc, eaddr, 1126 STE_EEADDR_NODE0, 3, 0)) { 1127 device_printf(dev, "failed to read station address\n"); 1128 error = ENXIO;; 1129 goto fail; 1130 } 1131 ste_sysctl_node(sc); 1132 1133 if ((error = ste_dma_alloc(sc)) != 0) 1134 goto fail; 1135 1136 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1137 if (ifp == NULL) { 1138 device_printf(dev, "can not if_alloc()\n"); 1139 error = ENOSPC; 1140 goto fail; 1141 } 1142 1143 /* Do MII setup. */ 1144 if (mii_phy_probe(dev, &sc->ste_miibus, 1145 ste_ifmedia_upd, ste_ifmedia_sts)) { 1146 device_printf(dev, "MII without any phy!\n"); 1147 error = ENXIO; 1148 goto fail; 1149 } 1150 1151 ifp->if_softc = sc; 1152 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1153 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1154 ifp->if_ioctl = ste_ioctl; 1155 ifp->if_start = ste_start; 1156 ifp->if_init = ste_init; 1157 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1158 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1159 IFQ_SET_READY(&ifp->if_snd); 1160 1161 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1162 1163 /* 1164 * Call MI attach routine. 1165 */ 1166 ether_ifattach(ifp, eaddr); 1167 1168 /* 1169 * Tell the upper layer(s) we support long frames. 1170 */ 1171 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1172 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1173 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 1174 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1175 ifp->if_capenable = ifp->if_capabilities; 1176#ifdef DEVICE_POLLING 1177 ifp->if_capabilities |= IFCAP_POLLING; 1178#endif 1179 1180 /* Hook interrupt last to avoid having to lock softc */ 1181 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1182 NULL, ste_intr, sc, &sc->ste_intrhand); 1183 1184 if (error) { 1185 device_printf(dev, "couldn't set up irq\n"); 1186 ether_ifdetach(ifp); 1187 goto fail; 1188 } 1189 1190fail: 1191 if (error) 1192 ste_detach(dev); 1193 1194 return (error); 1195} 1196 1197/* 1198 * Shutdown hardware and free up resources. This can be called any 1199 * time after the mutex has been initialized. It is called in both 1200 * the error case in attach and the normal detach case so it needs 1201 * to be careful about only freeing resources that have actually been 1202 * allocated. 1203 */ 1204static int 1205ste_detach(device_t dev) 1206{ 1207 struct ste_softc *sc; 1208 struct ifnet *ifp; 1209 1210 sc = device_get_softc(dev); 1211 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1212 ifp = sc->ste_ifp; 1213 1214#ifdef DEVICE_POLLING 1215 if (ifp->if_capenable & IFCAP_POLLING) 1216 ether_poll_deregister(ifp); 1217#endif 1218 1219 /* These should only be active if attach succeeded */ 1220 if (device_is_attached(dev)) { 1221 ether_ifdetach(ifp); 1222 STE_LOCK(sc); 1223 ste_stop(sc); 1224 STE_UNLOCK(sc); 1225 callout_drain(&sc->ste_callout); 1226 } 1227 if (sc->ste_miibus) 1228 device_delete_child(dev, sc->ste_miibus); 1229 bus_generic_detach(dev); 1230 1231 if (sc->ste_intrhand) 1232 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1233 if (sc->ste_irq) 1234 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1235 if (sc->ste_res) 1236 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1237 sc->ste_res); 1238 1239 if (ifp) 1240 if_free(ifp); 1241 1242 ste_dma_free(sc); 1243 mtx_destroy(&sc->ste_mtx); 1244 1245 return (0); 1246} 1247 1248struct ste_dmamap_arg { 1249 bus_addr_t ste_busaddr; 1250}; 1251 1252static void 1253ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1254{ 1255 struct ste_dmamap_arg *ctx; 1256 1257 if (error != 0) 1258 return; 1259 1260 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1261 1262 ctx = (struct ste_dmamap_arg *)arg; 1263 ctx->ste_busaddr = segs[0].ds_addr; 1264} 1265 1266static int 1267ste_dma_alloc(struct ste_softc *sc) 1268{ 1269 struct ste_chain *txc; 1270 struct ste_chain_onefrag *rxc; 1271 struct ste_dmamap_arg ctx; 1272 int error, i; 1273 1274 /* Create parent DMA tag. */ 1275 error = bus_dma_tag_create( 1276 bus_get_dma_tag(sc->ste_dev), /* parent */ 1277 1, 0, /* alignment, boundary */ 1278 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1279 BUS_SPACE_MAXADDR, /* highaddr */ 1280 NULL, NULL, /* filter, filterarg */ 1281 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1282 0, /* nsegments */ 1283 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1284 0, /* flags */ 1285 NULL, NULL, /* lockfunc, lockarg */ 1286 &sc->ste_cdata.ste_parent_tag); 1287 if (error != 0) { 1288 device_printf(sc->ste_dev, 1289 "could not create parent DMA tag.\n"); 1290 goto fail; 1291 } 1292 1293 /* Create DMA tag for Tx descriptor list. */ 1294 error = bus_dma_tag_create( 1295 sc->ste_cdata.ste_parent_tag, /* parent */ 1296 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1297 BUS_SPACE_MAXADDR, /* lowaddr */ 1298 BUS_SPACE_MAXADDR, /* highaddr */ 1299 NULL, NULL, /* filter, filterarg */ 1300 STE_TX_LIST_SZ, /* maxsize */ 1301 1, /* nsegments */ 1302 STE_TX_LIST_SZ, /* maxsegsize */ 1303 0, /* flags */ 1304 NULL, NULL, /* lockfunc, lockarg */ 1305 &sc->ste_cdata.ste_tx_list_tag); 1306 if (error != 0) { 1307 device_printf(sc->ste_dev, 1308 "could not create Tx list DMA tag.\n"); 1309 goto fail; 1310 } 1311 1312 /* Create DMA tag for Rx descriptor list. */ 1313 error = bus_dma_tag_create( 1314 sc->ste_cdata.ste_parent_tag, /* parent */ 1315 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1316 BUS_SPACE_MAXADDR, /* lowaddr */ 1317 BUS_SPACE_MAXADDR, /* highaddr */ 1318 NULL, NULL, /* filter, filterarg */ 1319 STE_RX_LIST_SZ, /* maxsize */ 1320 1, /* nsegments */ 1321 STE_RX_LIST_SZ, /* maxsegsize */ 1322 0, /* flags */ 1323 NULL, NULL, /* lockfunc, lockarg */ 1324 &sc->ste_cdata.ste_rx_list_tag); 1325 if (error != 0) { 1326 device_printf(sc->ste_dev, 1327 "could not create Rx list DMA tag.\n"); 1328 goto fail; 1329 } 1330 1331 /* Create DMA tag for Tx buffers. */ 1332 error = bus_dma_tag_create( 1333 sc->ste_cdata.ste_parent_tag, /* parent */ 1334 1, 0, /* alignment, boundary */ 1335 BUS_SPACE_MAXADDR, /* lowaddr */ 1336 BUS_SPACE_MAXADDR, /* highaddr */ 1337 NULL, NULL, /* filter, filterarg */ 1338 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1339 STE_MAXFRAGS, /* nsegments */ 1340 MCLBYTES, /* maxsegsize */ 1341 0, /* flags */ 1342 NULL, NULL, /* lockfunc, lockarg */ 1343 &sc->ste_cdata.ste_tx_tag); 1344 if (error != 0) { 1345 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1346 goto fail; 1347 } 1348 1349 /* Create DMA tag for Rx buffers. */ 1350 error = bus_dma_tag_create( 1351 sc->ste_cdata.ste_parent_tag, /* parent */ 1352 1, 0, /* alignment, boundary */ 1353 BUS_SPACE_MAXADDR, /* lowaddr */ 1354 BUS_SPACE_MAXADDR, /* highaddr */ 1355 NULL, NULL, /* filter, filterarg */ 1356 MCLBYTES, /* maxsize */ 1357 1, /* nsegments */ 1358 MCLBYTES, /* maxsegsize */ 1359 0, /* flags */ 1360 NULL, NULL, /* lockfunc, lockarg */ 1361 &sc->ste_cdata.ste_rx_tag); 1362 if (error != 0) { 1363 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1364 goto fail; 1365 } 1366 1367 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1368 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1369 (void **)&sc->ste_ldata.ste_tx_list, 1370 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1371 &sc->ste_cdata.ste_tx_list_map); 1372 if (error != 0) { 1373 device_printf(sc->ste_dev, 1374 "could not allocate DMA'able memory for Tx list.\n"); 1375 goto fail; 1376 } 1377 ctx.ste_busaddr = 0; 1378 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1379 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1380 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1381 if (error != 0 || ctx.ste_busaddr == 0) { 1382 device_printf(sc->ste_dev, 1383 "could not load DMA'able memory for Tx list.\n"); 1384 goto fail; 1385 } 1386 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1387 1388 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1389 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1390 (void **)&sc->ste_ldata.ste_rx_list, 1391 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1392 &sc->ste_cdata.ste_rx_list_map); 1393 if (error != 0) { 1394 device_printf(sc->ste_dev, 1395 "could not allocate DMA'able memory for Rx list.\n"); 1396 goto fail; 1397 } 1398 ctx.ste_busaddr = 0; 1399 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1400 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1401 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1402 if (error != 0 || ctx.ste_busaddr == 0) { 1403 device_printf(sc->ste_dev, 1404 "could not load DMA'able memory for Rx list.\n"); 1405 goto fail; 1406 } 1407 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1408 1409 /* Create DMA maps for Tx buffers. */ 1410 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1411 txc = &sc->ste_cdata.ste_tx_chain[i]; 1412 txc->ste_ptr = NULL; 1413 txc->ste_mbuf = NULL; 1414 txc->ste_next = NULL; 1415 txc->ste_phys = 0; 1416 txc->ste_map = NULL; 1417 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1418 &txc->ste_map); 1419 if (error != 0) { 1420 device_printf(sc->ste_dev, 1421 "could not create Tx dmamap.\n"); 1422 goto fail; 1423 } 1424 } 1425 /* Create DMA maps for Rx buffers. */ 1426 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1427 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1428 device_printf(sc->ste_dev, 1429 "could not create spare Rx dmamap.\n"); 1430 goto fail; 1431 } 1432 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1433 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1434 rxc->ste_ptr = NULL; 1435 rxc->ste_mbuf = NULL; 1436 rxc->ste_next = NULL; 1437 rxc->ste_map = NULL; 1438 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1439 &rxc->ste_map); 1440 if (error != 0) { 1441 device_printf(sc->ste_dev, 1442 "could not create Rx dmamap.\n"); 1443 goto fail; 1444 } 1445 } 1446 1447fail: 1448 return (error); 1449} 1450 1451static void 1452ste_dma_free(struct ste_softc *sc) 1453{ 1454 struct ste_chain *txc; 1455 struct ste_chain_onefrag *rxc; 1456 int i; 1457 1458 /* Tx buffers. */ 1459 if (sc->ste_cdata.ste_tx_tag != NULL) { 1460 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1461 txc = &sc->ste_cdata.ste_tx_chain[i]; 1462 if (txc->ste_map != NULL) { 1463 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1464 txc->ste_map); 1465 txc->ste_map = NULL; 1466 } 1467 } 1468 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1469 sc->ste_cdata.ste_tx_tag = NULL; 1470 } 1471 /* Rx buffers. */ 1472 if (sc->ste_cdata.ste_rx_tag != NULL) { 1473 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1474 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1475 if (rxc->ste_map != NULL) { 1476 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1477 rxc->ste_map); 1478 rxc->ste_map = NULL; 1479 } 1480 } 1481 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1482 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1483 sc->ste_cdata.ste_rx_sparemap); 1484 sc->ste_cdata.ste_rx_sparemap = NULL; 1485 } 1486 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1487 sc->ste_cdata.ste_rx_tag = NULL; 1488 } 1489 /* Tx descriptor list. */ 1490 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1491 if (sc->ste_cdata.ste_tx_list_map != NULL) 1492 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1493 sc->ste_cdata.ste_tx_list_map); 1494 if (sc->ste_cdata.ste_tx_list_map != NULL && 1495 sc->ste_ldata.ste_tx_list != NULL) 1496 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1497 sc->ste_ldata.ste_tx_list, 1498 sc->ste_cdata.ste_tx_list_map); 1499 sc->ste_ldata.ste_tx_list = NULL; 1500 sc->ste_cdata.ste_tx_list_map = NULL; 1501 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1502 sc->ste_cdata.ste_tx_list_tag = NULL; 1503 } 1504 /* Rx descriptor list. */ 1505 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1506 if (sc->ste_cdata.ste_rx_list_map != NULL) 1507 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1508 sc->ste_cdata.ste_rx_list_map); 1509 if (sc->ste_cdata.ste_rx_list_map != NULL && 1510 sc->ste_ldata.ste_rx_list != NULL) 1511 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1512 sc->ste_ldata.ste_rx_list, 1513 sc->ste_cdata.ste_rx_list_map); 1514 sc->ste_ldata.ste_rx_list = NULL; 1515 sc->ste_cdata.ste_rx_list_map = NULL; 1516 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1517 sc->ste_cdata.ste_rx_list_tag = NULL; 1518 } 1519 if (sc->ste_cdata.ste_parent_tag != NULL) { 1520 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1521 sc->ste_cdata.ste_parent_tag = NULL; 1522 } 1523} 1524 1525static int 1526ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1527{ 1528 struct mbuf *m; 1529 bus_dma_segment_t segs[1]; 1530 bus_dmamap_t map; 1531 int error, nsegs; 1532 1533 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1534 if (m == NULL) 1535 return (ENOBUFS); 1536 m->m_len = m->m_pkthdr.len = MCLBYTES; 1537 m_adj(m, ETHER_ALIGN); 1538 1539 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1540 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1541 m_freem(m); 1542 return (error); 1543 } 1544 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1545 1546 if (rxc->ste_mbuf != NULL) { 1547 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1548 BUS_DMASYNC_POSTREAD); 1549 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1550 } 1551 map = rxc->ste_map; 1552 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1553 sc->ste_cdata.ste_rx_sparemap = map; 1554 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1555 BUS_DMASYNC_PREREAD); 1556 rxc->ste_mbuf = m; 1557 rxc->ste_ptr->ste_status = 0; 1558 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1559 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1560 STE_FRAG_LAST); 1561 return (0); 1562} 1563 1564static int 1565ste_init_rx_list(struct ste_softc *sc) 1566{ 1567 struct ste_chain_data *cd; 1568 struct ste_list_data *ld; 1569 int error, i; 1570 1571 sc->ste_int_rx_act = 0; 1572 cd = &sc->ste_cdata; 1573 ld = &sc->ste_ldata; 1574 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1575 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1576 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1577 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1578 if (error != 0) 1579 return (error); 1580 if (i == (STE_RX_LIST_CNT - 1)) { 1581 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1582 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1583 (sizeof(struct ste_desc_onefrag) * 0); 1584 } else { 1585 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1586 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1587 (sizeof(struct ste_desc_onefrag) * (i + 1)); 1588 } 1589 } 1590 1591 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1592 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1593 sc->ste_cdata.ste_rx_list_map, 1594 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1595 1596 return (0); 1597} 1598 1599static void 1600ste_init_tx_list(struct ste_softc *sc) 1601{ 1602 struct ste_chain_data *cd; 1603 struct ste_list_data *ld; 1604 int i; 1605 1606 cd = &sc->ste_cdata; 1607 ld = &sc->ste_ldata; 1608 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1609 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1610 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1611 cd->ste_tx_chain[i].ste_mbuf = NULL; 1612 if (i == (STE_TX_LIST_CNT - 1)) { 1613 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1614 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1615 ld->ste_tx_list_paddr + 1616 (sizeof(struct ste_desc) * 0))); 1617 } else { 1618 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1619 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1620 ld->ste_tx_list_paddr + 1621 (sizeof(struct ste_desc) * (i + 1)))); 1622 } 1623 } 1624 1625 cd->ste_last_tx = NULL; 1626 cd->ste_tx_prod = 0; 1627 cd->ste_tx_cons = 0; 1628 cd->ste_tx_cnt = 0; 1629 1630 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1631 sc->ste_cdata.ste_tx_list_map, 1632 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1633} 1634 1635static void 1636ste_init(void *xsc) 1637{ 1638 struct ste_softc *sc; 1639 1640 sc = xsc; 1641 STE_LOCK(sc); 1642 ste_init_locked(sc); 1643 STE_UNLOCK(sc); 1644} 1645 1646static void 1647ste_init_locked(struct ste_softc *sc) 1648{ 1649 struct ifnet *ifp; 1650 struct mii_data *mii; 1651 uint8_t val; 1652 int i; 1653 1654 STE_LOCK_ASSERT(sc); 1655 ifp = sc->ste_ifp; 1656 mii = device_get_softc(sc->ste_miibus); 1657 1658 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1659 return; 1660 1661 ste_stop(sc); 1662 /* Reset the chip to a known state. */ 1663 ste_reset(sc); 1664 1665 /* Init our MAC address */ 1666 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1667 CSR_WRITE_2(sc, STE_PAR0 + i, 1668 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1669 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1670 } 1671 1672 /* Init RX list */ 1673 if (ste_init_rx_list(sc) != 0) { 1674 device_printf(sc->ste_dev, 1675 "initialization failed: no memory for RX buffers\n"); 1676 ste_stop(sc); 1677 return; 1678 } 1679 1680 /* Set RX polling interval */ 1681 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1682 1683 /* Init TX descriptors */ 1684 ste_init_tx_list(sc); 1685 1686 /* Clear and disable WOL. */ 1687 val = CSR_READ_1(sc, STE_WAKE_EVENT); 1688 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 1689 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 1690 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 1691 1692 /* Set the TX freethresh value */ 1693 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1694 1695 /* Set the TX start threshold for best performance. */ 1696 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1697 1698 /* Set the TX reclaim threshold. */ 1699 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1700 1701 /* Accept VLAN length packets */ 1702 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1703 1704 /* Set up the RX filter. */ 1705 ste_rxfilter(sc); 1706 1707 /* Load the address of the RX list. */ 1708 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1709 ste_wait(sc); 1710 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1711 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1712 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1713 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1714 1715 /* Set TX polling interval(defer until we TX first packet). */ 1716 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1717 1718 /* Load address of the TX list */ 1719 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1720 ste_wait(sc); 1721 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1722 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1723 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1724 ste_wait(sc); 1725 /* Select 3.2us timer. */ 1726 STE_CLRBIT4(sc, STE_DMACTL, STE_DMACTL_COUNTDOWN_SPEED | 1727 STE_DMACTL_COUNTDOWN_MODE); 1728 1729 /* Enable receiver and transmitter */ 1730 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1731 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1732 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1733 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1734 1735 /* Enable stats counters. */ 1736 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1737 /* Clear stats counters. */ 1738 ste_stats_clear(sc); 1739 1740 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1741 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1742#ifdef DEVICE_POLLING 1743 /* Disable interrupts if we are polling. */ 1744 if (ifp->if_capenable & IFCAP_POLLING) 1745 CSR_WRITE_2(sc, STE_IMR, 0); 1746 else 1747#endif 1748 /* Enable interrupts. */ 1749 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1750 1751 sc->ste_flags &= ~STE_FLAG_LINK; 1752 /* Switch to the current media. */ 1753 mii_mediachg(mii); 1754 1755 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1756 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1757 1758 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1759} 1760 1761static void 1762ste_stop(struct ste_softc *sc) 1763{ 1764 struct ifnet *ifp; 1765 struct ste_chain_onefrag *cur_rx; 1766 struct ste_chain *cur_tx; 1767 uint32_t val; 1768 int i; 1769 1770 STE_LOCK_ASSERT(sc); 1771 ifp = sc->ste_ifp; 1772 1773 callout_stop(&sc->ste_callout); 1774 sc->ste_timer = 0; 1775 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1776 1777 CSR_WRITE_2(sc, STE_IMR, 0); 1778 CSR_WRITE_2(sc, STE_COUNTDOWN, 0); 1779 /* Stop pending DMA. */ 1780 val = CSR_READ_4(sc, STE_DMACTL); 1781 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1782 CSR_WRITE_4(sc, STE_DMACTL, val); 1783 ste_wait(sc); 1784 /* Disable auto-polling. */ 1785 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1786 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1787 /* Nullify DMA address to stop any further DMA. */ 1788 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1789 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1790 /* Stop TX/RX MAC. */ 1791 val = CSR_READ_2(sc, STE_MACCTL1); 1792 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1793 STE_MACCTL1_STATS_DISABLE; 1794 CSR_WRITE_2(sc, STE_MACCTL1, val); 1795 for (i = 0; i < STE_TIMEOUT; i++) { 1796 DELAY(10); 1797 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1798 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1799 break; 1800 } 1801 if (i == STE_TIMEOUT) 1802 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1803 /* Acknowledge any pending interrupts. */ 1804 CSR_READ_2(sc, STE_ISR_ACK); 1805 ste_stats_update(sc); 1806 1807 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1808 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1809 if (cur_rx->ste_mbuf != NULL) { 1810 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1811 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1812 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1813 cur_rx->ste_map); 1814 m_freem(cur_rx->ste_mbuf); 1815 cur_rx->ste_mbuf = NULL; 1816 } 1817 } 1818 1819 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1820 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1821 if (cur_tx->ste_mbuf != NULL) { 1822 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1823 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1824 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1825 cur_tx->ste_map); 1826 m_freem(cur_tx->ste_mbuf); 1827 cur_tx->ste_mbuf = NULL; 1828 } 1829 } 1830} 1831 1832static void 1833ste_reset(struct ste_softc *sc) 1834{ 1835 uint32_t ctl; 1836 int i; 1837 1838 ctl = CSR_READ_4(sc, STE_ASICCTL); 1839 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET | 1840 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET | 1841 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET | 1842 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET | 1843 STE_ASICCTL_EXTRESET_RESET; 1844 CSR_WRITE_4(sc, STE_ASICCTL, ctl); 1845 CSR_READ_4(sc, STE_ASICCTL); 1846 /* 1847 * Due to the need of accessing EEPROM controller can take 1848 * up to 1ms to complete the global reset. 1849 */ 1850 DELAY(1000); 1851 1852 for (i = 0; i < STE_TIMEOUT; i++) { 1853 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1854 break; 1855 DELAY(10); 1856 } 1857 1858 if (i == STE_TIMEOUT) 1859 device_printf(sc->ste_dev, "global reset never completed\n"); 1860} 1861 1862static void 1863ste_restart_tx(struct ste_softc *sc) 1864{ 1865 uint16_t mac; 1866 int i; 1867 1868 for (i = 0; i < STE_TIMEOUT; i++) { 1869 mac = CSR_READ_2(sc, STE_MACCTL1); 1870 mac |= STE_MACCTL1_TX_ENABLE; 1871 CSR_WRITE_2(sc, STE_MACCTL1, mac); 1872 mac = CSR_READ_2(sc, STE_MACCTL1); 1873 if ((mac & STE_MACCTL1_TX_ENABLED) != 0) 1874 break; 1875 DELAY(10); 1876 } 1877 1878 if (i == STE_TIMEOUT) 1879 device_printf(sc->ste_dev, "starting Tx failed"); 1880} 1881 1882static int 1883ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1884{ 1885 struct ste_softc *sc; 1886 struct ifreq *ifr; 1887 struct mii_data *mii; 1888 int error = 0, mask; 1889 1890 sc = ifp->if_softc; 1891 ifr = (struct ifreq *)data; 1892 1893 switch (command) { 1894 case SIOCSIFFLAGS: 1895 STE_LOCK(sc); 1896 if ((ifp->if_flags & IFF_UP) != 0) { 1897 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1898 ((ifp->if_flags ^ sc->ste_if_flags) & 1899 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1900 ste_rxfilter(sc); 1901 else 1902 ste_init_locked(sc); 1903 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1904 ste_stop(sc); 1905 sc->ste_if_flags = ifp->if_flags; 1906 STE_UNLOCK(sc); 1907 break; 1908 case SIOCADDMULTI: 1909 case SIOCDELMULTI: 1910 STE_LOCK(sc); 1911 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1912 ste_rxfilter(sc); 1913 STE_UNLOCK(sc); 1914 break; 1915 case SIOCGIFMEDIA: 1916 case SIOCSIFMEDIA: 1917 mii = device_get_softc(sc->ste_miibus); 1918 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1919 break; 1920 case SIOCSIFCAP: 1921 STE_LOCK(sc); 1922 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1923#ifdef DEVICE_POLLING 1924 if ((mask & IFCAP_POLLING) != 0 && 1925 (IFCAP_POLLING & ifp->if_capabilities) != 0) { 1926 ifp->if_capenable ^= IFCAP_POLLING; 1927 if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 1928 error = ether_poll_register(ste_poll, ifp); 1929 if (error != 0) { 1930 STE_UNLOCK(sc); 1931 break; 1932 } 1933 /* Disable interrupts. */ 1934 CSR_WRITE_2(sc, STE_IMR, 0); 1935 } else { 1936 error = ether_poll_deregister(ifp); 1937 /* Enable interrupts. */ 1938 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1939 } 1940 } 1941#endif /* DEVICE_POLLING */ 1942 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1943 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1944 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1945 STE_UNLOCK(sc); 1946 break; 1947 default: 1948 error = ether_ioctl(ifp, command, data); 1949 break; 1950 } 1951 1952 return (error); 1953} 1954 1955static int 1956ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1957{ 1958 struct ste_frag *frag; 1959 struct mbuf *m; 1960 struct ste_desc *desc; 1961 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1962 int error, i, nsegs; 1963 1964 STE_LOCK_ASSERT(sc); 1965 M_ASSERTPKTHDR((*m_head)); 1966 1967 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1968 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1969 if (error == EFBIG) { 1970 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS); 1971 if (m == NULL) { 1972 m_freem(*m_head); 1973 *m_head = NULL; 1974 return (ENOMEM); 1975 } 1976 *m_head = m; 1977 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1978 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1979 if (error != 0) { 1980 m_freem(*m_head); 1981 *m_head = NULL; 1982 return (error); 1983 } 1984 } else if (error != 0) 1985 return (error); 1986 if (nsegs == 0) { 1987 m_freem(*m_head); 1988 *m_head = NULL; 1989 return (EIO); 1990 } 1991 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1992 BUS_DMASYNC_PREWRITE); 1993 1994 desc = txc->ste_ptr; 1995 for (i = 0; i < nsegs; i++) { 1996 frag = &desc->ste_frags[i]; 1997 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1998 frag->ste_len = htole32(txsegs[i].ds_len); 1999 } 2000 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 2001 /* 2002 * Because we use Tx polling we can't chain multiple 2003 * Tx descriptors here. Otherwise we race with controller. 2004 */ 2005 desc->ste_next = 0; 2006 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0) 2007 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | 2008 STE_TXCTL_DMAINTR); 2009 else 2010 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS); 2011 txc->ste_mbuf = *m_head; 2012 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 2013 sc->ste_cdata.ste_tx_cnt++; 2014 2015 return (0); 2016} 2017 2018static void 2019ste_start(struct ifnet *ifp) 2020{ 2021 struct ste_softc *sc; 2022 2023 sc = ifp->if_softc; 2024 STE_LOCK(sc); 2025 ste_start_locked(ifp); 2026 STE_UNLOCK(sc); 2027} 2028 2029static void 2030ste_start_locked(struct ifnet *ifp) 2031{ 2032 struct ste_softc *sc; 2033 struct ste_chain *cur_tx; 2034 struct mbuf *m_head = NULL; 2035 int enq; 2036 2037 sc = ifp->if_softc; 2038 STE_LOCK_ASSERT(sc); 2039 2040 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2041 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 2042 return; 2043 2044 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 2045 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 2046 /* 2047 * Controller may have cached copy of the last used 2048 * next ptr so we have to reserve one TFD to avoid 2049 * TFD overruns. 2050 */ 2051 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2052 break; 2053 } 2054 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2055 if (m_head == NULL) 2056 break; 2057 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 2058 if (ste_encap(sc, &m_head, cur_tx) != 0) { 2059 if (m_head == NULL) 2060 break; 2061 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2062 break; 2063 } 2064 if (sc->ste_cdata.ste_last_tx == NULL) { 2065 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 2066 sc->ste_cdata.ste_tx_list_map, 2067 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2068 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 2069 ste_wait(sc); 2070 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 2071 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 2072 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 2073 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 2074 ste_wait(sc); 2075 } else { 2076 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 2077 sc->ste_cdata.ste_last_tx->ste_phys; 2078 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 2079 sc->ste_cdata.ste_tx_list_map, 2080 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2081 } 2082 sc->ste_cdata.ste_last_tx = cur_tx; 2083 2084 enq++; 2085 /* 2086 * If there's a BPF listener, bounce a copy of this frame 2087 * to him. 2088 */ 2089 BPF_MTAP(ifp, m_head); 2090 } 2091 2092 if (enq > 0) 2093 sc->ste_timer = STE_TX_TIMEOUT; 2094} 2095 2096static void 2097ste_watchdog(struct ste_softc *sc) 2098{ 2099 struct ifnet *ifp; 2100 2101 ifp = sc->ste_ifp; 2102 STE_LOCK_ASSERT(sc); 2103 2104 if (sc->ste_timer == 0 || --sc->ste_timer) 2105 return; 2106 2107 ifp->if_oerrors++; 2108 if_printf(ifp, "watchdog timeout\n"); 2109 2110 ste_txeof(sc); 2111 ste_txeoc(sc); 2112 ste_rxeof(sc, -1); 2113 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2114 ste_init_locked(sc); 2115 2116 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2117 ste_start_locked(ifp); 2118} 2119 2120static int 2121ste_shutdown(device_t dev) 2122{ 2123 2124 return (ste_suspend(dev)); 2125} 2126 2127static int 2128ste_suspend(device_t dev) 2129{ 2130 struct ste_softc *sc; 2131 2132 sc = device_get_softc(dev); 2133 2134 STE_LOCK(sc); 2135 ste_stop(sc); 2136 ste_setwol(sc); 2137 STE_UNLOCK(sc); 2138 2139 return (0); 2140} 2141 2142static int 2143ste_resume(device_t dev) 2144{ 2145 struct ste_softc *sc; 2146 struct ifnet *ifp; 2147 int pmc; 2148 uint16_t pmstat; 2149 2150 sc = device_get_softc(dev); 2151 STE_LOCK(sc); 2152 if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) == 0) { 2153 /* Disable PME and clear PME status. */ 2154 pmstat = pci_read_config(sc->ste_dev, 2155 pmc + PCIR_POWER_STATUS, 2); 2156 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2157 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2158 pci_write_config(sc->ste_dev, 2159 pmc + PCIR_POWER_STATUS, pmstat, 2); 2160 } 2161 } 2162 ifp = sc->ste_ifp; 2163 if ((ifp->if_flags & IFF_UP) != 0) { 2164 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2165 ste_init_locked(sc); 2166 } 2167 STE_UNLOCK(sc); 2168 2169 return (0); 2170} 2171 2172#define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2173 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2174#define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2175 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2176 2177static void 2178ste_sysctl_node(struct ste_softc *sc) 2179{ 2180 struct sysctl_ctx_list *ctx; 2181 struct sysctl_oid_list *child, *parent; 2182 struct sysctl_oid *tree; 2183 struct ste_hw_stats *stats; 2184 2185 stats = &sc->ste_stats; 2186 ctx = device_get_sysctl_ctx(sc->ste_dev); 2187 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev)); 2188 2189 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_rx_mod", 2190 CTLFLAG_RW, &sc->ste_int_rx_mod, 0, "ste RX interrupt moderation"); 2191 /* Pull in device tunables. */ 2192 sc->ste_int_rx_mod = STE_IM_RX_TIMER_DEFAULT; 2193 resource_int_value(device_get_name(sc->ste_dev), 2194 device_get_unit(sc->ste_dev), "int_rx_mod", &sc->ste_int_rx_mod); 2195 2196 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 2197 NULL, "STE statistics"); 2198 parent = SYSCTL_CHILDREN(tree); 2199 2200 /* Rx statistics. */ 2201 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 2202 NULL, "Rx MAC statistics"); 2203 child = SYSCTL_CHILDREN(tree); 2204 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2205 &stats->rx_bytes, "Good octets"); 2206 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2207 &stats->rx_frames, "Good frames"); 2208 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2209 &stats->rx_bcast_frames, "Good broadcast frames"); 2210 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2211 &stats->rx_mcast_frames, "Good multicast frames"); 2212 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames", 2213 &stats->rx_lost_frames, "Lost frames"); 2214 2215 /* Tx statistics. */ 2216 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 2217 NULL, "Tx MAC statistics"); 2218 child = SYSCTL_CHILDREN(tree); 2219 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2220 &stats->tx_bytes, "Good octets"); 2221 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2222 &stats->tx_frames, "Good frames"); 2223 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2224 &stats->tx_bcast_frames, "Good broadcast frames"); 2225 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2226 &stats->tx_mcast_frames, "Good multicast frames"); 2227 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs", 2228 &stats->tx_carrsense_errs, "Carrier sense errors"); 2229 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 2230 &stats->tx_single_colls, "Single collisions"); 2231 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 2232 &stats->tx_multi_colls, "Multiple collisions"); 2233 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2234 &stats->tx_late_colls, "Late collisions"); 2235 STE_SYSCTL_STAT_ADD32(ctx, child, "defers", 2236 &stats->tx_frames_defered, "Frames with deferrals"); 2237 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 2238 &stats->tx_excess_defers, "Frames with excessive derferrals"); 2239 STE_SYSCTL_STAT_ADD32(ctx, child, "abort", 2240 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 2241} 2242 2243#undef STE_SYSCTL_STAT_ADD32 2244#undef STE_SYSCTL_STAT_ADD64 2245 2246static void 2247ste_setwol(struct ste_softc *sc) 2248{ 2249 struct ifnet *ifp; 2250 uint16_t pmstat; 2251 uint8_t val; 2252 int pmc; 2253 2254 STE_LOCK_ASSERT(sc); 2255 2256 if (pci_find_extcap(sc->ste_dev, PCIY_PMG, &pmc) != 0) { 2257 /* Disable WOL. */ 2258 CSR_READ_1(sc, STE_WAKE_EVENT); 2259 CSR_WRITE_1(sc, STE_WAKE_EVENT, 0); 2260 return; 2261 } 2262 2263 ifp = sc->ste_ifp; 2264 val = CSR_READ_1(sc, STE_WAKE_EVENT); 2265 val &= ~(STE_WAKEEVENT_WAKEPKT_ENB | STE_WAKEEVENT_MAGICPKT_ENB | 2266 STE_WAKEEVENT_LINKEVT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB); 2267 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2268 val |= STE_WAKEEVENT_MAGICPKT_ENB | STE_WAKEEVENT_WAKEONLAN_ENB; 2269 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); 2270 /* Request PME. */ 2271 pmstat = pci_read_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, 2); 2272 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2273 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2274 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2275 pci_write_config(sc->ste_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2276} 2277