if_ste.c revision 200913
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 200913 2009-12-23 19:38:22Z yongari $"); 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53 54#include <net/bpf.h> 55#include <net/if.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61#include <net/if_vlan_var.h> 62 63#include <machine/bus.h> 64#include <machine/resource.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <dev/ste/if_stereg.h> 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77MODULE_DEPEND(ste, pci, 1, 1, 1); 78MODULE_DEPEND(ste, ether, 1, 1, 1); 79MODULE_DEPEND(ste, miibus, 1, 1, 1); 80 81/* Define to show Tx error status. */ 82#define STE_SHOW_TXERRORS 83 84/* 85 * Various supported device vendors/types and their names. 86 */ 87static struct ste_type ste_devs[] = { 88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 91 { 0, 0, NULL } 92}; 93 94static int ste_attach(device_t); 95static int ste_detach(device_t); 96static int ste_probe(device_t); 97static int ste_shutdown(device_t); 98 99static int ste_dma_alloc(struct ste_softc *); 100static void ste_dma_free(struct ste_softc *); 101static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 102static int ste_eeprom_wait(struct ste_softc *); 103static int ste_encap(struct ste_softc *, struct mbuf **, 104 struct ste_chain *); 105static int ste_ifmedia_upd(struct ifnet *); 106static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 107static void ste_init(void *); 108static void ste_init_locked(struct ste_softc *); 109static int ste_init_rx_list(struct ste_softc *); 110static void ste_init_tx_list(struct ste_softc *); 111static void ste_intr(void *); 112static int ste_ioctl(struct ifnet *, u_long, caddr_t); 113static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 114static void ste_mii_send(struct ste_softc *, uint32_t, int); 115static void ste_mii_sync(struct ste_softc *); 116static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 117static int ste_miibus_readreg(device_t, int, int); 118static void ste_miibus_statchg(device_t); 119static int ste_miibus_writereg(device_t, int, int, int); 120static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 121static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 122static void ste_reset(struct ste_softc *); 123static void ste_restart_tx(struct ste_softc *); 124static int ste_rxeof(struct ste_softc *, int); 125static void ste_rxfilter(struct ste_softc *); 126static void ste_start(struct ifnet *); 127static void ste_start_locked(struct ifnet *); 128static void ste_stats_clear(struct ste_softc *); 129static void ste_stats_update(struct ste_softc *); 130static void ste_stop(struct ste_softc *); 131static void ste_sysctl_node(struct ste_softc *); 132static void ste_tick(void *); 133static void ste_txeoc(struct ste_softc *); 134static void ste_txeof(struct ste_softc *); 135static void ste_wait(struct ste_softc *); 136static void ste_watchdog(struct ste_softc *); 137 138static device_method_t ste_methods[] = { 139 /* Device interface */ 140 DEVMETHOD(device_probe, ste_probe), 141 DEVMETHOD(device_attach, ste_attach), 142 DEVMETHOD(device_detach, ste_detach), 143 DEVMETHOD(device_shutdown, ste_shutdown), 144 145 /* bus interface */ 146 DEVMETHOD(bus_print_child, bus_generic_print_child), 147 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 148 149 /* MII interface */ 150 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 151 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 152 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 153 154 { 0, 0 } 155}; 156 157static driver_t ste_driver = { 158 "ste", 159 ste_methods, 160 sizeof(struct ste_softc) 161}; 162 163static devclass_t ste_devclass; 164 165DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 166DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 167 168#define STE_SETBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 170 171#define STE_CLRBIT4(sc, reg, x) \ 172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 173 174#define STE_SETBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 176 177#define STE_CLRBIT2(sc, reg, x) \ 178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 179 180#define STE_SETBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 182 183#define STE_CLRBIT1(sc, reg, x) \ 184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 185 186 187#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 188#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 189 190/* 191 * Sync the PHYs by setting data bit and strobing the clock 32 times. 192 */ 193static void 194ste_mii_sync(struct ste_softc *sc) 195{ 196 int i; 197 198 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 199 200 for (i = 0; i < 32; i++) { 201 MII_SET(STE_PHYCTL_MCLK); 202 DELAY(1); 203 MII_CLR(STE_PHYCTL_MCLK); 204 DELAY(1); 205 } 206} 207 208/* 209 * Clock a series of bits through the MII. 210 */ 211static void 212ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt) 213{ 214 int i; 215 216 MII_CLR(STE_PHYCTL_MCLK); 217 218 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 219 if (bits & i) { 220 MII_SET(STE_PHYCTL_MDATA); 221 } else { 222 MII_CLR(STE_PHYCTL_MDATA); 223 } 224 DELAY(1); 225 MII_CLR(STE_PHYCTL_MCLK); 226 DELAY(1); 227 MII_SET(STE_PHYCTL_MCLK); 228 } 229} 230 231/* 232 * Read an PHY register through the MII. 233 */ 234static int 235ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 236{ 237 int i, ack; 238 239 /* 240 * Set up frame for RX. 241 */ 242 frame->mii_stdelim = STE_MII_STARTDELIM; 243 frame->mii_opcode = STE_MII_READOP; 244 frame->mii_turnaround = 0; 245 frame->mii_data = 0; 246 247 CSR_WRITE_2(sc, STE_PHYCTL, 0); 248 /* 249 * Turn on data xmit. 250 */ 251 MII_SET(STE_PHYCTL_MDIR); 252 253 ste_mii_sync(sc); 254 255 /* 256 * Send command/address info. 257 */ 258 ste_mii_send(sc, frame->mii_stdelim, 2); 259 ste_mii_send(sc, frame->mii_opcode, 2); 260 ste_mii_send(sc, frame->mii_phyaddr, 5); 261 ste_mii_send(sc, frame->mii_regaddr, 5); 262 263 /* Turn off xmit. */ 264 MII_CLR(STE_PHYCTL_MDIR); 265 266 /* Idle bit */ 267 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 268 DELAY(1); 269 MII_SET(STE_PHYCTL_MCLK); 270 DELAY(1); 271 272 /* Check for ack */ 273 MII_CLR(STE_PHYCTL_MCLK); 274 DELAY(1); 275 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 276 MII_SET(STE_PHYCTL_MCLK); 277 DELAY(1); 278 279 /* 280 * Now try reading data bits. If the ack failed, we still 281 * need to clock through 16 cycles to keep the PHY(s) in sync. 282 */ 283 if (ack) { 284 for (i = 0; i < 16; i++) { 285 MII_CLR(STE_PHYCTL_MCLK); 286 DELAY(1); 287 MII_SET(STE_PHYCTL_MCLK); 288 DELAY(1); 289 } 290 goto fail; 291 } 292 293 for (i = 0x8000; i; i >>= 1) { 294 MII_CLR(STE_PHYCTL_MCLK); 295 DELAY(1); 296 if (!ack) { 297 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 298 frame->mii_data |= i; 299 DELAY(1); 300 } 301 MII_SET(STE_PHYCTL_MCLK); 302 DELAY(1); 303 } 304 305fail: 306 307 MII_CLR(STE_PHYCTL_MCLK); 308 DELAY(1); 309 MII_SET(STE_PHYCTL_MCLK); 310 DELAY(1); 311 312 if (ack) 313 return (1); 314 return (0); 315} 316 317/* 318 * Write to a PHY register through the MII. 319 */ 320static int 321ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 322{ 323 324 /* 325 * Set up frame for TX. 326 */ 327 328 frame->mii_stdelim = STE_MII_STARTDELIM; 329 frame->mii_opcode = STE_MII_WRITEOP; 330 frame->mii_turnaround = STE_MII_TURNAROUND; 331 332 /* 333 * Turn on data output. 334 */ 335 MII_SET(STE_PHYCTL_MDIR); 336 337 ste_mii_sync(sc); 338 339 ste_mii_send(sc, frame->mii_stdelim, 2); 340 ste_mii_send(sc, frame->mii_opcode, 2); 341 ste_mii_send(sc, frame->mii_phyaddr, 5); 342 ste_mii_send(sc, frame->mii_regaddr, 5); 343 ste_mii_send(sc, frame->mii_turnaround, 2); 344 ste_mii_send(sc, frame->mii_data, 16); 345 346 /* Idle bit. */ 347 MII_SET(STE_PHYCTL_MCLK); 348 DELAY(1); 349 MII_CLR(STE_PHYCTL_MCLK); 350 DELAY(1); 351 352 /* 353 * Turn off xmit. 354 */ 355 MII_CLR(STE_PHYCTL_MDIR); 356 357 return (0); 358} 359 360static int 361ste_miibus_readreg(device_t dev, int phy, int reg) 362{ 363 struct ste_softc *sc; 364 struct ste_mii_frame frame; 365 366 sc = device_get_softc(dev); 367 368 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0 && phy != 0) 369 return (0); 370 371 bzero((char *)&frame, sizeof(frame)); 372 373 frame.mii_phyaddr = phy; 374 frame.mii_regaddr = reg; 375 ste_mii_readreg(sc, &frame); 376 377 return (frame.mii_data); 378} 379 380static int 381ste_miibus_writereg(device_t dev, int phy, int reg, int data) 382{ 383 struct ste_softc *sc; 384 struct ste_mii_frame frame; 385 386 sc = device_get_softc(dev); 387 bzero((char *)&frame, sizeof(frame)); 388 389 frame.mii_phyaddr = phy; 390 frame.mii_regaddr = reg; 391 frame.mii_data = data; 392 393 ste_mii_writereg(sc, &frame); 394 395 return (0); 396} 397 398static void 399ste_miibus_statchg(device_t dev) 400{ 401 struct ste_softc *sc; 402 struct mii_data *mii; 403 struct ifnet *ifp; 404 uint16_t cfg; 405 406 sc = device_get_softc(dev); 407 408 mii = device_get_softc(sc->ste_miibus); 409 ifp = sc->ste_ifp; 410 if (mii == NULL || ifp == NULL || 411 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 412 return; 413 414 sc->ste_flags &= ~STE_FLAG_LINK; 415 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 416 (IFM_ACTIVE | IFM_AVALID)) { 417 switch (IFM_SUBTYPE(mii->mii_media_active)) { 418 case IFM_10_T: 419 case IFM_100_TX: 420 case IFM_100_FX: 421 case IFM_100_T4: 422 sc->ste_flags |= STE_FLAG_LINK; 423 default: 424 break; 425 } 426 } 427 428 /* Program MACs with resolved speed/duplex/flow-control. */ 429 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 430 cfg = CSR_READ_2(sc, STE_MACCTL0); 431 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 432 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 433 /* 434 * ST201 data sheet says driver should enable receiving 435 * MAC control frames bit of receive mode register to 436 * receive flow-control frames but the register has no 437 * such bits. In addition the controller has no ability 438 * to send pause frames so it should be handled in 439 * driver. Implementing pause timer handling in driver 440 * layer is not trivial, so don't enable flow-control 441 * here. 442 */ 443 cfg |= STE_MACCTL0_FULLDUPLEX; 444 } 445 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 446 } 447} 448 449static int 450ste_ifmedia_upd(struct ifnet *ifp) 451{ 452 struct ste_softc *sc; 453 struct mii_data *mii; 454 struct mii_softc *miisc; 455 int error; 456 457 sc = ifp->if_softc; 458 STE_LOCK(sc); 459 mii = device_get_softc(sc->ste_miibus); 460 if (mii->mii_instance) { 461 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 462 mii_phy_reset(miisc); 463 } 464 error = mii_mediachg(mii); 465 STE_UNLOCK(sc); 466 467 return (error); 468} 469 470static void 471ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 472{ 473 struct ste_softc *sc; 474 struct mii_data *mii; 475 476 sc = ifp->if_softc; 477 mii = device_get_softc(sc->ste_miibus); 478 479 STE_LOCK(sc); 480 if ((ifp->if_flags & IFF_UP) == 0) { 481 STE_UNLOCK(sc); 482 return; 483 } 484 mii_pollstat(mii); 485 ifmr->ifm_active = mii->mii_media_active; 486 ifmr->ifm_status = mii->mii_media_status; 487 STE_UNLOCK(sc); 488} 489 490static void 491ste_wait(struct ste_softc *sc) 492{ 493 int i; 494 495 for (i = 0; i < STE_TIMEOUT; i++) { 496 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 497 break; 498 DELAY(1); 499 } 500 501 if (i == STE_TIMEOUT) 502 device_printf(sc->ste_dev, "command never completed!\n"); 503} 504 505/* 506 * The EEPROM is slow: give it time to come ready after issuing 507 * it a command. 508 */ 509static int 510ste_eeprom_wait(struct ste_softc *sc) 511{ 512 int i; 513 514 DELAY(1000); 515 516 for (i = 0; i < 100; i++) { 517 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 518 DELAY(1000); 519 else 520 break; 521 } 522 523 if (i == 100) { 524 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 525 return (1); 526 } 527 528 return (0); 529} 530 531/* 532 * Read a sequence of words from the EEPROM. Note that ethernet address 533 * data is stored in the EEPROM in network byte order. 534 */ 535static int 536ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 537{ 538 uint16_t word, *ptr; 539 int err = 0, i; 540 541 if (ste_eeprom_wait(sc)) 542 return (1); 543 544 for (i = 0; i < cnt; i++) { 545 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 546 err = ste_eeprom_wait(sc); 547 if (err) 548 break; 549 word = CSR_READ_2(sc, STE_EEPROM_DATA); 550 ptr = (uint16_t *)(dest + (i * 2)); 551 if (swap) 552 *ptr = ntohs(word); 553 else 554 *ptr = word; 555 } 556 557 return (err ? 1 : 0); 558} 559 560static void 561ste_rxfilter(struct ste_softc *sc) 562{ 563 struct ifnet *ifp; 564 struct ifmultiaddr *ifma; 565 uint32_t hashes[2] = { 0, 0 }; 566 uint8_t rxcfg; 567 int h; 568 569 STE_LOCK_ASSERT(sc); 570 571 ifp = sc->ste_ifp; 572 rxcfg = CSR_READ_1(sc, STE_RX_MODE); 573 rxcfg |= STE_RXMODE_UNICAST; 574 rxcfg &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_MULTIHASH | 575 STE_RXMODE_BROADCAST | STE_RXMODE_PROMISC); 576 if (ifp->if_flags & IFF_BROADCAST) 577 rxcfg |= STE_RXMODE_BROADCAST; 578 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 579 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 580 rxcfg |= STE_RXMODE_ALLMULTI; 581 if ((ifp->if_flags & IFF_PROMISC) != 0) 582 rxcfg |= STE_RXMODE_PROMISC; 583 goto chipit; 584 } 585 586 rxcfg |= STE_RXMODE_MULTIHASH; 587 /* Now program new ones. */ 588 if_maddr_rlock(ifp); 589 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 590 if (ifma->ifma_addr->sa_family != AF_LINK) 591 continue; 592 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 593 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 594 if (h < 32) 595 hashes[0] |= (1 << h); 596 else 597 hashes[1] |= (1 << (h - 32)); 598 } 599 if_maddr_runlock(ifp); 600 601chipit: 602 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 603 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 604 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 605 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 606 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg); 607 CSR_READ_1(sc, STE_RX_MODE); 608} 609 610#ifdef DEVICE_POLLING 611static poll_handler_t ste_poll, ste_poll_locked; 612 613static int 614ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 615{ 616 struct ste_softc *sc = ifp->if_softc; 617 int rx_npkts = 0; 618 619 STE_LOCK(sc); 620 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 621 rx_npkts = ste_poll_locked(ifp, cmd, count); 622 STE_UNLOCK(sc); 623 return (rx_npkts); 624} 625 626static int 627ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 628{ 629 struct ste_softc *sc = ifp->if_softc; 630 int rx_npkts; 631 632 STE_LOCK_ASSERT(sc); 633 634 rx_npkts = ste_rxeof(sc, count); 635 ste_txeof(sc); 636 ste_txeoc(sc); 637 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 638 ste_start_locked(ifp); 639 640 if (cmd == POLL_AND_CHECK_STATUS) { 641 uint16_t status; 642 643 status = CSR_READ_2(sc, STE_ISR_ACK); 644 645 if (status & STE_ISR_STATS_OFLOW) 646 ste_stats_update(sc); 647 648 if (status & STE_ISR_HOSTERR) { 649 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 650 ste_init_locked(sc); 651 } 652 } 653 return (rx_npkts); 654} 655#endif /* DEVICE_POLLING */ 656 657static void 658ste_intr(void *xsc) 659{ 660 struct ste_softc *sc; 661 struct ifnet *ifp; 662 uint16_t status; 663 664 sc = xsc; 665 STE_LOCK(sc); 666 ifp = sc->ste_ifp; 667 668#ifdef DEVICE_POLLING 669 if (ifp->if_capenable & IFCAP_POLLING) { 670 STE_UNLOCK(sc); 671 return; 672 } 673#endif 674 675 /* See if this is really our interrupt. */ 676 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 677 STE_UNLOCK(sc); 678 return; 679 } 680 681 for (;;) { 682 status = CSR_READ_2(sc, STE_ISR_ACK); 683 684 if (!(status & STE_INTRS)) 685 break; 686 687 if (status & STE_ISR_RX_DMADONE) 688 ste_rxeof(sc, -1); 689 690 if (status & STE_ISR_TX_DMADONE) 691 ste_txeof(sc); 692 693 if (status & STE_ISR_TX_DONE) 694 ste_txeoc(sc); 695 696 if (status & STE_ISR_STATS_OFLOW) 697 ste_stats_update(sc); 698 699 if (status & STE_ISR_HOSTERR) { 700 ste_init_locked(sc); 701 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 702 } 703 } 704 705 /* Re-enable interrupts */ 706 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 707 708 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 709 ste_start_locked(ifp); 710 711 STE_UNLOCK(sc); 712} 713 714/* 715 * A frame has been uploaded: pass the resulting mbuf chain up to 716 * the higher level protocols. 717 */ 718static int 719ste_rxeof(struct ste_softc *sc, int count) 720{ 721 struct mbuf *m; 722 struct ifnet *ifp; 723 struct ste_chain_onefrag *cur_rx; 724 uint32_t rxstat; 725 int total_len, rx_npkts; 726 727 ifp = sc->ste_ifp; 728 729 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 730 sc->ste_cdata.ste_rx_list_map, 731 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 732 733 cur_rx = sc->ste_cdata.ste_rx_head; 734 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 735 cur_rx = cur_rx->ste_next) { 736 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 737 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 738 break; 739#ifdef DEVICE_POLLING 740 if (ifp->if_capenable & IFCAP_POLLING) { 741 if (count == 0) 742 break; 743 count--; 744 } 745#endif 746 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 747 break; 748 /* 749 * If an error occurs, update stats, clear the 750 * status word and leave the mbuf cluster in place: 751 * it should simply get re-used next time this descriptor 752 * comes up in the ring. 753 */ 754 if (rxstat & STE_RXSTAT_FRAME_ERR) { 755 ifp->if_ierrors++; 756 cur_rx->ste_ptr->ste_status = 0; 757 continue; 758 } 759 760 /* No errors; receive the packet. */ 761 m = cur_rx->ste_mbuf; 762 total_len = STE_RX_BYTES(rxstat); 763 764 /* 765 * Try to conjure up a new mbuf cluster. If that 766 * fails, it means we have an out of memory condition and 767 * should leave the buffer in place and continue. This will 768 * result in a lost packet, but there's little else we 769 * can do in this situation. 770 */ 771 if (ste_newbuf(sc, cur_rx) != 0) { 772 ifp->if_ierrors++; 773 cur_rx->ste_ptr->ste_status = 0; 774 continue; 775 } 776 777 m->m_pkthdr.rcvif = ifp; 778 m->m_pkthdr.len = m->m_len = total_len; 779 780 ifp->if_ipackets++; 781 STE_UNLOCK(sc); 782 (*ifp->if_input)(ifp, m); 783 STE_LOCK(sc); 784 } 785 786 if (rx_npkts > 0) { 787 sc->ste_cdata.ste_rx_head = cur_rx; 788 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 789 sc->ste_cdata.ste_rx_list_map, 790 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 791 } 792 793 return (rx_npkts); 794} 795 796static void 797ste_txeoc(struct ste_softc *sc) 798{ 799 uint16_t txstat; 800 struct ifnet *ifp; 801 802 STE_LOCK_ASSERT(sc); 803 804 ifp = sc->ste_ifp; 805 806 /* 807 * STE_TX_STATUS register implements a queue of up to 31 808 * transmit status byte. Writing an arbitrary value to the 809 * register will advance the queue to the next transmit 810 * status byte. This means if driver does not read 811 * STE_TX_STATUS register after completing sending more 812 * than 31 frames the controller would be stalled so driver 813 * should re-wake the Tx MAC. This is the most severe 814 * limitation of ST201 based controller. 815 */ 816 for (;;) { 817 txstat = CSR_READ_2(sc, STE_TX_STATUS); 818 if ((txstat & STE_TXSTATUS_TXDONE) == 0) 819 break; 820 if ((txstat & (STE_TXSTATUS_UNDERRUN | 821 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR | 822 STE_TXSTATUS_STATSOFLOW)) != 0) { 823 ifp->if_oerrors++; 824#ifdef STE_SHOW_TXERRORS 825 device_printf(sc->ste_dev, "TX error : 0x%b\n", 826 txstat & 0xFF, STE_ERR_BITS); 827#endif 828 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 && 829 sc->ste_tx_thresh < STE_PACKET_SIZE) { 830 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 831 if (sc->ste_tx_thresh > STE_PACKET_SIZE) 832 sc->ste_tx_thresh = STE_PACKET_SIZE; 833 device_printf(sc->ste_dev, 834 "TX underrun, increasing TX" 835 " start threshold to %d bytes\n", 836 sc->ste_tx_thresh); 837 /* Make sure to disable active DMA cycles. */ 838 STE_SETBIT4(sc, STE_DMACTL, 839 STE_DMACTL_TXDMA_STALL); 840 ste_wait(sc); 841 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 842 ste_init_locked(sc); 843 break; 844 } 845 /* Restart Tx. */ 846 ste_restart_tx(sc); 847 } 848 /* 849 * Advance to next status and ACK TxComplete 850 * interrupt. ST201 data sheet was wrong here, to 851 * get next Tx status, we have to write both 852 * STE_TX_STATUS and STE_TX_FRAMEID register. 853 * Otherwise controller returns the same status 854 * as well as not acknowledge Tx completion 855 * interrupt. 856 */ 857 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 858 } 859} 860 861static void 862ste_tick(void *arg) 863{ 864 struct ste_softc *sc; 865 struct mii_data *mii; 866 867 sc = (struct ste_softc *)arg; 868 869 STE_LOCK_ASSERT(sc); 870 871 mii = device_get_softc(sc->ste_miibus); 872 mii_tick(mii); 873 /* 874 * ukphy(4) does not seem to generate CB that reports 875 * resolved link state so if we know we lost a link, 876 * explicitly check the link state. 877 */ 878 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 879 ste_miibus_statchg(sc->ste_dev); 880 /* 881 * Because we are not generating Tx completion 882 * interrupt for every frame, reclaim transmitted 883 * buffers here. 884 */ 885 ste_txeof(sc); 886 ste_txeoc(sc); 887 ste_stats_update(sc); 888 ste_watchdog(sc); 889 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 890} 891 892static void 893ste_txeof(struct ste_softc *sc) 894{ 895 struct ifnet *ifp; 896 struct ste_chain *cur_tx; 897 uint32_t txstat; 898 int idx; 899 900 STE_LOCK_ASSERT(sc); 901 902 ifp = sc->ste_ifp; 903 idx = sc->ste_cdata.ste_tx_cons; 904 if (idx == sc->ste_cdata.ste_tx_prod) 905 return; 906 907 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 908 sc->ste_cdata.ste_tx_list_map, 909 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 910 911 while (idx != sc->ste_cdata.ste_tx_prod) { 912 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 913 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 914 if ((txstat & STE_TXCTL_DMADONE) == 0) 915 break; 916 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 917 BUS_DMASYNC_POSTWRITE); 918 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 919 KASSERT(cur_tx->ste_mbuf != NULL, 920 ("%s: freeing NULL mbuf!\n", __func__)); 921 m_freem(cur_tx->ste_mbuf); 922 cur_tx->ste_mbuf = NULL; 923 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 924 ifp->if_opackets++; 925 sc->ste_cdata.ste_tx_cnt--; 926 STE_INC(idx, STE_TX_LIST_CNT); 927 } 928 929 sc->ste_cdata.ste_tx_cons = idx; 930 if (sc->ste_cdata.ste_tx_cnt == 0) 931 sc->ste_timer = 0; 932} 933 934static void 935ste_stats_clear(struct ste_softc *sc) 936{ 937 938 STE_LOCK_ASSERT(sc); 939 940 /* Rx stats. */ 941 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO); 942 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI); 943 CSR_READ_2(sc, STE_STAT_RX_FRAMES); 944 CSR_READ_1(sc, STE_STAT_RX_BCAST); 945 CSR_READ_1(sc, STE_STAT_RX_MCAST); 946 CSR_READ_1(sc, STE_STAT_RX_LOST); 947 /* Tx stats. */ 948 CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO); 949 CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI); 950 CSR_READ_2(sc, STE_STAT_TX_FRAMES); 951 CSR_READ_1(sc, STE_STAT_TX_BCAST); 952 CSR_READ_1(sc, STE_STAT_TX_MCAST); 953 CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 954 CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 955 CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 956 CSR_READ_1(sc, STE_STAT_LATE_COLLS); 957 CSR_READ_1(sc, STE_STAT_TX_DEFER); 958 CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 959 CSR_READ_1(sc, STE_STAT_TX_ABORT); 960} 961 962static void 963ste_stats_update(struct ste_softc *sc) 964{ 965 struct ifnet *ifp; 966 struct ste_hw_stats *stats; 967 uint32_t val; 968 969 STE_LOCK_ASSERT(sc); 970 971 ifp = sc->ste_ifp; 972 stats = &sc->ste_stats; 973 /* Rx stats. */ 974 val = (uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO) | 975 ((uint32_t)CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI)) << 16; 976 val &= 0x000FFFFF; 977 stats->rx_bytes += val; 978 stats->rx_frames += CSR_READ_2(sc, STE_STAT_RX_FRAMES); 979 stats->rx_bcast_frames += CSR_READ_1(sc, STE_STAT_RX_BCAST); 980 stats->rx_mcast_frames += CSR_READ_1(sc, STE_STAT_RX_MCAST); 981 stats->rx_lost_frames += CSR_READ_1(sc, STE_STAT_RX_LOST); 982 /* Tx stats. */ 983 val = (uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_LO) | 984 ((uint32_t)CSR_READ_2(sc, STE_STAT_TX_OCTETS_HI)) << 16; 985 val &= 0x000FFFFF; 986 stats->tx_bytes += val; 987 stats->tx_frames += CSR_READ_2(sc, STE_STAT_TX_FRAMES); 988 stats->tx_bcast_frames += CSR_READ_1(sc, STE_STAT_TX_BCAST); 989 stats->tx_mcast_frames += CSR_READ_1(sc, STE_STAT_TX_MCAST); 990 stats->tx_carrsense_errs += CSR_READ_1(sc, STE_STAT_CARRIER_ERR); 991 val = CSR_READ_1(sc, STE_STAT_SINGLE_COLLS); 992 stats->tx_single_colls += val; 993 ifp->if_collisions += val; 994 val = CSR_READ_1(sc, STE_STAT_MULTI_COLLS); 995 stats->tx_multi_colls += val; 996 ifp->if_collisions += val; 997 val += CSR_READ_1(sc, STE_STAT_LATE_COLLS); 998 stats->tx_late_colls += val; 999 ifp->if_collisions += val; 1000 stats->tx_frames_defered += CSR_READ_1(sc, STE_STAT_TX_DEFER); 1001 stats->tx_excess_defers += CSR_READ_1(sc, STE_STAT_TX_EXDEFER); 1002 stats->tx_abort += CSR_READ_1(sc, STE_STAT_TX_ABORT); 1003} 1004 1005/* 1006 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 1007 * IDs against our list and return a device name if we find a match. 1008 */ 1009static int 1010ste_probe(device_t dev) 1011{ 1012 struct ste_type *t; 1013 1014 t = ste_devs; 1015 1016 while (t->ste_name != NULL) { 1017 if ((pci_get_vendor(dev) == t->ste_vid) && 1018 (pci_get_device(dev) == t->ste_did)) { 1019 device_set_desc(dev, t->ste_name); 1020 return (BUS_PROBE_DEFAULT); 1021 } 1022 t++; 1023 } 1024 1025 return (ENXIO); 1026} 1027 1028/* 1029 * Attach the interface. Allocate softc structures, do ifmedia 1030 * setup and ethernet/BPF attach. 1031 */ 1032static int 1033ste_attach(device_t dev) 1034{ 1035 struct ste_softc *sc; 1036 struct ifnet *ifp; 1037 u_char eaddr[6]; 1038 int error = 0, rid; 1039 1040 sc = device_get_softc(dev); 1041 sc->ste_dev = dev; 1042 1043 /* 1044 * Only use one PHY since this chip reports multiple 1045 * Note on the DFE-550 the PHY is at 1 on the DFE-580 1046 * it is at 0 & 1. It is rev 0x12. 1047 */ 1048 if (pci_get_vendor(dev) == DL_VENDORID && 1049 pci_get_device(dev) == DL_DEVICEID_DL10050 && 1050 pci_get_revid(dev) == 0x12 ) 1051 sc->ste_flags |= STE_FLAG_ONE_PHY; 1052 1053 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1054 MTX_DEF); 1055 /* 1056 * Map control/status registers. 1057 */ 1058 pci_enable_busmaster(dev); 1059 1060 /* Prefer memory space register mapping over IO space. */ 1061 sc->ste_res_id = PCIR_BAR(1); 1062 sc->ste_res_type = SYS_RES_MEMORY; 1063 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 1064 &sc->ste_res_id, RF_ACTIVE); 1065 if (sc->ste_res == NULL) { 1066 sc->ste_res_id = PCIR_BAR(0); 1067 sc->ste_res_type = SYS_RES_IOPORT; 1068 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 1069 &sc->ste_res_id, RF_ACTIVE); 1070 } 1071 if (sc->ste_res == NULL) { 1072 device_printf(dev, "couldn't map ports/memory\n"); 1073 error = ENXIO; 1074 goto fail; 1075 } 1076 1077 /* Allocate interrupt */ 1078 rid = 0; 1079 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1080 RF_SHAREABLE | RF_ACTIVE); 1081 1082 if (sc->ste_irq == NULL) { 1083 device_printf(dev, "couldn't map interrupt\n"); 1084 error = ENXIO; 1085 goto fail; 1086 } 1087 1088 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 1089 1090 /* Reset the adapter. */ 1091 ste_reset(sc); 1092 1093 /* 1094 * Get station address from the EEPROM. 1095 */ 1096 if (ste_read_eeprom(sc, eaddr, 1097 STE_EEADDR_NODE0, 3, 0)) { 1098 device_printf(dev, "failed to read station address\n"); 1099 error = ENXIO;; 1100 goto fail; 1101 } 1102 ste_sysctl_node(sc); 1103 1104 if ((error = ste_dma_alloc(sc)) != 0) 1105 goto fail; 1106 1107 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1108 if (ifp == NULL) { 1109 device_printf(dev, "can not if_alloc()\n"); 1110 error = ENOSPC; 1111 goto fail; 1112 } 1113 1114 /* Do MII setup. */ 1115 if (mii_phy_probe(dev, &sc->ste_miibus, 1116 ste_ifmedia_upd, ste_ifmedia_sts)) { 1117 device_printf(dev, "MII without any phy!\n"); 1118 error = ENXIO; 1119 goto fail; 1120 } 1121 1122 ifp->if_softc = sc; 1123 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1124 ifp->if_mtu = ETHERMTU; 1125 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1126 ifp->if_ioctl = ste_ioctl; 1127 ifp->if_start = ste_start; 1128 ifp->if_init = ste_init; 1129 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1130 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1131 IFQ_SET_READY(&ifp->if_snd); 1132 1133 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1134 1135 /* 1136 * Call MI attach routine. 1137 */ 1138 ether_ifattach(ifp, eaddr); 1139 1140 /* 1141 * Tell the upper layer(s) we support long frames. 1142 */ 1143 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1144 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1145 ifp->if_capenable = ifp->if_capabilities; 1146#ifdef DEVICE_POLLING 1147 ifp->if_capabilities |= IFCAP_POLLING; 1148#endif 1149 1150 /* Hook interrupt last to avoid having to lock softc */ 1151 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1152 NULL, ste_intr, sc, &sc->ste_intrhand); 1153 1154 if (error) { 1155 device_printf(dev, "couldn't set up irq\n"); 1156 ether_ifdetach(ifp); 1157 goto fail; 1158 } 1159 1160fail: 1161 if (error) 1162 ste_detach(dev); 1163 1164 return (error); 1165} 1166 1167/* 1168 * Shutdown hardware and free up resources. This can be called any 1169 * time after the mutex has been initialized. It is called in both 1170 * the error case in attach and the normal detach case so it needs 1171 * to be careful about only freeing resources that have actually been 1172 * allocated. 1173 */ 1174static int 1175ste_detach(device_t dev) 1176{ 1177 struct ste_softc *sc; 1178 struct ifnet *ifp; 1179 1180 sc = device_get_softc(dev); 1181 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1182 ifp = sc->ste_ifp; 1183 1184#ifdef DEVICE_POLLING 1185 if (ifp->if_capenable & IFCAP_POLLING) 1186 ether_poll_deregister(ifp); 1187#endif 1188 1189 /* These should only be active if attach succeeded */ 1190 if (device_is_attached(dev)) { 1191 ether_ifdetach(ifp); 1192 STE_LOCK(sc); 1193 ste_stop(sc); 1194 STE_UNLOCK(sc); 1195 callout_drain(&sc->ste_callout); 1196 } 1197 if (sc->ste_miibus) 1198 device_delete_child(dev, sc->ste_miibus); 1199 bus_generic_detach(dev); 1200 1201 if (sc->ste_intrhand) 1202 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1203 if (sc->ste_irq) 1204 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1205 if (sc->ste_res) 1206 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1207 sc->ste_res); 1208 1209 if (ifp) 1210 if_free(ifp); 1211 1212 ste_dma_free(sc); 1213 mtx_destroy(&sc->ste_mtx); 1214 1215 return (0); 1216} 1217 1218struct ste_dmamap_arg { 1219 bus_addr_t ste_busaddr; 1220}; 1221 1222static void 1223ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1224{ 1225 struct ste_dmamap_arg *ctx; 1226 1227 if (error != 0) 1228 return; 1229 1230 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1231 1232 ctx = (struct ste_dmamap_arg *)arg; 1233 ctx->ste_busaddr = segs[0].ds_addr; 1234} 1235 1236static int 1237ste_dma_alloc(struct ste_softc *sc) 1238{ 1239 struct ste_chain *txc; 1240 struct ste_chain_onefrag *rxc; 1241 struct ste_dmamap_arg ctx; 1242 int error, i; 1243 1244 /* Create parent DMA tag. */ 1245 error = bus_dma_tag_create( 1246 bus_get_dma_tag(sc->ste_dev), /* parent */ 1247 1, 0, /* alignment, boundary */ 1248 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1249 BUS_SPACE_MAXADDR, /* highaddr */ 1250 NULL, NULL, /* filter, filterarg */ 1251 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1252 0, /* nsegments */ 1253 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1254 0, /* flags */ 1255 NULL, NULL, /* lockfunc, lockarg */ 1256 &sc->ste_cdata.ste_parent_tag); 1257 if (error != 0) { 1258 device_printf(sc->ste_dev, 1259 "could not create parent DMA tag.\n"); 1260 goto fail; 1261 } 1262 1263 /* Create DMA tag for Tx descriptor list. */ 1264 error = bus_dma_tag_create( 1265 sc->ste_cdata.ste_parent_tag, /* parent */ 1266 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1267 BUS_SPACE_MAXADDR, /* lowaddr */ 1268 BUS_SPACE_MAXADDR, /* highaddr */ 1269 NULL, NULL, /* filter, filterarg */ 1270 STE_TX_LIST_SZ, /* maxsize */ 1271 1, /* nsegments */ 1272 STE_TX_LIST_SZ, /* maxsegsize */ 1273 0, /* flags */ 1274 NULL, NULL, /* lockfunc, lockarg */ 1275 &sc->ste_cdata.ste_tx_list_tag); 1276 if (error != 0) { 1277 device_printf(sc->ste_dev, 1278 "could not create Tx list DMA tag.\n"); 1279 goto fail; 1280 } 1281 1282 /* Create DMA tag for Rx descriptor list. */ 1283 error = bus_dma_tag_create( 1284 sc->ste_cdata.ste_parent_tag, /* parent */ 1285 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1286 BUS_SPACE_MAXADDR, /* lowaddr */ 1287 BUS_SPACE_MAXADDR, /* highaddr */ 1288 NULL, NULL, /* filter, filterarg */ 1289 STE_RX_LIST_SZ, /* maxsize */ 1290 1, /* nsegments */ 1291 STE_RX_LIST_SZ, /* maxsegsize */ 1292 0, /* flags */ 1293 NULL, NULL, /* lockfunc, lockarg */ 1294 &sc->ste_cdata.ste_rx_list_tag); 1295 if (error != 0) { 1296 device_printf(sc->ste_dev, 1297 "could not create Rx list DMA tag.\n"); 1298 goto fail; 1299 } 1300 1301 /* Create DMA tag for Tx buffers. */ 1302 error = bus_dma_tag_create( 1303 sc->ste_cdata.ste_parent_tag, /* parent */ 1304 1, 0, /* alignment, boundary */ 1305 BUS_SPACE_MAXADDR, /* lowaddr */ 1306 BUS_SPACE_MAXADDR, /* highaddr */ 1307 NULL, NULL, /* filter, filterarg */ 1308 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1309 STE_MAXFRAGS, /* nsegments */ 1310 MCLBYTES, /* maxsegsize */ 1311 0, /* flags */ 1312 NULL, NULL, /* lockfunc, lockarg */ 1313 &sc->ste_cdata.ste_tx_tag); 1314 if (error != 0) { 1315 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1316 goto fail; 1317 } 1318 1319 /* Create DMA tag for Rx buffers. */ 1320 error = bus_dma_tag_create( 1321 sc->ste_cdata.ste_parent_tag, /* parent */ 1322 1, 0, /* alignment, boundary */ 1323 BUS_SPACE_MAXADDR, /* lowaddr */ 1324 BUS_SPACE_MAXADDR, /* highaddr */ 1325 NULL, NULL, /* filter, filterarg */ 1326 MCLBYTES, /* maxsize */ 1327 1, /* nsegments */ 1328 MCLBYTES, /* maxsegsize */ 1329 0, /* flags */ 1330 NULL, NULL, /* lockfunc, lockarg */ 1331 &sc->ste_cdata.ste_rx_tag); 1332 if (error != 0) { 1333 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1334 goto fail; 1335 } 1336 1337 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1338 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1339 (void **)&sc->ste_ldata.ste_tx_list, 1340 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1341 &sc->ste_cdata.ste_tx_list_map); 1342 if (error != 0) { 1343 device_printf(sc->ste_dev, 1344 "could not allocate DMA'able memory for Tx list.\n"); 1345 goto fail; 1346 } 1347 ctx.ste_busaddr = 0; 1348 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1349 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1350 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1351 if (error != 0 || ctx.ste_busaddr == 0) { 1352 device_printf(sc->ste_dev, 1353 "could not load DMA'able memory for Tx list.\n"); 1354 goto fail; 1355 } 1356 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1357 1358 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1359 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1360 (void **)&sc->ste_ldata.ste_rx_list, 1361 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1362 &sc->ste_cdata.ste_rx_list_map); 1363 if (error != 0) { 1364 device_printf(sc->ste_dev, 1365 "could not allocate DMA'able memory for Rx list.\n"); 1366 goto fail; 1367 } 1368 ctx.ste_busaddr = 0; 1369 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1370 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1371 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1372 if (error != 0 || ctx.ste_busaddr == 0) { 1373 device_printf(sc->ste_dev, 1374 "could not load DMA'able memory for Rx list.\n"); 1375 goto fail; 1376 } 1377 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1378 1379 /* Create DMA maps for Tx buffers. */ 1380 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1381 txc = &sc->ste_cdata.ste_tx_chain[i]; 1382 txc->ste_ptr = NULL; 1383 txc->ste_mbuf = NULL; 1384 txc->ste_next = NULL; 1385 txc->ste_phys = 0; 1386 txc->ste_map = NULL; 1387 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1388 &txc->ste_map); 1389 if (error != 0) { 1390 device_printf(sc->ste_dev, 1391 "could not create Tx dmamap.\n"); 1392 goto fail; 1393 } 1394 } 1395 /* Create DMA maps for Rx buffers. */ 1396 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1397 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1398 device_printf(sc->ste_dev, 1399 "could not create spare Rx dmamap.\n"); 1400 goto fail; 1401 } 1402 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1403 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1404 rxc->ste_ptr = NULL; 1405 rxc->ste_mbuf = NULL; 1406 rxc->ste_next = NULL; 1407 rxc->ste_map = NULL; 1408 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1409 &rxc->ste_map); 1410 if (error != 0) { 1411 device_printf(sc->ste_dev, 1412 "could not create Rx dmamap.\n"); 1413 goto fail; 1414 } 1415 } 1416 1417fail: 1418 return (error); 1419} 1420 1421static void 1422ste_dma_free(struct ste_softc *sc) 1423{ 1424 struct ste_chain *txc; 1425 struct ste_chain_onefrag *rxc; 1426 int i; 1427 1428 /* Tx buffers. */ 1429 if (sc->ste_cdata.ste_tx_tag != NULL) { 1430 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1431 txc = &sc->ste_cdata.ste_tx_chain[i]; 1432 if (txc->ste_map != NULL) { 1433 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1434 txc->ste_map); 1435 txc->ste_map = NULL; 1436 } 1437 } 1438 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1439 sc->ste_cdata.ste_tx_tag = NULL; 1440 } 1441 /* Rx buffers. */ 1442 if (sc->ste_cdata.ste_rx_tag != NULL) { 1443 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1444 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1445 if (rxc->ste_map != NULL) { 1446 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1447 rxc->ste_map); 1448 rxc->ste_map = NULL; 1449 } 1450 } 1451 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1452 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1453 sc->ste_cdata.ste_rx_sparemap); 1454 sc->ste_cdata.ste_rx_sparemap = NULL; 1455 } 1456 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1457 sc->ste_cdata.ste_rx_tag = NULL; 1458 } 1459 /* Tx descriptor list. */ 1460 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1461 if (sc->ste_cdata.ste_tx_list_map != NULL) 1462 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1463 sc->ste_cdata.ste_tx_list_map); 1464 if (sc->ste_cdata.ste_tx_list_map != NULL && 1465 sc->ste_ldata.ste_tx_list != NULL) 1466 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1467 sc->ste_ldata.ste_tx_list, 1468 sc->ste_cdata.ste_tx_list_map); 1469 sc->ste_ldata.ste_tx_list = NULL; 1470 sc->ste_cdata.ste_tx_list_map = NULL; 1471 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1472 sc->ste_cdata.ste_tx_list_tag = NULL; 1473 } 1474 /* Rx descriptor list. */ 1475 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1476 if (sc->ste_cdata.ste_rx_list_map != NULL) 1477 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1478 sc->ste_cdata.ste_rx_list_map); 1479 if (sc->ste_cdata.ste_rx_list_map != NULL && 1480 sc->ste_ldata.ste_rx_list != NULL) 1481 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1482 sc->ste_ldata.ste_rx_list, 1483 sc->ste_cdata.ste_rx_list_map); 1484 sc->ste_ldata.ste_rx_list = NULL; 1485 sc->ste_cdata.ste_rx_list_map = NULL; 1486 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1487 sc->ste_cdata.ste_rx_list_tag = NULL; 1488 } 1489 if (sc->ste_cdata.ste_parent_tag != NULL) { 1490 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1491 sc->ste_cdata.ste_parent_tag = NULL; 1492 } 1493} 1494 1495static int 1496ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1497{ 1498 struct mbuf *m; 1499 bus_dma_segment_t segs[1]; 1500 bus_dmamap_t map; 1501 int error, nsegs; 1502 1503 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1504 if (m == NULL) 1505 return (ENOBUFS); 1506 m->m_len = m->m_pkthdr.len = MCLBYTES; 1507 m_adj(m, ETHER_ALIGN); 1508 1509 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1510 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1511 m_freem(m); 1512 return (error); 1513 } 1514 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1515 1516 if (rxc->ste_mbuf != NULL) { 1517 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1518 BUS_DMASYNC_POSTREAD); 1519 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1520 } 1521 map = rxc->ste_map; 1522 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1523 sc->ste_cdata.ste_rx_sparemap = map; 1524 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1525 BUS_DMASYNC_PREREAD); 1526 rxc->ste_mbuf = m; 1527 rxc->ste_ptr->ste_status = 0; 1528 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1529 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1530 STE_FRAG_LAST); 1531 return (0); 1532} 1533 1534static int 1535ste_init_rx_list(struct ste_softc *sc) 1536{ 1537 struct ste_chain_data *cd; 1538 struct ste_list_data *ld; 1539 int error, i; 1540 1541 cd = &sc->ste_cdata; 1542 ld = &sc->ste_ldata; 1543 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1544 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1545 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1546 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1547 if (error != 0) 1548 return (error); 1549 if (i == (STE_RX_LIST_CNT - 1)) { 1550 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1551 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1552 (sizeof(struct ste_desc_onefrag) * 0); 1553 } else { 1554 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1555 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1556 (sizeof(struct ste_desc_onefrag) * (i + 1)); 1557 } 1558 } 1559 1560 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1561 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1562 sc->ste_cdata.ste_rx_list_map, 1563 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1564 1565 return (0); 1566} 1567 1568static void 1569ste_init_tx_list(struct ste_softc *sc) 1570{ 1571 struct ste_chain_data *cd; 1572 struct ste_list_data *ld; 1573 int i; 1574 1575 cd = &sc->ste_cdata; 1576 ld = &sc->ste_ldata; 1577 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1578 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1579 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1580 cd->ste_tx_chain[i].ste_mbuf = NULL; 1581 if (i == (STE_TX_LIST_CNT - 1)) { 1582 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1583 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1584 ld->ste_tx_list_paddr + 1585 (sizeof(struct ste_desc) * 0))); 1586 } else { 1587 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1588 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1589 ld->ste_tx_list_paddr + 1590 (sizeof(struct ste_desc) * (i + 1)))); 1591 } 1592 } 1593 1594 cd->ste_last_tx = NULL; 1595 cd->ste_tx_prod = 0; 1596 cd->ste_tx_cons = 0; 1597 cd->ste_tx_cnt = 0; 1598 1599 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1600 sc->ste_cdata.ste_tx_list_map, 1601 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1602} 1603 1604static void 1605ste_init(void *xsc) 1606{ 1607 struct ste_softc *sc; 1608 1609 sc = xsc; 1610 STE_LOCK(sc); 1611 ste_init_locked(sc); 1612 STE_UNLOCK(sc); 1613} 1614 1615static void 1616ste_init_locked(struct ste_softc *sc) 1617{ 1618 struct ifnet *ifp; 1619 struct mii_data *mii; 1620 int i; 1621 1622 STE_LOCK_ASSERT(sc); 1623 ifp = sc->ste_ifp; 1624 mii = device_get_softc(sc->ste_miibus); 1625 1626 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1627 return; 1628 1629 ste_stop(sc); 1630 /* Reset the chip to a known state. */ 1631 ste_reset(sc); 1632 1633 /* Init our MAC address */ 1634 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1635 CSR_WRITE_2(sc, STE_PAR0 + i, 1636 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1637 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1638 } 1639 1640 /* Init RX list */ 1641 if (ste_init_rx_list(sc) != 0) { 1642 device_printf(sc->ste_dev, 1643 "initialization failed: no memory for RX buffers\n"); 1644 ste_stop(sc); 1645 return; 1646 } 1647 1648 /* Set RX polling interval */ 1649 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1650 1651 /* Init TX descriptors */ 1652 ste_init_tx_list(sc); 1653 1654 /* Set the TX freethresh value */ 1655 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1656 1657 /* Set the TX start threshold for best performance. */ 1658 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1659 1660 /* Set the TX reclaim threshold. */ 1661 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1662 1663 /* Accept VLAN length packets */ 1664 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1665 1666 /* Set up the RX filter. */ 1667 ste_rxfilter(sc); 1668 1669 /* Load the address of the RX list. */ 1670 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1671 ste_wait(sc); 1672 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1673 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1674 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1675 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1676 1677 /* Set TX polling interval(defer until we TX first packet). */ 1678 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1679 1680 /* Load address of the TX list */ 1681 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1682 ste_wait(sc); 1683 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1684 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1685 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1686 ste_wait(sc); 1687 1688 /* Enable receiver and transmitter */ 1689 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1690 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1691 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1692 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1693 1694 /* Enable stats counters. */ 1695 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1696 /* Clear stats counters. */ 1697 ste_stats_clear(sc); 1698 1699 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1700#ifdef DEVICE_POLLING 1701 /* Disable interrupts if we are polling. */ 1702 if (ifp->if_capenable & IFCAP_POLLING) 1703 CSR_WRITE_2(sc, STE_IMR, 0); 1704 else 1705#endif 1706 /* Enable interrupts. */ 1707 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1708 1709 sc->ste_flags &= ~STE_FLAG_LINK; 1710 /* Switch to the current media. */ 1711 mii_mediachg(mii); 1712 1713 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1714 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1715 1716 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1717} 1718 1719static void 1720ste_stop(struct ste_softc *sc) 1721{ 1722 struct ifnet *ifp; 1723 struct ste_chain_onefrag *cur_rx; 1724 struct ste_chain *cur_tx; 1725 uint32_t val; 1726 int i; 1727 1728 STE_LOCK_ASSERT(sc); 1729 ifp = sc->ste_ifp; 1730 1731 callout_stop(&sc->ste_callout); 1732 sc->ste_timer = 0; 1733 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1734 1735 CSR_WRITE_2(sc, STE_IMR, 0); 1736 /* Stop pending DMA. */ 1737 val = CSR_READ_4(sc, STE_DMACTL); 1738 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1739 CSR_WRITE_4(sc, STE_DMACTL, val); 1740 ste_wait(sc); 1741 /* Disable auto-polling. */ 1742 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1743 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1744 /* Nullify DMA address to stop any further DMA. */ 1745 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1746 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1747 /* Stop TX/RX MAC. */ 1748 val = CSR_READ_2(sc, STE_MACCTL1); 1749 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1750 STE_MACCTL1_STATS_DISABLE; 1751 CSR_WRITE_2(sc, STE_MACCTL1, val); 1752 for (i = 0; i < STE_TIMEOUT; i++) { 1753 DELAY(10); 1754 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1755 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1756 break; 1757 } 1758 if (i == STE_TIMEOUT) 1759 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1760 /* Acknowledge any pending interrupts. */ 1761 CSR_READ_2(sc, STE_ISR_ACK); 1762 ste_stats_update(sc); 1763 1764 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1765 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1766 if (cur_rx->ste_mbuf != NULL) { 1767 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1768 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1769 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1770 cur_rx->ste_map); 1771 m_freem(cur_rx->ste_mbuf); 1772 cur_rx->ste_mbuf = NULL; 1773 } 1774 } 1775 1776 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1777 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1778 if (cur_tx->ste_mbuf != NULL) { 1779 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1780 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1781 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1782 cur_tx->ste_map); 1783 m_freem(cur_tx->ste_mbuf); 1784 cur_tx->ste_mbuf = NULL; 1785 } 1786 } 1787} 1788 1789static void 1790ste_reset(struct ste_softc *sc) 1791{ 1792 uint32_t ctl; 1793 int i; 1794 1795 ctl = CSR_READ_4(sc, STE_ASICCTL); 1796 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET | 1797 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET | 1798 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET | 1799 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET | 1800 STE_ASICCTL_EXTRESET_RESET; 1801 CSR_WRITE_4(sc, STE_ASICCTL, ctl); 1802 CSR_READ_4(sc, STE_ASICCTL); 1803 /* 1804 * Due to the need of accessing EEPROM controller can take 1805 * up to 1ms to complete the global reset. 1806 */ 1807 DELAY(1000); 1808 1809 for (i = 0; i < STE_TIMEOUT; i++) { 1810 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1811 break; 1812 DELAY(10); 1813 } 1814 1815 if (i == STE_TIMEOUT) 1816 device_printf(sc->ste_dev, "global reset never completed\n"); 1817} 1818 1819static void 1820ste_restart_tx(struct ste_softc *sc) 1821{ 1822 uint16_t mac; 1823 int i; 1824 1825 for (i = 0; i < STE_TIMEOUT; i++) { 1826 mac = CSR_READ_2(sc, STE_MACCTL1); 1827 mac |= STE_MACCTL1_TX_ENABLE; 1828 CSR_WRITE_2(sc, STE_MACCTL1, mac); 1829 mac = CSR_READ_2(sc, STE_MACCTL1); 1830 if ((mac & STE_MACCTL1_TX_ENABLED) != 0) 1831 break; 1832 DELAY(10); 1833 } 1834 1835 if (i == STE_TIMEOUT) 1836 device_printf(sc->ste_dev, "starting Tx failed"); 1837} 1838 1839static int 1840ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1841{ 1842 struct ste_softc *sc; 1843 struct ifreq *ifr; 1844 struct mii_data *mii; 1845 int error = 0; 1846 1847 sc = ifp->if_softc; 1848 ifr = (struct ifreq *)data; 1849 1850 switch (command) { 1851 case SIOCSIFFLAGS: 1852 STE_LOCK(sc); 1853 if ((ifp->if_flags & IFF_UP) != 0) { 1854 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1855 ((ifp->if_flags ^ sc->ste_if_flags) & 1856 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1857 ste_rxfilter(sc); 1858 else 1859 ste_init_locked(sc); 1860 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1861 ste_stop(sc); 1862 sc->ste_if_flags = ifp->if_flags; 1863 STE_UNLOCK(sc); 1864 break; 1865 case SIOCADDMULTI: 1866 case SIOCDELMULTI: 1867 STE_LOCK(sc); 1868 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1869 ste_rxfilter(sc); 1870 STE_UNLOCK(sc); 1871 break; 1872 case SIOCGIFMEDIA: 1873 case SIOCSIFMEDIA: 1874 mii = device_get_softc(sc->ste_miibus); 1875 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1876 break; 1877 case SIOCSIFCAP: 1878#ifdef DEVICE_POLLING 1879 if (ifr->ifr_reqcap & IFCAP_POLLING && 1880 !(ifp->if_capenable & IFCAP_POLLING)) { 1881 error = ether_poll_register(ste_poll, ifp); 1882 if (error) 1883 return (error); 1884 STE_LOCK(sc); 1885 /* Disable interrupts */ 1886 CSR_WRITE_2(sc, STE_IMR, 0); 1887 ifp->if_capenable |= IFCAP_POLLING; 1888 STE_UNLOCK(sc); 1889 return (error); 1890 1891 } 1892 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1893 ifp->if_capenable & IFCAP_POLLING) { 1894 error = ether_poll_deregister(ifp); 1895 /* Enable interrupts. */ 1896 STE_LOCK(sc); 1897 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1898 ifp->if_capenable &= ~IFCAP_POLLING; 1899 STE_UNLOCK(sc); 1900 return (error); 1901 } 1902#endif /* DEVICE_POLLING */ 1903 break; 1904 default: 1905 error = ether_ioctl(ifp, command, data); 1906 break; 1907 } 1908 1909 return (error); 1910} 1911 1912static int 1913ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1914{ 1915 struct ste_frag *frag; 1916 struct mbuf *m; 1917 struct ste_desc *desc; 1918 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1919 int error, i, nsegs; 1920 1921 STE_LOCK_ASSERT(sc); 1922 M_ASSERTPKTHDR((*m_head)); 1923 1924 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1925 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1926 if (error == EFBIG) { 1927 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS); 1928 if (m == NULL) { 1929 m_freem(*m_head); 1930 *m_head = NULL; 1931 return (ENOMEM); 1932 } 1933 *m_head = m; 1934 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1935 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1936 if (error != 0) { 1937 m_freem(*m_head); 1938 *m_head = NULL; 1939 return (error); 1940 } 1941 } else if (error != 0) 1942 return (error); 1943 if (nsegs == 0) { 1944 m_freem(*m_head); 1945 *m_head = NULL; 1946 return (EIO); 1947 } 1948 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1949 BUS_DMASYNC_PREWRITE); 1950 1951 desc = txc->ste_ptr; 1952 for (i = 0; i < nsegs; i++) { 1953 frag = &desc->ste_frags[i]; 1954 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1955 frag->ste_len = htole32(txsegs[i].ds_len); 1956 } 1957 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1958 /* 1959 * Because we use Tx polling we can't chain multiple 1960 * Tx descriptors here. Otherwise we race with controller. 1961 */ 1962 desc->ste_next = 0; 1963 if ((sc->ste_cdata.ste_tx_prod % STE_TX_INTR_FRAMES) == 0) 1964 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | 1965 STE_TXCTL_DMAINTR); 1966 else 1967 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS); 1968 txc->ste_mbuf = *m_head; 1969 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1970 sc->ste_cdata.ste_tx_cnt++; 1971 1972 return (0); 1973} 1974 1975static void 1976ste_start(struct ifnet *ifp) 1977{ 1978 struct ste_softc *sc; 1979 1980 sc = ifp->if_softc; 1981 STE_LOCK(sc); 1982 ste_start_locked(ifp); 1983 STE_UNLOCK(sc); 1984} 1985 1986static void 1987ste_start_locked(struct ifnet *ifp) 1988{ 1989 struct ste_softc *sc; 1990 struct ste_chain *cur_tx; 1991 struct mbuf *m_head = NULL; 1992 int enq; 1993 1994 sc = ifp->if_softc; 1995 STE_LOCK_ASSERT(sc); 1996 1997 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1998 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 1999 return; 2000 2001 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 2002 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 2003 /* 2004 * Controller may have cached copy of the last used 2005 * next ptr so we have to reserve one TFD to avoid 2006 * TFD overruns. 2007 */ 2008 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2009 break; 2010 } 2011 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2012 if (m_head == NULL) 2013 break; 2014 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 2015 if (ste_encap(sc, &m_head, cur_tx) != 0) { 2016 if (m_head == NULL) 2017 break; 2018 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2019 break; 2020 } 2021 if (sc->ste_cdata.ste_last_tx == NULL) { 2022 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 2023 sc->ste_cdata.ste_tx_list_map, 2024 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2025 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 2026 ste_wait(sc); 2027 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 2028 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 2029 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 2030 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 2031 ste_wait(sc); 2032 } else { 2033 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 2034 sc->ste_cdata.ste_last_tx->ste_phys; 2035 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 2036 sc->ste_cdata.ste_tx_list_map, 2037 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2038 } 2039 sc->ste_cdata.ste_last_tx = cur_tx; 2040 2041 enq++; 2042 /* 2043 * If there's a BPF listener, bounce a copy of this frame 2044 * to him. 2045 */ 2046 BPF_MTAP(ifp, m_head); 2047 } 2048 2049 if (enq > 0) 2050 sc->ste_timer = STE_TX_TIMEOUT; 2051} 2052 2053static void 2054ste_watchdog(struct ste_softc *sc) 2055{ 2056 struct ifnet *ifp; 2057 2058 ifp = sc->ste_ifp; 2059 STE_LOCK_ASSERT(sc); 2060 2061 if (sc->ste_timer == 0 || --sc->ste_timer) 2062 return; 2063 2064 ifp->if_oerrors++; 2065 if_printf(ifp, "watchdog timeout\n"); 2066 2067 ste_txeof(sc); 2068 ste_txeoc(sc); 2069 ste_rxeof(sc, -1); 2070 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2071 ste_init_locked(sc); 2072 2073 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2074 ste_start_locked(ifp); 2075} 2076 2077static int 2078ste_shutdown(device_t dev) 2079{ 2080 struct ste_softc *sc; 2081 2082 sc = device_get_softc(dev); 2083 2084 STE_LOCK(sc); 2085 ste_stop(sc); 2086 STE_UNLOCK(sc); 2087 2088 return (0); 2089} 2090 2091#define STE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2092 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2093#define STE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2094 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2095 2096static void 2097ste_sysctl_node(struct ste_softc *sc) 2098{ 2099 struct sysctl_ctx_list *ctx; 2100 struct sysctl_oid_list *child, *parent; 2101 struct sysctl_oid *tree; 2102 struct ste_hw_stats *stats; 2103 2104 stats = &sc->ste_stats; 2105 ctx = device_get_sysctl_ctx(sc->ste_dev); 2106 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ste_dev)); 2107 2108 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 2109 NULL, "STE statistics"); 2110 parent = SYSCTL_CHILDREN(tree); 2111 2112 /* Rx statistics. */ 2113 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 2114 NULL, "Rx MAC statistics"); 2115 child = SYSCTL_CHILDREN(tree); 2116 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2117 &stats->rx_bytes, "Good octets"); 2118 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2119 &stats->rx_frames, "Good frames"); 2120 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2121 &stats->rx_bcast_frames, "Good broadcast frames"); 2122 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2123 &stats->rx_mcast_frames, "Good multicast frames"); 2124 STE_SYSCTL_STAT_ADD32(ctx, child, "lost_frames", 2125 &stats->rx_lost_frames, "Lost frames"); 2126 2127 /* Tx statistics. */ 2128 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 2129 NULL, "Tx MAC statistics"); 2130 child = SYSCTL_CHILDREN(tree); 2131 STE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 2132 &stats->tx_bytes, "Good octets"); 2133 STE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2134 &stats->tx_frames, "Good frames"); 2135 STE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 2136 &stats->tx_bcast_frames, "Good broadcast frames"); 2137 STE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 2138 &stats->tx_mcast_frames, "Good multicast frames"); 2139 STE_SYSCTL_STAT_ADD32(ctx, child, "carrier_errs", 2140 &stats->tx_carrsense_errs, "Carrier sense errors"); 2141 STE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 2142 &stats->tx_single_colls, "Single collisions"); 2143 STE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 2144 &stats->tx_multi_colls, "Multiple collisions"); 2145 STE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2146 &stats->tx_late_colls, "Late collisions"); 2147 STE_SYSCTL_STAT_ADD32(ctx, child, "defers", 2148 &stats->tx_frames_defered, "Frames with deferrals"); 2149 STE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 2150 &stats->tx_excess_defers, "Frames with excessive derferrals"); 2151 STE_SYSCTL_STAT_ADD32(ctx, child, "abort", 2152 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 2153} 2154 2155#undef STE_SYSCTL_STAT_ADD32 2156#undef STE_SYSCTL_STAT_ADD64 2157