if_ste.c revision 200884
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 200884 2009-12-22 23:57:10Z yongari $"); 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53 54#include <net/bpf.h> 55#include <net/if.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61#include <net/if_vlan_var.h> 62 63#include <machine/bus.h> 64#include <machine/resource.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <dev/ste/if_stereg.h> 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77MODULE_DEPEND(ste, pci, 1, 1, 1); 78MODULE_DEPEND(ste, ether, 1, 1, 1); 79MODULE_DEPEND(ste, miibus, 1, 1, 1); 80 81/* Define to show Tx error status. */ 82#define STE_SHOW_TXERRORS 83 84/* 85 * Various supported device vendors/types and their names. 86 */ 87static struct ste_type ste_devs[] = { 88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 91 { 0, 0, NULL } 92}; 93 94static int ste_attach(device_t); 95static int ste_detach(device_t); 96static int ste_probe(device_t); 97static int ste_shutdown(device_t); 98 99static int ste_dma_alloc(struct ste_softc *); 100static void ste_dma_free(struct ste_softc *); 101static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 102static int ste_eeprom_wait(struct ste_softc *); 103static int ste_encap(struct ste_softc *, struct mbuf **, 104 struct ste_chain *); 105static int ste_ifmedia_upd(struct ifnet *); 106static void ste_ifmedia_upd_locked(struct ifnet *); 107static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 108static void ste_init(void *); 109static void ste_init_locked(struct ste_softc *); 110static int ste_init_rx_list(struct ste_softc *); 111static void ste_init_tx_list(struct ste_softc *); 112static void ste_intr(void *); 113static int ste_ioctl(struct ifnet *, u_long, caddr_t); 114static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 115static void ste_mii_send(struct ste_softc *, uint32_t, int); 116static void ste_mii_sync(struct ste_softc *); 117static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 118static int ste_miibus_readreg(device_t, int, int); 119static void ste_miibus_statchg(device_t); 120static int ste_miibus_writereg(device_t, int, int, int); 121static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 122static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 123static void ste_reset(struct ste_softc *); 124static void ste_restart_tx(struct ste_softc *); 125static int ste_rxeof(struct ste_softc *, int); 126static void ste_setmulti(struct ste_softc *); 127static void ste_start(struct ifnet *); 128static void ste_start_locked(struct ifnet *); 129static void ste_stats_update(struct ste_softc *); 130static void ste_stop(struct ste_softc *); 131static void ste_tick(void *); 132static void ste_txeoc(struct ste_softc *); 133static void ste_txeof(struct ste_softc *); 134static void ste_wait(struct ste_softc *); 135static void ste_watchdog(struct ste_softc *); 136 137static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160}; 161 162static devclass_t ste_devclass; 163 164DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167#define STE_SETBIT4(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 169 170#define STE_CLRBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 172 173#define STE_SETBIT2(sc, reg, x) \ 174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 175 176#define STE_CLRBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 178 179#define STE_SETBIT1(sc, reg, x) \ 180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 181 182#define STE_CLRBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 184 185 186#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 187#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 188 189/* 190 * Sync the PHYs by setting data bit and strobing the clock 32 times. 191 */ 192static void 193ste_mii_sync(struct ste_softc *sc) 194{ 195 int i; 196 197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 198 199 for (i = 0; i < 32; i++) { 200 MII_SET(STE_PHYCTL_MCLK); 201 DELAY(1); 202 MII_CLR(STE_PHYCTL_MCLK); 203 DELAY(1); 204 } 205} 206 207/* 208 * Clock a series of bits through the MII. 209 */ 210static void 211ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt) 212{ 213 int i; 214 215 MII_CLR(STE_PHYCTL_MCLK); 216 217 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 218 if (bits & i) { 219 MII_SET(STE_PHYCTL_MDATA); 220 } else { 221 MII_CLR(STE_PHYCTL_MDATA); 222 } 223 DELAY(1); 224 MII_CLR(STE_PHYCTL_MCLK); 225 DELAY(1); 226 MII_SET(STE_PHYCTL_MCLK); 227 } 228} 229 230/* 231 * Read an PHY register through the MII. 232 */ 233static int 234ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 235{ 236 int i, ack; 237 238 /* 239 * Set up frame for RX. 240 */ 241 frame->mii_stdelim = STE_MII_STARTDELIM; 242 frame->mii_opcode = STE_MII_READOP; 243 frame->mii_turnaround = 0; 244 frame->mii_data = 0; 245 246 CSR_WRITE_2(sc, STE_PHYCTL, 0); 247 /* 248 * Turn on data xmit. 249 */ 250 MII_SET(STE_PHYCTL_MDIR); 251 252 ste_mii_sync(sc); 253 254 /* 255 * Send command/address info. 256 */ 257 ste_mii_send(sc, frame->mii_stdelim, 2); 258 ste_mii_send(sc, frame->mii_opcode, 2); 259 ste_mii_send(sc, frame->mii_phyaddr, 5); 260 ste_mii_send(sc, frame->mii_regaddr, 5); 261 262 /* Turn off xmit. */ 263 MII_CLR(STE_PHYCTL_MDIR); 264 265 /* Idle bit */ 266 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 267 DELAY(1); 268 MII_SET(STE_PHYCTL_MCLK); 269 DELAY(1); 270 271 /* Check for ack */ 272 MII_CLR(STE_PHYCTL_MCLK); 273 DELAY(1); 274 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 275 MII_SET(STE_PHYCTL_MCLK); 276 DELAY(1); 277 278 /* 279 * Now try reading data bits. If the ack failed, we still 280 * need to clock through 16 cycles to keep the PHY(s) in sync. 281 */ 282 if (ack) { 283 for (i = 0; i < 16; i++) { 284 MII_CLR(STE_PHYCTL_MCLK); 285 DELAY(1); 286 MII_SET(STE_PHYCTL_MCLK); 287 DELAY(1); 288 } 289 goto fail; 290 } 291 292 for (i = 0x8000; i; i >>= 1) { 293 MII_CLR(STE_PHYCTL_MCLK); 294 DELAY(1); 295 if (!ack) { 296 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 297 frame->mii_data |= i; 298 DELAY(1); 299 } 300 MII_SET(STE_PHYCTL_MCLK); 301 DELAY(1); 302 } 303 304fail: 305 306 MII_CLR(STE_PHYCTL_MCLK); 307 DELAY(1); 308 MII_SET(STE_PHYCTL_MCLK); 309 DELAY(1); 310 311 if (ack) 312 return (1); 313 return (0); 314} 315 316/* 317 * Write to a PHY register through the MII. 318 */ 319static int 320ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 321{ 322 323 /* 324 * Set up frame for TX. 325 */ 326 327 frame->mii_stdelim = STE_MII_STARTDELIM; 328 frame->mii_opcode = STE_MII_WRITEOP; 329 frame->mii_turnaround = STE_MII_TURNAROUND; 330 331 /* 332 * Turn on data output. 333 */ 334 MII_SET(STE_PHYCTL_MDIR); 335 336 ste_mii_sync(sc); 337 338 ste_mii_send(sc, frame->mii_stdelim, 2); 339 ste_mii_send(sc, frame->mii_opcode, 2); 340 ste_mii_send(sc, frame->mii_phyaddr, 5); 341 ste_mii_send(sc, frame->mii_regaddr, 5); 342 ste_mii_send(sc, frame->mii_turnaround, 2); 343 ste_mii_send(sc, frame->mii_data, 16); 344 345 /* Idle bit. */ 346 MII_SET(STE_PHYCTL_MCLK); 347 DELAY(1); 348 MII_CLR(STE_PHYCTL_MCLK); 349 DELAY(1); 350 351 /* 352 * Turn off xmit. 353 */ 354 MII_CLR(STE_PHYCTL_MDIR); 355 356 return (0); 357} 358 359static int 360ste_miibus_readreg(device_t dev, int phy, int reg) 361{ 362 struct ste_softc *sc; 363 struct ste_mii_frame frame; 364 365 sc = device_get_softc(dev); 366 367 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0 && phy != 0) 368 return (0); 369 370 bzero((char *)&frame, sizeof(frame)); 371 372 frame.mii_phyaddr = phy; 373 frame.mii_regaddr = reg; 374 ste_mii_readreg(sc, &frame); 375 376 return (frame.mii_data); 377} 378 379static int 380ste_miibus_writereg(device_t dev, int phy, int reg, int data) 381{ 382 struct ste_softc *sc; 383 struct ste_mii_frame frame; 384 385 sc = device_get_softc(dev); 386 bzero((char *)&frame, sizeof(frame)); 387 388 frame.mii_phyaddr = phy; 389 frame.mii_regaddr = reg; 390 frame.mii_data = data; 391 392 ste_mii_writereg(sc, &frame); 393 394 return (0); 395} 396 397static void 398ste_miibus_statchg(device_t dev) 399{ 400 struct ste_softc *sc; 401 struct mii_data *mii; 402 struct ifnet *ifp; 403 uint16_t cfg; 404 405 sc = device_get_softc(dev); 406 407 mii = device_get_softc(sc->ste_miibus); 408 ifp = sc->ste_ifp; 409 if (mii == NULL || ifp == NULL || 410 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 411 return; 412 413 sc->ste_flags &= ~STE_FLAG_LINK; 414 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 415 (IFM_ACTIVE | IFM_AVALID)) { 416 switch (IFM_SUBTYPE(mii->mii_media_active)) { 417 case IFM_10_T: 418 case IFM_100_TX: 419 case IFM_100_FX: 420 case IFM_100_T4: 421 sc->ste_flags |= STE_FLAG_LINK; 422 default: 423 break; 424 } 425 } 426 427 /* Program MACs with resolved speed/duplex/flow-control. */ 428 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 429 cfg = CSR_READ_2(sc, STE_MACCTL0); 430 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 431 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 432 /* 433 * ST201 data sheet says driver should enable receiving 434 * MAC control frames bit of receive mode register to 435 * receive flow-control frames but the register has no 436 * such bits. In addition the controller has no ability 437 * to send pause frames so it should be handled in 438 * driver. Implementing pause timer handling in driver 439 * layer is not trivial, so don't enable flow-control 440 * here. 441 */ 442 cfg |= STE_MACCTL0_FULLDUPLEX; 443 } 444 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 445 } 446} 447 448static int 449ste_ifmedia_upd(struct ifnet *ifp) 450{ 451 struct ste_softc *sc; 452 453 sc = ifp->if_softc; 454 STE_LOCK(sc); 455 ste_ifmedia_upd_locked(ifp); 456 STE_UNLOCK(sc); 457 458 return (0); 459} 460 461static void 462ste_ifmedia_upd_locked(struct ifnet *ifp) 463{ 464 struct ste_softc *sc; 465 struct mii_data *mii; 466 467 sc = ifp->if_softc; 468 STE_LOCK_ASSERT(sc); 469 mii = device_get_softc(sc->ste_miibus); 470 sc->ste_flags &= ~STE_FLAG_LINK; 471 if (mii->mii_instance) { 472 struct mii_softc *miisc; 473 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 474 mii_phy_reset(miisc); 475 } 476 mii_mediachg(mii); 477} 478 479static void 480ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 481{ 482 struct ste_softc *sc; 483 struct mii_data *mii; 484 485 sc = ifp->if_softc; 486 mii = device_get_softc(sc->ste_miibus); 487 488 STE_LOCK(sc); 489 mii_pollstat(mii); 490 ifmr->ifm_active = mii->mii_media_active; 491 ifmr->ifm_status = mii->mii_media_status; 492 STE_UNLOCK(sc); 493} 494 495static void 496ste_wait(struct ste_softc *sc) 497{ 498 int i; 499 500 for (i = 0; i < STE_TIMEOUT; i++) { 501 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 502 break; 503 DELAY(1); 504 } 505 506 if (i == STE_TIMEOUT) 507 device_printf(sc->ste_dev, "command never completed!\n"); 508} 509 510/* 511 * The EEPROM is slow: give it time to come ready after issuing 512 * it a command. 513 */ 514static int 515ste_eeprom_wait(struct ste_softc *sc) 516{ 517 int i; 518 519 DELAY(1000); 520 521 for (i = 0; i < 100; i++) { 522 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 523 DELAY(1000); 524 else 525 break; 526 } 527 528 if (i == 100) { 529 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 530 return (1); 531 } 532 533 return (0); 534} 535 536/* 537 * Read a sequence of words from the EEPROM. Note that ethernet address 538 * data is stored in the EEPROM in network byte order. 539 */ 540static int 541ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 542{ 543 uint16_t word, *ptr; 544 int err = 0, i; 545 546 if (ste_eeprom_wait(sc)) 547 return (1); 548 549 for (i = 0; i < cnt; i++) { 550 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 551 err = ste_eeprom_wait(sc); 552 if (err) 553 break; 554 word = CSR_READ_2(sc, STE_EEPROM_DATA); 555 ptr = (uint16_t *)(dest + (i * 2)); 556 if (swap) 557 *ptr = ntohs(word); 558 else 559 *ptr = word; 560 } 561 562 return (err ? 1 : 0); 563} 564 565static void 566ste_setmulti(struct ste_softc *sc) 567{ 568 struct ifnet *ifp; 569 struct ifmultiaddr *ifma; 570 uint32_t hashes[2] = { 0, 0 }; 571 int h; 572 573 ifp = sc->ste_ifp; 574 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 575 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 576 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 577 return; 578 } 579 580 /* first, zot all the existing hash bits */ 581 CSR_WRITE_2(sc, STE_MAR0, 0); 582 CSR_WRITE_2(sc, STE_MAR1, 0); 583 CSR_WRITE_2(sc, STE_MAR2, 0); 584 CSR_WRITE_2(sc, STE_MAR3, 0); 585 586 /* now program new ones */ 587 if_maddr_rlock(ifp); 588 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 589 if (ifma->ifma_addr->sa_family != AF_LINK) 590 continue; 591 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 592 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 593 if (h < 32) 594 hashes[0] |= (1 << h); 595 else 596 hashes[1] |= (1 << (h - 32)); 597 } 598 if_maddr_runlock(ifp); 599 600 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 601 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 602 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 603 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 604 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 605 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 606} 607 608#ifdef DEVICE_POLLING 609static poll_handler_t ste_poll, ste_poll_locked; 610 611static int 612ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 613{ 614 struct ste_softc *sc = ifp->if_softc; 615 int rx_npkts = 0; 616 617 STE_LOCK(sc); 618 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 619 rx_npkts = ste_poll_locked(ifp, cmd, count); 620 STE_UNLOCK(sc); 621 return (rx_npkts); 622} 623 624static int 625ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 626{ 627 struct ste_softc *sc = ifp->if_softc; 628 int rx_npkts; 629 630 STE_LOCK_ASSERT(sc); 631 632 rx_npkts = ste_rxeof(sc, count); 633 ste_txeof(sc); 634 ste_txeoc(sc); 635 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 636 ste_start_locked(ifp); 637 638 if (cmd == POLL_AND_CHECK_STATUS) { 639 uint16_t status; 640 641 status = CSR_READ_2(sc, STE_ISR_ACK); 642 643 if (status & STE_ISR_STATS_OFLOW) 644 ste_stats_update(sc); 645 646 if (status & STE_ISR_HOSTERR) 647 ste_init_locked(sc); 648 } 649 return (rx_npkts); 650} 651#endif /* DEVICE_POLLING */ 652 653static void 654ste_intr(void *xsc) 655{ 656 struct ste_softc *sc; 657 struct ifnet *ifp; 658 uint16_t status; 659 660 sc = xsc; 661 STE_LOCK(sc); 662 ifp = sc->ste_ifp; 663 664#ifdef DEVICE_POLLING 665 if (ifp->if_capenable & IFCAP_POLLING) { 666 STE_UNLOCK(sc); 667 return; 668 } 669#endif 670 671 /* See if this is really our interrupt. */ 672 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 673 STE_UNLOCK(sc); 674 return; 675 } 676 677 for (;;) { 678 status = CSR_READ_2(sc, STE_ISR_ACK); 679 680 if (!(status & STE_INTRS)) 681 break; 682 683 if (status & STE_ISR_RX_DMADONE) 684 ste_rxeof(sc, -1); 685 686 if (status & STE_ISR_TX_DMADONE) 687 ste_txeof(sc); 688 689 if (status & STE_ISR_TX_DONE) 690 ste_txeoc(sc); 691 692 if (status & STE_ISR_STATS_OFLOW) 693 ste_stats_update(sc); 694 695 if (status & STE_ISR_HOSTERR) 696 ste_init_locked(sc); 697 } 698 699 /* Re-enable interrupts */ 700 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 701 702 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 703 ste_start_locked(ifp); 704 705 STE_UNLOCK(sc); 706} 707 708/* 709 * A frame has been uploaded: pass the resulting mbuf chain up to 710 * the higher level protocols. 711 */ 712static int 713ste_rxeof(struct ste_softc *sc, int count) 714{ 715 struct mbuf *m; 716 struct ifnet *ifp; 717 struct ste_chain_onefrag *cur_rx; 718 uint32_t rxstat; 719 int total_len, rx_npkts; 720 721 ifp = sc->ste_ifp; 722 723 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 724 sc->ste_cdata.ste_rx_list_map, 725 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 726 727 cur_rx = sc->ste_cdata.ste_rx_head; 728 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 729 cur_rx = cur_rx->ste_next) { 730 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 731 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 732 break; 733#ifdef DEVICE_POLLING 734 if (ifp->if_capenable & IFCAP_POLLING) { 735 if (count == 0) 736 break; 737 count--; 738 } 739#endif 740 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 741 break; 742 /* 743 * If an error occurs, update stats, clear the 744 * status word and leave the mbuf cluster in place: 745 * it should simply get re-used next time this descriptor 746 * comes up in the ring. 747 */ 748 if (rxstat & STE_RXSTAT_FRAME_ERR) { 749 ifp->if_ierrors++; 750 cur_rx->ste_ptr->ste_status = 0; 751 continue; 752 } 753 754 /* No errors; receive the packet. */ 755 m = cur_rx->ste_mbuf; 756 total_len = STE_RX_BYTES(rxstat); 757 758 /* 759 * Try to conjure up a new mbuf cluster. If that 760 * fails, it means we have an out of memory condition and 761 * should leave the buffer in place and continue. This will 762 * result in a lost packet, but there's little else we 763 * can do in this situation. 764 */ 765 if (ste_newbuf(sc, cur_rx) != 0) { 766 ifp->if_ierrors++; 767 cur_rx->ste_ptr->ste_status = 0; 768 continue; 769 } 770 771 m->m_pkthdr.rcvif = ifp; 772 m->m_pkthdr.len = m->m_len = total_len; 773 774 ifp->if_ipackets++; 775 STE_UNLOCK(sc); 776 (*ifp->if_input)(ifp, m); 777 STE_LOCK(sc); 778 } 779 780 if (rx_npkts > 0) { 781 sc->ste_cdata.ste_rx_head = cur_rx; 782 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 783 sc->ste_cdata.ste_rx_list_map, 784 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 785 } 786 787 return (rx_npkts); 788} 789 790static void 791ste_txeoc(struct ste_softc *sc) 792{ 793 uint16_t txstat; 794 struct ifnet *ifp; 795 796 STE_LOCK_ASSERT(sc); 797 798 ifp = sc->ste_ifp; 799 800 /* 801 * STE_TX_STATUS register implements a queue of up to 31 802 * transmit status byte. Writing an arbitrary value to the 803 * register will advance the queue to the next transmit 804 * status byte. This means if driver does not read 805 * STE_TX_STATUS register after completing sending more 806 * than 31 frames the controller would be stalled so driver 807 * should re-wake the Tx MAC. This is the most severe 808 * limitation of ST201 based controller. 809 */ 810 for (;;) { 811 txstat = CSR_READ_2(sc, STE_TX_STATUS); 812 if ((txstat & STE_TXSTATUS_TXDONE) == 0) 813 break; 814 if ((txstat & (STE_TXSTATUS_UNDERRUN | 815 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR | 816 STE_TXSTATUS_STATSOFLOW)) != 0) { 817 ifp->if_oerrors++; 818#ifdef STE_SHOW_TXERRORS 819 device_printf(sc->ste_dev, "TX error : 0x%b\n", 820 txstat & 0xFF, STE_ERR_BITS); 821#endif 822 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 && 823 sc->ste_tx_thresh < STE_PACKET_SIZE) { 824 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 825 if (sc->ste_tx_thresh > STE_PACKET_SIZE) 826 sc->ste_tx_thresh = STE_PACKET_SIZE; 827 device_printf(sc->ste_dev, 828 "TX underrun, increasing TX" 829 " start threshold to %d bytes\n", 830 sc->ste_tx_thresh); 831 /* Make sure to disable active DMA cycles. */ 832 STE_SETBIT4(sc, STE_DMACTL, 833 STE_DMACTL_TXDMA_STALL); 834 ste_wait(sc); 835 ste_init_locked(sc); 836 break; 837 } 838 /* Restart Tx. */ 839 ste_restart_tx(sc); 840 } 841 /* 842 * Advance to next status and ACK TxComplete 843 * interrupt. ST201 data sheet was wrong here, to 844 * get next Tx status, we have to write both 845 * STE_TX_STATUS and STE_TX_FRAMEID register. 846 * Otherwise controller returns the same status 847 * as well as not acknowledge Tx completion 848 * interrupt. 849 */ 850 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 851 } 852} 853 854static void 855ste_tick(void *arg) 856{ 857 struct ste_softc *sc; 858 struct mii_data *mii; 859 860 sc = (struct ste_softc *)arg; 861 862 STE_LOCK_ASSERT(sc); 863 864 mii = device_get_softc(sc->ste_miibus); 865 mii_tick(mii); 866 /* 867 * ukphy(4) does not seem to generate CB that reports 868 * resolved link state so if we know we lost a link, 869 * explicitly check the link state. 870 */ 871 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 872 ste_miibus_statchg(sc->ste_dev); 873 ste_stats_update(sc); 874 ste_watchdog(sc); 875 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 876} 877 878static void 879ste_txeof(struct ste_softc *sc) 880{ 881 struct ifnet *ifp; 882 struct ste_chain *cur_tx; 883 uint32_t txstat; 884 int idx; 885 886 STE_LOCK_ASSERT(sc); 887 888 ifp = sc->ste_ifp; 889 idx = sc->ste_cdata.ste_tx_cons; 890 if (idx == sc->ste_cdata.ste_tx_prod) 891 return; 892 893 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 894 sc->ste_cdata.ste_tx_list_map, 895 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 896 897 while (idx != sc->ste_cdata.ste_tx_prod) { 898 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 899 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 900 if ((txstat & STE_TXCTL_DMADONE) == 0) 901 break; 902 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 903 BUS_DMASYNC_POSTWRITE); 904 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 905 KASSERT(cur_tx->ste_mbuf != NULL, 906 ("%s: freeing NULL mbuf!\n", __func__)); 907 m_freem(cur_tx->ste_mbuf); 908 cur_tx->ste_mbuf = NULL; 909 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 910 ifp->if_opackets++; 911 sc->ste_cdata.ste_tx_cnt--; 912 STE_INC(idx, STE_TX_LIST_CNT); 913 } 914 915 sc->ste_cdata.ste_tx_cons = idx; 916 if (sc->ste_cdata.ste_tx_cnt == 0) 917 sc->ste_timer = 0; 918} 919 920static void 921ste_stats_update(struct ste_softc *sc) 922{ 923 struct ifnet *ifp; 924 925 STE_LOCK_ASSERT(sc); 926 927 ifp = sc->ste_ifp; 928 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 929 + CSR_READ_1(sc, STE_MULTI_COLLS) 930 + CSR_READ_1(sc, STE_SINGLE_COLLS); 931} 932 933/* 934 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 935 * IDs against our list and return a device name if we find a match. 936 */ 937static int 938ste_probe(device_t dev) 939{ 940 struct ste_type *t; 941 942 t = ste_devs; 943 944 while (t->ste_name != NULL) { 945 if ((pci_get_vendor(dev) == t->ste_vid) && 946 (pci_get_device(dev) == t->ste_did)) { 947 device_set_desc(dev, t->ste_name); 948 return (BUS_PROBE_DEFAULT); 949 } 950 t++; 951 } 952 953 return (ENXIO); 954} 955 956/* 957 * Attach the interface. Allocate softc structures, do ifmedia 958 * setup and ethernet/BPF attach. 959 */ 960static int 961ste_attach(device_t dev) 962{ 963 struct ste_softc *sc; 964 struct ifnet *ifp; 965 u_char eaddr[6]; 966 int error = 0, rid; 967 968 sc = device_get_softc(dev); 969 sc->ste_dev = dev; 970 971 /* 972 * Only use one PHY since this chip reports multiple 973 * Note on the DFE-550 the PHY is at 1 on the DFE-580 974 * it is at 0 & 1. It is rev 0x12. 975 */ 976 if (pci_get_vendor(dev) == DL_VENDORID && 977 pci_get_device(dev) == DL_DEVICEID_DL10050 && 978 pci_get_revid(dev) == 0x12 ) 979 sc->ste_flags |= STE_FLAG_ONE_PHY; 980 981 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 982 MTX_DEF); 983 /* 984 * Map control/status registers. 985 */ 986 pci_enable_busmaster(dev); 987 988 /* Prefer memory space register mapping over IO space. */ 989 sc->ste_res_id = PCIR_BAR(1); 990 sc->ste_res_type = SYS_RES_MEMORY; 991 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 992 &sc->ste_res_id, RF_ACTIVE); 993 if (sc->ste_res == NULL) { 994 sc->ste_res_id = PCIR_BAR(0); 995 sc->ste_res_type = SYS_RES_IOPORT; 996 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 997 &sc->ste_res_id, RF_ACTIVE); 998 } 999 if (sc->ste_res == NULL) { 1000 device_printf(dev, "couldn't map ports/memory\n"); 1001 error = ENXIO; 1002 goto fail; 1003 } 1004 1005 /* Allocate interrupt */ 1006 rid = 0; 1007 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1008 RF_SHAREABLE | RF_ACTIVE); 1009 1010 if (sc->ste_irq == NULL) { 1011 device_printf(dev, "couldn't map interrupt\n"); 1012 error = ENXIO; 1013 goto fail; 1014 } 1015 1016 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 1017 1018 /* Reset the adapter. */ 1019 ste_reset(sc); 1020 1021 /* 1022 * Get station address from the EEPROM. 1023 */ 1024 if (ste_read_eeprom(sc, eaddr, 1025 STE_EEADDR_NODE0, 3, 0)) { 1026 device_printf(dev, "failed to read station address\n"); 1027 error = ENXIO;; 1028 goto fail; 1029 } 1030 1031 if ((error = ste_dma_alloc(sc)) != 0) 1032 goto fail; 1033 1034 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1035 if (ifp == NULL) { 1036 device_printf(dev, "can not if_alloc()\n"); 1037 error = ENOSPC; 1038 goto fail; 1039 } 1040 1041 /* Do MII setup. */ 1042 if (mii_phy_probe(dev, &sc->ste_miibus, 1043 ste_ifmedia_upd, ste_ifmedia_sts)) { 1044 device_printf(dev, "MII without any phy!\n"); 1045 error = ENXIO; 1046 goto fail; 1047 } 1048 1049 ifp->if_softc = sc; 1050 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1051 ifp->if_mtu = ETHERMTU; 1052 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1053 ifp->if_ioctl = ste_ioctl; 1054 ifp->if_start = ste_start; 1055 ifp->if_init = ste_init; 1056 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1057 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1058 IFQ_SET_READY(&ifp->if_snd); 1059 1060 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1061 1062 /* 1063 * Call MI attach routine. 1064 */ 1065 ether_ifattach(ifp, eaddr); 1066 1067 /* 1068 * Tell the upper layer(s) we support long frames. 1069 */ 1070 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1071 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1072 ifp->if_capenable = ifp->if_capabilities; 1073#ifdef DEVICE_POLLING 1074 ifp->if_capabilities |= IFCAP_POLLING; 1075#endif 1076 1077 /* Hook interrupt last to avoid having to lock softc */ 1078 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1079 NULL, ste_intr, sc, &sc->ste_intrhand); 1080 1081 if (error) { 1082 device_printf(dev, "couldn't set up irq\n"); 1083 ether_ifdetach(ifp); 1084 goto fail; 1085 } 1086 1087fail: 1088 if (error) 1089 ste_detach(dev); 1090 1091 return (error); 1092} 1093 1094/* 1095 * Shutdown hardware and free up resources. This can be called any 1096 * time after the mutex has been initialized. It is called in both 1097 * the error case in attach and the normal detach case so it needs 1098 * to be careful about only freeing resources that have actually been 1099 * allocated. 1100 */ 1101static int 1102ste_detach(device_t dev) 1103{ 1104 struct ste_softc *sc; 1105 struct ifnet *ifp; 1106 1107 sc = device_get_softc(dev); 1108 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1109 ifp = sc->ste_ifp; 1110 1111#ifdef DEVICE_POLLING 1112 if (ifp->if_capenable & IFCAP_POLLING) 1113 ether_poll_deregister(ifp); 1114#endif 1115 1116 /* These should only be active if attach succeeded */ 1117 if (device_is_attached(dev)) { 1118 ether_ifdetach(ifp); 1119 STE_LOCK(sc); 1120 ste_stop(sc); 1121 STE_UNLOCK(sc); 1122 callout_drain(&sc->ste_callout); 1123 } 1124 if (sc->ste_miibus) 1125 device_delete_child(dev, sc->ste_miibus); 1126 bus_generic_detach(dev); 1127 1128 if (sc->ste_intrhand) 1129 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1130 if (sc->ste_irq) 1131 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1132 if (sc->ste_res) 1133 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1134 sc->ste_res); 1135 1136 if (ifp) 1137 if_free(ifp); 1138 1139 ste_dma_free(sc); 1140 mtx_destroy(&sc->ste_mtx); 1141 1142 return (0); 1143} 1144 1145struct ste_dmamap_arg { 1146 bus_addr_t ste_busaddr; 1147}; 1148 1149static void 1150ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1151{ 1152 struct ste_dmamap_arg *ctx; 1153 1154 if (error != 0) 1155 return; 1156 1157 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1158 1159 ctx = (struct ste_dmamap_arg *)arg; 1160 ctx->ste_busaddr = segs[0].ds_addr; 1161} 1162 1163static int 1164ste_dma_alloc(struct ste_softc *sc) 1165{ 1166 struct ste_chain *txc; 1167 struct ste_chain_onefrag *rxc; 1168 struct ste_dmamap_arg ctx; 1169 int error, i; 1170 1171 /* Create parent DMA tag. */ 1172 error = bus_dma_tag_create( 1173 bus_get_dma_tag(sc->ste_dev), /* parent */ 1174 1, 0, /* alignment, boundary */ 1175 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1176 BUS_SPACE_MAXADDR, /* highaddr */ 1177 NULL, NULL, /* filter, filterarg */ 1178 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1179 0, /* nsegments */ 1180 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1181 0, /* flags */ 1182 NULL, NULL, /* lockfunc, lockarg */ 1183 &sc->ste_cdata.ste_parent_tag); 1184 if (error != 0) { 1185 device_printf(sc->ste_dev, 1186 "could not create parent DMA tag.\n"); 1187 goto fail; 1188 } 1189 1190 /* Create DMA tag for Tx descriptor list. */ 1191 error = bus_dma_tag_create( 1192 sc->ste_cdata.ste_parent_tag, /* parent */ 1193 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1194 BUS_SPACE_MAXADDR, /* lowaddr */ 1195 BUS_SPACE_MAXADDR, /* highaddr */ 1196 NULL, NULL, /* filter, filterarg */ 1197 STE_TX_LIST_SZ, /* maxsize */ 1198 1, /* nsegments */ 1199 STE_TX_LIST_SZ, /* maxsegsize */ 1200 0, /* flags */ 1201 NULL, NULL, /* lockfunc, lockarg */ 1202 &sc->ste_cdata.ste_tx_list_tag); 1203 if (error != 0) { 1204 device_printf(sc->ste_dev, 1205 "could not create Tx list DMA tag.\n"); 1206 goto fail; 1207 } 1208 1209 /* Create DMA tag for Rx descriptor list. */ 1210 error = bus_dma_tag_create( 1211 sc->ste_cdata.ste_parent_tag, /* parent */ 1212 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1213 BUS_SPACE_MAXADDR, /* lowaddr */ 1214 BUS_SPACE_MAXADDR, /* highaddr */ 1215 NULL, NULL, /* filter, filterarg */ 1216 STE_RX_LIST_SZ, /* maxsize */ 1217 1, /* nsegments */ 1218 STE_RX_LIST_SZ, /* maxsegsize */ 1219 0, /* flags */ 1220 NULL, NULL, /* lockfunc, lockarg */ 1221 &sc->ste_cdata.ste_rx_list_tag); 1222 if (error != 0) { 1223 device_printf(sc->ste_dev, 1224 "could not create Rx list DMA tag.\n"); 1225 goto fail; 1226 } 1227 1228 /* Create DMA tag for Tx buffers. */ 1229 error = bus_dma_tag_create( 1230 sc->ste_cdata.ste_parent_tag, /* parent */ 1231 1, 0, /* alignment, boundary */ 1232 BUS_SPACE_MAXADDR, /* lowaddr */ 1233 BUS_SPACE_MAXADDR, /* highaddr */ 1234 NULL, NULL, /* filter, filterarg */ 1235 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1236 STE_MAXFRAGS, /* nsegments */ 1237 MCLBYTES, /* maxsegsize */ 1238 0, /* flags */ 1239 NULL, NULL, /* lockfunc, lockarg */ 1240 &sc->ste_cdata.ste_tx_tag); 1241 if (error != 0) { 1242 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1243 goto fail; 1244 } 1245 1246 /* Create DMA tag for Rx buffers. */ 1247 error = bus_dma_tag_create( 1248 sc->ste_cdata.ste_parent_tag, /* parent */ 1249 1, 0, /* alignment, boundary */ 1250 BUS_SPACE_MAXADDR, /* lowaddr */ 1251 BUS_SPACE_MAXADDR, /* highaddr */ 1252 NULL, NULL, /* filter, filterarg */ 1253 MCLBYTES, /* maxsize */ 1254 1, /* nsegments */ 1255 MCLBYTES, /* maxsegsize */ 1256 0, /* flags */ 1257 NULL, NULL, /* lockfunc, lockarg */ 1258 &sc->ste_cdata.ste_rx_tag); 1259 if (error != 0) { 1260 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1261 goto fail; 1262 } 1263 1264 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1265 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1266 (void **)&sc->ste_ldata.ste_tx_list, 1267 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1268 &sc->ste_cdata.ste_tx_list_map); 1269 if (error != 0) { 1270 device_printf(sc->ste_dev, 1271 "could not allocate DMA'able memory for Tx list.\n"); 1272 goto fail; 1273 } 1274 ctx.ste_busaddr = 0; 1275 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1276 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1277 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1278 if (error != 0 || ctx.ste_busaddr == 0) { 1279 device_printf(sc->ste_dev, 1280 "could not load DMA'able memory for Tx list.\n"); 1281 goto fail; 1282 } 1283 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1284 1285 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1286 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1287 (void **)&sc->ste_ldata.ste_rx_list, 1288 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1289 &sc->ste_cdata.ste_rx_list_map); 1290 if (error != 0) { 1291 device_printf(sc->ste_dev, 1292 "could not allocate DMA'able memory for Rx list.\n"); 1293 goto fail; 1294 } 1295 ctx.ste_busaddr = 0; 1296 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1297 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1298 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1299 if (error != 0 || ctx.ste_busaddr == 0) { 1300 device_printf(sc->ste_dev, 1301 "could not load DMA'able memory for Rx list.\n"); 1302 goto fail; 1303 } 1304 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1305 1306 /* Create DMA maps for Tx buffers. */ 1307 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1308 txc = &sc->ste_cdata.ste_tx_chain[i]; 1309 txc->ste_ptr = NULL; 1310 txc->ste_mbuf = NULL; 1311 txc->ste_next = NULL; 1312 txc->ste_phys = 0; 1313 txc->ste_map = NULL; 1314 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1315 &txc->ste_map); 1316 if (error != 0) { 1317 device_printf(sc->ste_dev, 1318 "could not create Tx dmamap.\n"); 1319 goto fail; 1320 } 1321 } 1322 /* Create DMA maps for Rx buffers. */ 1323 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1324 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1325 device_printf(sc->ste_dev, 1326 "could not create spare Rx dmamap.\n"); 1327 goto fail; 1328 } 1329 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1330 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1331 rxc->ste_ptr = NULL; 1332 rxc->ste_mbuf = NULL; 1333 rxc->ste_next = NULL; 1334 rxc->ste_map = NULL; 1335 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1336 &rxc->ste_map); 1337 if (error != 0) { 1338 device_printf(sc->ste_dev, 1339 "could not create Rx dmamap.\n"); 1340 goto fail; 1341 } 1342 } 1343 1344fail: 1345 return (error); 1346} 1347 1348static void 1349ste_dma_free(struct ste_softc *sc) 1350{ 1351 struct ste_chain *txc; 1352 struct ste_chain_onefrag *rxc; 1353 int i; 1354 1355 /* Tx buffers. */ 1356 if (sc->ste_cdata.ste_tx_tag != NULL) { 1357 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1358 txc = &sc->ste_cdata.ste_tx_chain[i]; 1359 if (txc->ste_map != NULL) { 1360 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1361 txc->ste_map); 1362 txc->ste_map = NULL; 1363 } 1364 } 1365 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1366 sc->ste_cdata.ste_tx_tag = NULL; 1367 } 1368 /* Rx buffers. */ 1369 if (sc->ste_cdata.ste_rx_tag != NULL) { 1370 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1371 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1372 if (rxc->ste_map != NULL) { 1373 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1374 rxc->ste_map); 1375 rxc->ste_map = NULL; 1376 } 1377 } 1378 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1379 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1380 sc->ste_cdata.ste_rx_sparemap); 1381 sc->ste_cdata.ste_rx_sparemap = NULL; 1382 } 1383 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1384 sc->ste_cdata.ste_rx_tag = NULL; 1385 } 1386 /* Tx descriptor list. */ 1387 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1388 if (sc->ste_cdata.ste_tx_list_map != NULL) 1389 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1390 sc->ste_cdata.ste_tx_list_map); 1391 if (sc->ste_cdata.ste_tx_list_map != NULL && 1392 sc->ste_ldata.ste_tx_list != NULL) 1393 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1394 sc->ste_ldata.ste_tx_list, 1395 sc->ste_cdata.ste_tx_list_map); 1396 sc->ste_ldata.ste_tx_list = NULL; 1397 sc->ste_cdata.ste_tx_list_map = NULL; 1398 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1399 sc->ste_cdata.ste_tx_list_tag = NULL; 1400 } 1401 /* Rx descriptor list. */ 1402 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1403 if (sc->ste_cdata.ste_rx_list_map != NULL) 1404 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1405 sc->ste_cdata.ste_rx_list_map); 1406 if (sc->ste_cdata.ste_rx_list_map != NULL && 1407 sc->ste_ldata.ste_rx_list != NULL) 1408 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1409 sc->ste_ldata.ste_rx_list, 1410 sc->ste_cdata.ste_rx_list_map); 1411 sc->ste_ldata.ste_rx_list = NULL; 1412 sc->ste_cdata.ste_rx_list_map = NULL; 1413 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1414 sc->ste_cdata.ste_rx_list_tag = NULL; 1415 } 1416 if (sc->ste_cdata.ste_parent_tag != NULL) { 1417 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1418 sc->ste_cdata.ste_parent_tag = NULL; 1419 } 1420} 1421 1422static int 1423ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1424{ 1425 struct mbuf *m; 1426 bus_dma_segment_t segs[1]; 1427 bus_dmamap_t map; 1428 int error, nsegs; 1429 1430 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1431 if (m == NULL) 1432 return (ENOBUFS); 1433 m->m_len = m->m_pkthdr.len = MCLBYTES; 1434 m_adj(m, ETHER_ALIGN); 1435 1436 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1437 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1438 m_freem(m); 1439 return (error); 1440 } 1441 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1442 1443 if (rxc->ste_mbuf != NULL) { 1444 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1445 BUS_DMASYNC_POSTREAD); 1446 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1447 } 1448 map = rxc->ste_map; 1449 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1450 sc->ste_cdata.ste_rx_sparemap = map; 1451 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1452 BUS_DMASYNC_PREREAD); 1453 rxc->ste_mbuf = m; 1454 rxc->ste_ptr->ste_status = 0; 1455 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1456 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1457 STE_FRAG_LAST); 1458 return (0); 1459} 1460 1461static int 1462ste_init_rx_list(struct ste_softc *sc) 1463{ 1464 struct ste_chain_data *cd; 1465 struct ste_list_data *ld; 1466 int error, i; 1467 1468 cd = &sc->ste_cdata; 1469 ld = &sc->ste_ldata; 1470 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1471 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1472 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1473 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1474 if (error != 0) 1475 return (error); 1476 if (i == (STE_RX_LIST_CNT - 1)) { 1477 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1478 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1479 (sizeof(struct ste_desc_onefrag) * 0); 1480 } else { 1481 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1482 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1483 (sizeof(struct ste_desc_onefrag) * (i + 1)); 1484 } 1485 } 1486 1487 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1488 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1489 sc->ste_cdata.ste_rx_list_map, 1490 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1491 1492 return (0); 1493} 1494 1495static void 1496ste_init_tx_list(struct ste_softc *sc) 1497{ 1498 struct ste_chain_data *cd; 1499 struct ste_list_data *ld; 1500 int i; 1501 1502 cd = &sc->ste_cdata; 1503 ld = &sc->ste_ldata; 1504 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1505 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1506 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1507 cd->ste_tx_chain[i].ste_mbuf = NULL; 1508 if (i == (STE_TX_LIST_CNT - 1)) { 1509 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1510 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1511 ld->ste_tx_list_paddr + 1512 (sizeof(struct ste_desc) * 0))); 1513 } else { 1514 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1515 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1516 ld->ste_tx_list_paddr + 1517 (sizeof(struct ste_desc) * (i + 1)))); 1518 } 1519 } 1520 1521 cd->ste_last_tx = NULL; 1522 cd->ste_tx_prod = 0; 1523 cd->ste_tx_cons = 0; 1524 cd->ste_tx_cnt = 0; 1525 1526 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1527 sc->ste_cdata.ste_tx_list_map, 1528 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1529} 1530 1531static void 1532ste_init(void *xsc) 1533{ 1534 struct ste_softc *sc; 1535 1536 sc = xsc; 1537 STE_LOCK(sc); 1538 ste_init_locked(sc); 1539 STE_UNLOCK(sc); 1540} 1541 1542static void 1543ste_init_locked(struct ste_softc *sc) 1544{ 1545 struct ifnet *ifp; 1546 int i; 1547 1548 STE_LOCK_ASSERT(sc); 1549 ifp = sc->ste_ifp; 1550 1551 ste_stop(sc); 1552 /* Reset the chip to a known state. */ 1553 ste_reset(sc); 1554 1555 /* Init our MAC address */ 1556 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1557 CSR_WRITE_2(sc, STE_PAR0 + i, 1558 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1559 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1560 } 1561 1562 /* Init RX list */ 1563 if (ste_init_rx_list(sc) != 0) { 1564 device_printf(sc->ste_dev, 1565 "initialization failed: no memory for RX buffers\n"); 1566 ste_stop(sc); 1567 return; 1568 } 1569 1570 /* Set RX polling interval */ 1571 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1572 1573 /* Init TX descriptors */ 1574 ste_init_tx_list(sc); 1575 1576 /* Set the TX freethresh value */ 1577 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1578 1579 /* Set the TX start threshold for best performance. */ 1580 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1581 1582 /* Set the TX reclaim threshold. */ 1583 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1584 1585 /* Set up the RX filter. */ 1586 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1587 1588 /* If we want promiscuous mode, set the allframes bit. */ 1589 if (ifp->if_flags & IFF_PROMISC) { 1590 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1591 } else { 1592 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1593 } 1594 1595 /* Set capture broadcast bit to accept broadcast frames. */ 1596 if (ifp->if_flags & IFF_BROADCAST) { 1597 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1598 } else { 1599 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1600 } 1601 1602 ste_setmulti(sc); 1603 1604 /* Load the address of the RX list. */ 1605 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1606 ste_wait(sc); 1607 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1608 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1609 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1610 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1611 1612 /* Set TX polling interval(defer until we TX first packet). */ 1613 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1614 1615 /* Load address of the TX list */ 1616 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1617 ste_wait(sc); 1618 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1619 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1620 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1621 ste_wait(sc); 1622 1623 /* Enable receiver and transmitter */ 1624 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1625 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1626 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1627 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1628 1629 /* Enable stats counters. */ 1630 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1631 1632 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1633#ifdef DEVICE_POLLING 1634 /* Disable interrupts if we are polling. */ 1635 if (ifp->if_capenable & IFCAP_POLLING) 1636 CSR_WRITE_2(sc, STE_IMR, 0); 1637 else 1638#endif 1639 /* Enable interrupts. */ 1640 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1641 1642 /* Accept VLAN length packets */ 1643 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1644 1645 ste_ifmedia_upd_locked(ifp); 1646 1647 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1648 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1649 1650 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1651} 1652 1653static void 1654ste_stop(struct ste_softc *sc) 1655{ 1656 struct ifnet *ifp; 1657 struct ste_chain_onefrag *cur_rx; 1658 struct ste_chain *cur_tx; 1659 uint32_t val; 1660 int i; 1661 1662 STE_LOCK_ASSERT(sc); 1663 ifp = sc->ste_ifp; 1664 1665 callout_stop(&sc->ste_callout); 1666 sc->ste_timer = 0; 1667 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1668 1669 CSR_WRITE_2(sc, STE_IMR, 0); 1670 /* Stop pending DMA. */ 1671 val = CSR_READ_4(sc, STE_DMACTL); 1672 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1673 CSR_WRITE_4(sc, STE_DMACTL, val); 1674 ste_wait(sc); 1675 /* Disable auto-polling. */ 1676 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1677 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1678 /* Nullify DMA address to stop any further DMA. */ 1679 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1680 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1681 /* Stop TX/RX MAC. */ 1682 val = CSR_READ_2(sc, STE_MACCTL1); 1683 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1684 STE_MACCTL1_STATS_DISABLE; 1685 CSR_WRITE_2(sc, STE_MACCTL1, val); 1686 for (i = 0; i < STE_TIMEOUT; i++) { 1687 DELAY(10); 1688 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1689 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1690 break; 1691 } 1692 if (i == STE_TIMEOUT) 1693 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1694 /* Acknowledge any pending interrupts. */ 1695 CSR_READ_2(sc, STE_ISR_ACK); 1696 ste_stats_update(sc); 1697 1698 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1699 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1700 if (cur_rx->ste_mbuf != NULL) { 1701 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1702 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1703 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1704 cur_rx->ste_map); 1705 m_freem(cur_rx->ste_mbuf); 1706 cur_rx->ste_mbuf = NULL; 1707 } 1708 } 1709 1710 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1711 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1712 if (cur_tx->ste_mbuf != NULL) { 1713 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1714 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1716 cur_tx->ste_map); 1717 m_freem(cur_tx->ste_mbuf); 1718 cur_tx->ste_mbuf = NULL; 1719 } 1720 } 1721} 1722 1723static void 1724ste_reset(struct ste_softc *sc) 1725{ 1726 int i; 1727 1728 STE_SETBIT4(sc, STE_ASICCTL, 1729 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1730 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1731 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1732 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1733 STE_ASICCTL_EXTRESET_RESET); 1734 1735 DELAY(100000); 1736 1737 for (i = 0; i < STE_TIMEOUT; i++) { 1738 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1739 break; 1740 } 1741 1742 if (i == STE_TIMEOUT) 1743 device_printf(sc->ste_dev, "global reset never completed\n"); 1744} 1745 1746static void 1747ste_restart_tx(struct ste_softc *sc) 1748{ 1749 uint16_t mac; 1750 int i; 1751 1752 for (i = 0; i < STE_TIMEOUT; i++) { 1753 mac = CSR_READ_2(sc, STE_MACCTL1); 1754 mac |= STE_MACCTL1_TX_ENABLE; 1755 CSR_WRITE_2(sc, STE_MACCTL1, mac); 1756 mac = CSR_READ_2(sc, STE_MACCTL1); 1757 if ((mac & STE_MACCTL1_TX_ENABLED) != 0) 1758 break; 1759 DELAY(10); 1760 } 1761 1762 if (i == STE_TIMEOUT) 1763 device_printf(sc->ste_dev, "starting Tx failed"); 1764} 1765 1766static int 1767ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1768{ 1769 struct ste_softc *sc; 1770 struct ifreq *ifr; 1771 struct mii_data *mii; 1772 int error = 0; 1773 1774 sc = ifp->if_softc; 1775 ifr = (struct ifreq *)data; 1776 1777 switch (command) { 1778 case SIOCSIFFLAGS: 1779 STE_LOCK(sc); 1780 if (ifp->if_flags & IFF_UP) { 1781 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1782 ifp->if_flags & IFF_PROMISC && 1783 !(sc->ste_if_flags & IFF_PROMISC)) { 1784 STE_SETBIT1(sc, STE_RX_MODE, 1785 STE_RXMODE_PROMISC); 1786 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1787 !(ifp->if_flags & IFF_PROMISC) && 1788 sc->ste_if_flags & IFF_PROMISC) { 1789 STE_CLRBIT1(sc, STE_RX_MODE, 1790 STE_RXMODE_PROMISC); 1791 } 1792 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1793 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1794 ste_setmulti(sc); 1795 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1796 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1797 ste_init_locked(sc); 1798 } 1799 } else { 1800 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1801 ste_stop(sc); 1802 } 1803 sc->ste_if_flags = ifp->if_flags; 1804 STE_UNLOCK(sc); 1805 error = 0; 1806 break; 1807 case SIOCADDMULTI: 1808 case SIOCDELMULTI: 1809 STE_LOCK(sc); 1810 ste_setmulti(sc); 1811 STE_UNLOCK(sc); 1812 error = 0; 1813 break; 1814 case SIOCGIFMEDIA: 1815 case SIOCSIFMEDIA: 1816 mii = device_get_softc(sc->ste_miibus); 1817 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1818 break; 1819 case SIOCSIFCAP: 1820#ifdef DEVICE_POLLING 1821 if (ifr->ifr_reqcap & IFCAP_POLLING && 1822 !(ifp->if_capenable & IFCAP_POLLING)) { 1823 error = ether_poll_register(ste_poll, ifp); 1824 if (error) 1825 return (error); 1826 STE_LOCK(sc); 1827 /* Disable interrupts */ 1828 CSR_WRITE_2(sc, STE_IMR, 0); 1829 ifp->if_capenable |= IFCAP_POLLING; 1830 STE_UNLOCK(sc); 1831 return (error); 1832 1833 } 1834 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1835 ifp->if_capenable & IFCAP_POLLING) { 1836 error = ether_poll_deregister(ifp); 1837 /* Enable interrupts. */ 1838 STE_LOCK(sc); 1839 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1840 ifp->if_capenable &= ~IFCAP_POLLING; 1841 STE_UNLOCK(sc); 1842 return (error); 1843 } 1844#endif /* DEVICE_POLLING */ 1845 break; 1846 default: 1847 error = ether_ioctl(ifp, command, data); 1848 break; 1849 } 1850 1851 return (error); 1852} 1853 1854static int 1855ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1856{ 1857 struct ste_frag *frag; 1858 struct mbuf *m; 1859 struct ste_desc *desc; 1860 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1861 int error, i, nsegs; 1862 1863 STE_LOCK_ASSERT(sc); 1864 M_ASSERTPKTHDR((*m_head)); 1865 1866 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1867 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1868 if (error == EFBIG) { 1869 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS); 1870 if (m == NULL) { 1871 m_freem(*m_head); 1872 *m_head = NULL; 1873 return (ENOMEM); 1874 } 1875 *m_head = m; 1876 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1877 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1878 if (error != 0) { 1879 m_freem(*m_head); 1880 *m_head = NULL; 1881 return (error); 1882 } 1883 } else if (error != 0) 1884 return (error); 1885 if (nsegs == 0) { 1886 m_freem(*m_head); 1887 *m_head = NULL; 1888 return (EIO); 1889 } 1890 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1891 BUS_DMASYNC_PREWRITE); 1892 1893 desc = txc->ste_ptr; 1894 for (i = 0; i < nsegs; i++) { 1895 frag = &desc->ste_frags[i]; 1896 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1897 frag->ste_len = htole32(txsegs[i].ds_len); 1898 } 1899 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1900 /* 1901 * Because we use Tx polling we can't chain multiple 1902 * Tx descriptors here. Otherwise we race with controller. 1903 */ 1904 desc->ste_next = 0; 1905 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | STE_TXCTL_DMAINTR); 1906 txc->ste_mbuf = *m_head; 1907 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1908 sc->ste_cdata.ste_tx_cnt++; 1909 1910 return (0); 1911} 1912 1913static void 1914ste_start(struct ifnet *ifp) 1915{ 1916 struct ste_softc *sc; 1917 1918 sc = ifp->if_softc; 1919 STE_LOCK(sc); 1920 ste_start_locked(ifp); 1921 STE_UNLOCK(sc); 1922} 1923 1924static void 1925ste_start_locked(struct ifnet *ifp) 1926{ 1927 struct ste_softc *sc; 1928 struct ste_chain *cur_tx; 1929 struct mbuf *m_head = NULL; 1930 int enq; 1931 1932 sc = ifp->if_softc; 1933 STE_LOCK_ASSERT(sc); 1934 1935 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1936 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 1937 return; 1938 1939 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 1940 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1941 /* 1942 * Controller may have cached copy of the last used 1943 * next ptr so we have to reserve one TFD to avoid 1944 * TFD overruns. 1945 */ 1946 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1947 break; 1948 } 1949 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1950 if (m_head == NULL) 1951 break; 1952 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1953 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1954 if (m_head == NULL) 1955 break; 1956 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1957 break; 1958 } 1959 if (sc->ste_cdata.ste_last_tx == NULL) { 1960 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1961 sc->ste_cdata.ste_tx_list_map, 1962 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1963 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1964 ste_wait(sc); 1965 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1966 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1967 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1968 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1969 ste_wait(sc); 1970 } else { 1971 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1972 sc->ste_cdata.ste_last_tx->ste_phys; 1973 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1974 sc->ste_cdata.ste_tx_list_map, 1975 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1976 } 1977 sc->ste_cdata.ste_last_tx = cur_tx; 1978 1979 enq++; 1980 /* 1981 * If there's a BPF listener, bounce a copy of this frame 1982 * to him. 1983 */ 1984 BPF_MTAP(ifp, m_head); 1985 } 1986 1987 if (enq > 0) 1988 sc->ste_timer = STE_TX_TIMEOUT; 1989} 1990 1991static void 1992ste_watchdog(struct ste_softc *sc) 1993{ 1994 struct ifnet *ifp; 1995 1996 ifp = sc->ste_ifp; 1997 STE_LOCK_ASSERT(sc); 1998 1999 if (sc->ste_timer == 0 || --sc->ste_timer) 2000 return; 2001 2002 ifp->if_oerrors++; 2003 if_printf(ifp, "watchdog timeout\n"); 2004 2005 ste_txeof(sc); 2006 ste_txeoc(sc); 2007 ste_rxeof(sc, -1); 2008 ste_init_locked(sc); 2009 2010 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2011 ste_start_locked(ifp); 2012} 2013 2014static int 2015ste_shutdown(device_t dev) 2016{ 2017 struct ste_softc *sc; 2018 2019 sc = device_get_softc(dev); 2020 2021 STE_LOCK(sc); 2022 ste_stop(sc); 2023 STE_UNLOCK(sc); 2024 2025 return (0); 2026} 2027