if_ste.c revision 200877
156055Srwatson/*- 274191Srwatson * Copyright (c) 1997, 1998, 1999 356055Srwatson * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 456055Srwatson * 556055Srwatson * Redistribution and use in source and binary forms, with or without 656055Srwatson * modification, are permitted provided that the following conditions 756055Srwatson * are met: 856055Srwatson * 1. Redistributions of source code must retain the above copyright 956055Srwatson * notice, this list of conditions and the following disclaimer. 1056055Srwatson * 2. Redistributions in binary form must reproduce the above copyright 1156055Srwatson * notice, this list of conditions and the following disclaimer in the 1256055Srwatson * documentation and/or other materials provided with the distribution. 1356055Srwatson * 3. All advertising materials mentioning features or use of this software 1456055Srwatson * must display the following acknowledgement: 1556055Srwatson * This product includes software developed by Bill Paul. 1656055Srwatson * 4. Neither the name of the author nor the names of any co-contributors 1756055Srwatson * may be used to endorse or promote products derived from this software 1856055Srwatson * without specific prior written permission. 1956055Srwatson * 2056055Srwatson * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2156055Srwatson * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2256055Srwatson * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2356055Srwatson * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2456055Srwatson * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2556055Srwatson * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2666259Srwatson * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2756055Srwatson * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2856055Srwatson * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2966259Srwatson * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3056055Srwatson * THE POSSIBILITY OF SUCH DAMAGE. 3156055Srwatson */ 3256055Srwatson 3375185Stmm#include <sys/cdefs.h> 3456055Srwatson__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 200877 2009-12-22 21:44:25Z yongari $"); 3575185Stmm 3656055Srwatson#ifdef HAVE_KERNEL_OPTION_HEADERS 3756055Srwatson#include "opt_device_polling.h" 3856055Srwatson#endif 3956055Srwatson 4056055Srwatson#include <sys/param.h> 4156055Srwatson#include <sys/systm.h> 4256055Srwatson#include <sys/bus.h> 4391032Sjedgar#include <sys/endian.h> 4491032Sjedgar#include <sys/kernel.h> 4591032Sjedgar#include <sys/lock.h> 4691032Sjedgar#include <sys/malloc.h> 4756055Srwatson#include <sys/mbuf.h> 4856055Srwatson#include <sys/module.h> 4956055Srwatson#include <sys/rman.h> 5056055Srwatson#include <sys/socket.h> 5156055Srwatson#include <sys/sockio.h> 5256055Srwatson#include <sys/sysctl.h> 5356055Srwatson 5456055Srwatson#include <net/bpf.h> 5556055Srwatson#include <net/if.h> 5656055Srwatson#include <net/if_arp.h> 5756055Srwatson#include <net/ethernet.h> 5856055Srwatson#include <net/if_dl.h> 5956055Srwatson#include <net/if_media.h> 6056055Srwatson#include <net/if_types.h> 6156055Srwatson#include <net/if_vlan_var.h> 6256055Srwatson 6356055Srwatson#include <machine/bus.h> 6456055Srwatson#include <machine/resource.h> 6556055Srwatson 6656055Srwatson#include <dev/mii/mii.h> 6756055Srwatson#include <dev/mii/miivar.h> 6856055Srwatson 6956055Srwatson#include <dev/pci/pcireg.h> 7056055Srwatson#include <dev/pci/pcivar.h> 7156055Srwatson 7256055Srwatson#include <dev/ste/if_stereg.h> 7356055Srwatson 7456055Srwatson/* "device miibus" required. See GENERIC if you get errors here. */ 7556055Srwatson#include "miibus_if.h" 7656055Srwatson 7756055SrwatsonMODULE_DEPEND(ste, pci, 1, 1, 1); 7856055SrwatsonMODULE_DEPEND(ste, ether, 1, 1, 1); 7991032SjedgarMODULE_DEPEND(ste, miibus, 1, 1, 1); 8056055Srwatson 8156055Srwatson/* 8256055Srwatson * Various supported device vendors/types and their names. 8356055Srwatson */ 8456055Srwatsonstatic struct ste_type ste_devs[] = { 8556055Srwatson { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 8656055Srwatson { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 8756055Srwatson { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 8856055Srwatson { 0, 0, NULL } 8956055Srwatson}; 9056055Srwatson 9156055Srwatsonstatic int ste_attach(device_t); 9256055Srwatsonstatic int ste_detach(device_t); 9356055Srwatsonstatic int ste_probe(device_t); 9456055Srwatsonstatic int ste_shutdown(device_t); 9556055Srwatson 9656055Srwatsonstatic int ste_dma_alloc(struct ste_softc *); 9756055Srwatsonstatic void ste_dma_free(struct ste_softc *); 9856055Srwatsonstatic void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 9956055Srwatsonstatic int ste_eeprom_wait(struct ste_softc *); 10056055Srwatsonstatic int ste_encap(struct ste_softc *, struct mbuf **, 10156055Srwatson struct ste_chain *); 10256055Srwatsonstatic int ste_ifmedia_upd(struct ifnet *); 10356055Srwatsonstatic void ste_ifmedia_upd_locked(struct ifnet *); 10456055Srwatsonstatic void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 10556055Srwatsonstatic void ste_init(void *); 10656055Srwatsonstatic void ste_init_locked(struct ste_softc *); 10756055Srwatsonstatic int ste_init_rx_list(struct ste_softc *); 10856055Srwatsonstatic void ste_init_tx_list(struct ste_softc *); 10966259Srwatsonstatic void ste_intr(void *); 11066259Srwatsonstatic int ste_ioctl(struct ifnet *, u_long, caddr_t); 11156055Srwatsonstatic int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 11256055Srwatsonstatic void ste_mii_send(struct ste_softc *, uint32_t, int); 11356055Srwatsonstatic void ste_mii_sync(struct ste_softc *); 11456055Srwatsonstatic int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 11556055Srwatsonstatic int ste_miibus_readreg(device_t, int, int); 11675928Sjedgarstatic void ste_miibus_statchg(device_t); 11775928Sjedgarstatic int ste_miibus_writereg(device_t, int, int, int); 11875928Sjedgarstatic int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 11975928Sjedgarstatic int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 12075928Sjedgarstatic void ste_reset(struct ste_softc *); 12175928Sjedgarstatic int ste_rxeof(struct ste_softc *, int); 12275928Sjedgarstatic void ste_setmulti(struct ste_softc *); 12356055Srwatsonstatic void ste_start(struct ifnet *); 12466259Srwatsonstatic void ste_start_locked(struct ifnet *); 12556055Srwatsonstatic void ste_stats_update(struct ste_softc *); 12670841Srwatsonstatic void ste_stop(struct ste_softc *); 12771142Srwatsonstatic void ste_tick(void *); 12856055Srwatsonstatic void ste_txeoc(struct ste_softc *); 12956055Srwatsonstatic void ste_txeof(struct ste_softc *); 13056055Srwatsonstatic void ste_wait(struct ste_softc *); 13156055Srwatsonstatic void ste_watchdog(struct ste_softc *); 13271142Srwatson 13356055Srwatsonstatic device_method_t ste_methods[] = { 13456055Srwatson /* Device interface */ 13566259Srwatson DEVMETHOD(device_probe, ste_probe), 13656055Srwatson DEVMETHOD(device_attach, ste_attach), 13756055Srwatson DEVMETHOD(device_detach, ste_detach), 13866259Srwatson DEVMETHOD(device_shutdown, ste_shutdown), 13956055Srwatson 14056055Srwatson /* bus interface */ 14156055Srwatson DEVMETHOD(bus_print_child, bus_generic_print_child), 14266259Srwatson DEVMETHOD(bus_driver_added, bus_generic_driver_added), 14356055Srwatson 14466259Srwatson /* MII interface */ 14556055Srwatson DEVMETHOD(miibus_readreg, ste_miibus_readreg), 14656055Srwatson DEVMETHOD(miibus_writereg, ste_miibus_writereg), 14756055Srwatson DEVMETHOD(miibus_statchg, ste_miibus_statchg), 14856055Srwatson 14956055Srwatson { 0, 0 } 15056055Srwatson}; 15156055Srwatson 15256055Srwatsonstatic driver_t ste_driver = { 15366259Srwatson "ste", 15466259Srwatson ste_methods, 15556055Srwatson sizeof(struct ste_softc) 15656055Srwatson}; 15756055Srwatson 15856055Srwatsonstatic devclass_t ste_devclass; 15956055Srwatson 16056055SrwatsonDRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 16156055SrwatsonDRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 16256055Srwatson 16356055Srwatson#define STE_SETBIT4(sc, reg, x) \ 16456055Srwatson CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 16556055Srwatson 16656055Srwatson#define STE_CLRBIT4(sc, reg, x) \ 16756055Srwatson CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 16856055Srwatson 16956055Srwatson#define STE_SETBIT2(sc, reg, x) \ 17056055Srwatson CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 17156055Srwatson 17256055Srwatson#define STE_CLRBIT2(sc, reg, x) \ 17356055Srwatson CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 17456055Srwatson 17556055Srwatson#define STE_SETBIT1(sc, reg, x) \ 17656055Srwatson CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 17756055Srwatson 17856055Srwatson#define STE_CLRBIT1(sc, reg, x) \ 17956055Srwatson CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 18056055Srwatson 18156055Srwatson 18274191Srwatson#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 18356055Srwatson#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 18456055Srwatson 18556055Srwatson/* 18656055Srwatson * Sync the PHYs by setting data bit and strobing the clock 32 times. 18756055Srwatson */ 18856055Srwatsonstatic void 18956055Srwatsonste_mii_sync(struct ste_softc *sc) 19056055Srwatson{ 19156055Srwatson int i; 19256055Srwatson 19356055Srwatson MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 19456055Srwatson 19556055Srwatson for (i = 0; i < 32; i++) { 19656055Srwatson MII_SET(STE_PHYCTL_MCLK); 19756055Srwatson DELAY(1); 19856055Srwatson MII_CLR(STE_PHYCTL_MCLK); 19956055Srwatson DELAY(1); 20056055Srwatson } 20156055Srwatson} 20274191Srwatson 20374191Srwatson/* 20456055Srwatson * Clock a series of bits through the MII. 20556055Srwatson */ 20656055Srwatsonstatic void 20756055Srwatsonste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt) 20856055Srwatson{ 20956055Srwatson int i; 21056055Srwatson 21156055Srwatson MII_CLR(STE_PHYCTL_MCLK); 21256055Srwatson 21374191Srwatson for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 21456055Srwatson if (bits & i) { 21556055Srwatson MII_SET(STE_PHYCTL_MDATA); 21656055Srwatson } else { 21756055Srwatson MII_CLR(STE_PHYCTL_MDATA); 21856055Srwatson } 21956055Srwatson DELAY(1); 22066259Srwatson MII_CLR(STE_PHYCTL_MCLK); 22166259Srwatson DELAY(1); 22256055Srwatson MII_SET(STE_PHYCTL_MCLK); 22356055Srwatson } 22456055Srwatson} 22556055Srwatson 22656055Srwatson/* 22756055Srwatson * Read an PHY register through the MII. 22856055Srwatson */ 22956055Srwatsonstatic int 23056055Srwatsonste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 23156055Srwatson{ 23256055Srwatson int i, ack; 23371142Srwatson 23456055Srwatson /* 23556055Srwatson * Set up frame for RX. 23656055Srwatson */ 23756055Srwatson frame->mii_stdelim = STE_MII_STARTDELIM; 238 frame->mii_opcode = STE_MII_READOP; 239 frame->mii_turnaround = 0; 240 frame->mii_data = 0; 241 242 CSR_WRITE_2(sc, STE_PHYCTL, 0); 243 /* 244 * Turn on data xmit. 245 */ 246 MII_SET(STE_PHYCTL_MDIR); 247 248 ste_mii_sync(sc); 249 250 /* 251 * Send command/address info. 252 */ 253 ste_mii_send(sc, frame->mii_stdelim, 2); 254 ste_mii_send(sc, frame->mii_opcode, 2); 255 ste_mii_send(sc, frame->mii_phyaddr, 5); 256 ste_mii_send(sc, frame->mii_regaddr, 5); 257 258 /* Turn off xmit. */ 259 MII_CLR(STE_PHYCTL_MDIR); 260 261 /* Idle bit */ 262 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 263 DELAY(1); 264 MII_SET(STE_PHYCTL_MCLK); 265 DELAY(1); 266 267 /* Check for ack */ 268 MII_CLR(STE_PHYCTL_MCLK); 269 DELAY(1); 270 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 271 MII_SET(STE_PHYCTL_MCLK); 272 DELAY(1); 273 274 /* 275 * Now try reading data bits. If the ack failed, we still 276 * need to clock through 16 cycles to keep the PHY(s) in sync. 277 */ 278 if (ack) { 279 for (i = 0; i < 16; i++) { 280 MII_CLR(STE_PHYCTL_MCLK); 281 DELAY(1); 282 MII_SET(STE_PHYCTL_MCLK); 283 DELAY(1); 284 } 285 goto fail; 286 } 287 288 for (i = 0x8000; i; i >>= 1) { 289 MII_CLR(STE_PHYCTL_MCLK); 290 DELAY(1); 291 if (!ack) { 292 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 293 frame->mii_data |= i; 294 DELAY(1); 295 } 296 MII_SET(STE_PHYCTL_MCLK); 297 DELAY(1); 298 } 299 300fail: 301 302 MII_CLR(STE_PHYCTL_MCLK); 303 DELAY(1); 304 MII_SET(STE_PHYCTL_MCLK); 305 DELAY(1); 306 307 if (ack) 308 return (1); 309 return (0); 310} 311 312/* 313 * Write to a PHY register through the MII. 314 */ 315static int 316ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 317{ 318 319 /* 320 * Set up frame for TX. 321 */ 322 323 frame->mii_stdelim = STE_MII_STARTDELIM; 324 frame->mii_opcode = STE_MII_WRITEOP; 325 frame->mii_turnaround = STE_MII_TURNAROUND; 326 327 /* 328 * Turn on data output. 329 */ 330 MII_SET(STE_PHYCTL_MDIR); 331 332 ste_mii_sync(sc); 333 334 ste_mii_send(sc, frame->mii_stdelim, 2); 335 ste_mii_send(sc, frame->mii_opcode, 2); 336 ste_mii_send(sc, frame->mii_phyaddr, 5); 337 ste_mii_send(sc, frame->mii_regaddr, 5); 338 ste_mii_send(sc, frame->mii_turnaround, 2); 339 ste_mii_send(sc, frame->mii_data, 16); 340 341 /* Idle bit. */ 342 MII_SET(STE_PHYCTL_MCLK); 343 DELAY(1); 344 MII_CLR(STE_PHYCTL_MCLK); 345 DELAY(1); 346 347 /* 348 * Turn off xmit. 349 */ 350 MII_CLR(STE_PHYCTL_MDIR); 351 352 return (0); 353} 354 355static int 356ste_miibus_readreg(device_t dev, int phy, int reg) 357{ 358 struct ste_softc *sc; 359 struct ste_mii_frame frame; 360 361 sc = device_get_softc(dev); 362 363 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0 && phy != 0) 364 return (0); 365 366 bzero((char *)&frame, sizeof(frame)); 367 368 frame.mii_phyaddr = phy; 369 frame.mii_regaddr = reg; 370 ste_mii_readreg(sc, &frame); 371 372 return (frame.mii_data); 373} 374 375static int 376ste_miibus_writereg(device_t dev, int phy, int reg, int data) 377{ 378 struct ste_softc *sc; 379 struct ste_mii_frame frame; 380 381 sc = device_get_softc(dev); 382 bzero((char *)&frame, sizeof(frame)); 383 384 frame.mii_phyaddr = phy; 385 frame.mii_regaddr = reg; 386 frame.mii_data = data; 387 388 ste_mii_writereg(sc, &frame); 389 390 return (0); 391} 392 393static void 394ste_miibus_statchg(device_t dev) 395{ 396 struct ste_softc *sc; 397 struct mii_data *mii; 398 struct ifnet *ifp; 399 uint16_t cfg; 400 401 sc = device_get_softc(dev); 402 403 mii = device_get_softc(sc->ste_miibus); 404 ifp = sc->ste_ifp; 405 if (mii == NULL || ifp == NULL || 406 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 407 return; 408 409 sc->ste_flags &= ~STE_FLAG_LINK; 410 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 411 (IFM_ACTIVE | IFM_AVALID)) { 412 switch (IFM_SUBTYPE(mii->mii_media_active)) { 413 case IFM_10_T: 414 case IFM_100_TX: 415 case IFM_100_FX: 416 case IFM_100_T4: 417 sc->ste_flags |= STE_FLAG_LINK; 418 default: 419 break; 420 } 421 } 422 423 /* Program MACs with resolved speed/duplex/flow-control. */ 424 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 425 cfg = CSR_READ_2(sc, STE_MACCTL0); 426 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 427 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 428 /* 429 * ST201 data sheet says driver should enable receiving 430 * MAC control frames bit of receive mode register to 431 * receive flow-control frames but the register has no 432 * such bits. In addition the controller has no ability 433 * to send pause frames so it should be handled in 434 * driver. Implementing pause timer handling in driver 435 * layer is not trivial, so don't enable flow-control 436 * here. 437 */ 438 cfg |= STE_MACCTL0_FULLDUPLEX; 439 } 440 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 441 } 442} 443 444static int 445ste_ifmedia_upd(struct ifnet *ifp) 446{ 447 struct ste_softc *sc; 448 449 sc = ifp->if_softc; 450 STE_LOCK(sc); 451 ste_ifmedia_upd_locked(ifp); 452 STE_UNLOCK(sc); 453 454 return (0); 455} 456 457static void 458ste_ifmedia_upd_locked(struct ifnet *ifp) 459{ 460 struct ste_softc *sc; 461 struct mii_data *mii; 462 463 sc = ifp->if_softc; 464 STE_LOCK_ASSERT(sc); 465 mii = device_get_softc(sc->ste_miibus); 466 sc->ste_flags &= ~STE_FLAG_LINK; 467 if (mii->mii_instance) { 468 struct mii_softc *miisc; 469 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 470 mii_phy_reset(miisc); 471 } 472 mii_mediachg(mii); 473} 474 475static void 476ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 477{ 478 struct ste_softc *sc; 479 struct mii_data *mii; 480 481 sc = ifp->if_softc; 482 mii = device_get_softc(sc->ste_miibus); 483 484 STE_LOCK(sc); 485 mii_pollstat(mii); 486 ifmr->ifm_active = mii->mii_media_active; 487 ifmr->ifm_status = mii->mii_media_status; 488 STE_UNLOCK(sc); 489} 490 491static void 492ste_wait(struct ste_softc *sc) 493{ 494 int i; 495 496 for (i = 0; i < STE_TIMEOUT; i++) { 497 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 498 break; 499 DELAY(1); 500 } 501 502 if (i == STE_TIMEOUT) 503 device_printf(sc->ste_dev, "command never completed!\n"); 504} 505 506/* 507 * The EEPROM is slow: give it time to come ready after issuing 508 * it a command. 509 */ 510static int 511ste_eeprom_wait(struct ste_softc *sc) 512{ 513 int i; 514 515 DELAY(1000); 516 517 for (i = 0; i < 100; i++) { 518 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 519 DELAY(1000); 520 else 521 break; 522 } 523 524 if (i == 100) { 525 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 526 return (1); 527 } 528 529 return (0); 530} 531 532/* 533 * Read a sequence of words from the EEPROM. Note that ethernet address 534 * data is stored in the EEPROM in network byte order. 535 */ 536static int 537ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 538{ 539 uint16_t word, *ptr; 540 int err = 0, i; 541 542 if (ste_eeprom_wait(sc)) 543 return (1); 544 545 for (i = 0; i < cnt; i++) { 546 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 547 err = ste_eeprom_wait(sc); 548 if (err) 549 break; 550 word = CSR_READ_2(sc, STE_EEPROM_DATA); 551 ptr = (uint16_t *)(dest + (i * 2)); 552 if (swap) 553 *ptr = ntohs(word); 554 else 555 *ptr = word; 556 } 557 558 return (err ? 1 : 0); 559} 560 561static void 562ste_setmulti(struct ste_softc *sc) 563{ 564 struct ifnet *ifp; 565 struct ifmultiaddr *ifma; 566 uint32_t hashes[2] = { 0, 0 }; 567 int h; 568 569 ifp = sc->ste_ifp; 570 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 571 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 572 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 573 return; 574 } 575 576 /* first, zot all the existing hash bits */ 577 CSR_WRITE_2(sc, STE_MAR0, 0); 578 CSR_WRITE_2(sc, STE_MAR1, 0); 579 CSR_WRITE_2(sc, STE_MAR2, 0); 580 CSR_WRITE_2(sc, STE_MAR3, 0); 581 582 /* now program new ones */ 583 if_maddr_rlock(ifp); 584 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 585 if (ifma->ifma_addr->sa_family != AF_LINK) 586 continue; 587 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 588 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 589 if (h < 32) 590 hashes[0] |= (1 << h); 591 else 592 hashes[1] |= (1 << (h - 32)); 593 } 594 if_maddr_runlock(ifp); 595 596 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 597 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 598 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 599 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 600 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 601 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 602} 603 604#ifdef DEVICE_POLLING 605static poll_handler_t ste_poll, ste_poll_locked; 606 607static int 608ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 609{ 610 struct ste_softc *sc = ifp->if_softc; 611 int rx_npkts = 0; 612 613 STE_LOCK(sc); 614 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 615 rx_npkts = ste_poll_locked(ifp, cmd, count); 616 STE_UNLOCK(sc); 617 return (rx_npkts); 618} 619 620static int 621ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 622{ 623 struct ste_softc *sc = ifp->if_softc; 624 int rx_npkts; 625 626 STE_LOCK_ASSERT(sc); 627 628 rx_npkts = ste_rxeof(sc, count); 629 ste_txeof(sc); 630 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 631 ste_start_locked(ifp); 632 633 if (cmd == POLL_AND_CHECK_STATUS) { 634 uint16_t status; 635 636 status = CSR_READ_2(sc, STE_ISR_ACK); 637 638 if (status & STE_ISR_TX_DONE) 639 ste_txeoc(sc); 640 641 if (status & STE_ISR_STATS_OFLOW) 642 ste_stats_update(sc); 643 644 if (status & STE_ISR_HOSTERR) 645 ste_init_locked(sc); 646 } 647 return (rx_npkts); 648} 649#endif /* DEVICE_POLLING */ 650 651static void 652ste_intr(void *xsc) 653{ 654 struct ste_softc *sc; 655 struct ifnet *ifp; 656 uint16_t status; 657 658 sc = xsc; 659 STE_LOCK(sc); 660 ifp = sc->ste_ifp; 661 662#ifdef DEVICE_POLLING 663 if (ifp->if_capenable & IFCAP_POLLING) { 664 STE_UNLOCK(sc); 665 return; 666 } 667#endif 668 669 /* See if this is really our interrupt. */ 670 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 671 STE_UNLOCK(sc); 672 return; 673 } 674 675 for (;;) { 676 status = CSR_READ_2(sc, STE_ISR_ACK); 677 678 if (!(status & STE_INTRS)) 679 break; 680 681 if (status & STE_ISR_RX_DMADONE) 682 ste_rxeof(sc, -1); 683 684 if (status & STE_ISR_TX_DMADONE) 685 ste_txeof(sc); 686 687 if (status & STE_ISR_TX_DONE) 688 ste_txeoc(sc); 689 690 if (status & STE_ISR_STATS_OFLOW) 691 ste_stats_update(sc); 692 693 if (status & STE_ISR_HOSTERR) 694 ste_init_locked(sc); 695 } 696 697 /* Re-enable interrupts */ 698 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 699 700 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 701 ste_start_locked(ifp); 702 703 STE_UNLOCK(sc); 704} 705 706/* 707 * A frame has been uploaded: pass the resulting mbuf chain up to 708 * the higher level protocols. 709 */ 710static int 711ste_rxeof(struct ste_softc *sc, int count) 712{ 713 struct mbuf *m; 714 struct ifnet *ifp; 715 struct ste_chain_onefrag *cur_rx; 716 uint32_t rxstat; 717 int total_len, rx_npkts; 718 719 ifp = sc->ste_ifp; 720 721 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 722 sc->ste_cdata.ste_rx_list_map, 723 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 724 725 cur_rx = sc->ste_cdata.ste_rx_head; 726 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 727 cur_rx = cur_rx->ste_next) { 728 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 729 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 730 break; 731#ifdef DEVICE_POLLING 732 if (ifp->if_capenable & IFCAP_POLLING) { 733 if (count == 0) 734 break; 735 count--; 736 } 737#endif 738 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 739 break; 740 /* 741 * If an error occurs, update stats, clear the 742 * status word and leave the mbuf cluster in place: 743 * it should simply get re-used next time this descriptor 744 * comes up in the ring. 745 */ 746 if (rxstat & STE_RXSTAT_FRAME_ERR) { 747 ifp->if_ierrors++; 748 cur_rx->ste_ptr->ste_status = 0; 749 continue; 750 } 751 752 /* No errors; receive the packet. */ 753 m = cur_rx->ste_mbuf; 754 total_len = STE_RX_BYTES(rxstat); 755 756 /* 757 * Try to conjure up a new mbuf cluster. If that 758 * fails, it means we have an out of memory condition and 759 * should leave the buffer in place and continue. This will 760 * result in a lost packet, but there's little else we 761 * can do in this situation. 762 */ 763 if (ste_newbuf(sc, cur_rx) != 0) { 764 ifp->if_ierrors++; 765 cur_rx->ste_ptr->ste_status = 0; 766 continue; 767 } 768 769 m->m_pkthdr.rcvif = ifp; 770 m->m_pkthdr.len = m->m_len = total_len; 771 772 ifp->if_ipackets++; 773 STE_UNLOCK(sc); 774 (*ifp->if_input)(ifp, m); 775 STE_LOCK(sc); 776 } 777 778 if (rx_npkts > 0) { 779 sc->ste_cdata.ste_rx_head = cur_rx; 780 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 781 sc->ste_cdata.ste_rx_list_map, 782 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 783 } 784 785 return (rx_npkts); 786} 787 788static void 789ste_txeoc(struct ste_softc *sc) 790{ 791 struct ifnet *ifp; 792 uint8_t txstat; 793 794 ifp = sc->ste_ifp; 795 796 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 797 STE_TXSTATUS_TXDONE) { 798 if (txstat & STE_TXSTATUS_UNDERRUN || 799 txstat & STE_TXSTATUS_EXCESSCOLLS || 800 txstat & STE_TXSTATUS_RECLAIMERR) { 801 ifp->if_oerrors++; 802 device_printf(sc->ste_dev, 803 "transmission error: %x\n", txstat); 804 805 ste_init_locked(sc); 806 807 if (txstat & STE_TXSTATUS_UNDERRUN && 808 sc->ste_tx_thresh < STE_PACKET_SIZE) { 809 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 810 device_printf(sc->ste_dev, 811 "tx underrun, increasing tx" 812 " start threshold to %d bytes\n", 813 sc->ste_tx_thresh); 814 } 815 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 816 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 817 (STE_PACKET_SIZE >> 4)); 818 } 819 ste_init_locked(sc); 820 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 821 } 822} 823 824static void 825ste_tick(void *arg) 826{ 827 struct ste_softc *sc; 828 struct mii_data *mii; 829 830 sc = (struct ste_softc *)arg; 831 832 STE_LOCK_ASSERT(sc); 833 834 mii = device_get_softc(sc->ste_miibus); 835 mii_tick(mii); 836 /* 837 * ukphy(4) does not seem to generate CB that reports 838 * resolved link state so if we know we lost a link, 839 * explicitly check the link state. 840 */ 841 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 842 ste_miibus_statchg(sc->ste_dev); 843 ste_stats_update(sc); 844 ste_watchdog(sc); 845 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 846} 847 848static void 849ste_txeof(struct ste_softc *sc) 850{ 851 struct ifnet *ifp; 852 struct ste_chain *cur_tx; 853 uint32_t txstat; 854 int idx; 855 856 STE_LOCK_ASSERT(sc); 857 858 ifp = sc->ste_ifp; 859 idx = sc->ste_cdata.ste_tx_cons; 860 if (idx == sc->ste_cdata.ste_tx_prod) 861 return; 862 863 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 864 sc->ste_cdata.ste_tx_list_map, 865 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 866 867 while (idx != sc->ste_cdata.ste_tx_prod) { 868 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 869 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 870 if ((txstat & STE_TXCTL_DMADONE) == 0) 871 break; 872 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 873 BUS_DMASYNC_POSTWRITE); 874 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 875 KASSERT(cur_tx->ste_mbuf != NULL, 876 ("%s: freeing NULL mbuf!\n", __func__)); 877 m_freem(cur_tx->ste_mbuf); 878 cur_tx->ste_mbuf = NULL; 879 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 880 ifp->if_opackets++; 881 sc->ste_cdata.ste_tx_cnt--; 882 STE_INC(idx, STE_TX_LIST_CNT); 883 } 884 885 sc->ste_cdata.ste_tx_cons = idx; 886 if (sc->ste_cdata.ste_tx_cnt == 0) 887 sc->ste_timer = 0; 888} 889 890static void 891ste_stats_update(struct ste_softc *sc) 892{ 893 struct ifnet *ifp; 894 895 STE_LOCK_ASSERT(sc); 896 897 ifp = sc->ste_ifp; 898 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 899 + CSR_READ_1(sc, STE_MULTI_COLLS) 900 + CSR_READ_1(sc, STE_SINGLE_COLLS); 901} 902 903/* 904 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 905 * IDs against our list and return a device name if we find a match. 906 */ 907static int 908ste_probe(device_t dev) 909{ 910 struct ste_type *t; 911 912 t = ste_devs; 913 914 while (t->ste_name != NULL) { 915 if ((pci_get_vendor(dev) == t->ste_vid) && 916 (pci_get_device(dev) == t->ste_did)) { 917 device_set_desc(dev, t->ste_name); 918 return (BUS_PROBE_DEFAULT); 919 } 920 t++; 921 } 922 923 return (ENXIO); 924} 925 926/* 927 * Attach the interface. Allocate softc structures, do ifmedia 928 * setup and ethernet/BPF attach. 929 */ 930static int 931ste_attach(device_t dev) 932{ 933 struct ste_softc *sc; 934 struct ifnet *ifp; 935 u_char eaddr[6]; 936 int error = 0, rid; 937 938 sc = device_get_softc(dev); 939 sc->ste_dev = dev; 940 941 /* 942 * Only use one PHY since this chip reports multiple 943 * Note on the DFE-550 the PHY is at 1 on the DFE-580 944 * it is at 0 & 1. It is rev 0x12. 945 */ 946 if (pci_get_vendor(dev) == DL_VENDORID && 947 pci_get_device(dev) == DL_DEVICEID_DL10050 && 948 pci_get_revid(dev) == 0x12 ) 949 sc->ste_flags |= STE_FLAG_ONE_PHY; 950 951 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 952 MTX_DEF); 953 /* 954 * Map control/status registers. 955 */ 956 pci_enable_busmaster(dev); 957 958 /* Prefer memory space register mapping over IO space. */ 959 sc->ste_res_id = PCIR_BAR(1); 960 sc->ste_res_type = SYS_RES_MEMORY; 961 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 962 &sc->ste_res_id, RF_ACTIVE); 963 if (sc->ste_res == NULL) { 964 sc->ste_res_id = PCIR_BAR(0); 965 sc->ste_res_type = SYS_RES_IOPORT; 966 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 967 &sc->ste_res_id, RF_ACTIVE); 968 } 969 if (sc->ste_res == NULL) { 970 device_printf(dev, "couldn't map ports/memory\n"); 971 error = ENXIO; 972 goto fail; 973 } 974 975 /* Allocate interrupt */ 976 rid = 0; 977 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 978 RF_SHAREABLE | RF_ACTIVE); 979 980 if (sc->ste_irq == NULL) { 981 device_printf(dev, "couldn't map interrupt\n"); 982 error = ENXIO; 983 goto fail; 984 } 985 986 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 987 988 /* Reset the adapter. */ 989 ste_reset(sc); 990 991 /* 992 * Get station address from the EEPROM. 993 */ 994 if (ste_read_eeprom(sc, eaddr, 995 STE_EEADDR_NODE0, 3, 0)) { 996 device_printf(dev, "failed to read station address\n"); 997 error = ENXIO;; 998 goto fail; 999 } 1000 1001 if ((error = ste_dma_alloc(sc)) != 0) 1002 goto fail; 1003 1004 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1005 if (ifp == NULL) { 1006 device_printf(dev, "can not if_alloc()\n"); 1007 error = ENOSPC; 1008 goto fail; 1009 } 1010 1011 /* Do MII setup. */ 1012 if (mii_phy_probe(dev, &sc->ste_miibus, 1013 ste_ifmedia_upd, ste_ifmedia_sts)) { 1014 device_printf(dev, "MII without any phy!\n"); 1015 error = ENXIO; 1016 goto fail; 1017 } 1018 1019 ifp->if_softc = sc; 1020 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1021 ifp->if_mtu = ETHERMTU; 1022 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1023 ifp->if_ioctl = ste_ioctl; 1024 ifp->if_start = ste_start; 1025 ifp->if_init = ste_init; 1026 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1027 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1028 IFQ_SET_READY(&ifp->if_snd); 1029 1030 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1031 1032 /* 1033 * Call MI attach routine. 1034 */ 1035 ether_ifattach(ifp, eaddr); 1036 1037 /* 1038 * Tell the upper layer(s) we support long frames. 1039 */ 1040 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1041 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1042 ifp->if_capenable = ifp->if_capabilities; 1043#ifdef DEVICE_POLLING 1044 ifp->if_capabilities |= IFCAP_POLLING; 1045#endif 1046 1047 /* Hook interrupt last to avoid having to lock softc */ 1048 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1049 NULL, ste_intr, sc, &sc->ste_intrhand); 1050 1051 if (error) { 1052 device_printf(dev, "couldn't set up irq\n"); 1053 ether_ifdetach(ifp); 1054 goto fail; 1055 } 1056 1057fail: 1058 if (error) 1059 ste_detach(dev); 1060 1061 return (error); 1062} 1063 1064/* 1065 * Shutdown hardware and free up resources. This can be called any 1066 * time after the mutex has been initialized. It is called in both 1067 * the error case in attach and the normal detach case so it needs 1068 * to be careful about only freeing resources that have actually been 1069 * allocated. 1070 */ 1071static int 1072ste_detach(device_t dev) 1073{ 1074 struct ste_softc *sc; 1075 struct ifnet *ifp; 1076 1077 sc = device_get_softc(dev); 1078 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1079 ifp = sc->ste_ifp; 1080 1081#ifdef DEVICE_POLLING 1082 if (ifp->if_capenable & IFCAP_POLLING) 1083 ether_poll_deregister(ifp); 1084#endif 1085 1086 /* These should only be active if attach succeeded */ 1087 if (device_is_attached(dev)) { 1088 ether_ifdetach(ifp); 1089 STE_LOCK(sc); 1090 ste_stop(sc); 1091 STE_UNLOCK(sc); 1092 callout_drain(&sc->ste_callout); 1093 } 1094 if (sc->ste_miibus) 1095 device_delete_child(dev, sc->ste_miibus); 1096 bus_generic_detach(dev); 1097 1098 if (sc->ste_intrhand) 1099 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1100 if (sc->ste_irq) 1101 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1102 if (sc->ste_res) 1103 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1104 sc->ste_res); 1105 1106 if (ifp) 1107 if_free(ifp); 1108 1109 ste_dma_free(sc); 1110 mtx_destroy(&sc->ste_mtx); 1111 1112 return (0); 1113} 1114 1115struct ste_dmamap_arg { 1116 bus_addr_t ste_busaddr; 1117}; 1118 1119static void 1120ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1121{ 1122 struct ste_dmamap_arg *ctx; 1123 1124 if (error != 0) 1125 return; 1126 1127 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1128 1129 ctx = (struct ste_dmamap_arg *)arg; 1130 ctx->ste_busaddr = segs[0].ds_addr; 1131} 1132 1133static int 1134ste_dma_alloc(struct ste_softc *sc) 1135{ 1136 struct ste_chain *txc; 1137 struct ste_chain_onefrag *rxc; 1138 struct ste_dmamap_arg ctx; 1139 int error, i; 1140 1141 /* Create parent DMA tag. */ 1142 error = bus_dma_tag_create( 1143 bus_get_dma_tag(sc->ste_dev), /* parent */ 1144 1, 0, /* alignment, boundary */ 1145 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1146 BUS_SPACE_MAXADDR, /* highaddr */ 1147 NULL, NULL, /* filter, filterarg */ 1148 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1149 0, /* nsegments */ 1150 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1151 0, /* flags */ 1152 NULL, NULL, /* lockfunc, lockarg */ 1153 &sc->ste_cdata.ste_parent_tag); 1154 if (error != 0) { 1155 device_printf(sc->ste_dev, 1156 "could not create parent DMA tag.\n"); 1157 goto fail; 1158 } 1159 1160 /* Create DMA tag for Tx descriptor list. */ 1161 error = bus_dma_tag_create( 1162 sc->ste_cdata.ste_parent_tag, /* parent */ 1163 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1164 BUS_SPACE_MAXADDR, /* lowaddr */ 1165 BUS_SPACE_MAXADDR, /* highaddr */ 1166 NULL, NULL, /* filter, filterarg */ 1167 STE_TX_LIST_SZ, /* maxsize */ 1168 1, /* nsegments */ 1169 STE_TX_LIST_SZ, /* maxsegsize */ 1170 0, /* flags */ 1171 NULL, NULL, /* lockfunc, lockarg */ 1172 &sc->ste_cdata.ste_tx_list_tag); 1173 if (error != 0) { 1174 device_printf(sc->ste_dev, 1175 "could not create Tx list DMA tag.\n"); 1176 goto fail; 1177 } 1178 1179 /* Create DMA tag for Rx descriptor list. */ 1180 error = bus_dma_tag_create( 1181 sc->ste_cdata.ste_parent_tag, /* parent */ 1182 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1183 BUS_SPACE_MAXADDR, /* lowaddr */ 1184 BUS_SPACE_MAXADDR, /* highaddr */ 1185 NULL, NULL, /* filter, filterarg */ 1186 STE_RX_LIST_SZ, /* maxsize */ 1187 1, /* nsegments */ 1188 STE_RX_LIST_SZ, /* maxsegsize */ 1189 0, /* flags */ 1190 NULL, NULL, /* lockfunc, lockarg */ 1191 &sc->ste_cdata.ste_rx_list_tag); 1192 if (error != 0) { 1193 device_printf(sc->ste_dev, 1194 "could not create Rx list DMA tag.\n"); 1195 goto fail; 1196 } 1197 1198 /* Create DMA tag for Tx buffers. */ 1199 error = bus_dma_tag_create( 1200 sc->ste_cdata.ste_parent_tag, /* parent */ 1201 1, 0, /* alignment, boundary */ 1202 BUS_SPACE_MAXADDR, /* lowaddr */ 1203 BUS_SPACE_MAXADDR, /* highaddr */ 1204 NULL, NULL, /* filter, filterarg */ 1205 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1206 STE_MAXFRAGS, /* nsegments */ 1207 MCLBYTES, /* maxsegsize */ 1208 0, /* flags */ 1209 NULL, NULL, /* lockfunc, lockarg */ 1210 &sc->ste_cdata.ste_tx_tag); 1211 if (error != 0) { 1212 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1213 goto fail; 1214 } 1215 1216 /* Create DMA tag for Rx buffers. */ 1217 error = bus_dma_tag_create( 1218 sc->ste_cdata.ste_parent_tag, /* parent */ 1219 1, 0, /* alignment, boundary */ 1220 BUS_SPACE_MAXADDR, /* lowaddr */ 1221 BUS_SPACE_MAXADDR, /* highaddr */ 1222 NULL, NULL, /* filter, filterarg */ 1223 MCLBYTES, /* maxsize */ 1224 1, /* nsegments */ 1225 MCLBYTES, /* maxsegsize */ 1226 0, /* flags */ 1227 NULL, NULL, /* lockfunc, lockarg */ 1228 &sc->ste_cdata.ste_rx_tag); 1229 if (error != 0) { 1230 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1231 goto fail; 1232 } 1233 1234 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1235 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1236 (void **)&sc->ste_ldata.ste_tx_list, 1237 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1238 &sc->ste_cdata.ste_tx_list_map); 1239 if (error != 0) { 1240 device_printf(sc->ste_dev, 1241 "could not allocate DMA'able memory for Tx list.\n"); 1242 goto fail; 1243 } 1244 ctx.ste_busaddr = 0; 1245 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1246 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1247 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1248 if (error != 0 || ctx.ste_busaddr == 0) { 1249 device_printf(sc->ste_dev, 1250 "could not load DMA'able memory for Tx list.\n"); 1251 goto fail; 1252 } 1253 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1254 1255 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1256 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1257 (void **)&sc->ste_ldata.ste_rx_list, 1258 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1259 &sc->ste_cdata.ste_rx_list_map); 1260 if (error != 0) { 1261 device_printf(sc->ste_dev, 1262 "could not allocate DMA'able memory for Rx list.\n"); 1263 goto fail; 1264 } 1265 ctx.ste_busaddr = 0; 1266 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1267 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1268 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1269 if (error != 0 || ctx.ste_busaddr == 0) { 1270 device_printf(sc->ste_dev, 1271 "could not load DMA'able memory for Rx list.\n"); 1272 goto fail; 1273 } 1274 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1275 1276 /* Create DMA maps for Tx buffers. */ 1277 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1278 txc = &sc->ste_cdata.ste_tx_chain[i]; 1279 txc->ste_ptr = NULL; 1280 txc->ste_mbuf = NULL; 1281 txc->ste_next = NULL; 1282 txc->ste_phys = 0; 1283 txc->ste_map = NULL; 1284 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1285 &txc->ste_map); 1286 if (error != 0) { 1287 device_printf(sc->ste_dev, 1288 "could not create Tx dmamap.\n"); 1289 goto fail; 1290 } 1291 } 1292 /* Create DMA maps for Rx buffers. */ 1293 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1294 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1295 device_printf(sc->ste_dev, 1296 "could not create spare Rx dmamap.\n"); 1297 goto fail; 1298 } 1299 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1300 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1301 rxc->ste_ptr = NULL; 1302 rxc->ste_mbuf = NULL; 1303 rxc->ste_next = NULL; 1304 rxc->ste_map = NULL; 1305 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1306 &rxc->ste_map); 1307 if (error != 0) { 1308 device_printf(sc->ste_dev, 1309 "could not create Rx dmamap.\n"); 1310 goto fail; 1311 } 1312 } 1313 1314fail: 1315 return (error); 1316} 1317 1318static void 1319ste_dma_free(struct ste_softc *sc) 1320{ 1321 struct ste_chain *txc; 1322 struct ste_chain_onefrag *rxc; 1323 int i; 1324 1325 /* Tx buffers. */ 1326 if (sc->ste_cdata.ste_tx_tag != NULL) { 1327 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1328 txc = &sc->ste_cdata.ste_tx_chain[i]; 1329 if (txc->ste_map != NULL) { 1330 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1331 txc->ste_map); 1332 txc->ste_map = NULL; 1333 } 1334 } 1335 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1336 sc->ste_cdata.ste_tx_tag = NULL; 1337 } 1338 /* Rx buffers. */ 1339 if (sc->ste_cdata.ste_rx_tag != NULL) { 1340 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1341 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1342 if (rxc->ste_map != NULL) { 1343 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1344 rxc->ste_map); 1345 rxc->ste_map = NULL; 1346 } 1347 } 1348 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1349 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1350 sc->ste_cdata.ste_rx_sparemap); 1351 sc->ste_cdata.ste_rx_sparemap = NULL; 1352 } 1353 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1354 sc->ste_cdata.ste_rx_tag = NULL; 1355 } 1356 /* Tx descriptor list. */ 1357 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1358 if (sc->ste_cdata.ste_tx_list_map != NULL) 1359 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1360 sc->ste_cdata.ste_tx_list_map); 1361 if (sc->ste_cdata.ste_tx_list_map != NULL && 1362 sc->ste_ldata.ste_tx_list != NULL) 1363 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1364 sc->ste_ldata.ste_tx_list, 1365 sc->ste_cdata.ste_tx_list_map); 1366 sc->ste_ldata.ste_tx_list = NULL; 1367 sc->ste_cdata.ste_tx_list_map = NULL; 1368 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1369 sc->ste_cdata.ste_tx_list_tag = NULL; 1370 } 1371 /* Rx descriptor list. */ 1372 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1373 if (sc->ste_cdata.ste_rx_list_map != NULL) 1374 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1375 sc->ste_cdata.ste_rx_list_map); 1376 if (sc->ste_cdata.ste_rx_list_map != NULL && 1377 sc->ste_ldata.ste_rx_list != NULL) 1378 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1379 sc->ste_ldata.ste_rx_list, 1380 sc->ste_cdata.ste_rx_list_map); 1381 sc->ste_ldata.ste_rx_list = NULL; 1382 sc->ste_cdata.ste_rx_list_map = NULL; 1383 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1384 sc->ste_cdata.ste_rx_list_tag = NULL; 1385 } 1386 if (sc->ste_cdata.ste_parent_tag != NULL) { 1387 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1388 sc->ste_cdata.ste_parent_tag = NULL; 1389 } 1390} 1391 1392static int 1393ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1394{ 1395 struct mbuf *m; 1396 bus_dma_segment_t segs[1]; 1397 bus_dmamap_t map; 1398 int error, nsegs; 1399 1400 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1401 if (m == NULL) 1402 return (ENOBUFS); 1403 m->m_len = m->m_pkthdr.len = MCLBYTES; 1404 m_adj(m, ETHER_ALIGN); 1405 1406 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1407 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1408 m_freem(m); 1409 return (error); 1410 } 1411 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1412 1413 if (rxc->ste_mbuf != NULL) { 1414 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1415 BUS_DMASYNC_POSTREAD); 1416 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1417 } 1418 map = rxc->ste_map; 1419 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1420 sc->ste_cdata.ste_rx_sparemap = map; 1421 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1422 BUS_DMASYNC_PREREAD); 1423 rxc->ste_mbuf = m; 1424 rxc->ste_ptr->ste_status = 0; 1425 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1426 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1427 STE_FRAG_LAST); 1428 return (0); 1429} 1430 1431static int 1432ste_init_rx_list(struct ste_softc *sc) 1433{ 1434 struct ste_chain_data *cd; 1435 struct ste_list_data *ld; 1436 int error, i; 1437 1438 cd = &sc->ste_cdata; 1439 ld = &sc->ste_ldata; 1440 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1441 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1442 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1443 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1444 if (error != 0) 1445 return (error); 1446 if (i == (STE_RX_LIST_CNT - 1)) { 1447 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1448 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1449 (sizeof(struct ste_desc_onefrag) * 0); 1450 } else { 1451 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1452 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1453 (sizeof(struct ste_desc_onefrag) * (i + 1)); 1454 } 1455 } 1456 1457 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1458 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1459 sc->ste_cdata.ste_rx_list_map, 1460 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1461 1462 return (0); 1463} 1464 1465static void 1466ste_init_tx_list(struct ste_softc *sc) 1467{ 1468 struct ste_chain_data *cd; 1469 struct ste_list_data *ld; 1470 int i; 1471 1472 cd = &sc->ste_cdata; 1473 ld = &sc->ste_ldata; 1474 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1475 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1476 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1477 cd->ste_tx_chain[i].ste_mbuf = NULL; 1478 if (i == (STE_TX_LIST_CNT - 1)) { 1479 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1480 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1481 ld->ste_tx_list_paddr + 1482 (sizeof(struct ste_desc) * 0))); 1483 } else { 1484 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1485 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1486 ld->ste_tx_list_paddr + 1487 (sizeof(struct ste_desc) * (i + 1)))); 1488 } 1489 } 1490 1491 cd->ste_last_tx = NULL; 1492 cd->ste_tx_prod = 0; 1493 cd->ste_tx_cons = 0; 1494 cd->ste_tx_cnt = 0; 1495 1496 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1497 sc->ste_cdata.ste_tx_list_map, 1498 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1499} 1500 1501static void 1502ste_init(void *xsc) 1503{ 1504 struct ste_softc *sc; 1505 1506 sc = xsc; 1507 STE_LOCK(sc); 1508 ste_init_locked(sc); 1509 STE_UNLOCK(sc); 1510} 1511 1512static void 1513ste_init_locked(struct ste_softc *sc) 1514{ 1515 struct ifnet *ifp; 1516 int i; 1517 1518 STE_LOCK_ASSERT(sc); 1519 ifp = sc->ste_ifp; 1520 1521 ste_stop(sc); 1522 /* Reset the chip to a known state. */ 1523 ste_reset(sc); 1524 1525 /* Init our MAC address */ 1526 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1527 CSR_WRITE_2(sc, STE_PAR0 + i, 1528 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1529 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1530 } 1531 1532 /* Init RX list */ 1533 if (ste_init_rx_list(sc) != 0) { 1534 device_printf(sc->ste_dev, 1535 "initialization failed: no memory for RX buffers\n"); 1536 ste_stop(sc); 1537 return; 1538 } 1539 1540 /* Set RX polling interval */ 1541 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1542 1543 /* Init TX descriptors */ 1544 ste_init_tx_list(sc); 1545 1546 /* Set the TX freethresh value */ 1547 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1548 1549 /* Set the TX start threshold for best performance. */ 1550 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1551 1552 /* Set the TX reclaim threshold. */ 1553 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1554 1555 /* Set up the RX filter. */ 1556 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1557 1558 /* If we want promiscuous mode, set the allframes bit. */ 1559 if (ifp->if_flags & IFF_PROMISC) { 1560 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1561 } else { 1562 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1563 } 1564 1565 /* Set capture broadcast bit to accept broadcast frames. */ 1566 if (ifp->if_flags & IFF_BROADCAST) { 1567 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1568 } else { 1569 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1570 } 1571 1572 ste_setmulti(sc); 1573 1574 /* Load the address of the RX list. */ 1575 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1576 ste_wait(sc); 1577 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1578 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1579 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1580 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1581 1582 /* Set TX polling interval(defer until we TX first packet). */ 1583 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1584 1585 /* Load address of the TX list */ 1586 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1587 ste_wait(sc); 1588 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1589 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1590 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1591 ste_wait(sc); 1592 1593 /* Enable receiver and transmitter */ 1594 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1595 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1596 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1597 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1598 1599 /* Enable stats counters. */ 1600 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1601 1602 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1603#ifdef DEVICE_POLLING 1604 /* Disable interrupts if we are polling. */ 1605 if (ifp->if_capenable & IFCAP_POLLING) 1606 CSR_WRITE_2(sc, STE_IMR, 0); 1607 else 1608#endif 1609 /* Enable interrupts. */ 1610 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1611 1612 /* Accept VLAN length packets */ 1613 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1614 1615 ste_ifmedia_upd_locked(ifp); 1616 1617 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1618 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1619 1620 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1621} 1622 1623static void 1624ste_stop(struct ste_softc *sc) 1625{ 1626 struct ifnet *ifp; 1627 struct ste_chain_onefrag *cur_rx; 1628 struct ste_chain *cur_tx; 1629 uint32_t val; 1630 int i; 1631 1632 STE_LOCK_ASSERT(sc); 1633 ifp = sc->ste_ifp; 1634 1635 callout_stop(&sc->ste_callout); 1636 sc->ste_timer = 0; 1637 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1638 1639 CSR_WRITE_2(sc, STE_IMR, 0); 1640 /* Stop pending DMA. */ 1641 val = CSR_READ_4(sc, STE_DMACTL); 1642 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1643 CSR_WRITE_4(sc, STE_DMACTL, val); 1644 ste_wait(sc); 1645 /* Disable auto-polling. */ 1646 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1647 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1648 /* Nullify DMA address to stop any further DMA. */ 1649 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1650 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1651 /* Stop TX/RX MAC. */ 1652 val = CSR_READ_2(sc, STE_MACCTL1); 1653 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1654 STE_MACCTL1_STATS_DISABLE; 1655 CSR_WRITE_2(sc, STE_MACCTL1, val); 1656 for (i = 0; i < STE_TIMEOUT; i++) { 1657 DELAY(10); 1658 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1659 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1660 break; 1661 } 1662 if (i == STE_TIMEOUT) 1663 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1664 /* Acknowledge any pending interrupts. */ 1665 CSR_READ_2(sc, STE_ISR_ACK); 1666 ste_stats_update(sc); 1667 1668 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1669 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1670 if (cur_rx->ste_mbuf != NULL) { 1671 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1672 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1673 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1674 cur_rx->ste_map); 1675 m_freem(cur_rx->ste_mbuf); 1676 cur_rx->ste_mbuf = NULL; 1677 } 1678 } 1679 1680 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1681 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1682 if (cur_tx->ste_mbuf != NULL) { 1683 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1684 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1685 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1686 cur_tx->ste_map); 1687 m_freem(cur_tx->ste_mbuf); 1688 cur_tx->ste_mbuf = NULL; 1689 } 1690 } 1691} 1692 1693static void 1694ste_reset(struct ste_softc *sc) 1695{ 1696 int i; 1697 1698 STE_SETBIT4(sc, STE_ASICCTL, 1699 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1700 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1701 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1702 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1703 STE_ASICCTL_EXTRESET_RESET); 1704 1705 DELAY(100000); 1706 1707 for (i = 0; i < STE_TIMEOUT; i++) { 1708 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1709 break; 1710 } 1711 1712 if (i == STE_TIMEOUT) 1713 device_printf(sc->ste_dev, "global reset never completed\n"); 1714} 1715 1716static int 1717ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1718{ 1719 struct ste_softc *sc; 1720 struct ifreq *ifr; 1721 struct mii_data *mii; 1722 int error = 0; 1723 1724 sc = ifp->if_softc; 1725 ifr = (struct ifreq *)data; 1726 1727 switch (command) { 1728 case SIOCSIFFLAGS: 1729 STE_LOCK(sc); 1730 if (ifp->if_flags & IFF_UP) { 1731 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1732 ifp->if_flags & IFF_PROMISC && 1733 !(sc->ste_if_flags & IFF_PROMISC)) { 1734 STE_SETBIT1(sc, STE_RX_MODE, 1735 STE_RXMODE_PROMISC); 1736 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1737 !(ifp->if_flags & IFF_PROMISC) && 1738 sc->ste_if_flags & IFF_PROMISC) { 1739 STE_CLRBIT1(sc, STE_RX_MODE, 1740 STE_RXMODE_PROMISC); 1741 } 1742 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1743 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1744 ste_setmulti(sc); 1745 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1746 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1747 ste_init_locked(sc); 1748 } 1749 } else { 1750 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1751 ste_stop(sc); 1752 } 1753 sc->ste_if_flags = ifp->if_flags; 1754 STE_UNLOCK(sc); 1755 error = 0; 1756 break; 1757 case SIOCADDMULTI: 1758 case SIOCDELMULTI: 1759 STE_LOCK(sc); 1760 ste_setmulti(sc); 1761 STE_UNLOCK(sc); 1762 error = 0; 1763 break; 1764 case SIOCGIFMEDIA: 1765 case SIOCSIFMEDIA: 1766 mii = device_get_softc(sc->ste_miibus); 1767 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1768 break; 1769 case SIOCSIFCAP: 1770#ifdef DEVICE_POLLING 1771 if (ifr->ifr_reqcap & IFCAP_POLLING && 1772 !(ifp->if_capenable & IFCAP_POLLING)) { 1773 error = ether_poll_register(ste_poll, ifp); 1774 if (error) 1775 return (error); 1776 STE_LOCK(sc); 1777 /* Disable interrupts */ 1778 CSR_WRITE_2(sc, STE_IMR, 0); 1779 ifp->if_capenable |= IFCAP_POLLING; 1780 STE_UNLOCK(sc); 1781 return (error); 1782 1783 } 1784 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1785 ifp->if_capenable & IFCAP_POLLING) { 1786 error = ether_poll_deregister(ifp); 1787 /* Enable interrupts. */ 1788 STE_LOCK(sc); 1789 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1790 ifp->if_capenable &= ~IFCAP_POLLING; 1791 STE_UNLOCK(sc); 1792 return (error); 1793 } 1794#endif /* DEVICE_POLLING */ 1795 break; 1796 default: 1797 error = ether_ioctl(ifp, command, data); 1798 break; 1799 } 1800 1801 return (error); 1802} 1803 1804static int 1805ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1806{ 1807 struct ste_frag *frag; 1808 struct mbuf *m; 1809 struct ste_desc *desc; 1810 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1811 int error, i, nsegs; 1812 1813 STE_LOCK_ASSERT(sc); 1814 M_ASSERTPKTHDR((*m_head)); 1815 1816 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1817 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1818 if (error == EFBIG) { 1819 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS); 1820 if (m == NULL) { 1821 m_freem(*m_head); 1822 *m_head = NULL; 1823 return (ENOMEM); 1824 } 1825 *m_head = m; 1826 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1827 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1828 if (error != 0) { 1829 m_freem(*m_head); 1830 *m_head = NULL; 1831 return (error); 1832 } 1833 } else if (error != 0) 1834 return (error); 1835 if (nsegs == 0) { 1836 m_freem(*m_head); 1837 *m_head = NULL; 1838 return (EIO); 1839 } 1840 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1841 BUS_DMASYNC_PREWRITE); 1842 1843 desc = txc->ste_ptr; 1844 for (i = 0; i < nsegs; i++) { 1845 frag = &desc->ste_frags[i]; 1846 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1847 frag->ste_len = htole32(txsegs[i].ds_len); 1848 } 1849 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1850 /* 1851 * Because we use Tx polling we can't chain multiple 1852 * Tx descriptors here. Otherwise we race with controller. 1853 */ 1854 desc->ste_next = 0; 1855 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | STE_TXCTL_DMAINTR); 1856 txc->ste_mbuf = *m_head; 1857 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1858 sc->ste_cdata.ste_tx_cnt++; 1859 1860 return (0); 1861} 1862 1863static void 1864ste_start(struct ifnet *ifp) 1865{ 1866 struct ste_softc *sc; 1867 1868 sc = ifp->if_softc; 1869 STE_LOCK(sc); 1870 ste_start_locked(ifp); 1871 STE_UNLOCK(sc); 1872} 1873 1874static void 1875ste_start_locked(struct ifnet *ifp) 1876{ 1877 struct ste_softc *sc; 1878 struct ste_chain *cur_tx; 1879 struct mbuf *m_head = NULL; 1880 int enq; 1881 1882 sc = ifp->if_softc; 1883 STE_LOCK_ASSERT(sc); 1884 1885 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1886 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 1887 return; 1888 1889 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 1890 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1891 /* 1892 * Controller may have cached copy of the last used 1893 * next ptr so we have to reserve one TFD to avoid 1894 * TFD overruns. 1895 */ 1896 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1897 break; 1898 } 1899 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1900 if (m_head == NULL) 1901 break; 1902 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1903 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1904 if (m_head == NULL) 1905 break; 1906 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1907 break; 1908 } 1909 if (sc->ste_cdata.ste_last_tx == NULL) { 1910 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1911 sc->ste_cdata.ste_tx_list_map, 1912 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1913 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1914 ste_wait(sc); 1915 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1916 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1917 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1918 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1919 ste_wait(sc); 1920 } else { 1921 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1922 sc->ste_cdata.ste_last_tx->ste_phys; 1923 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1924 sc->ste_cdata.ste_tx_list_map, 1925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1926 } 1927 sc->ste_cdata.ste_last_tx = cur_tx; 1928 1929 enq++; 1930 /* 1931 * If there's a BPF listener, bounce a copy of this frame 1932 * to him. 1933 */ 1934 BPF_MTAP(ifp, m_head); 1935 } 1936 1937 if (enq > 0) 1938 sc->ste_timer = STE_TX_TIMEOUT; 1939} 1940 1941static void 1942ste_watchdog(struct ste_softc *sc) 1943{ 1944 struct ifnet *ifp; 1945 1946 ifp = sc->ste_ifp; 1947 STE_LOCK_ASSERT(sc); 1948 1949 if (sc->ste_timer == 0 || --sc->ste_timer) 1950 return; 1951 1952 ifp->if_oerrors++; 1953 if_printf(ifp, "watchdog timeout\n"); 1954 1955 ste_txeoc(sc); 1956 ste_txeof(sc); 1957 ste_rxeof(sc, -1); 1958 ste_init_locked(sc); 1959 1960 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1961 ste_start_locked(ifp); 1962} 1963 1964static int 1965ste_shutdown(device_t dev) 1966{ 1967 struct ste_softc *sc; 1968 1969 sc = device_get_softc(dev); 1970 1971 STE_LOCK(sc); 1972 ste_stop(sc); 1973 STE_UNLOCK(sc); 1974 1975 return (0); 1976} 1977