if_ste.c revision 200875
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 200875 2009-12-22 21:39:34Z yongari $"); 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53 54#include <net/bpf.h> 55#include <net/if.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61#include <net/if_vlan_var.h> 62 63#include <machine/bus.h> 64#include <machine/resource.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <dev/ste/if_stereg.h> 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77MODULE_DEPEND(ste, pci, 1, 1, 1); 78MODULE_DEPEND(ste, ether, 1, 1, 1); 79MODULE_DEPEND(ste, miibus, 1, 1, 1); 80 81/* 82 * Various supported device vendors/types and their names. 83 */ 84static struct ste_type ste_devs[] = { 85 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 86 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 87 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 88 { 0, 0, NULL } 89}; 90 91static int ste_attach(device_t); 92static int ste_detach(device_t); 93static int ste_probe(device_t); 94static int ste_shutdown(device_t); 95 96static int ste_dma_alloc(struct ste_softc *); 97static void ste_dma_free(struct ste_softc *); 98static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 99static int ste_eeprom_wait(struct ste_softc *); 100static int ste_encap(struct ste_softc *, struct mbuf **, 101 struct ste_chain *); 102static int ste_ifmedia_upd(struct ifnet *); 103static void ste_ifmedia_upd_locked(struct ifnet *); 104static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 105static void ste_init(void *); 106static void ste_init_locked(struct ste_softc *); 107static int ste_init_rx_list(struct ste_softc *); 108static void ste_init_tx_list(struct ste_softc *); 109static void ste_intr(void *); 110static int ste_ioctl(struct ifnet *, u_long, caddr_t); 111static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 112static void ste_mii_send(struct ste_softc *, uint32_t, int); 113static void ste_mii_sync(struct ste_softc *); 114static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 115static int ste_miibus_readreg(device_t, int, int); 116static void ste_miibus_statchg(device_t); 117static int ste_miibus_writereg(device_t, int, int, int); 118static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 119static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 120static void ste_reset(struct ste_softc *); 121static int ste_rxeof(struct ste_softc *, int); 122static void ste_setmulti(struct ste_softc *); 123static void ste_start(struct ifnet *); 124static void ste_start_locked(struct ifnet *); 125static void ste_stats_update(struct ste_softc *); 126static void ste_stop(struct ste_softc *); 127static void ste_tick(void *); 128static void ste_txeoc(struct ste_softc *); 129static void ste_txeof(struct ste_softc *); 130static void ste_wait(struct ste_softc *); 131static void ste_watchdog(struct ste_softc *); 132 133static device_method_t ste_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, ste_probe), 136 DEVMETHOD(device_attach, ste_attach), 137 DEVMETHOD(device_detach, ste_detach), 138 DEVMETHOD(device_shutdown, ste_shutdown), 139 140 /* bus interface */ 141 DEVMETHOD(bus_print_child, bus_generic_print_child), 142 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143 144 /* MII interface */ 145 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 146 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 147 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 148 149 { 0, 0 } 150}; 151 152static driver_t ste_driver = { 153 "ste", 154 ste_methods, 155 sizeof(struct ste_softc) 156}; 157 158static devclass_t ste_devclass; 159 160DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 161DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 162 163#define STE_SETBIT4(sc, reg, x) \ 164 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 165 166#define STE_CLRBIT4(sc, reg, x) \ 167 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 168 169#define STE_SETBIT2(sc, reg, x) \ 170 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 171 172#define STE_CLRBIT2(sc, reg, x) \ 173 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 174 175#define STE_SETBIT1(sc, reg, x) \ 176 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 177 178#define STE_CLRBIT1(sc, reg, x) \ 179 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 180 181 182#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 183#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 184 185/* 186 * Sync the PHYs by setting data bit and strobing the clock 32 times. 187 */ 188static void 189ste_mii_sync(struct ste_softc *sc) 190{ 191 int i; 192 193 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 194 195 for (i = 0; i < 32; i++) { 196 MII_SET(STE_PHYCTL_MCLK); 197 DELAY(1); 198 MII_CLR(STE_PHYCTL_MCLK); 199 DELAY(1); 200 } 201} 202 203/* 204 * Clock a series of bits through the MII. 205 */ 206static void 207ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt) 208{ 209 int i; 210 211 MII_CLR(STE_PHYCTL_MCLK); 212 213 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 214 if (bits & i) { 215 MII_SET(STE_PHYCTL_MDATA); 216 } else { 217 MII_CLR(STE_PHYCTL_MDATA); 218 } 219 DELAY(1); 220 MII_CLR(STE_PHYCTL_MCLK); 221 DELAY(1); 222 MII_SET(STE_PHYCTL_MCLK); 223 } 224} 225 226/* 227 * Read an PHY register through the MII. 228 */ 229static int 230ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 231{ 232 int i, ack; 233 234 /* 235 * Set up frame for RX. 236 */ 237 frame->mii_stdelim = STE_MII_STARTDELIM; 238 frame->mii_opcode = STE_MII_READOP; 239 frame->mii_turnaround = 0; 240 frame->mii_data = 0; 241 242 CSR_WRITE_2(sc, STE_PHYCTL, 0); 243 /* 244 * Turn on data xmit. 245 */ 246 MII_SET(STE_PHYCTL_MDIR); 247 248 ste_mii_sync(sc); 249 250 /* 251 * Send command/address info. 252 */ 253 ste_mii_send(sc, frame->mii_stdelim, 2); 254 ste_mii_send(sc, frame->mii_opcode, 2); 255 ste_mii_send(sc, frame->mii_phyaddr, 5); 256 ste_mii_send(sc, frame->mii_regaddr, 5); 257 258 /* Turn off xmit. */ 259 MII_CLR(STE_PHYCTL_MDIR); 260 261 /* Idle bit */ 262 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 263 DELAY(1); 264 MII_SET(STE_PHYCTL_MCLK); 265 DELAY(1); 266 267 /* Check for ack */ 268 MII_CLR(STE_PHYCTL_MCLK); 269 DELAY(1); 270 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 271 MII_SET(STE_PHYCTL_MCLK); 272 DELAY(1); 273 274 /* 275 * Now try reading data bits. If the ack failed, we still 276 * need to clock through 16 cycles to keep the PHY(s) in sync. 277 */ 278 if (ack) { 279 for (i = 0; i < 16; i++) { 280 MII_CLR(STE_PHYCTL_MCLK); 281 DELAY(1); 282 MII_SET(STE_PHYCTL_MCLK); 283 DELAY(1); 284 } 285 goto fail; 286 } 287 288 for (i = 0x8000; i; i >>= 1) { 289 MII_CLR(STE_PHYCTL_MCLK); 290 DELAY(1); 291 if (!ack) { 292 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 293 frame->mii_data |= i; 294 DELAY(1); 295 } 296 MII_SET(STE_PHYCTL_MCLK); 297 DELAY(1); 298 } 299 300fail: 301 302 MII_CLR(STE_PHYCTL_MCLK); 303 DELAY(1); 304 MII_SET(STE_PHYCTL_MCLK); 305 DELAY(1); 306 307 if (ack) 308 return (1); 309 return (0); 310} 311 312/* 313 * Write to a PHY register through the MII. 314 */ 315static int 316ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 317{ 318 319 /* 320 * Set up frame for TX. 321 */ 322 323 frame->mii_stdelim = STE_MII_STARTDELIM; 324 frame->mii_opcode = STE_MII_WRITEOP; 325 frame->mii_turnaround = STE_MII_TURNAROUND; 326 327 /* 328 * Turn on data output. 329 */ 330 MII_SET(STE_PHYCTL_MDIR); 331 332 ste_mii_sync(sc); 333 334 ste_mii_send(sc, frame->mii_stdelim, 2); 335 ste_mii_send(sc, frame->mii_opcode, 2); 336 ste_mii_send(sc, frame->mii_phyaddr, 5); 337 ste_mii_send(sc, frame->mii_regaddr, 5); 338 ste_mii_send(sc, frame->mii_turnaround, 2); 339 ste_mii_send(sc, frame->mii_data, 16); 340 341 /* Idle bit. */ 342 MII_SET(STE_PHYCTL_MCLK); 343 DELAY(1); 344 MII_CLR(STE_PHYCTL_MCLK); 345 DELAY(1); 346 347 /* 348 * Turn off xmit. 349 */ 350 MII_CLR(STE_PHYCTL_MDIR); 351 352 return (0); 353} 354 355static int 356ste_miibus_readreg(device_t dev, int phy, int reg) 357{ 358 struct ste_softc *sc; 359 struct ste_mii_frame frame; 360 361 sc = device_get_softc(dev); 362 363 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0 && phy != 0) 364 return (0); 365 366 bzero((char *)&frame, sizeof(frame)); 367 368 frame.mii_phyaddr = phy; 369 frame.mii_regaddr = reg; 370 ste_mii_readreg(sc, &frame); 371 372 return (frame.mii_data); 373} 374 375static int 376ste_miibus_writereg(device_t dev, int phy, int reg, int data) 377{ 378 struct ste_softc *sc; 379 struct ste_mii_frame frame; 380 381 sc = device_get_softc(dev); 382 bzero((char *)&frame, sizeof(frame)); 383 384 frame.mii_phyaddr = phy; 385 frame.mii_regaddr = reg; 386 frame.mii_data = data; 387 388 ste_mii_writereg(sc, &frame); 389 390 return (0); 391} 392 393static void 394ste_miibus_statchg(device_t dev) 395{ 396 struct ste_softc *sc; 397 struct mii_data *mii; 398 struct ifnet *ifp; 399 uint16_t cfg; 400 401 sc = device_get_softc(dev); 402 403 mii = device_get_softc(sc->ste_miibus); 404 ifp = sc->ste_ifp; 405 if (mii == NULL || ifp == NULL || 406 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 407 return; 408 409 sc->ste_flags &= ~STE_FLAG_LINK; 410 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 411 (IFM_ACTIVE | IFM_AVALID)) { 412 switch (IFM_SUBTYPE(mii->mii_media_active)) { 413 case IFM_10_T: 414 case IFM_100_TX: 415 case IFM_100_FX: 416 case IFM_100_T4: 417 sc->ste_flags |= STE_FLAG_LINK; 418 default: 419 break; 420 } 421 } 422 423 /* Program MACs with resolved speed/duplex/flow-control. */ 424 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 425 cfg = CSR_READ_2(sc, STE_MACCTL0); 426 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 427 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 428 /* 429 * ST201 data sheet says driver should enable receiving 430 * MAC control frames bit of receive mode register to 431 * receive flow-control frames but the register has no 432 * such bits. In addition the controller has no ability 433 * to send pause frames so it should be handled in 434 * driver. Implementing pause timer handling in driver 435 * layer is not trivial, so don't enable flow-control 436 * here. 437 */ 438 cfg |= STE_MACCTL0_FULLDUPLEX; 439 } 440 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 441 } 442} 443 444static int 445ste_ifmedia_upd(struct ifnet *ifp) 446{ 447 struct ste_softc *sc; 448 449 sc = ifp->if_softc; 450 STE_LOCK(sc); 451 ste_ifmedia_upd_locked(ifp); 452 STE_UNLOCK(sc); 453 454 return (0); 455} 456 457static void 458ste_ifmedia_upd_locked(struct ifnet *ifp) 459{ 460 struct ste_softc *sc; 461 struct mii_data *mii; 462 463 sc = ifp->if_softc; 464 STE_LOCK_ASSERT(sc); 465 mii = device_get_softc(sc->ste_miibus); 466 sc->ste_flags &= ~STE_FLAG_LINK; 467 if (mii->mii_instance) { 468 struct mii_softc *miisc; 469 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 470 mii_phy_reset(miisc); 471 } 472 mii_mediachg(mii); 473} 474 475static void 476ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 477{ 478 struct ste_softc *sc; 479 struct mii_data *mii; 480 481 sc = ifp->if_softc; 482 mii = device_get_softc(sc->ste_miibus); 483 484 STE_LOCK(sc); 485 mii_pollstat(mii); 486 ifmr->ifm_active = mii->mii_media_active; 487 ifmr->ifm_status = mii->mii_media_status; 488 STE_UNLOCK(sc); 489} 490 491static void 492ste_wait(struct ste_softc *sc) 493{ 494 int i; 495 496 for (i = 0; i < STE_TIMEOUT; i++) { 497 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 498 break; 499 DELAY(1); 500 } 501 502 if (i == STE_TIMEOUT) 503 device_printf(sc->ste_dev, "command never completed!\n"); 504} 505 506/* 507 * The EEPROM is slow: give it time to come ready after issuing 508 * it a command. 509 */ 510static int 511ste_eeprom_wait(struct ste_softc *sc) 512{ 513 int i; 514 515 DELAY(1000); 516 517 for (i = 0; i < 100; i++) { 518 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 519 DELAY(1000); 520 else 521 break; 522 } 523 524 if (i == 100) { 525 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 526 return (1); 527 } 528 529 return (0); 530} 531 532/* 533 * Read a sequence of words from the EEPROM. Note that ethernet address 534 * data is stored in the EEPROM in network byte order. 535 */ 536static int 537ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 538{ 539 uint16_t word, *ptr; 540 int err = 0, i; 541 542 if (ste_eeprom_wait(sc)) 543 return (1); 544 545 for (i = 0; i < cnt; i++) { 546 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 547 err = ste_eeprom_wait(sc); 548 if (err) 549 break; 550 word = CSR_READ_2(sc, STE_EEPROM_DATA); 551 ptr = (uint16_t *)(dest + (i * 2)); 552 if (swap) 553 *ptr = ntohs(word); 554 else 555 *ptr = word; 556 } 557 558 return (err ? 1 : 0); 559} 560 561static void 562ste_setmulti(struct ste_softc *sc) 563{ 564 struct ifnet *ifp; 565 struct ifmultiaddr *ifma; 566 uint32_t hashes[2] = { 0, 0 }; 567 int h; 568 569 ifp = sc->ste_ifp; 570 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 571 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 572 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 573 return; 574 } 575 576 /* first, zot all the existing hash bits */ 577 CSR_WRITE_2(sc, STE_MAR0, 0); 578 CSR_WRITE_2(sc, STE_MAR1, 0); 579 CSR_WRITE_2(sc, STE_MAR2, 0); 580 CSR_WRITE_2(sc, STE_MAR3, 0); 581 582 /* now program new ones */ 583 if_maddr_rlock(ifp); 584 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 585 if (ifma->ifma_addr->sa_family != AF_LINK) 586 continue; 587 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 588 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 589 if (h < 32) 590 hashes[0] |= (1 << h); 591 else 592 hashes[1] |= (1 << (h - 32)); 593 } 594 if_maddr_runlock(ifp); 595 596 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 597 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 598 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 599 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 600 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 601 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 602} 603 604#ifdef DEVICE_POLLING 605static poll_handler_t ste_poll, ste_poll_locked; 606 607static int 608ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 609{ 610 struct ste_softc *sc = ifp->if_softc; 611 int rx_npkts = 0; 612 613 STE_LOCK(sc); 614 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 615 rx_npkts = ste_poll_locked(ifp, cmd, count); 616 STE_UNLOCK(sc); 617 return (rx_npkts); 618} 619 620static int 621ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 622{ 623 struct ste_softc *sc = ifp->if_softc; 624 int rx_npkts; 625 626 STE_LOCK_ASSERT(sc); 627 628 rx_npkts = ste_rxeof(sc, count); 629 ste_txeof(sc); 630 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 631 ste_start_locked(ifp); 632 633 if (cmd == POLL_AND_CHECK_STATUS) { 634 uint16_t status; 635 636 status = CSR_READ_2(sc, STE_ISR_ACK); 637 638 if (status & STE_ISR_TX_DONE) 639 ste_txeoc(sc); 640 641 if (status & STE_ISR_STATS_OFLOW) 642 ste_stats_update(sc); 643 644 if (status & STE_ISR_HOSTERR) 645 ste_init_locked(sc); 646 } 647 return (rx_npkts); 648} 649#endif /* DEVICE_POLLING */ 650 651static void 652ste_intr(void *xsc) 653{ 654 struct ste_softc *sc; 655 struct ifnet *ifp; 656 uint16_t status; 657 658 sc = xsc; 659 STE_LOCK(sc); 660 ifp = sc->ste_ifp; 661 662#ifdef DEVICE_POLLING 663 if (ifp->if_capenable & IFCAP_POLLING) { 664 STE_UNLOCK(sc); 665 return; 666 } 667#endif 668 669 /* See if this is really our interrupt. */ 670 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 671 STE_UNLOCK(sc); 672 return; 673 } 674 675 for (;;) { 676 status = CSR_READ_2(sc, STE_ISR_ACK); 677 678 if (!(status & STE_INTRS)) 679 break; 680 681 if (status & STE_ISR_RX_DMADONE) 682 ste_rxeof(sc, -1); 683 684 if (status & STE_ISR_TX_DMADONE) 685 ste_txeof(sc); 686 687 if (status & STE_ISR_TX_DONE) 688 ste_txeoc(sc); 689 690 if (status & STE_ISR_STATS_OFLOW) 691 ste_stats_update(sc); 692 693 if (status & STE_ISR_HOSTERR) 694 ste_init_locked(sc); 695 } 696 697 /* Re-enable interrupts */ 698 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 699 700 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 701 ste_start_locked(ifp); 702 703 STE_UNLOCK(sc); 704} 705 706/* 707 * A frame has been uploaded: pass the resulting mbuf chain up to 708 * the higher level protocols. 709 */ 710static int 711ste_rxeof(struct ste_softc *sc, int count) 712{ 713 struct mbuf *m; 714 struct ifnet *ifp; 715 struct ste_chain_onefrag *cur_rx; 716 uint32_t rxstat; 717 int total_len, rx_npkts; 718 719 ifp = sc->ste_ifp; 720 721 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 722 sc->ste_cdata.ste_rx_list_map, 723 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 724 725 cur_rx = sc->ste_cdata.ste_rx_head; 726 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 727 cur_rx = cur_rx->ste_next) { 728 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 729 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 730 break; 731#ifdef DEVICE_POLLING 732 if (ifp->if_capenable & IFCAP_POLLING) { 733 if (count == 0) 734 break; 735 count--; 736 } 737#endif 738 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 739 break; 740 /* 741 * If an error occurs, update stats, clear the 742 * status word and leave the mbuf cluster in place: 743 * it should simply get re-used next time this descriptor 744 * comes up in the ring. 745 */ 746 if (rxstat & STE_RXSTAT_FRAME_ERR) { 747 ifp->if_ierrors++; 748 cur_rx->ste_ptr->ste_status = 0; 749 continue; 750 } 751 752 /* No errors; receive the packet. */ 753 m = cur_rx->ste_mbuf; 754 total_len = STE_RX_BYTES(rxstat); 755 756 /* 757 * Try to conjure up a new mbuf cluster. If that 758 * fails, it means we have an out of memory condition and 759 * should leave the buffer in place and continue. This will 760 * result in a lost packet, but there's little else we 761 * can do in this situation. 762 */ 763 if (ste_newbuf(sc, cur_rx) != 0) { 764 ifp->if_ierrors++; 765 cur_rx->ste_ptr->ste_status = 0; 766 continue; 767 } 768 769 m->m_pkthdr.rcvif = ifp; 770 m->m_pkthdr.len = m->m_len = total_len; 771 772 ifp->if_ipackets++; 773 STE_UNLOCK(sc); 774 (*ifp->if_input)(ifp, m); 775 STE_LOCK(sc); 776 } 777 778 if (rx_npkts > 0) { 779 sc->ste_cdata.ste_rx_head = cur_rx; 780 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 781 sc->ste_cdata.ste_rx_list_map, 782 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 783 } 784 785 return (rx_npkts); 786} 787 788static void 789ste_txeoc(struct ste_softc *sc) 790{ 791 struct ifnet *ifp; 792 uint8_t txstat; 793 794 ifp = sc->ste_ifp; 795 796 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 797 STE_TXSTATUS_TXDONE) { 798 if (txstat & STE_TXSTATUS_UNDERRUN || 799 txstat & STE_TXSTATUS_EXCESSCOLLS || 800 txstat & STE_TXSTATUS_RECLAIMERR) { 801 ifp->if_oerrors++; 802 device_printf(sc->ste_dev, 803 "transmission error: %x\n", txstat); 804 805 ste_init_locked(sc); 806 807 if (txstat & STE_TXSTATUS_UNDERRUN && 808 sc->ste_tx_thresh < STE_PACKET_SIZE) { 809 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 810 device_printf(sc->ste_dev, 811 "tx underrun, increasing tx" 812 " start threshold to %d bytes\n", 813 sc->ste_tx_thresh); 814 } 815 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 816 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 817 (STE_PACKET_SIZE >> 4)); 818 } 819 ste_init_locked(sc); 820 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 821 } 822} 823 824static void 825ste_tick(void *arg) 826{ 827 struct ste_softc *sc; 828 struct mii_data *mii; 829 830 sc = (struct ste_softc *)arg; 831 832 STE_LOCK_ASSERT(sc); 833 834 mii = device_get_softc(sc->ste_miibus); 835 mii_tick(mii); 836 /* 837 * ukphy(4) does not seem to generate CB that reports 838 * resolved link state so if we know we lost a link, 839 * explicitly check the link state. 840 */ 841 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 842 ste_miibus_statchg(sc->ste_dev); 843 ste_stats_update(sc); 844 ste_watchdog(sc); 845 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 846} 847 848static void 849ste_txeof(struct ste_softc *sc) 850{ 851 struct ifnet *ifp; 852 struct ste_chain *cur_tx; 853 uint32_t txstat; 854 int idx; 855 856 STE_LOCK_ASSERT(sc); 857 858 ifp = sc->ste_ifp; 859 idx = sc->ste_cdata.ste_tx_cons; 860 if (idx == sc->ste_cdata.ste_tx_prod) 861 return; 862 863 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 864 sc->ste_cdata.ste_tx_list_map, 865 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 866 867 while (idx != sc->ste_cdata.ste_tx_prod) { 868 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 869 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 870 if ((txstat & STE_TXCTL_DMADONE) == 0) 871 break; 872 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 873 BUS_DMASYNC_POSTWRITE); 874 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 875 KASSERT(cur_tx->ste_mbuf != NULL, 876 ("%s: freeing NULL mbuf!\n", __func__)); 877 m_freem(cur_tx->ste_mbuf); 878 cur_tx->ste_mbuf = NULL; 879 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 880 ifp->if_opackets++; 881 sc->ste_cdata.ste_tx_cnt--; 882 STE_INC(idx, STE_TX_LIST_CNT); 883 } 884 885 sc->ste_cdata.ste_tx_cons = idx; 886 if (sc->ste_cdata.ste_tx_cnt == 0) 887 sc->ste_timer = 0; 888} 889 890static void 891ste_stats_update(struct ste_softc *sc) 892{ 893 struct ifnet *ifp; 894 895 STE_LOCK_ASSERT(sc); 896 897 ifp = sc->ste_ifp; 898 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 899 + CSR_READ_1(sc, STE_MULTI_COLLS) 900 + CSR_READ_1(sc, STE_SINGLE_COLLS); 901} 902 903/* 904 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 905 * IDs against our list and return a device name if we find a match. 906 */ 907static int 908ste_probe(device_t dev) 909{ 910 struct ste_type *t; 911 912 t = ste_devs; 913 914 while (t->ste_name != NULL) { 915 if ((pci_get_vendor(dev) == t->ste_vid) && 916 (pci_get_device(dev) == t->ste_did)) { 917 device_set_desc(dev, t->ste_name); 918 return (BUS_PROBE_DEFAULT); 919 } 920 t++; 921 } 922 923 return (ENXIO); 924} 925 926/* 927 * Attach the interface. Allocate softc structures, do ifmedia 928 * setup and ethernet/BPF attach. 929 */ 930static int 931ste_attach(device_t dev) 932{ 933 struct ste_softc *sc; 934 struct ifnet *ifp; 935 u_char eaddr[6]; 936 int error = 0, rid; 937 938 sc = device_get_softc(dev); 939 sc->ste_dev = dev; 940 941 /* 942 * Only use one PHY since this chip reports multiple 943 * Note on the DFE-550 the PHY is at 1 on the DFE-580 944 * it is at 0 & 1. It is rev 0x12. 945 */ 946 if (pci_get_vendor(dev) == DL_VENDORID && 947 pci_get_device(dev) == DL_DEVICEID_DL10050 && 948 pci_get_revid(dev) == 0x12 ) 949 sc->ste_flags |= STE_FLAG_ONE_PHY; 950 951 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 952 MTX_DEF); 953 /* 954 * Map control/status registers. 955 */ 956 pci_enable_busmaster(dev); 957 958 /* Prefer memory space register mapping over IO space. */ 959 sc->ste_res_id = PCIR_BAR(1); 960 sc->ste_res_type = SYS_RES_MEMORY; 961 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 962 &sc->ste_res_id, RF_ACTIVE); 963 if (sc->ste_res == NULL) { 964 sc->ste_res_id = PCIR_BAR(0); 965 sc->ste_res_type = SYS_RES_IOPORT; 966 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 967 &sc->ste_res_id, RF_ACTIVE); 968 } 969 if (sc->ste_res == NULL) { 970 device_printf(dev, "couldn't map ports/memory\n"); 971 error = ENXIO; 972 goto fail; 973 } 974 975 sc->ste_btag = rman_get_bustag(sc->ste_res); 976 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 977 978 /* Allocate interrupt */ 979 rid = 0; 980 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 981 RF_SHAREABLE | RF_ACTIVE); 982 983 if (sc->ste_irq == NULL) { 984 device_printf(dev, "couldn't map interrupt\n"); 985 error = ENXIO; 986 goto fail; 987 } 988 989 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 990 991 /* Reset the adapter. */ 992 ste_reset(sc); 993 994 /* 995 * Get station address from the EEPROM. 996 */ 997 if (ste_read_eeprom(sc, eaddr, 998 STE_EEADDR_NODE0, 3, 0)) { 999 device_printf(dev, "failed to read station address\n"); 1000 error = ENXIO;; 1001 goto fail; 1002 } 1003 1004 if ((error = ste_dma_alloc(sc)) != 0) 1005 goto fail; 1006 1007 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1008 if (ifp == NULL) { 1009 device_printf(dev, "can not if_alloc()\n"); 1010 error = ENOSPC; 1011 goto fail; 1012 } 1013 1014 /* Do MII setup. */ 1015 if (mii_phy_probe(dev, &sc->ste_miibus, 1016 ste_ifmedia_upd, ste_ifmedia_sts)) { 1017 device_printf(dev, "MII without any phy!\n"); 1018 error = ENXIO; 1019 goto fail; 1020 } 1021 1022 ifp->if_softc = sc; 1023 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1024 ifp->if_mtu = ETHERMTU; 1025 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1026 ifp->if_ioctl = ste_ioctl; 1027 ifp->if_start = ste_start; 1028 ifp->if_init = ste_init; 1029 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1030 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1031 IFQ_SET_READY(&ifp->if_snd); 1032 1033 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1034 1035 /* 1036 * Call MI attach routine. 1037 */ 1038 ether_ifattach(ifp, eaddr); 1039 1040 /* 1041 * Tell the upper layer(s) we support long frames. 1042 */ 1043 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1044 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1045 ifp->if_capenable = ifp->if_capabilities; 1046#ifdef DEVICE_POLLING 1047 ifp->if_capabilities |= IFCAP_POLLING; 1048#endif 1049 1050 /* Hook interrupt last to avoid having to lock softc */ 1051 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1052 NULL, ste_intr, sc, &sc->ste_intrhand); 1053 1054 if (error) { 1055 device_printf(dev, "couldn't set up irq\n"); 1056 ether_ifdetach(ifp); 1057 goto fail; 1058 } 1059 1060fail: 1061 if (error) 1062 ste_detach(dev); 1063 1064 return (error); 1065} 1066 1067/* 1068 * Shutdown hardware and free up resources. This can be called any 1069 * time after the mutex has been initialized. It is called in both 1070 * the error case in attach and the normal detach case so it needs 1071 * to be careful about only freeing resources that have actually been 1072 * allocated. 1073 */ 1074static int 1075ste_detach(device_t dev) 1076{ 1077 struct ste_softc *sc; 1078 struct ifnet *ifp; 1079 1080 sc = device_get_softc(dev); 1081 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1082 ifp = sc->ste_ifp; 1083 1084#ifdef DEVICE_POLLING 1085 if (ifp->if_capenable & IFCAP_POLLING) 1086 ether_poll_deregister(ifp); 1087#endif 1088 1089 /* These should only be active if attach succeeded */ 1090 if (device_is_attached(dev)) { 1091 ether_ifdetach(ifp); 1092 STE_LOCK(sc); 1093 ste_stop(sc); 1094 STE_UNLOCK(sc); 1095 callout_drain(&sc->ste_callout); 1096 } 1097 if (sc->ste_miibus) 1098 device_delete_child(dev, sc->ste_miibus); 1099 bus_generic_detach(dev); 1100 1101 if (sc->ste_intrhand) 1102 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1103 if (sc->ste_irq) 1104 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1105 if (sc->ste_res) 1106 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1107 sc->ste_res); 1108 1109 if (ifp) 1110 if_free(ifp); 1111 1112 ste_dma_free(sc); 1113 mtx_destroy(&sc->ste_mtx); 1114 1115 return (0); 1116} 1117 1118struct ste_dmamap_arg { 1119 bus_addr_t ste_busaddr; 1120}; 1121 1122static void 1123ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1124{ 1125 struct ste_dmamap_arg *ctx; 1126 1127 if (error != 0) 1128 return; 1129 1130 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1131 1132 ctx = (struct ste_dmamap_arg *)arg; 1133 ctx->ste_busaddr = segs[0].ds_addr; 1134} 1135 1136static int 1137ste_dma_alloc(struct ste_softc *sc) 1138{ 1139 struct ste_chain *txc; 1140 struct ste_chain_onefrag *rxc; 1141 struct ste_dmamap_arg ctx; 1142 int error, i; 1143 1144 /* Create parent DMA tag. */ 1145 error = bus_dma_tag_create( 1146 bus_get_dma_tag(sc->ste_dev), /* parent */ 1147 1, 0, /* alignment, boundary */ 1148 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1149 BUS_SPACE_MAXADDR, /* highaddr */ 1150 NULL, NULL, /* filter, filterarg */ 1151 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1152 0, /* nsegments */ 1153 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1154 0, /* flags */ 1155 NULL, NULL, /* lockfunc, lockarg */ 1156 &sc->ste_cdata.ste_parent_tag); 1157 if (error != 0) { 1158 device_printf(sc->ste_dev, 1159 "could not create parent DMA tag.\n"); 1160 goto fail; 1161 } 1162 1163 /* Create DMA tag for Tx descriptor list. */ 1164 error = bus_dma_tag_create( 1165 sc->ste_cdata.ste_parent_tag, /* parent */ 1166 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1167 BUS_SPACE_MAXADDR, /* lowaddr */ 1168 BUS_SPACE_MAXADDR, /* highaddr */ 1169 NULL, NULL, /* filter, filterarg */ 1170 STE_TX_LIST_SZ, /* maxsize */ 1171 1, /* nsegments */ 1172 STE_TX_LIST_SZ, /* maxsegsize */ 1173 0, /* flags */ 1174 NULL, NULL, /* lockfunc, lockarg */ 1175 &sc->ste_cdata.ste_tx_list_tag); 1176 if (error != 0) { 1177 device_printf(sc->ste_dev, 1178 "could not create Tx list DMA tag.\n"); 1179 goto fail; 1180 } 1181 1182 /* Create DMA tag for Rx descriptor list. */ 1183 error = bus_dma_tag_create( 1184 sc->ste_cdata.ste_parent_tag, /* parent */ 1185 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1186 BUS_SPACE_MAXADDR, /* lowaddr */ 1187 BUS_SPACE_MAXADDR, /* highaddr */ 1188 NULL, NULL, /* filter, filterarg */ 1189 STE_RX_LIST_SZ, /* maxsize */ 1190 1, /* nsegments */ 1191 STE_RX_LIST_SZ, /* maxsegsize */ 1192 0, /* flags */ 1193 NULL, NULL, /* lockfunc, lockarg */ 1194 &sc->ste_cdata.ste_rx_list_tag); 1195 if (error != 0) { 1196 device_printf(sc->ste_dev, 1197 "could not create Rx list DMA tag.\n"); 1198 goto fail; 1199 } 1200 1201 /* Create DMA tag for Tx buffers. */ 1202 error = bus_dma_tag_create( 1203 sc->ste_cdata.ste_parent_tag, /* parent */ 1204 1, 0, /* alignment, boundary */ 1205 BUS_SPACE_MAXADDR, /* lowaddr */ 1206 BUS_SPACE_MAXADDR, /* highaddr */ 1207 NULL, NULL, /* filter, filterarg */ 1208 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1209 STE_MAXFRAGS, /* nsegments */ 1210 MCLBYTES, /* maxsegsize */ 1211 0, /* flags */ 1212 NULL, NULL, /* lockfunc, lockarg */ 1213 &sc->ste_cdata.ste_tx_tag); 1214 if (error != 0) { 1215 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1216 goto fail; 1217 } 1218 1219 /* Create DMA tag for Rx buffers. */ 1220 error = bus_dma_tag_create( 1221 sc->ste_cdata.ste_parent_tag, /* parent */ 1222 1, 0, /* alignment, boundary */ 1223 BUS_SPACE_MAXADDR, /* lowaddr */ 1224 BUS_SPACE_MAXADDR, /* highaddr */ 1225 NULL, NULL, /* filter, filterarg */ 1226 MCLBYTES, /* maxsize */ 1227 1, /* nsegments */ 1228 MCLBYTES, /* maxsegsize */ 1229 0, /* flags */ 1230 NULL, NULL, /* lockfunc, lockarg */ 1231 &sc->ste_cdata.ste_rx_tag); 1232 if (error != 0) { 1233 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1234 goto fail; 1235 } 1236 1237 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1238 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1239 (void **)&sc->ste_ldata.ste_tx_list, 1240 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1241 &sc->ste_cdata.ste_tx_list_map); 1242 if (error != 0) { 1243 device_printf(sc->ste_dev, 1244 "could not allocate DMA'able memory for Tx list.\n"); 1245 goto fail; 1246 } 1247 ctx.ste_busaddr = 0; 1248 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1249 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1250 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1251 if (error != 0 || ctx.ste_busaddr == 0) { 1252 device_printf(sc->ste_dev, 1253 "could not load DMA'able memory for Tx list.\n"); 1254 goto fail; 1255 } 1256 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1257 1258 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1259 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1260 (void **)&sc->ste_ldata.ste_rx_list, 1261 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1262 &sc->ste_cdata.ste_rx_list_map); 1263 if (error != 0) { 1264 device_printf(sc->ste_dev, 1265 "could not allocate DMA'able memory for Rx list.\n"); 1266 goto fail; 1267 } 1268 ctx.ste_busaddr = 0; 1269 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1270 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1271 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1272 if (error != 0 || ctx.ste_busaddr == 0) { 1273 device_printf(sc->ste_dev, 1274 "could not load DMA'able memory for Rx list.\n"); 1275 goto fail; 1276 } 1277 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1278 1279 /* Create DMA maps for Tx buffers. */ 1280 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1281 txc = &sc->ste_cdata.ste_tx_chain[i]; 1282 txc->ste_ptr = NULL; 1283 txc->ste_mbuf = NULL; 1284 txc->ste_next = NULL; 1285 txc->ste_phys = 0; 1286 txc->ste_map = NULL; 1287 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1288 &txc->ste_map); 1289 if (error != 0) { 1290 device_printf(sc->ste_dev, 1291 "could not create Tx dmamap.\n"); 1292 goto fail; 1293 } 1294 } 1295 /* Create DMA maps for Rx buffers. */ 1296 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1297 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1298 device_printf(sc->ste_dev, 1299 "could not create spare Rx dmamap.\n"); 1300 goto fail; 1301 } 1302 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1303 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1304 rxc->ste_ptr = NULL; 1305 rxc->ste_mbuf = NULL; 1306 rxc->ste_next = NULL; 1307 rxc->ste_map = NULL; 1308 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1309 &rxc->ste_map); 1310 if (error != 0) { 1311 device_printf(sc->ste_dev, 1312 "could not create Rx dmamap.\n"); 1313 goto fail; 1314 } 1315 } 1316 1317fail: 1318 return (error); 1319} 1320 1321static void 1322ste_dma_free(struct ste_softc *sc) 1323{ 1324 struct ste_chain *txc; 1325 struct ste_chain_onefrag *rxc; 1326 int i; 1327 1328 /* Tx buffers. */ 1329 if (sc->ste_cdata.ste_tx_tag != NULL) { 1330 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1331 txc = &sc->ste_cdata.ste_tx_chain[i]; 1332 if (txc->ste_map != NULL) { 1333 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1334 txc->ste_map); 1335 txc->ste_map = NULL; 1336 } 1337 } 1338 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1339 sc->ste_cdata.ste_tx_tag = NULL; 1340 } 1341 /* Rx buffers. */ 1342 if (sc->ste_cdata.ste_rx_tag != NULL) { 1343 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1344 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1345 if (rxc->ste_map != NULL) { 1346 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1347 rxc->ste_map); 1348 rxc->ste_map = NULL; 1349 } 1350 } 1351 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1352 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1353 sc->ste_cdata.ste_rx_sparemap); 1354 sc->ste_cdata.ste_rx_sparemap = NULL; 1355 } 1356 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1357 sc->ste_cdata.ste_rx_tag = NULL; 1358 } 1359 /* Tx descriptor list. */ 1360 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1361 if (sc->ste_cdata.ste_tx_list_map != NULL) 1362 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1363 sc->ste_cdata.ste_tx_list_map); 1364 if (sc->ste_cdata.ste_tx_list_map != NULL && 1365 sc->ste_ldata.ste_tx_list != NULL) 1366 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1367 sc->ste_ldata.ste_tx_list, 1368 sc->ste_cdata.ste_tx_list_map); 1369 sc->ste_ldata.ste_tx_list = NULL; 1370 sc->ste_cdata.ste_tx_list_map = NULL; 1371 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1372 sc->ste_cdata.ste_tx_list_tag = NULL; 1373 } 1374 /* Rx descriptor list. */ 1375 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1376 if (sc->ste_cdata.ste_rx_list_map != NULL) 1377 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1378 sc->ste_cdata.ste_rx_list_map); 1379 if (sc->ste_cdata.ste_rx_list_map != NULL && 1380 sc->ste_ldata.ste_rx_list != NULL) 1381 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1382 sc->ste_ldata.ste_rx_list, 1383 sc->ste_cdata.ste_rx_list_map); 1384 sc->ste_ldata.ste_rx_list = NULL; 1385 sc->ste_cdata.ste_rx_list_map = NULL; 1386 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1387 sc->ste_cdata.ste_rx_list_tag = NULL; 1388 } 1389 if (sc->ste_cdata.ste_parent_tag != NULL) { 1390 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1391 sc->ste_cdata.ste_parent_tag = NULL; 1392 } 1393} 1394 1395static int 1396ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1397{ 1398 struct mbuf *m; 1399 bus_dma_segment_t segs[1]; 1400 bus_dmamap_t map; 1401 int error, nsegs; 1402 1403 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1404 if (m == NULL) 1405 return (ENOBUFS); 1406 m->m_len = m->m_pkthdr.len = MCLBYTES; 1407 m_adj(m, ETHER_ALIGN); 1408 1409 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1410 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1411 m_freem(m); 1412 return (error); 1413 } 1414 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1415 1416 if (rxc->ste_mbuf != NULL) { 1417 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1418 BUS_DMASYNC_POSTREAD); 1419 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1420 } 1421 map = rxc->ste_map; 1422 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1423 sc->ste_cdata.ste_rx_sparemap = map; 1424 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1425 BUS_DMASYNC_PREREAD); 1426 rxc->ste_mbuf = m; 1427 rxc->ste_ptr->ste_status = 0; 1428 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1429 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1430 STE_FRAG_LAST); 1431 return (0); 1432} 1433 1434static int 1435ste_init_rx_list(struct ste_softc *sc) 1436{ 1437 struct ste_chain_data *cd; 1438 struct ste_list_data *ld; 1439 int error, i; 1440 1441 cd = &sc->ste_cdata; 1442 ld = &sc->ste_ldata; 1443 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1444 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1445 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1446 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1447 if (error != 0) 1448 return (error); 1449 if (i == (STE_RX_LIST_CNT - 1)) { 1450 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1451 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1452 (sizeof(struct ste_desc_onefrag) * 0); 1453 } else { 1454 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1455 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1456 (sizeof(struct ste_desc_onefrag) * (i + 1)); 1457 } 1458 } 1459 1460 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1461 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1462 sc->ste_cdata.ste_rx_list_map, 1463 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1464 1465 return (0); 1466} 1467 1468static void 1469ste_init_tx_list(struct ste_softc *sc) 1470{ 1471 struct ste_chain_data *cd; 1472 struct ste_list_data *ld; 1473 int i; 1474 1475 cd = &sc->ste_cdata; 1476 ld = &sc->ste_ldata; 1477 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1478 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1479 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1480 cd->ste_tx_chain[i].ste_mbuf = NULL; 1481 if (i == (STE_TX_LIST_CNT - 1)) { 1482 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1483 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1484 ld->ste_tx_list_paddr + 1485 (sizeof(struct ste_desc) * 0))); 1486 } else { 1487 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1488 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1489 ld->ste_tx_list_paddr + 1490 (sizeof(struct ste_desc) * (i + 1)))); 1491 } 1492 } 1493 1494 cd->ste_last_tx = NULL; 1495 cd->ste_tx_prod = 0; 1496 cd->ste_tx_cons = 0; 1497 cd->ste_tx_cnt = 0; 1498 1499 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1500 sc->ste_cdata.ste_tx_list_map, 1501 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1502} 1503 1504static void 1505ste_init(void *xsc) 1506{ 1507 struct ste_softc *sc; 1508 1509 sc = xsc; 1510 STE_LOCK(sc); 1511 ste_init_locked(sc); 1512 STE_UNLOCK(sc); 1513} 1514 1515static void 1516ste_init_locked(struct ste_softc *sc) 1517{ 1518 struct ifnet *ifp; 1519 int i; 1520 1521 STE_LOCK_ASSERT(sc); 1522 ifp = sc->ste_ifp; 1523 1524 ste_stop(sc); 1525 /* Reset the chip to a known state. */ 1526 ste_reset(sc); 1527 1528 /* Init our MAC address */ 1529 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1530 CSR_WRITE_2(sc, STE_PAR0 + i, 1531 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1532 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1533 } 1534 1535 /* Init RX list */ 1536 if (ste_init_rx_list(sc) != 0) { 1537 device_printf(sc->ste_dev, 1538 "initialization failed: no memory for RX buffers\n"); 1539 ste_stop(sc); 1540 return; 1541 } 1542 1543 /* Set RX polling interval */ 1544 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1545 1546 /* Init TX descriptors */ 1547 ste_init_tx_list(sc); 1548 1549 /* Set the TX freethresh value */ 1550 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1551 1552 /* Set the TX start threshold for best performance. */ 1553 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1554 1555 /* Set the TX reclaim threshold. */ 1556 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1557 1558 /* Set up the RX filter. */ 1559 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1560 1561 /* If we want promiscuous mode, set the allframes bit. */ 1562 if (ifp->if_flags & IFF_PROMISC) { 1563 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1564 } else { 1565 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1566 } 1567 1568 /* Set capture broadcast bit to accept broadcast frames. */ 1569 if (ifp->if_flags & IFF_BROADCAST) { 1570 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1571 } else { 1572 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1573 } 1574 1575 ste_setmulti(sc); 1576 1577 /* Load the address of the RX list. */ 1578 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1579 ste_wait(sc); 1580 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1581 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1582 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1583 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1584 1585 /* Set TX polling interval(defer until we TX first packet). */ 1586 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1587 1588 /* Load address of the TX list */ 1589 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1590 ste_wait(sc); 1591 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1592 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1593 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1594 ste_wait(sc); 1595 1596 /* Enable receiver and transmitter */ 1597 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1598 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1599 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1600 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1601 1602 /* Enable stats counters. */ 1603 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1604 1605 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1606#ifdef DEVICE_POLLING 1607 /* Disable interrupts if we are polling. */ 1608 if (ifp->if_capenable & IFCAP_POLLING) 1609 CSR_WRITE_2(sc, STE_IMR, 0); 1610 else 1611#endif 1612 /* Enable interrupts. */ 1613 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1614 1615 /* Accept VLAN length packets */ 1616 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1617 1618 ste_ifmedia_upd_locked(ifp); 1619 1620 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1621 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1622 1623 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1624} 1625 1626static void 1627ste_stop(struct ste_softc *sc) 1628{ 1629 struct ifnet *ifp; 1630 struct ste_chain_onefrag *cur_rx; 1631 struct ste_chain *cur_tx; 1632 uint32_t val; 1633 int i; 1634 1635 STE_LOCK_ASSERT(sc); 1636 ifp = sc->ste_ifp; 1637 1638 callout_stop(&sc->ste_callout); 1639 sc->ste_timer = 0; 1640 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1641 1642 CSR_WRITE_2(sc, STE_IMR, 0); 1643 /* Stop pending DMA. */ 1644 val = CSR_READ_4(sc, STE_DMACTL); 1645 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1646 CSR_WRITE_4(sc, STE_DMACTL, val); 1647 ste_wait(sc); 1648 /* Disable auto-polling. */ 1649 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1650 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1651 /* Nullify DMA address to stop any further DMA. */ 1652 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1653 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1654 /* Stop TX/RX MAC. */ 1655 val = CSR_READ_2(sc, STE_MACCTL1); 1656 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1657 STE_MACCTL1_STATS_DISABLE; 1658 CSR_WRITE_2(sc, STE_MACCTL1, val); 1659 for (i = 0; i < STE_TIMEOUT; i++) { 1660 DELAY(10); 1661 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1662 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1663 break; 1664 } 1665 if (i == STE_TIMEOUT) 1666 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1667 /* Acknowledge any pending interrupts. */ 1668 CSR_READ_2(sc, STE_ISR_ACK); 1669 ste_stats_update(sc); 1670 1671 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1672 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1673 if (cur_rx->ste_mbuf != NULL) { 1674 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1675 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1676 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1677 cur_rx->ste_map); 1678 m_freem(cur_rx->ste_mbuf); 1679 cur_rx->ste_mbuf = NULL; 1680 } 1681 } 1682 1683 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1684 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1685 if (cur_tx->ste_mbuf != NULL) { 1686 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1687 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1688 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1689 cur_tx->ste_map); 1690 m_freem(cur_tx->ste_mbuf); 1691 cur_tx->ste_mbuf = NULL; 1692 } 1693 } 1694} 1695 1696static void 1697ste_reset(struct ste_softc *sc) 1698{ 1699 int i; 1700 1701 STE_SETBIT4(sc, STE_ASICCTL, 1702 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1703 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1704 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1705 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1706 STE_ASICCTL_EXTRESET_RESET); 1707 1708 DELAY(100000); 1709 1710 for (i = 0; i < STE_TIMEOUT; i++) { 1711 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1712 break; 1713 } 1714 1715 if (i == STE_TIMEOUT) 1716 device_printf(sc->ste_dev, "global reset never completed\n"); 1717} 1718 1719static int 1720ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1721{ 1722 struct ste_softc *sc; 1723 struct ifreq *ifr; 1724 struct mii_data *mii; 1725 int error = 0; 1726 1727 sc = ifp->if_softc; 1728 ifr = (struct ifreq *)data; 1729 1730 switch (command) { 1731 case SIOCSIFFLAGS: 1732 STE_LOCK(sc); 1733 if (ifp->if_flags & IFF_UP) { 1734 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1735 ifp->if_flags & IFF_PROMISC && 1736 !(sc->ste_if_flags & IFF_PROMISC)) { 1737 STE_SETBIT1(sc, STE_RX_MODE, 1738 STE_RXMODE_PROMISC); 1739 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1740 !(ifp->if_flags & IFF_PROMISC) && 1741 sc->ste_if_flags & IFF_PROMISC) { 1742 STE_CLRBIT1(sc, STE_RX_MODE, 1743 STE_RXMODE_PROMISC); 1744 } 1745 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1746 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1747 ste_setmulti(sc); 1748 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1749 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1750 ste_init_locked(sc); 1751 } 1752 } else { 1753 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1754 ste_stop(sc); 1755 } 1756 sc->ste_if_flags = ifp->if_flags; 1757 STE_UNLOCK(sc); 1758 error = 0; 1759 break; 1760 case SIOCADDMULTI: 1761 case SIOCDELMULTI: 1762 STE_LOCK(sc); 1763 ste_setmulti(sc); 1764 STE_UNLOCK(sc); 1765 error = 0; 1766 break; 1767 case SIOCGIFMEDIA: 1768 case SIOCSIFMEDIA: 1769 mii = device_get_softc(sc->ste_miibus); 1770 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1771 break; 1772 case SIOCSIFCAP: 1773#ifdef DEVICE_POLLING 1774 if (ifr->ifr_reqcap & IFCAP_POLLING && 1775 !(ifp->if_capenable & IFCAP_POLLING)) { 1776 error = ether_poll_register(ste_poll, ifp); 1777 if (error) 1778 return (error); 1779 STE_LOCK(sc); 1780 /* Disable interrupts */ 1781 CSR_WRITE_2(sc, STE_IMR, 0); 1782 ifp->if_capenable |= IFCAP_POLLING; 1783 STE_UNLOCK(sc); 1784 return (error); 1785 1786 } 1787 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1788 ifp->if_capenable & IFCAP_POLLING) { 1789 error = ether_poll_deregister(ifp); 1790 /* Enable interrupts. */ 1791 STE_LOCK(sc); 1792 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1793 ifp->if_capenable &= ~IFCAP_POLLING; 1794 STE_UNLOCK(sc); 1795 return (error); 1796 } 1797#endif /* DEVICE_POLLING */ 1798 break; 1799 default: 1800 error = ether_ioctl(ifp, command, data); 1801 break; 1802 } 1803 1804 return (error); 1805} 1806 1807static int 1808ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1809{ 1810 struct ste_frag *frag; 1811 struct mbuf *m; 1812 struct ste_desc *desc; 1813 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1814 int error, i, nsegs; 1815 1816 STE_LOCK_ASSERT(sc); 1817 M_ASSERTPKTHDR((*m_head)); 1818 1819 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1820 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1821 if (error == EFBIG) { 1822 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS); 1823 if (m == NULL) { 1824 m_freem(*m_head); 1825 *m_head = NULL; 1826 return (ENOMEM); 1827 } 1828 *m_head = m; 1829 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1830 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1831 if (error != 0) { 1832 m_freem(*m_head); 1833 *m_head = NULL; 1834 return (error); 1835 } 1836 } else if (error != 0) 1837 return (error); 1838 if (nsegs == 0) { 1839 m_freem(*m_head); 1840 *m_head = NULL; 1841 return (EIO); 1842 } 1843 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1844 BUS_DMASYNC_PREWRITE); 1845 1846 desc = txc->ste_ptr; 1847 for (i = 0; i < nsegs; i++) { 1848 frag = &desc->ste_frags[i]; 1849 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1850 frag->ste_len = htole32(txsegs[i].ds_len); 1851 } 1852 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1853 /* 1854 * Because we use Tx polling we can't chain multiple 1855 * Tx descriptors here. Otherwise we race with controller. 1856 */ 1857 desc->ste_next = 0; 1858 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | STE_TXCTL_DMAINTR); 1859 txc->ste_mbuf = *m_head; 1860 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1861 sc->ste_cdata.ste_tx_cnt++; 1862 1863 return (0); 1864} 1865 1866static void 1867ste_start(struct ifnet *ifp) 1868{ 1869 struct ste_softc *sc; 1870 1871 sc = ifp->if_softc; 1872 STE_LOCK(sc); 1873 ste_start_locked(ifp); 1874 STE_UNLOCK(sc); 1875} 1876 1877static void 1878ste_start_locked(struct ifnet *ifp) 1879{ 1880 struct ste_softc *sc; 1881 struct ste_chain *cur_tx; 1882 struct mbuf *m_head = NULL; 1883 int enq; 1884 1885 sc = ifp->if_softc; 1886 STE_LOCK_ASSERT(sc); 1887 1888 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1889 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 1890 return; 1891 1892 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 1893 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1894 /* 1895 * Controller may have cached copy of the last used 1896 * next ptr so we have to reserve one TFD to avoid 1897 * TFD overruns. 1898 */ 1899 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1900 break; 1901 } 1902 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1903 if (m_head == NULL) 1904 break; 1905 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1906 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1907 if (m_head == NULL) 1908 break; 1909 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1910 break; 1911 } 1912 if (sc->ste_cdata.ste_last_tx == NULL) { 1913 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1914 sc->ste_cdata.ste_tx_list_map, 1915 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1916 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1917 ste_wait(sc); 1918 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1919 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1920 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1921 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1922 ste_wait(sc); 1923 } else { 1924 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1925 sc->ste_cdata.ste_last_tx->ste_phys; 1926 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1927 sc->ste_cdata.ste_tx_list_map, 1928 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1929 } 1930 sc->ste_cdata.ste_last_tx = cur_tx; 1931 1932 enq++; 1933 /* 1934 * If there's a BPF listener, bounce a copy of this frame 1935 * to him. 1936 */ 1937 BPF_MTAP(ifp, m_head); 1938 } 1939 1940 if (enq > 0) 1941 sc->ste_timer = STE_TX_TIMEOUT; 1942} 1943 1944static void 1945ste_watchdog(struct ste_softc *sc) 1946{ 1947 struct ifnet *ifp; 1948 1949 ifp = sc->ste_ifp; 1950 STE_LOCK_ASSERT(sc); 1951 1952 if (sc->ste_timer == 0 || --sc->ste_timer) 1953 return; 1954 1955 ifp->if_oerrors++; 1956 if_printf(ifp, "watchdog timeout\n"); 1957 1958 ste_txeoc(sc); 1959 ste_txeof(sc); 1960 ste_rxeof(sc, -1); 1961 ste_init_locked(sc); 1962 1963 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1964 ste_start_locked(ifp); 1965} 1966 1967static int 1968ste_shutdown(device_t dev) 1969{ 1970 struct ste_softc *sc; 1971 1972 sc = device_get_softc(dev); 1973 1974 STE_LOCK(sc); 1975 ste_stop(sc); 1976 STE_UNLOCK(sc); 1977 1978 return (0); 1979} 1980