if_ste.c revision 200854
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 200854 2009-12-22 19:00:18Z yongari $"); 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53 54#include <net/bpf.h> 55#include <net/if.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61#include <net/if_vlan_var.h> 62 63#include <machine/bus.h> 64#include <machine/resource.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <dev/ste/if_stereg.h> 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77#define STE_USEIOSPACE 78 79MODULE_DEPEND(ste, pci, 1, 1, 1); 80MODULE_DEPEND(ste, ether, 1, 1, 1); 81MODULE_DEPEND(ste, miibus, 1, 1, 1); 82 83/* 84 * Various supported device vendors/types and their names. 85 */ 86static struct ste_type ste_devs[] = { 87 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 88 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 89 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 90 { 0, 0, NULL } 91}; 92 93static int ste_attach(device_t); 94static int ste_detach(device_t); 95static int ste_probe(device_t); 96static int ste_shutdown(device_t); 97 98static int ste_dma_alloc(struct ste_softc *); 99static void ste_dma_free(struct ste_softc *); 100static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 101static int ste_eeprom_wait(struct ste_softc *); 102static int ste_encap(struct ste_softc *, struct mbuf **, 103 struct ste_chain *); 104static int ste_ifmedia_upd(struct ifnet *); 105static void ste_ifmedia_upd_locked(struct ifnet *); 106static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 107static void ste_init(void *); 108static void ste_init_locked(struct ste_softc *); 109static int ste_init_rx_list(struct ste_softc *); 110static void ste_init_tx_list(struct ste_softc *); 111static void ste_intr(void *); 112static int ste_ioctl(struct ifnet *, u_long, caddr_t); 113static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 114static void ste_mii_send(struct ste_softc *, uint32_t, int); 115static void ste_mii_sync(struct ste_softc *); 116static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 117static int ste_miibus_readreg(device_t, int, int); 118static void ste_miibus_statchg(device_t); 119static int ste_miibus_writereg(device_t, int, int, int); 120static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 121static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 122static void ste_reset(struct ste_softc *); 123static int ste_rxeof(struct ste_softc *, int); 124static void ste_setmulti(struct ste_softc *); 125static void ste_start(struct ifnet *); 126static void ste_start_locked(struct ifnet *); 127static void ste_stats_update(void *); 128static void ste_stop(struct ste_softc *); 129static void ste_txeoc(struct ste_softc *); 130static void ste_txeof(struct ste_softc *); 131static void ste_wait(struct ste_softc *); 132static void ste_watchdog(struct ste_softc *); 133 134#ifdef STE_USEIOSPACE 135#define STE_RES SYS_RES_IOPORT 136#define STE_RID STE_PCI_LOIO 137#else 138#define STE_RES SYS_RES_MEMORY 139#define STE_RID STE_PCI_LOMEM 140#endif 141 142static device_method_t ste_methods[] = { 143 /* Device interface */ 144 DEVMETHOD(device_probe, ste_probe), 145 DEVMETHOD(device_attach, ste_attach), 146 DEVMETHOD(device_detach, ste_detach), 147 DEVMETHOD(device_shutdown, ste_shutdown), 148 149 /* bus interface */ 150 DEVMETHOD(bus_print_child, bus_generic_print_child), 151 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 152 153 /* MII interface */ 154 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 155 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 156 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 157 158 { 0, 0 } 159}; 160 161static driver_t ste_driver = { 162 "ste", 163 ste_methods, 164 sizeof(struct ste_softc) 165}; 166 167static devclass_t ste_devclass; 168 169DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 170DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 171 172#define STE_SETBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 174 175#define STE_CLRBIT4(sc, reg, x) \ 176 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 177 178#define STE_SETBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 180 181#define STE_CLRBIT2(sc, reg, x) \ 182 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 183 184#define STE_SETBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 186 187#define STE_CLRBIT1(sc, reg, x) \ 188 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 189 190 191#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 192#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 193 194/* 195 * Sync the PHYs by setting data bit and strobing the clock 32 times. 196 */ 197static void 198ste_mii_sync(struct ste_softc *sc) 199{ 200 int i; 201 202 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 203 204 for (i = 0; i < 32; i++) { 205 MII_SET(STE_PHYCTL_MCLK); 206 DELAY(1); 207 MII_CLR(STE_PHYCTL_MCLK); 208 DELAY(1); 209 } 210} 211 212/* 213 * Clock a series of bits through the MII. 214 */ 215static void 216ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt) 217{ 218 int i; 219 220 MII_CLR(STE_PHYCTL_MCLK); 221 222 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 223 if (bits & i) { 224 MII_SET(STE_PHYCTL_MDATA); 225 } else { 226 MII_CLR(STE_PHYCTL_MDATA); 227 } 228 DELAY(1); 229 MII_CLR(STE_PHYCTL_MCLK); 230 DELAY(1); 231 MII_SET(STE_PHYCTL_MCLK); 232 } 233} 234 235/* 236 * Read an PHY register through the MII. 237 */ 238static int 239ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 240{ 241 int i, ack; 242 243 /* 244 * Set up frame for RX. 245 */ 246 frame->mii_stdelim = STE_MII_STARTDELIM; 247 frame->mii_opcode = STE_MII_READOP; 248 frame->mii_turnaround = 0; 249 frame->mii_data = 0; 250 251 CSR_WRITE_2(sc, STE_PHYCTL, 0); 252 /* 253 * Turn on data xmit. 254 */ 255 MII_SET(STE_PHYCTL_MDIR); 256 257 ste_mii_sync(sc); 258 259 /* 260 * Send command/address info. 261 */ 262 ste_mii_send(sc, frame->mii_stdelim, 2); 263 ste_mii_send(sc, frame->mii_opcode, 2); 264 ste_mii_send(sc, frame->mii_phyaddr, 5); 265 ste_mii_send(sc, frame->mii_regaddr, 5); 266 267 /* Turn off xmit. */ 268 MII_CLR(STE_PHYCTL_MDIR); 269 270 /* Idle bit */ 271 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 272 DELAY(1); 273 MII_SET(STE_PHYCTL_MCLK); 274 DELAY(1); 275 276 /* Check for ack */ 277 MII_CLR(STE_PHYCTL_MCLK); 278 DELAY(1); 279 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 280 MII_SET(STE_PHYCTL_MCLK); 281 DELAY(1); 282 283 /* 284 * Now try reading data bits. If the ack failed, we still 285 * need to clock through 16 cycles to keep the PHY(s) in sync. 286 */ 287 if (ack) { 288 for (i = 0; i < 16; i++) { 289 MII_CLR(STE_PHYCTL_MCLK); 290 DELAY(1); 291 MII_SET(STE_PHYCTL_MCLK); 292 DELAY(1); 293 } 294 goto fail; 295 } 296 297 for (i = 0x8000; i; i >>= 1) { 298 MII_CLR(STE_PHYCTL_MCLK); 299 DELAY(1); 300 if (!ack) { 301 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 302 frame->mii_data |= i; 303 DELAY(1); 304 } 305 MII_SET(STE_PHYCTL_MCLK); 306 DELAY(1); 307 } 308 309fail: 310 311 MII_CLR(STE_PHYCTL_MCLK); 312 DELAY(1); 313 MII_SET(STE_PHYCTL_MCLK); 314 DELAY(1); 315 316 if (ack) 317 return (1); 318 return (0); 319} 320 321/* 322 * Write to a PHY register through the MII. 323 */ 324static int 325ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 326{ 327 328 /* 329 * Set up frame for TX. 330 */ 331 332 frame->mii_stdelim = STE_MII_STARTDELIM; 333 frame->mii_opcode = STE_MII_WRITEOP; 334 frame->mii_turnaround = STE_MII_TURNAROUND; 335 336 /* 337 * Turn on data output. 338 */ 339 MII_SET(STE_PHYCTL_MDIR); 340 341 ste_mii_sync(sc); 342 343 ste_mii_send(sc, frame->mii_stdelim, 2); 344 ste_mii_send(sc, frame->mii_opcode, 2); 345 ste_mii_send(sc, frame->mii_phyaddr, 5); 346 ste_mii_send(sc, frame->mii_regaddr, 5); 347 ste_mii_send(sc, frame->mii_turnaround, 2); 348 ste_mii_send(sc, frame->mii_data, 16); 349 350 /* Idle bit. */ 351 MII_SET(STE_PHYCTL_MCLK); 352 DELAY(1); 353 MII_CLR(STE_PHYCTL_MCLK); 354 DELAY(1); 355 356 /* 357 * Turn off xmit. 358 */ 359 MII_CLR(STE_PHYCTL_MDIR); 360 361 return (0); 362} 363 364static int 365ste_miibus_readreg(device_t dev, int phy, int reg) 366{ 367 struct ste_softc *sc; 368 struct ste_mii_frame frame; 369 370 sc = device_get_softc(dev); 371 372 if ( sc->ste_one_phy && phy != 0 ) 373 return (0); 374 375 bzero((char *)&frame, sizeof(frame)); 376 377 frame.mii_phyaddr = phy; 378 frame.mii_regaddr = reg; 379 ste_mii_readreg(sc, &frame); 380 381 return (frame.mii_data); 382} 383 384static int 385ste_miibus_writereg(device_t dev, int phy, int reg, int data) 386{ 387 struct ste_softc *sc; 388 struct ste_mii_frame frame; 389 390 sc = device_get_softc(dev); 391 bzero((char *)&frame, sizeof(frame)); 392 393 frame.mii_phyaddr = phy; 394 frame.mii_regaddr = reg; 395 frame.mii_data = data; 396 397 ste_mii_writereg(sc, &frame); 398 399 return (0); 400} 401 402static void 403ste_miibus_statchg(device_t dev) 404{ 405 struct ste_softc *sc; 406 struct mii_data *mii; 407 408 sc = device_get_softc(dev); 409 410 mii = device_get_softc(sc->ste_miibus); 411 412 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 413 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 414 } else { 415 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 416 } 417} 418 419static int 420ste_ifmedia_upd(struct ifnet *ifp) 421{ 422 struct ste_softc *sc; 423 424 sc = ifp->if_softc; 425 STE_LOCK(sc); 426 ste_ifmedia_upd_locked(ifp); 427 STE_UNLOCK(sc); 428 429 return (0); 430} 431 432static void 433ste_ifmedia_upd_locked(struct ifnet *ifp) 434{ 435 struct ste_softc *sc; 436 struct mii_data *mii; 437 438 sc = ifp->if_softc; 439 STE_LOCK_ASSERT(sc); 440 mii = device_get_softc(sc->ste_miibus); 441 sc->ste_link = 0; 442 if (mii->mii_instance) { 443 struct mii_softc *miisc; 444 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 445 mii_phy_reset(miisc); 446 } 447 mii_mediachg(mii); 448} 449 450static void 451ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 452{ 453 struct ste_softc *sc; 454 struct mii_data *mii; 455 456 sc = ifp->if_softc; 457 mii = device_get_softc(sc->ste_miibus); 458 459 STE_LOCK(sc); 460 mii_pollstat(mii); 461 ifmr->ifm_active = mii->mii_media_active; 462 ifmr->ifm_status = mii->mii_media_status; 463 STE_UNLOCK(sc); 464} 465 466static void 467ste_wait(struct ste_softc *sc) 468{ 469 int i; 470 471 for (i = 0; i < STE_TIMEOUT; i++) { 472 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 473 break; 474 DELAY(1); 475 } 476 477 if (i == STE_TIMEOUT) 478 device_printf(sc->ste_dev, "command never completed!\n"); 479} 480 481/* 482 * The EEPROM is slow: give it time to come ready after issuing 483 * it a command. 484 */ 485static int 486ste_eeprom_wait(struct ste_softc *sc) 487{ 488 int i; 489 490 DELAY(1000); 491 492 for (i = 0; i < 100; i++) { 493 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 494 DELAY(1000); 495 else 496 break; 497 } 498 499 if (i == 100) { 500 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 501 return (1); 502 } 503 504 return (0); 505} 506 507/* 508 * Read a sequence of words from the EEPROM. Note that ethernet address 509 * data is stored in the EEPROM in network byte order. 510 */ 511static int 512ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 513{ 514 uint16_t word, *ptr; 515 int err = 0, i; 516 517 if (ste_eeprom_wait(sc)) 518 return (1); 519 520 for (i = 0; i < cnt; i++) { 521 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 522 err = ste_eeprom_wait(sc); 523 if (err) 524 break; 525 word = CSR_READ_2(sc, STE_EEPROM_DATA); 526 ptr = (uint16_t *)(dest + (i * 2)); 527 if (swap) 528 *ptr = ntohs(word); 529 else 530 *ptr = word; 531 } 532 533 return (err ? 1 : 0); 534} 535 536static void 537ste_setmulti(struct ste_softc *sc) 538{ 539 struct ifnet *ifp; 540 struct ifmultiaddr *ifma; 541 uint32_t hashes[2] = { 0, 0 }; 542 int h; 543 544 ifp = sc->ste_ifp; 545 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 546 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 547 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 548 return; 549 } 550 551 /* first, zot all the existing hash bits */ 552 CSR_WRITE_2(sc, STE_MAR0, 0); 553 CSR_WRITE_2(sc, STE_MAR1, 0); 554 CSR_WRITE_2(sc, STE_MAR2, 0); 555 CSR_WRITE_2(sc, STE_MAR3, 0); 556 557 /* now program new ones */ 558 if_maddr_rlock(ifp); 559 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 560 if (ifma->ifma_addr->sa_family != AF_LINK) 561 continue; 562 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 563 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 564 if (h < 32) 565 hashes[0] |= (1 << h); 566 else 567 hashes[1] |= (1 << (h - 32)); 568 } 569 if_maddr_runlock(ifp); 570 571 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 572 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 573 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 574 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 575 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 576 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 577} 578 579#ifdef DEVICE_POLLING 580static poll_handler_t ste_poll, ste_poll_locked; 581 582static int 583ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 584{ 585 struct ste_softc *sc = ifp->if_softc; 586 int rx_npkts = 0; 587 588 STE_LOCK(sc); 589 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 590 rx_npkts = ste_poll_locked(ifp, cmd, count); 591 STE_UNLOCK(sc); 592 return (rx_npkts); 593} 594 595static int 596ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 597{ 598 struct ste_softc *sc = ifp->if_softc; 599 int rx_npkts; 600 601 STE_LOCK_ASSERT(sc); 602 603 rx_npkts = ste_rxeof(sc, count); 604 ste_txeof(sc); 605 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 606 ste_start_locked(ifp); 607 608 if (cmd == POLL_AND_CHECK_STATUS) { 609 uint16_t status; 610 611 status = CSR_READ_2(sc, STE_ISR_ACK); 612 613 if (status & STE_ISR_TX_DONE) 614 ste_txeoc(sc); 615 616 if (status & STE_ISR_STATS_OFLOW) { 617 callout_stop(&sc->ste_stat_callout); 618 ste_stats_update(sc); 619 } 620 621 if (status & STE_ISR_LINKEVENT) 622 mii_pollstat(device_get_softc(sc->ste_miibus)); 623 624 if (status & STE_ISR_HOSTERR) { 625 ste_reset(sc); 626 ste_init_locked(sc); 627 } 628 } 629 return (rx_npkts); 630} 631#endif /* DEVICE_POLLING */ 632 633static void 634ste_intr(void *xsc) 635{ 636 struct ste_softc *sc; 637 struct ifnet *ifp; 638 uint16_t status; 639 640 sc = xsc; 641 STE_LOCK(sc); 642 ifp = sc->ste_ifp; 643 644#ifdef DEVICE_POLLING 645 if (ifp->if_capenable & IFCAP_POLLING) { 646 STE_UNLOCK(sc); 647 return; 648 } 649#endif 650 651 /* See if this is really our interrupt. */ 652 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 653 STE_UNLOCK(sc); 654 return; 655 } 656 657 for (;;) { 658 status = CSR_READ_2(sc, STE_ISR_ACK); 659 660 if (!(status & STE_INTRS)) 661 break; 662 663 if (status & STE_ISR_RX_DMADONE) 664 ste_rxeof(sc, -1); 665 666 if (status & STE_ISR_TX_DMADONE) 667 ste_txeof(sc); 668 669 if (status & STE_ISR_TX_DONE) 670 ste_txeoc(sc); 671 672 if (status & STE_ISR_STATS_OFLOW) { 673 callout_stop(&sc->ste_stat_callout); 674 ste_stats_update(sc); 675 } 676 677 if (status & STE_ISR_LINKEVENT) 678 mii_pollstat(device_get_softc(sc->ste_miibus)); 679 680 681 if (status & STE_ISR_HOSTERR) { 682 ste_reset(sc); 683 ste_init_locked(sc); 684 } 685 } 686 687 /* Re-enable interrupts */ 688 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 689 690 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 691 ste_start_locked(ifp); 692 693 STE_UNLOCK(sc); 694} 695 696/* 697 * A frame has been uploaded: pass the resulting mbuf chain up to 698 * the higher level protocols. 699 */ 700static int 701ste_rxeof(struct ste_softc *sc, int count) 702{ 703 struct mbuf *m; 704 struct ifnet *ifp; 705 struct ste_chain_onefrag *cur_rx; 706 uint32_t rxstat; 707 int total_len, rx_npkts; 708 709 ifp = sc->ste_ifp; 710 711 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 712 sc->ste_cdata.ste_rx_list_map, 713 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 714 715 cur_rx = sc->ste_cdata.ste_rx_head; 716 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 717 cur_rx = cur_rx->ste_next) { 718 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 719 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 720 break; 721#ifdef DEVICE_POLLING 722 if (ifp->if_capenable & IFCAP_POLLING) { 723 if (count == 0) 724 break; 725 count--; 726 } 727#endif 728 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 729 break; 730 /* 731 * If an error occurs, update stats, clear the 732 * status word and leave the mbuf cluster in place: 733 * it should simply get re-used next time this descriptor 734 * comes up in the ring. 735 */ 736 if (rxstat & STE_RXSTAT_FRAME_ERR) { 737 ifp->if_ierrors++; 738 cur_rx->ste_ptr->ste_status = 0; 739 continue; 740 } 741 742 /* No errors; receive the packet. */ 743 m = cur_rx->ste_mbuf; 744 total_len = STE_RX_BYTES(rxstat); 745 746 /* 747 * Try to conjure up a new mbuf cluster. If that 748 * fails, it means we have an out of memory condition and 749 * should leave the buffer in place and continue. This will 750 * result in a lost packet, but there's little else we 751 * can do in this situation. 752 */ 753 if (ste_newbuf(sc, cur_rx) != 0) { 754 ifp->if_ierrors++; 755 cur_rx->ste_ptr->ste_status = 0; 756 continue; 757 } 758 759 m->m_pkthdr.rcvif = ifp; 760 m->m_pkthdr.len = m->m_len = total_len; 761 762 ifp->if_ipackets++; 763 STE_UNLOCK(sc); 764 (*ifp->if_input)(ifp, m); 765 STE_LOCK(sc); 766 } 767 768 if (rx_npkts > 0) { 769 sc->ste_cdata.ste_rx_head = cur_rx; 770 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 771 sc->ste_cdata.ste_rx_list_map, 772 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 773 } 774 775 return (rx_npkts); 776} 777 778static void 779ste_txeoc(struct ste_softc *sc) 780{ 781 struct ifnet *ifp; 782 uint8_t txstat; 783 784 ifp = sc->ste_ifp; 785 786 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 787 STE_TXSTATUS_TXDONE) { 788 if (txstat & STE_TXSTATUS_UNDERRUN || 789 txstat & STE_TXSTATUS_EXCESSCOLLS || 790 txstat & STE_TXSTATUS_RECLAIMERR) { 791 ifp->if_oerrors++; 792 device_printf(sc->ste_dev, 793 "transmission error: %x\n", txstat); 794 795 ste_reset(sc); 796 ste_init_locked(sc); 797 798 if (txstat & STE_TXSTATUS_UNDERRUN && 799 sc->ste_tx_thresh < STE_PACKET_SIZE) { 800 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 801 device_printf(sc->ste_dev, 802 "tx underrun, increasing tx" 803 " start threshold to %d bytes\n", 804 sc->ste_tx_thresh); 805 } 806 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 807 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 808 (STE_PACKET_SIZE >> 4)); 809 } 810 ste_init_locked(sc); 811 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 812 } 813} 814 815static void 816ste_txeof(struct ste_softc *sc) 817{ 818 struct ifnet *ifp; 819 struct ste_chain *cur_tx; 820 uint32_t txstat; 821 int idx; 822 823 STE_LOCK_ASSERT(sc); 824 825 ifp = sc->ste_ifp; 826 idx = sc->ste_cdata.ste_tx_cons; 827 if (idx == sc->ste_cdata.ste_tx_prod) 828 return; 829 830 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 831 sc->ste_cdata.ste_tx_list_map, 832 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 833 834 while (idx != sc->ste_cdata.ste_tx_prod) { 835 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 836 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 837 if ((txstat & STE_TXCTL_DMADONE) == 0) 838 break; 839 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 840 BUS_DMASYNC_POSTWRITE); 841 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 842 KASSERT(cur_tx->ste_mbuf != NULL, 843 ("%s: freeing NULL mbuf!\n", __func__)); 844 m_freem(cur_tx->ste_mbuf); 845 cur_tx->ste_mbuf = NULL; 846 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 847 ifp->if_opackets++; 848 sc->ste_cdata.ste_tx_cnt--; 849 STE_INC(idx, STE_TX_LIST_CNT); 850 } 851 852 sc->ste_cdata.ste_tx_cons = idx; 853 if (sc->ste_cdata.ste_tx_cnt == 0) 854 sc->ste_timer = 0; 855} 856 857static void 858ste_stats_update(void *xsc) 859{ 860 struct ste_softc *sc; 861 struct ifnet *ifp; 862 struct mii_data *mii; 863 864 sc = xsc; 865 STE_LOCK_ASSERT(sc); 866 867 ifp = sc->ste_ifp; 868 mii = device_get_softc(sc->ste_miibus); 869 870 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 871 + CSR_READ_1(sc, STE_MULTI_COLLS) 872 + CSR_READ_1(sc, STE_SINGLE_COLLS); 873 874 if (!sc->ste_link) { 875 mii_pollstat(mii); 876 if (mii->mii_media_status & IFM_ACTIVE && 877 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 878 sc->ste_link++; 879 /* 880 * we don't get a call-back on re-init so do it 881 * otherwise we get stuck in the wrong link state 882 */ 883 ste_miibus_statchg(sc->ste_dev); 884 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 885 ste_start_locked(ifp); 886 } 887 } 888 889 if (sc->ste_timer > 0 && --sc->ste_timer == 0) 890 ste_watchdog(sc); 891 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 892} 893 894 895/* 896 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 897 * IDs against our list and return a device name if we find a match. 898 */ 899static int 900ste_probe(device_t dev) 901{ 902 struct ste_type *t; 903 904 t = ste_devs; 905 906 while (t->ste_name != NULL) { 907 if ((pci_get_vendor(dev) == t->ste_vid) && 908 (pci_get_device(dev) == t->ste_did)) { 909 device_set_desc(dev, t->ste_name); 910 return (BUS_PROBE_DEFAULT); 911 } 912 t++; 913 } 914 915 return (ENXIO); 916} 917 918/* 919 * Attach the interface. Allocate softc structures, do ifmedia 920 * setup and ethernet/BPF attach. 921 */ 922static int 923ste_attach(device_t dev) 924{ 925 struct ste_softc *sc; 926 struct ifnet *ifp; 927 u_char eaddr[6]; 928 int error = 0, rid; 929 930 sc = device_get_softc(dev); 931 sc->ste_dev = dev; 932 933 /* 934 * Only use one PHY since this chip reports multiple 935 * Note on the DFE-550 the PHY is at 1 on the DFE-580 936 * it is at 0 & 1. It is rev 0x12. 937 */ 938 if (pci_get_vendor(dev) == DL_VENDORID && 939 pci_get_device(dev) == DL_DEVICEID_DL10050 && 940 pci_get_revid(dev) == 0x12 ) 941 sc->ste_one_phy = 1; 942 943 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 944 MTX_DEF); 945 /* 946 * Map control/status registers. 947 */ 948 pci_enable_busmaster(dev); 949 950 rid = STE_RID; 951 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 952 953 if (sc->ste_res == NULL) { 954 device_printf(dev, "couldn't map ports/memory\n"); 955 error = ENXIO; 956 goto fail; 957 } 958 959 sc->ste_btag = rman_get_bustag(sc->ste_res); 960 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 961 962 /* Allocate interrupt */ 963 rid = 0; 964 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 965 RF_SHAREABLE | RF_ACTIVE); 966 967 if (sc->ste_irq == NULL) { 968 device_printf(dev, "couldn't map interrupt\n"); 969 error = ENXIO; 970 goto fail; 971 } 972 973 callout_init_mtx(&sc->ste_stat_callout, &sc->ste_mtx, 0); 974 975 /* Reset the adapter. */ 976 ste_reset(sc); 977 978 /* 979 * Get station address from the EEPROM. 980 */ 981 if (ste_read_eeprom(sc, eaddr, 982 STE_EEADDR_NODE0, 3, 0)) { 983 device_printf(dev, "failed to read station address\n"); 984 error = ENXIO;; 985 goto fail; 986 } 987 988 if ((error = ste_dma_alloc(sc)) != 0) 989 goto fail; 990 991 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 992 if (ifp == NULL) { 993 device_printf(dev, "can not if_alloc()\n"); 994 error = ENOSPC; 995 goto fail; 996 } 997 998 /* Do MII setup. */ 999 if (mii_phy_probe(dev, &sc->ste_miibus, 1000 ste_ifmedia_upd, ste_ifmedia_sts)) { 1001 device_printf(dev, "MII without any phy!\n"); 1002 error = ENXIO; 1003 goto fail; 1004 } 1005 1006 ifp->if_softc = sc; 1007 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1008 ifp->if_mtu = ETHERMTU; 1009 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1010 ifp->if_ioctl = ste_ioctl; 1011 ifp->if_start = ste_start; 1012 ifp->if_init = ste_init; 1013 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1014 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1015 IFQ_SET_READY(&ifp->if_snd); 1016 1017 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1018 1019 /* 1020 * Call MI attach routine. 1021 */ 1022 ether_ifattach(ifp, eaddr); 1023 1024 /* 1025 * Tell the upper layer(s) we support long frames. 1026 */ 1027 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1028 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1029 ifp->if_capenable = ifp->if_capabilities; 1030#ifdef DEVICE_POLLING 1031 ifp->if_capabilities |= IFCAP_POLLING; 1032#endif 1033 1034 /* Hook interrupt last to avoid having to lock softc */ 1035 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1036 NULL, ste_intr, sc, &sc->ste_intrhand); 1037 1038 if (error) { 1039 device_printf(dev, "couldn't set up irq\n"); 1040 ether_ifdetach(ifp); 1041 goto fail; 1042 } 1043 1044fail: 1045 if (error) 1046 ste_detach(dev); 1047 1048 return (error); 1049} 1050 1051/* 1052 * Shutdown hardware and free up resources. This can be called any 1053 * time after the mutex has been initialized. It is called in both 1054 * the error case in attach and the normal detach case so it needs 1055 * to be careful about only freeing resources that have actually been 1056 * allocated. 1057 */ 1058static int 1059ste_detach(device_t dev) 1060{ 1061 struct ste_softc *sc; 1062 struct ifnet *ifp; 1063 1064 sc = device_get_softc(dev); 1065 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1066 ifp = sc->ste_ifp; 1067 1068#ifdef DEVICE_POLLING 1069 if (ifp->if_capenable & IFCAP_POLLING) 1070 ether_poll_deregister(ifp); 1071#endif 1072 1073 /* These should only be active if attach succeeded */ 1074 if (device_is_attached(dev)) { 1075 ether_ifdetach(ifp); 1076 STE_LOCK(sc); 1077 ste_stop(sc); 1078 STE_UNLOCK(sc); 1079 callout_drain(&sc->ste_stat_callout); 1080 } 1081 if (sc->ste_miibus) 1082 device_delete_child(dev, sc->ste_miibus); 1083 bus_generic_detach(dev); 1084 1085 if (sc->ste_intrhand) 1086 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1087 if (sc->ste_irq) 1088 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1089 if (sc->ste_res) 1090 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1091 1092 if (ifp) 1093 if_free(ifp); 1094 1095 ste_dma_free(sc); 1096 mtx_destroy(&sc->ste_mtx); 1097 1098 return (0); 1099} 1100 1101struct ste_dmamap_arg { 1102 bus_addr_t ste_busaddr; 1103}; 1104 1105static void 1106ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1107{ 1108 struct ste_dmamap_arg *ctx; 1109 1110 if (error != 0) 1111 return; 1112 1113 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1114 1115 ctx = (struct ste_dmamap_arg *)arg; 1116 ctx->ste_busaddr = segs[0].ds_addr; 1117} 1118 1119static int 1120ste_dma_alloc(struct ste_softc *sc) 1121{ 1122 struct ste_chain *txc; 1123 struct ste_chain_onefrag *rxc; 1124 struct ste_dmamap_arg ctx; 1125 int error, i; 1126 1127 /* Create parent DMA tag. */ 1128 error = bus_dma_tag_create( 1129 bus_get_dma_tag(sc->ste_dev), /* parent */ 1130 1, 0, /* alignment, boundary */ 1131 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1132 BUS_SPACE_MAXADDR, /* highaddr */ 1133 NULL, NULL, /* filter, filterarg */ 1134 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1135 0, /* nsegments */ 1136 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1137 0, /* flags */ 1138 NULL, NULL, /* lockfunc, lockarg */ 1139 &sc->ste_cdata.ste_parent_tag); 1140 if (error != 0) { 1141 device_printf(sc->ste_dev, 1142 "could not create parent DMA tag.\n"); 1143 goto fail; 1144 } 1145 1146 /* Create DMA tag for Tx descriptor list. */ 1147 error = bus_dma_tag_create( 1148 sc->ste_cdata.ste_parent_tag, /* parent */ 1149 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1150 BUS_SPACE_MAXADDR, /* lowaddr */ 1151 BUS_SPACE_MAXADDR, /* highaddr */ 1152 NULL, NULL, /* filter, filterarg */ 1153 STE_TX_LIST_SZ, /* maxsize */ 1154 1, /* nsegments */ 1155 STE_TX_LIST_SZ, /* maxsegsize */ 1156 0, /* flags */ 1157 NULL, NULL, /* lockfunc, lockarg */ 1158 &sc->ste_cdata.ste_tx_list_tag); 1159 if (error != 0) { 1160 device_printf(sc->ste_dev, 1161 "could not create Tx list DMA tag.\n"); 1162 goto fail; 1163 } 1164 1165 /* Create DMA tag for Rx descriptor list. */ 1166 error = bus_dma_tag_create( 1167 sc->ste_cdata.ste_parent_tag, /* parent */ 1168 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1169 BUS_SPACE_MAXADDR, /* lowaddr */ 1170 BUS_SPACE_MAXADDR, /* highaddr */ 1171 NULL, NULL, /* filter, filterarg */ 1172 STE_RX_LIST_SZ, /* maxsize */ 1173 1, /* nsegments */ 1174 STE_RX_LIST_SZ, /* maxsegsize */ 1175 0, /* flags */ 1176 NULL, NULL, /* lockfunc, lockarg */ 1177 &sc->ste_cdata.ste_rx_list_tag); 1178 if (error != 0) { 1179 device_printf(sc->ste_dev, 1180 "could not create Rx list DMA tag.\n"); 1181 goto fail; 1182 } 1183 1184 /* Create DMA tag for Tx buffers. */ 1185 error = bus_dma_tag_create( 1186 sc->ste_cdata.ste_parent_tag, /* parent */ 1187 1, 0, /* alignment, boundary */ 1188 BUS_SPACE_MAXADDR, /* lowaddr */ 1189 BUS_SPACE_MAXADDR, /* highaddr */ 1190 NULL, NULL, /* filter, filterarg */ 1191 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1192 STE_MAXFRAGS, /* nsegments */ 1193 MCLBYTES, /* maxsegsize */ 1194 0, /* flags */ 1195 NULL, NULL, /* lockfunc, lockarg */ 1196 &sc->ste_cdata.ste_tx_tag); 1197 if (error != 0) { 1198 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1199 goto fail; 1200 } 1201 1202 /* Create DMA tag for Rx buffers. */ 1203 error = bus_dma_tag_create( 1204 sc->ste_cdata.ste_parent_tag, /* parent */ 1205 1, 0, /* alignment, boundary */ 1206 BUS_SPACE_MAXADDR, /* lowaddr */ 1207 BUS_SPACE_MAXADDR, /* highaddr */ 1208 NULL, NULL, /* filter, filterarg */ 1209 MCLBYTES, /* maxsize */ 1210 1, /* nsegments */ 1211 MCLBYTES, /* maxsegsize */ 1212 0, /* flags */ 1213 NULL, NULL, /* lockfunc, lockarg */ 1214 &sc->ste_cdata.ste_rx_tag); 1215 if (error != 0) { 1216 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1217 goto fail; 1218 } 1219 1220 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1221 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1222 (void **)&sc->ste_ldata.ste_tx_list, 1223 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1224 &sc->ste_cdata.ste_tx_list_map); 1225 if (error != 0) { 1226 device_printf(sc->ste_dev, 1227 "could not allocate DMA'able memory for Tx list.\n"); 1228 goto fail; 1229 } 1230 ctx.ste_busaddr = 0; 1231 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1232 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1233 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1234 if (error != 0 || ctx.ste_busaddr == 0) { 1235 device_printf(sc->ste_dev, 1236 "could not load DMA'able memory for Tx list.\n"); 1237 goto fail; 1238 } 1239 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1240 1241 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1242 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1243 (void **)&sc->ste_ldata.ste_rx_list, 1244 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1245 &sc->ste_cdata.ste_rx_list_map); 1246 if (error != 0) { 1247 device_printf(sc->ste_dev, 1248 "could not allocate DMA'able memory for Rx list.\n"); 1249 goto fail; 1250 } 1251 ctx.ste_busaddr = 0; 1252 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1253 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1254 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1255 if (error != 0 || ctx.ste_busaddr == 0) { 1256 device_printf(sc->ste_dev, 1257 "could not load DMA'able memory for Rx list.\n"); 1258 goto fail; 1259 } 1260 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1261 1262 /* Create DMA maps for Tx buffers. */ 1263 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1264 txc = &sc->ste_cdata.ste_tx_chain[i]; 1265 txc->ste_ptr = NULL; 1266 txc->ste_mbuf = NULL; 1267 txc->ste_next = NULL; 1268 txc->ste_phys = 0; 1269 txc->ste_map = NULL; 1270 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1271 &txc->ste_map); 1272 if (error != 0) { 1273 device_printf(sc->ste_dev, 1274 "could not create Tx dmamap.\n"); 1275 goto fail; 1276 } 1277 } 1278 /* Create DMA maps for Rx buffers. */ 1279 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1280 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1281 device_printf(sc->ste_dev, 1282 "could not create spare Rx dmamap.\n"); 1283 goto fail; 1284 } 1285 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1286 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1287 rxc->ste_ptr = NULL; 1288 rxc->ste_mbuf = NULL; 1289 rxc->ste_next = NULL; 1290 rxc->ste_map = NULL; 1291 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1292 &rxc->ste_map); 1293 if (error != 0) { 1294 device_printf(sc->ste_dev, 1295 "could not create Rx dmamap.\n"); 1296 goto fail; 1297 } 1298 } 1299 1300fail: 1301 return (error); 1302} 1303 1304static void 1305ste_dma_free(struct ste_softc *sc) 1306{ 1307 struct ste_chain *txc; 1308 struct ste_chain_onefrag *rxc; 1309 int i; 1310 1311 /* Tx buffers. */ 1312 if (sc->ste_cdata.ste_tx_tag != NULL) { 1313 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1314 txc = &sc->ste_cdata.ste_tx_chain[i]; 1315 if (txc->ste_map != NULL) { 1316 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1317 txc->ste_map); 1318 txc->ste_map = NULL; 1319 } 1320 } 1321 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1322 sc->ste_cdata.ste_tx_tag = NULL; 1323 } 1324 /* Rx buffers. */ 1325 if (sc->ste_cdata.ste_rx_tag != NULL) { 1326 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1327 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1328 if (rxc->ste_map != NULL) { 1329 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1330 rxc->ste_map); 1331 rxc->ste_map = NULL; 1332 } 1333 } 1334 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1335 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1336 sc->ste_cdata.ste_rx_sparemap); 1337 sc->ste_cdata.ste_rx_sparemap = NULL; 1338 } 1339 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1340 sc->ste_cdata.ste_rx_tag = NULL; 1341 } 1342 /* Tx descriptor list. */ 1343 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1344 if (sc->ste_cdata.ste_tx_list_map != NULL) 1345 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1346 sc->ste_cdata.ste_tx_list_map); 1347 if (sc->ste_cdata.ste_tx_list_map != NULL && 1348 sc->ste_ldata.ste_tx_list != NULL) 1349 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1350 sc->ste_ldata.ste_tx_list, 1351 sc->ste_cdata.ste_tx_list_map); 1352 sc->ste_ldata.ste_tx_list = NULL; 1353 sc->ste_cdata.ste_tx_list_map = NULL; 1354 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1355 sc->ste_cdata.ste_tx_list_tag = NULL; 1356 } 1357 /* Rx descriptor list. */ 1358 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1359 if (sc->ste_cdata.ste_rx_list_map != NULL) 1360 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1361 sc->ste_cdata.ste_rx_list_map); 1362 if (sc->ste_cdata.ste_rx_list_map != NULL && 1363 sc->ste_ldata.ste_rx_list != NULL) 1364 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1365 sc->ste_ldata.ste_rx_list, 1366 sc->ste_cdata.ste_rx_list_map); 1367 sc->ste_ldata.ste_rx_list = NULL; 1368 sc->ste_cdata.ste_rx_list_map = NULL; 1369 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1370 sc->ste_cdata.ste_rx_list_tag = NULL; 1371 } 1372 if (sc->ste_cdata.ste_parent_tag != NULL) { 1373 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1374 sc->ste_cdata.ste_parent_tag = NULL; 1375 } 1376} 1377 1378static int 1379ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1380{ 1381 struct mbuf *m; 1382 bus_dma_segment_t segs[1]; 1383 bus_dmamap_t map; 1384 int error, nsegs; 1385 1386 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1387 if (m == NULL) 1388 return (ENOBUFS); 1389 m->m_len = m->m_pkthdr.len = MCLBYTES; 1390 m_adj(m, ETHER_ALIGN); 1391 1392 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1393 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1394 m_freem(m); 1395 return (error); 1396 } 1397 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1398 1399 if (rxc->ste_mbuf != NULL) { 1400 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1401 BUS_DMASYNC_POSTREAD); 1402 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1403 } 1404 map = rxc->ste_map; 1405 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1406 sc->ste_cdata.ste_rx_sparemap = map; 1407 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1408 BUS_DMASYNC_PREREAD); 1409 rxc->ste_mbuf = m; 1410 rxc->ste_ptr->ste_status = 0; 1411 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1412 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1413 STE_FRAG_LAST); 1414 return (0); 1415} 1416 1417static int 1418ste_init_rx_list(struct ste_softc *sc) 1419{ 1420 struct ste_chain_data *cd; 1421 struct ste_list_data *ld; 1422 int error, i; 1423 1424 cd = &sc->ste_cdata; 1425 ld = &sc->ste_ldata; 1426 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1427 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1428 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1429 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1430 if (error != 0) 1431 return (error); 1432 if (i == (STE_RX_LIST_CNT - 1)) { 1433 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1434 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1435 (sizeof(struct ste_desc_onefrag) * 0); 1436 } else { 1437 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1438 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1439 (sizeof(struct ste_desc_onefrag) * (i + 1)); 1440 } 1441 } 1442 1443 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1444 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1445 sc->ste_cdata.ste_rx_list_map, 1446 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1447 1448 return (0); 1449} 1450 1451static void 1452ste_init_tx_list(struct ste_softc *sc) 1453{ 1454 struct ste_chain_data *cd; 1455 struct ste_list_data *ld; 1456 int i; 1457 1458 cd = &sc->ste_cdata; 1459 ld = &sc->ste_ldata; 1460 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1461 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1462 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1463 cd->ste_tx_chain[i].ste_mbuf = NULL; 1464 if (i == (STE_TX_LIST_CNT - 1)) { 1465 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1466 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1467 ld->ste_tx_list_paddr + 1468 (sizeof(struct ste_desc) * 0))); 1469 } else { 1470 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1471 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1472 ld->ste_tx_list_paddr + 1473 (sizeof(struct ste_desc) * (i + 1)))); 1474 } 1475 } 1476 1477 cd->ste_last_tx = NULL; 1478 cd->ste_tx_prod = 0; 1479 cd->ste_tx_cons = 0; 1480 cd->ste_tx_cnt = 0; 1481 1482 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1483 sc->ste_cdata.ste_tx_list_map, 1484 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1485} 1486 1487static void 1488ste_init(void *xsc) 1489{ 1490 struct ste_softc *sc; 1491 1492 sc = xsc; 1493 STE_LOCK(sc); 1494 ste_init_locked(sc); 1495 STE_UNLOCK(sc); 1496} 1497 1498static void 1499ste_init_locked(struct ste_softc *sc) 1500{ 1501 struct ifnet *ifp; 1502 int i; 1503 1504 STE_LOCK_ASSERT(sc); 1505 ifp = sc->ste_ifp; 1506 1507 ste_stop(sc); 1508 1509 /* Init our MAC address */ 1510 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1511 CSR_WRITE_2(sc, STE_PAR0 + i, 1512 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1513 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1514 } 1515 1516 /* Init RX list */ 1517 if (ste_init_rx_list(sc) != 0) { 1518 device_printf(sc->ste_dev, 1519 "initialization failed: no memory for RX buffers\n"); 1520 ste_stop(sc); 1521 return; 1522 } 1523 1524 /* Set RX polling interval */ 1525 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1526 1527 /* Init TX descriptors */ 1528 ste_init_tx_list(sc); 1529 1530 /* Set the TX freethresh value */ 1531 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1532 1533 /* Set the TX start threshold for best performance. */ 1534 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1535 1536 /* Set the TX reclaim threshold. */ 1537 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1538 1539 /* Set up the RX filter. */ 1540 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1541 1542 /* If we want promiscuous mode, set the allframes bit. */ 1543 if (ifp->if_flags & IFF_PROMISC) { 1544 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1545 } else { 1546 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1547 } 1548 1549 /* Set capture broadcast bit to accept broadcast frames. */ 1550 if (ifp->if_flags & IFF_BROADCAST) { 1551 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1552 } else { 1553 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1554 } 1555 1556 ste_setmulti(sc); 1557 1558 /* Load the address of the RX list. */ 1559 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1560 ste_wait(sc); 1561 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1562 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1563 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1564 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1565 1566 /* Set TX polling interval(defer until we TX first packet). */ 1567 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1568 1569 /* Load address of the TX list */ 1570 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1571 ste_wait(sc); 1572 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1573 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1574 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1575 ste_wait(sc); 1576 1577 /* Enable receiver and transmitter */ 1578 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1579 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1580 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1581 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1582 1583 /* Enable stats counters. */ 1584 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1585 1586 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1587#ifdef DEVICE_POLLING 1588 /* Disable interrupts if we are polling. */ 1589 if (ifp->if_capenable & IFCAP_POLLING) 1590 CSR_WRITE_2(sc, STE_IMR, 0); 1591 else 1592#endif 1593 /* Enable interrupts. */ 1594 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1595 1596 /* Accept VLAN length packets */ 1597 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1598 1599 ste_ifmedia_upd_locked(ifp); 1600 1601 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1602 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1603 1604 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 1605} 1606 1607static void 1608ste_stop(struct ste_softc *sc) 1609{ 1610 struct ifnet *ifp; 1611 struct ste_chain_onefrag *cur_rx; 1612 struct ste_chain *cur_tx; 1613 int i; 1614 1615 STE_LOCK_ASSERT(sc); 1616 ifp = sc->ste_ifp; 1617 1618 callout_stop(&sc->ste_stat_callout); 1619 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1620 1621 CSR_WRITE_2(sc, STE_IMR, 0); 1622 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1623 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1624 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1625 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1626 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1627 ste_wait(sc); 1628 /* 1629 * Try really hard to stop the RX engine or under heavy RX 1630 * data chip will write into de-allocated memory. 1631 */ 1632 ste_reset(sc); 1633 1634 sc->ste_link = 0; 1635 1636 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1637 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1638 if (cur_rx->ste_mbuf != NULL) { 1639 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1640 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1641 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1642 cur_rx->ste_map); 1643 m_freem(cur_rx->ste_mbuf); 1644 cur_rx->ste_mbuf = NULL; 1645 } 1646 } 1647 1648 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1649 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1650 if (cur_tx->ste_mbuf != NULL) { 1651 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1652 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1653 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1654 cur_tx->ste_map); 1655 m_freem(cur_tx->ste_mbuf); 1656 cur_tx->ste_mbuf = NULL; 1657 } 1658 } 1659} 1660 1661static void 1662ste_reset(struct ste_softc *sc) 1663{ 1664 int i; 1665 1666 STE_SETBIT4(sc, STE_ASICCTL, 1667 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1668 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1669 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1670 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1671 STE_ASICCTL_EXTRESET_RESET); 1672 1673 DELAY(100000); 1674 1675 for (i = 0; i < STE_TIMEOUT; i++) { 1676 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1677 break; 1678 } 1679 1680 if (i == STE_TIMEOUT) 1681 device_printf(sc->ste_dev, "global reset never completed\n"); 1682} 1683 1684static int 1685ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1686{ 1687 struct ste_softc *sc; 1688 struct ifreq *ifr; 1689 struct mii_data *mii; 1690 int error = 0; 1691 1692 sc = ifp->if_softc; 1693 ifr = (struct ifreq *)data; 1694 1695 switch (command) { 1696 case SIOCSIFFLAGS: 1697 STE_LOCK(sc); 1698 if (ifp->if_flags & IFF_UP) { 1699 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1700 ifp->if_flags & IFF_PROMISC && 1701 !(sc->ste_if_flags & IFF_PROMISC)) { 1702 STE_SETBIT1(sc, STE_RX_MODE, 1703 STE_RXMODE_PROMISC); 1704 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1705 !(ifp->if_flags & IFF_PROMISC) && 1706 sc->ste_if_flags & IFF_PROMISC) { 1707 STE_CLRBIT1(sc, STE_RX_MODE, 1708 STE_RXMODE_PROMISC); 1709 } 1710 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1711 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1712 ste_setmulti(sc); 1713 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1714 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1715 ste_init_locked(sc); 1716 } 1717 } else { 1718 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1719 ste_stop(sc); 1720 } 1721 sc->ste_if_flags = ifp->if_flags; 1722 STE_UNLOCK(sc); 1723 error = 0; 1724 break; 1725 case SIOCADDMULTI: 1726 case SIOCDELMULTI: 1727 STE_LOCK(sc); 1728 ste_setmulti(sc); 1729 STE_UNLOCK(sc); 1730 error = 0; 1731 break; 1732 case SIOCGIFMEDIA: 1733 case SIOCSIFMEDIA: 1734 mii = device_get_softc(sc->ste_miibus); 1735 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1736 break; 1737 case SIOCSIFCAP: 1738#ifdef DEVICE_POLLING 1739 if (ifr->ifr_reqcap & IFCAP_POLLING && 1740 !(ifp->if_capenable & IFCAP_POLLING)) { 1741 error = ether_poll_register(ste_poll, ifp); 1742 if (error) 1743 return (error); 1744 STE_LOCK(sc); 1745 /* Disable interrupts */ 1746 CSR_WRITE_2(sc, STE_IMR, 0); 1747 ifp->if_capenable |= IFCAP_POLLING; 1748 STE_UNLOCK(sc); 1749 return (error); 1750 1751 } 1752 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1753 ifp->if_capenable & IFCAP_POLLING) { 1754 error = ether_poll_deregister(ifp); 1755 /* Enable interrupts. */ 1756 STE_LOCK(sc); 1757 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1758 ifp->if_capenable &= ~IFCAP_POLLING; 1759 STE_UNLOCK(sc); 1760 return (error); 1761 } 1762#endif /* DEVICE_POLLING */ 1763 break; 1764 default: 1765 error = ether_ioctl(ifp, command, data); 1766 break; 1767 } 1768 1769 return (error); 1770} 1771 1772static int 1773ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1774{ 1775 struct ste_frag *frag; 1776 struct mbuf *m; 1777 struct ste_desc *desc; 1778 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1779 int error, i, nsegs; 1780 1781 STE_LOCK_ASSERT(sc); 1782 M_ASSERTPKTHDR((*m_head)); 1783 1784 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1785 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1786 if (error == EFBIG) { 1787 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS); 1788 if (m == NULL) { 1789 m_freem(*m_head); 1790 *m_head = NULL; 1791 return (ENOMEM); 1792 } 1793 *m_head = m; 1794 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1795 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1796 if (error != 0) { 1797 m_freem(*m_head); 1798 *m_head = NULL; 1799 return (error); 1800 } 1801 } else if (error != 0) 1802 return (error); 1803 if (nsegs == 0) { 1804 m_freem(*m_head); 1805 *m_head = NULL; 1806 return (EIO); 1807 } 1808 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1809 BUS_DMASYNC_PREWRITE); 1810 1811 desc = txc->ste_ptr; 1812 for (i = 0; i < nsegs; i++) { 1813 frag = &desc->ste_frags[i]; 1814 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1815 frag->ste_len = htole32(txsegs[i].ds_len); 1816 } 1817 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1818 /* 1819 * Because we use Tx polling we can't chain multiple 1820 * Tx descriptors here. Otherwise we race with controller. 1821 */ 1822 desc->ste_next = 0; 1823 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | STE_TXCTL_DMAINTR); 1824 txc->ste_mbuf = *m_head; 1825 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1826 sc->ste_cdata.ste_tx_cnt++; 1827 1828 return (0); 1829} 1830 1831static void 1832ste_start(struct ifnet *ifp) 1833{ 1834 struct ste_softc *sc; 1835 1836 sc = ifp->if_softc; 1837 STE_LOCK(sc); 1838 ste_start_locked(ifp); 1839 STE_UNLOCK(sc); 1840} 1841 1842static void 1843ste_start_locked(struct ifnet *ifp) 1844{ 1845 struct ste_softc *sc; 1846 struct ste_chain *cur_tx; 1847 struct mbuf *m_head = NULL; 1848 int enq; 1849 1850 sc = ifp->if_softc; 1851 STE_LOCK_ASSERT(sc); 1852 1853 if (!sc->ste_link) 1854 return; 1855 1856 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1857 return; 1858 1859 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 1860 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1861 /* 1862 * Controller may have cached copy of the last used 1863 * next ptr so we have to reserve one TFD to avoid 1864 * TFD overruns. 1865 */ 1866 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1867 break; 1868 } 1869 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1870 if (m_head == NULL) 1871 break; 1872 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1873 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1874 if (m_head == NULL) 1875 break; 1876 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1877 break; 1878 } 1879 if (sc->ste_cdata.ste_last_tx == NULL) { 1880 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1881 sc->ste_cdata.ste_tx_list_map, 1882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1883 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1884 ste_wait(sc); 1885 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1886 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1887 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1888 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1889 ste_wait(sc); 1890 } else { 1891 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1892 sc->ste_cdata.ste_last_tx->ste_phys; 1893 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1894 sc->ste_cdata.ste_tx_list_map, 1895 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1896 } 1897 sc->ste_cdata.ste_last_tx = cur_tx; 1898 1899 enq++; 1900 /* 1901 * If there's a BPF listener, bounce a copy of this frame 1902 * to him. 1903 */ 1904 BPF_MTAP(ifp, m_head); 1905 } 1906 1907 if (enq > 0) 1908 sc->ste_timer = STE_TX_TIMEOUT; 1909} 1910 1911static void 1912ste_watchdog(struct ste_softc *sc) 1913{ 1914 struct ifnet *ifp; 1915 1916 ifp = sc->ste_ifp; 1917 STE_LOCK_ASSERT(sc); 1918 1919 ifp->if_oerrors++; 1920 if_printf(ifp, "watchdog timeout\n"); 1921 1922 ste_txeoc(sc); 1923 ste_txeof(sc); 1924 ste_rxeof(sc, -1); 1925 ste_reset(sc); 1926 ste_init_locked(sc); 1927 1928 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1929 ste_start_locked(ifp); 1930} 1931 1932static int 1933ste_shutdown(device_t dev) 1934{ 1935 struct ste_softc *sc; 1936 1937 sc = device_get_softc(dev); 1938 1939 STE_LOCK(sc); 1940 ste_stop(sc); 1941 STE_UNLOCK(sc); 1942 1943 return (0); 1944} 1945