if_ste.c revision 200853
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 200853 2009-12-22 18:57:07Z yongari $"); 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53 54#include <net/bpf.h> 55#include <net/if.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61#include <net/if_vlan_var.h> 62 63#include <machine/bus.h> 64#include <machine/resource.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <dev/ste/if_stereg.h> 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77#define STE_USEIOSPACE 78 79MODULE_DEPEND(ste, pci, 1, 1, 1); 80MODULE_DEPEND(ste, ether, 1, 1, 1); 81MODULE_DEPEND(ste, miibus, 1, 1, 1); 82 83/* 84 * Various supported device vendors/types and their names. 85 */ 86static struct ste_type ste_devs[] = { 87 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 88 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 89 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 90 { 0, 0, NULL } 91}; 92 93static int ste_attach(device_t); 94static int ste_detach(device_t); 95static int ste_probe(device_t); 96static int ste_shutdown(device_t); 97 98static int ste_dma_alloc(struct ste_softc *); 99static void ste_dma_free(struct ste_softc *); 100static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 101static int ste_eeprom_wait(struct ste_softc *); 102static int ste_encap(struct ste_softc *, struct mbuf **, 103 struct ste_chain *); 104static int ste_ifmedia_upd(struct ifnet *); 105static void ste_ifmedia_upd_locked(struct ifnet *); 106static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 107static void ste_init(void *); 108static void ste_init_locked(struct ste_softc *); 109static int ste_init_rx_list(struct ste_softc *); 110static void ste_init_tx_list(struct ste_softc *); 111static void ste_intr(void *); 112static int ste_ioctl(struct ifnet *, u_long, caddr_t); 113static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 114static void ste_mii_send(struct ste_softc *, uint32_t, int); 115static void ste_mii_sync(struct ste_softc *); 116static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 117static int ste_miibus_readreg(device_t, int, int); 118static void ste_miibus_statchg(device_t); 119static int ste_miibus_writereg(device_t, int, int, int); 120static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 121static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 122static void ste_reset(struct ste_softc *); 123static int ste_rxeof(struct ste_softc *, int); 124static void ste_setmulti(struct ste_softc *); 125static void ste_start(struct ifnet *); 126static void ste_start_locked(struct ifnet *); 127static void ste_stats_update(void *); 128static void ste_stop(struct ste_softc *); 129static void ste_txeoc(struct ste_softc *); 130static void ste_txeof(struct ste_softc *); 131static void ste_wait(struct ste_softc *); 132static void ste_watchdog(struct ste_softc *); 133 134#ifdef STE_USEIOSPACE 135#define STE_RES SYS_RES_IOPORT 136#define STE_RID STE_PCI_LOIO 137#else 138#define STE_RES SYS_RES_MEMORY 139#define STE_RID STE_PCI_LOMEM 140#endif 141 142static device_method_t ste_methods[] = { 143 /* Device interface */ 144 DEVMETHOD(device_probe, ste_probe), 145 DEVMETHOD(device_attach, ste_attach), 146 DEVMETHOD(device_detach, ste_detach), 147 DEVMETHOD(device_shutdown, ste_shutdown), 148 149 /* bus interface */ 150 DEVMETHOD(bus_print_child, bus_generic_print_child), 151 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 152 153 /* MII interface */ 154 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 155 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 156 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 157 158 { 0, 0 } 159}; 160 161static driver_t ste_driver = { 162 "ste", 163 ste_methods, 164 sizeof(struct ste_softc) 165}; 166 167static devclass_t ste_devclass; 168 169DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 170DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 171 172#define STE_SETBIT4(sc, reg, x) \ 173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 174 175#define STE_CLRBIT4(sc, reg, x) \ 176 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 177 178#define STE_SETBIT2(sc, reg, x) \ 179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 180 181#define STE_CLRBIT2(sc, reg, x) \ 182 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 183 184#define STE_SETBIT1(sc, reg, x) \ 185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 186 187#define STE_CLRBIT1(sc, reg, x) \ 188 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 189 190 191#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 192#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 193 194/* 195 * Sync the PHYs by setting data bit and strobing the clock 32 times. 196 */ 197static void 198ste_mii_sync(struct ste_softc *sc) 199{ 200 int i; 201 202 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 203 204 for (i = 0; i < 32; i++) { 205 MII_SET(STE_PHYCTL_MCLK); 206 DELAY(1); 207 MII_CLR(STE_PHYCTL_MCLK); 208 DELAY(1); 209 } 210} 211 212/* 213 * Clock a series of bits through the MII. 214 */ 215static void 216ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt) 217{ 218 int i; 219 220 MII_CLR(STE_PHYCTL_MCLK); 221 222 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 223 if (bits & i) { 224 MII_SET(STE_PHYCTL_MDATA); 225 } else { 226 MII_CLR(STE_PHYCTL_MDATA); 227 } 228 DELAY(1); 229 MII_CLR(STE_PHYCTL_MCLK); 230 DELAY(1); 231 MII_SET(STE_PHYCTL_MCLK); 232 } 233} 234 235/* 236 * Read an PHY register through the MII. 237 */ 238static int 239ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 240{ 241 int i, ack; 242 243 /* 244 * Set up frame for RX. 245 */ 246 frame->mii_stdelim = STE_MII_STARTDELIM; 247 frame->mii_opcode = STE_MII_READOP; 248 frame->mii_turnaround = 0; 249 frame->mii_data = 0; 250 251 CSR_WRITE_2(sc, STE_PHYCTL, 0); 252 /* 253 * Turn on data xmit. 254 */ 255 MII_SET(STE_PHYCTL_MDIR); 256 257 ste_mii_sync(sc); 258 259 /* 260 * Send command/address info. 261 */ 262 ste_mii_send(sc, frame->mii_stdelim, 2); 263 ste_mii_send(sc, frame->mii_opcode, 2); 264 ste_mii_send(sc, frame->mii_phyaddr, 5); 265 ste_mii_send(sc, frame->mii_regaddr, 5); 266 267 /* Turn off xmit. */ 268 MII_CLR(STE_PHYCTL_MDIR); 269 270 /* Idle bit */ 271 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 272 DELAY(1); 273 MII_SET(STE_PHYCTL_MCLK); 274 DELAY(1); 275 276 /* Check for ack */ 277 MII_CLR(STE_PHYCTL_MCLK); 278 DELAY(1); 279 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 280 MII_SET(STE_PHYCTL_MCLK); 281 DELAY(1); 282 283 /* 284 * Now try reading data bits. If the ack failed, we still 285 * need to clock through 16 cycles to keep the PHY(s) in sync. 286 */ 287 if (ack) { 288 for (i = 0; i < 16; i++) { 289 MII_CLR(STE_PHYCTL_MCLK); 290 DELAY(1); 291 MII_SET(STE_PHYCTL_MCLK); 292 DELAY(1); 293 } 294 goto fail; 295 } 296 297 for (i = 0x8000; i; i >>= 1) { 298 MII_CLR(STE_PHYCTL_MCLK); 299 DELAY(1); 300 if (!ack) { 301 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 302 frame->mii_data |= i; 303 DELAY(1); 304 } 305 MII_SET(STE_PHYCTL_MCLK); 306 DELAY(1); 307 } 308 309fail: 310 311 MII_CLR(STE_PHYCTL_MCLK); 312 DELAY(1); 313 MII_SET(STE_PHYCTL_MCLK); 314 DELAY(1); 315 316 if (ack) 317 return (1); 318 return (0); 319} 320 321/* 322 * Write to a PHY register through the MII. 323 */ 324static int 325ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 326{ 327 328 /* 329 * Set up frame for TX. 330 */ 331 332 frame->mii_stdelim = STE_MII_STARTDELIM; 333 frame->mii_opcode = STE_MII_WRITEOP; 334 frame->mii_turnaround = STE_MII_TURNAROUND; 335 336 /* 337 * Turn on data output. 338 */ 339 MII_SET(STE_PHYCTL_MDIR); 340 341 ste_mii_sync(sc); 342 343 ste_mii_send(sc, frame->mii_stdelim, 2); 344 ste_mii_send(sc, frame->mii_opcode, 2); 345 ste_mii_send(sc, frame->mii_phyaddr, 5); 346 ste_mii_send(sc, frame->mii_regaddr, 5); 347 ste_mii_send(sc, frame->mii_turnaround, 2); 348 ste_mii_send(sc, frame->mii_data, 16); 349 350 /* Idle bit. */ 351 MII_SET(STE_PHYCTL_MCLK); 352 DELAY(1); 353 MII_CLR(STE_PHYCTL_MCLK); 354 DELAY(1); 355 356 /* 357 * Turn off xmit. 358 */ 359 MII_CLR(STE_PHYCTL_MDIR); 360 361 return (0); 362} 363 364static int 365ste_miibus_readreg(device_t dev, int phy, int reg) 366{ 367 struct ste_softc *sc; 368 struct ste_mii_frame frame; 369 370 sc = device_get_softc(dev); 371 372 if ( sc->ste_one_phy && phy != 0 ) 373 return (0); 374 375 bzero((char *)&frame, sizeof(frame)); 376 377 frame.mii_phyaddr = phy; 378 frame.mii_regaddr = reg; 379 ste_mii_readreg(sc, &frame); 380 381 return (frame.mii_data); 382} 383 384static int 385ste_miibus_writereg(device_t dev, int phy, int reg, int data) 386{ 387 struct ste_softc *sc; 388 struct ste_mii_frame frame; 389 390 sc = device_get_softc(dev); 391 bzero((char *)&frame, sizeof(frame)); 392 393 frame.mii_phyaddr = phy; 394 frame.mii_regaddr = reg; 395 frame.mii_data = data; 396 397 ste_mii_writereg(sc, &frame); 398 399 return (0); 400} 401 402static void 403ste_miibus_statchg(device_t dev) 404{ 405 struct ste_softc *sc; 406 struct mii_data *mii; 407 408 sc = device_get_softc(dev); 409 410 mii = device_get_softc(sc->ste_miibus); 411 412 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 413 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 414 } else { 415 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 416 } 417} 418 419static int 420ste_ifmedia_upd(struct ifnet *ifp) 421{ 422 struct ste_softc *sc; 423 424 sc = ifp->if_softc; 425 STE_LOCK(sc); 426 ste_ifmedia_upd_locked(ifp); 427 STE_UNLOCK(sc); 428 429 return (0); 430} 431 432static void 433ste_ifmedia_upd_locked(struct ifnet *ifp) 434{ 435 struct ste_softc *sc; 436 struct mii_data *mii; 437 438 sc = ifp->if_softc; 439 STE_LOCK_ASSERT(sc); 440 mii = device_get_softc(sc->ste_miibus); 441 sc->ste_link = 0; 442 if (mii->mii_instance) { 443 struct mii_softc *miisc; 444 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 445 mii_phy_reset(miisc); 446 } 447 mii_mediachg(mii); 448} 449 450static void 451ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 452{ 453 struct ste_softc *sc; 454 struct mii_data *mii; 455 456 sc = ifp->if_softc; 457 mii = device_get_softc(sc->ste_miibus); 458 459 STE_LOCK(sc); 460 mii_pollstat(mii); 461 ifmr->ifm_active = mii->mii_media_active; 462 ifmr->ifm_status = mii->mii_media_status; 463 STE_UNLOCK(sc); 464} 465 466static void 467ste_wait(struct ste_softc *sc) 468{ 469 int i; 470 471 for (i = 0; i < STE_TIMEOUT; i++) { 472 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 473 break; 474 } 475 476 if (i == STE_TIMEOUT) 477 device_printf(sc->ste_dev, "command never completed!\n"); 478} 479 480/* 481 * The EEPROM is slow: give it time to come ready after issuing 482 * it a command. 483 */ 484static int 485ste_eeprom_wait(struct ste_softc *sc) 486{ 487 int i; 488 489 DELAY(1000); 490 491 for (i = 0; i < 100; i++) { 492 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 493 DELAY(1000); 494 else 495 break; 496 } 497 498 if (i == 100) { 499 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 500 return (1); 501 } 502 503 return (0); 504} 505 506/* 507 * Read a sequence of words from the EEPROM. Note that ethernet address 508 * data is stored in the EEPROM in network byte order. 509 */ 510static int 511ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 512{ 513 uint16_t word, *ptr; 514 int err = 0, i; 515 516 if (ste_eeprom_wait(sc)) 517 return (1); 518 519 for (i = 0; i < cnt; i++) { 520 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 521 err = ste_eeprom_wait(sc); 522 if (err) 523 break; 524 word = CSR_READ_2(sc, STE_EEPROM_DATA); 525 ptr = (uint16_t *)(dest + (i * 2)); 526 if (swap) 527 *ptr = ntohs(word); 528 else 529 *ptr = word; 530 } 531 532 return (err ? 1 : 0); 533} 534 535static void 536ste_setmulti(struct ste_softc *sc) 537{ 538 struct ifnet *ifp; 539 struct ifmultiaddr *ifma; 540 uint32_t hashes[2] = { 0, 0 }; 541 int h; 542 543 ifp = sc->ste_ifp; 544 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 545 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 546 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 547 return; 548 } 549 550 /* first, zot all the existing hash bits */ 551 CSR_WRITE_2(sc, STE_MAR0, 0); 552 CSR_WRITE_2(sc, STE_MAR1, 0); 553 CSR_WRITE_2(sc, STE_MAR2, 0); 554 CSR_WRITE_2(sc, STE_MAR3, 0); 555 556 /* now program new ones */ 557 if_maddr_rlock(ifp); 558 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 559 if (ifma->ifma_addr->sa_family != AF_LINK) 560 continue; 561 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 562 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 563 if (h < 32) 564 hashes[0] |= (1 << h); 565 else 566 hashes[1] |= (1 << (h - 32)); 567 } 568 if_maddr_runlock(ifp); 569 570 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 571 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 572 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 573 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 574 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 575 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 576} 577 578#ifdef DEVICE_POLLING 579static poll_handler_t ste_poll, ste_poll_locked; 580 581static int 582ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 583{ 584 struct ste_softc *sc = ifp->if_softc; 585 int rx_npkts = 0; 586 587 STE_LOCK(sc); 588 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 589 rx_npkts = ste_poll_locked(ifp, cmd, count); 590 STE_UNLOCK(sc); 591 return (rx_npkts); 592} 593 594static int 595ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 596{ 597 struct ste_softc *sc = ifp->if_softc; 598 int rx_npkts; 599 600 STE_LOCK_ASSERT(sc); 601 602 rx_npkts = ste_rxeof(sc, count); 603 ste_txeof(sc); 604 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 605 ste_start_locked(ifp); 606 607 if (cmd == POLL_AND_CHECK_STATUS) { 608 uint16_t status; 609 610 status = CSR_READ_2(sc, STE_ISR_ACK); 611 612 if (status & STE_ISR_TX_DONE) 613 ste_txeoc(sc); 614 615 if (status & STE_ISR_STATS_OFLOW) { 616 callout_stop(&sc->ste_stat_callout); 617 ste_stats_update(sc); 618 } 619 620 if (status & STE_ISR_LINKEVENT) 621 mii_pollstat(device_get_softc(sc->ste_miibus)); 622 623 if (status & STE_ISR_HOSTERR) { 624 ste_reset(sc); 625 ste_init_locked(sc); 626 } 627 } 628 return (rx_npkts); 629} 630#endif /* DEVICE_POLLING */ 631 632static void 633ste_intr(void *xsc) 634{ 635 struct ste_softc *sc; 636 struct ifnet *ifp; 637 uint16_t status; 638 639 sc = xsc; 640 STE_LOCK(sc); 641 ifp = sc->ste_ifp; 642 643#ifdef DEVICE_POLLING 644 if (ifp->if_capenable & IFCAP_POLLING) { 645 STE_UNLOCK(sc); 646 return; 647 } 648#endif 649 650 /* See if this is really our interrupt. */ 651 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 652 STE_UNLOCK(sc); 653 return; 654 } 655 656 for (;;) { 657 status = CSR_READ_2(sc, STE_ISR_ACK); 658 659 if (!(status & STE_INTRS)) 660 break; 661 662 if (status & STE_ISR_RX_DMADONE) 663 ste_rxeof(sc, -1); 664 665 if (status & STE_ISR_TX_DMADONE) 666 ste_txeof(sc); 667 668 if (status & STE_ISR_TX_DONE) 669 ste_txeoc(sc); 670 671 if (status & STE_ISR_STATS_OFLOW) { 672 callout_stop(&sc->ste_stat_callout); 673 ste_stats_update(sc); 674 } 675 676 if (status & STE_ISR_LINKEVENT) 677 mii_pollstat(device_get_softc(sc->ste_miibus)); 678 679 680 if (status & STE_ISR_HOSTERR) { 681 ste_reset(sc); 682 ste_init_locked(sc); 683 } 684 } 685 686 /* Re-enable interrupts */ 687 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 688 689 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 690 ste_start_locked(ifp); 691 692 STE_UNLOCK(sc); 693} 694 695/* 696 * A frame has been uploaded: pass the resulting mbuf chain up to 697 * the higher level protocols. 698 */ 699static int 700ste_rxeof(struct ste_softc *sc, int count) 701{ 702 struct mbuf *m; 703 struct ifnet *ifp; 704 struct ste_chain_onefrag *cur_rx; 705 uint32_t rxstat; 706 int total_len, rx_npkts; 707 708 ifp = sc->ste_ifp; 709 710 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 711 sc->ste_cdata.ste_rx_list_map, 712 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 713 714 cur_rx = sc->ste_cdata.ste_rx_head; 715 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 716 cur_rx = cur_rx->ste_next) { 717 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 718 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 719 break; 720#ifdef DEVICE_POLLING 721 if (ifp->if_capenable & IFCAP_POLLING) { 722 if (count == 0) 723 break; 724 count--; 725 } 726#endif 727 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 728 break; 729 /* 730 * If an error occurs, update stats, clear the 731 * status word and leave the mbuf cluster in place: 732 * it should simply get re-used next time this descriptor 733 * comes up in the ring. 734 */ 735 if (rxstat & STE_RXSTAT_FRAME_ERR) { 736 ifp->if_ierrors++; 737 cur_rx->ste_ptr->ste_status = 0; 738 continue; 739 } 740 741 /* No errors; receive the packet. */ 742 m = cur_rx->ste_mbuf; 743 total_len = STE_RX_BYTES(rxstat); 744 745 /* 746 * Try to conjure up a new mbuf cluster. If that 747 * fails, it means we have an out of memory condition and 748 * should leave the buffer in place and continue. This will 749 * result in a lost packet, but there's little else we 750 * can do in this situation. 751 */ 752 if (ste_newbuf(sc, cur_rx) != 0) { 753 ifp->if_ierrors++; 754 cur_rx->ste_ptr->ste_status = 0; 755 continue; 756 } 757 758 m->m_pkthdr.rcvif = ifp; 759 m->m_pkthdr.len = m->m_len = total_len; 760 761 ifp->if_ipackets++; 762 STE_UNLOCK(sc); 763 (*ifp->if_input)(ifp, m); 764 STE_LOCK(sc); 765 } 766 767 if (rx_npkts > 0) { 768 sc->ste_cdata.ste_rx_head = cur_rx; 769 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 770 sc->ste_cdata.ste_rx_list_map, 771 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 772 } 773 774 return (rx_npkts); 775} 776 777static void 778ste_txeoc(struct ste_softc *sc) 779{ 780 struct ifnet *ifp; 781 uint8_t txstat; 782 783 ifp = sc->ste_ifp; 784 785 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 786 STE_TXSTATUS_TXDONE) { 787 if (txstat & STE_TXSTATUS_UNDERRUN || 788 txstat & STE_TXSTATUS_EXCESSCOLLS || 789 txstat & STE_TXSTATUS_RECLAIMERR) { 790 ifp->if_oerrors++; 791 device_printf(sc->ste_dev, 792 "transmission error: %x\n", txstat); 793 794 ste_reset(sc); 795 ste_init_locked(sc); 796 797 if (txstat & STE_TXSTATUS_UNDERRUN && 798 sc->ste_tx_thresh < STE_PACKET_SIZE) { 799 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 800 device_printf(sc->ste_dev, 801 "tx underrun, increasing tx" 802 " start threshold to %d bytes\n", 803 sc->ste_tx_thresh); 804 } 805 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 806 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 807 (STE_PACKET_SIZE >> 4)); 808 } 809 ste_init_locked(sc); 810 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 811 } 812} 813 814static void 815ste_txeof(struct ste_softc *sc) 816{ 817 struct ifnet *ifp; 818 struct ste_chain *cur_tx; 819 uint32_t txstat; 820 int idx; 821 822 STE_LOCK_ASSERT(sc); 823 824 ifp = sc->ste_ifp; 825 idx = sc->ste_cdata.ste_tx_cons; 826 if (idx == sc->ste_cdata.ste_tx_prod) 827 return; 828 829 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 830 sc->ste_cdata.ste_tx_list_map, 831 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 832 833 while (idx != sc->ste_cdata.ste_tx_prod) { 834 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 835 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 836 if ((txstat & STE_TXCTL_DMADONE) == 0) 837 break; 838 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 839 BUS_DMASYNC_POSTWRITE); 840 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 841 KASSERT(cur_tx->ste_mbuf != NULL, 842 ("%s: freeing NULL mbuf!\n", __func__)); 843 m_freem(cur_tx->ste_mbuf); 844 cur_tx->ste_mbuf = NULL; 845 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 846 ifp->if_opackets++; 847 sc->ste_cdata.ste_tx_cnt--; 848 STE_INC(idx, STE_TX_LIST_CNT); 849 } 850 851 sc->ste_cdata.ste_tx_cons = idx; 852 if (sc->ste_cdata.ste_tx_cnt == 0) 853 sc->ste_timer = 0; 854} 855 856static void 857ste_stats_update(void *xsc) 858{ 859 struct ste_softc *sc; 860 struct ifnet *ifp; 861 struct mii_data *mii; 862 863 sc = xsc; 864 STE_LOCK_ASSERT(sc); 865 866 ifp = sc->ste_ifp; 867 mii = device_get_softc(sc->ste_miibus); 868 869 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 870 + CSR_READ_1(sc, STE_MULTI_COLLS) 871 + CSR_READ_1(sc, STE_SINGLE_COLLS); 872 873 if (!sc->ste_link) { 874 mii_pollstat(mii); 875 if (mii->mii_media_status & IFM_ACTIVE && 876 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 877 sc->ste_link++; 878 /* 879 * we don't get a call-back on re-init so do it 880 * otherwise we get stuck in the wrong link state 881 */ 882 ste_miibus_statchg(sc->ste_dev); 883 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 884 ste_start_locked(ifp); 885 } 886 } 887 888 if (sc->ste_timer > 0 && --sc->ste_timer == 0) 889 ste_watchdog(sc); 890 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 891} 892 893 894/* 895 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 896 * IDs against our list and return a device name if we find a match. 897 */ 898static int 899ste_probe(device_t dev) 900{ 901 struct ste_type *t; 902 903 t = ste_devs; 904 905 while (t->ste_name != NULL) { 906 if ((pci_get_vendor(dev) == t->ste_vid) && 907 (pci_get_device(dev) == t->ste_did)) { 908 device_set_desc(dev, t->ste_name); 909 return (BUS_PROBE_DEFAULT); 910 } 911 t++; 912 } 913 914 return (ENXIO); 915} 916 917/* 918 * Attach the interface. Allocate softc structures, do ifmedia 919 * setup and ethernet/BPF attach. 920 */ 921static int 922ste_attach(device_t dev) 923{ 924 struct ste_softc *sc; 925 struct ifnet *ifp; 926 u_char eaddr[6]; 927 int error = 0, rid; 928 929 sc = device_get_softc(dev); 930 sc->ste_dev = dev; 931 932 /* 933 * Only use one PHY since this chip reports multiple 934 * Note on the DFE-550 the PHY is at 1 on the DFE-580 935 * it is at 0 & 1. It is rev 0x12. 936 */ 937 if (pci_get_vendor(dev) == DL_VENDORID && 938 pci_get_device(dev) == DL_DEVICEID_DL10050 && 939 pci_get_revid(dev) == 0x12 ) 940 sc->ste_one_phy = 1; 941 942 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 943 MTX_DEF); 944 /* 945 * Map control/status registers. 946 */ 947 pci_enable_busmaster(dev); 948 949 rid = STE_RID; 950 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 951 952 if (sc->ste_res == NULL) { 953 device_printf(dev, "couldn't map ports/memory\n"); 954 error = ENXIO; 955 goto fail; 956 } 957 958 sc->ste_btag = rman_get_bustag(sc->ste_res); 959 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 960 961 /* Allocate interrupt */ 962 rid = 0; 963 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 964 RF_SHAREABLE | RF_ACTIVE); 965 966 if (sc->ste_irq == NULL) { 967 device_printf(dev, "couldn't map interrupt\n"); 968 error = ENXIO; 969 goto fail; 970 } 971 972 callout_init_mtx(&sc->ste_stat_callout, &sc->ste_mtx, 0); 973 974 /* Reset the adapter. */ 975 ste_reset(sc); 976 977 /* 978 * Get station address from the EEPROM. 979 */ 980 if (ste_read_eeprom(sc, eaddr, 981 STE_EEADDR_NODE0, 3, 0)) { 982 device_printf(dev, "failed to read station address\n"); 983 error = ENXIO;; 984 goto fail; 985 } 986 987 if ((error = ste_dma_alloc(sc)) != 0) 988 goto fail; 989 990 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 991 if (ifp == NULL) { 992 device_printf(dev, "can not if_alloc()\n"); 993 error = ENOSPC; 994 goto fail; 995 } 996 997 /* Do MII setup. */ 998 if (mii_phy_probe(dev, &sc->ste_miibus, 999 ste_ifmedia_upd, ste_ifmedia_sts)) { 1000 device_printf(dev, "MII without any phy!\n"); 1001 error = ENXIO; 1002 goto fail; 1003 } 1004 1005 ifp->if_softc = sc; 1006 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1007 ifp->if_mtu = ETHERMTU; 1008 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1009 ifp->if_ioctl = ste_ioctl; 1010 ifp->if_start = ste_start; 1011 ifp->if_init = ste_init; 1012 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1013 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1014 IFQ_SET_READY(&ifp->if_snd); 1015 1016 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1017 1018 /* 1019 * Call MI attach routine. 1020 */ 1021 ether_ifattach(ifp, eaddr); 1022 1023 /* 1024 * Tell the upper layer(s) we support long frames. 1025 */ 1026 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1027 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1028 ifp->if_capenable = ifp->if_capabilities; 1029#ifdef DEVICE_POLLING 1030 ifp->if_capabilities |= IFCAP_POLLING; 1031#endif 1032 1033 /* Hook interrupt last to avoid having to lock softc */ 1034 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1035 NULL, ste_intr, sc, &sc->ste_intrhand); 1036 1037 if (error) { 1038 device_printf(dev, "couldn't set up irq\n"); 1039 ether_ifdetach(ifp); 1040 goto fail; 1041 } 1042 1043fail: 1044 if (error) 1045 ste_detach(dev); 1046 1047 return (error); 1048} 1049 1050/* 1051 * Shutdown hardware and free up resources. This can be called any 1052 * time after the mutex has been initialized. It is called in both 1053 * the error case in attach and the normal detach case so it needs 1054 * to be careful about only freeing resources that have actually been 1055 * allocated. 1056 */ 1057static int 1058ste_detach(device_t dev) 1059{ 1060 struct ste_softc *sc; 1061 struct ifnet *ifp; 1062 1063 sc = device_get_softc(dev); 1064 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1065 ifp = sc->ste_ifp; 1066 1067#ifdef DEVICE_POLLING 1068 if (ifp->if_capenable & IFCAP_POLLING) 1069 ether_poll_deregister(ifp); 1070#endif 1071 1072 /* These should only be active if attach succeeded */ 1073 if (device_is_attached(dev)) { 1074 ether_ifdetach(ifp); 1075 STE_LOCK(sc); 1076 ste_stop(sc); 1077 STE_UNLOCK(sc); 1078 callout_drain(&sc->ste_stat_callout); 1079 } 1080 if (sc->ste_miibus) 1081 device_delete_child(dev, sc->ste_miibus); 1082 bus_generic_detach(dev); 1083 1084 if (sc->ste_intrhand) 1085 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1086 if (sc->ste_irq) 1087 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1088 if (sc->ste_res) 1089 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1090 1091 if (ifp) 1092 if_free(ifp); 1093 1094 ste_dma_free(sc); 1095 mtx_destroy(&sc->ste_mtx); 1096 1097 return (0); 1098} 1099 1100struct ste_dmamap_arg { 1101 bus_addr_t ste_busaddr; 1102}; 1103 1104static void 1105ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1106{ 1107 struct ste_dmamap_arg *ctx; 1108 1109 if (error != 0) 1110 return; 1111 1112 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1113 1114 ctx = (struct ste_dmamap_arg *)arg; 1115 ctx->ste_busaddr = segs[0].ds_addr; 1116} 1117 1118static int 1119ste_dma_alloc(struct ste_softc *sc) 1120{ 1121 struct ste_chain *txc; 1122 struct ste_chain_onefrag *rxc; 1123 struct ste_dmamap_arg ctx; 1124 int error, i; 1125 1126 /* Create parent DMA tag. */ 1127 error = bus_dma_tag_create( 1128 bus_get_dma_tag(sc->ste_dev), /* parent */ 1129 1, 0, /* alignment, boundary */ 1130 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1131 BUS_SPACE_MAXADDR, /* highaddr */ 1132 NULL, NULL, /* filter, filterarg */ 1133 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1134 0, /* nsegments */ 1135 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1136 0, /* flags */ 1137 NULL, NULL, /* lockfunc, lockarg */ 1138 &sc->ste_cdata.ste_parent_tag); 1139 if (error != 0) { 1140 device_printf(sc->ste_dev, 1141 "could not create parent DMA tag.\n"); 1142 goto fail; 1143 } 1144 1145 /* Create DMA tag for Tx descriptor list. */ 1146 error = bus_dma_tag_create( 1147 sc->ste_cdata.ste_parent_tag, /* parent */ 1148 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1149 BUS_SPACE_MAXADDR, /* lowaddr */ 1150 BUS_SPACE_MAXADDR, /* highaddr */ 1151 NULL, NULL, /* filter, filterarg */ 1152 STE_TX_LIST_SZ, /* maxsize */ 1153 1, /* nsegments */ 1154 STE_TX_LIST_SZ, /* maxsegsize */ 1155 0, /* flags */ 1156 NULL, NULL, /* lockfunc, lockarg */ 1157 &sc->ste_cdata.ste_tx_list_tag); 1158 if (error != 0) { 1159 device_printf(sc->ste_dev, 1160 "could not create Tx list DMA tag.\n"); 1161 goto fail; 1162 } 1163 1164 /* Create DMA tag for Rx descriptor list. */ 1165 error = bus_dma_tag_create( 1166 sc->ste_cdata.ste_parent_tag, /* parent */ 1167 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1168 BUS_SPACE_MAXADDR, /* lowaddr */ 1169 BUS_SPACE_MAXADDR, /* highaddr */ 1170 NULL, NULL, /* filter, filterarg */ 1171 STE_RX_LIST_SZ, /* maxsize */ 1172 1, /* nsegments */ 1173 STE_RX_LIST_SZ, /* maxsegsize */ 1174 0, /* flags */ 1175 NULL, NULL, /* lockfunc, lockarg */ 1176 &sc->ste_cdata.ste_rx_list_tag); 1177 if (error != 0) { 1178 device_printf(sc->ste_dev, 1179 "could not create Rx list DMA tag.\n"); 1180 goto fail; 1181 } 1182 1183 /* Create DMA tag for Tx buffers. */ 1184 error = bus_dma_tag_create( 1185 sc->ste_cdata.ste_parent_tag, /* parent */ 1186 1, 0, /* alignment, boundary */ 1187 BUS_SPACE_MAXADDR, /* lowaddr */ 1188 BUS_SPACE_MAXADDR, /* highaddr */ 1189 NULL, NULL, /* filter, filterarg */ 1190 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1191 STE_MAXFRAGS, /* nsegments */ 1192 MCLBYTES, /* maxsegsize */ 1193 0, /* flags */ 1194 NULL, NULL, /* lockfunc, lockarg */ 1195 &sc->ste_cdata.ste_tx_tag); 1196 if (error != 0) { 1197 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1198 goto fail; 1199 } 1200 1201 /* Create DMA tag for Rx buffers. */ 1202 error = bus_dma_tag_create( 1203 sc->ste_cdata.ste_parent_tag, /* parent */ 1204 1, 0, /* alignment, boundary */ 1205 BUS_SPACE_MAXADDR, /* lowaddr */ 1206 BUS_SPACE_MAXADDR, /* highaddr */ 1207 NULL, NULL, /* filter, filterarg */ 1208 MCLBYTES, /* maxsize */ 1209 1, /* nsegments */ 1210 MCLBYTES, /* maxsegsize */ 1211 0, /* flags */ 1212 NULL, NULL, /* lockfunc, lockarg */ 1213 &sc->ste_cdata.ste_rx_tag); 1214 if (error != 0) { 1215 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1216 goto fail; 1217 } 1218 1219 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1220 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1221 (void **)&sc->ste_ldata.ste_tx_list, 1222 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1223 &sc->ste_cdata.ste_tx_list_map); 1224 if (error != 0) { 1225 device_printf(sc->ste_dev, 1226 "could not allocate DMA'able memory for Tx list.\n"); 1227 goto fail; 1228 } 1229 ctx.ste_busaddr = 0; 1230 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1231 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1232 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1233 if (error != 0 || ctx.ste_busaddr == 0) { 1234 device_printf(sc->ste_dev, 1235 "could not load DMA'able memory for Tx list.\n"); 1236 goto fail; 1237 } 1238 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1239 1240 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1241 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1242 (void **)&sc->ste_ldata.ste_rx_list, 1243 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1244 &sc->ste_cdata.ste_rx_list_map); 1245 if (error != 0) { 1246 device_printf(sc->ste_dev, 1247 "could not allocate DMA'able memory for Rx list.\n"); 1248 goto fail; 1249 } 1250 ctx.ste_busaddr = 0; 1251 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1252 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1253 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1254 if (error != 0 || ctx.ste_busaddr == 0) { 1255 device_printf(sc->ste_dev, 1256 "could not load DMA'able memory for Rx list.\n"); 1257 goto fail; 1258 } 1259 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1260 1261 /* Create DMA maps for Tx buffers. */ 1262 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1263 txc = &sc->ste_cdata.ste_tx_chain[i]; 1264 txc->ste_ptr = NULL; 1265 txc->ste_mbuf = NULL; 1266 txc->ste_next = NULL; 1267 txc->ste_phys = 0; 1268 txc->ste_map = NULL; 1269 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1270 &txc->ste_map); 1271 if (error != 0) { 1272 device_printf(sc->ste_dev, 1273 "could not create Tx dmamap.\n"); 1274 goto fail; 1275 } 1276 } 1277 /* Create DMA maps for Rx buffers. */ 1278 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1279 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1280 device_printf(sc->ste_dev, 1281 "could not create spare Rx dmamap.\n"); 1282 goto fail; 1283 } 1284 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1285 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1286 rxc->ste_ptr = NULL; 1287 rxc->ste_mbuf = NULL; 1288 rxc->ste_next = NULL; 1289 rxc->ste_map = NULL; 1290 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1291 &rxc->ste_map); 1292 if (error != 0) { 1293 device_printf(sc->ste_dev, 1294 "could not create Rx dmamap.\n"); 1295 goto fail; 1296 } 1297 } 1298 1299fail: 1300 return (error); 1301} 1302 1303static void 1304ste_dma_free(struct ste_softc *sc) 1305{ 1306 struct ste_chain *txc; 1307 struct ste_chain_onefrag *rxc; 1308 int i; 1309 1310 /* Tx buffers. */ 1311 if (sc->ste_cdata.ste_tx_tag != NULL) { 1312 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1313 txc = &sc->ste_cdata.ste_tx_chain[i]; 1314 if (txc->ste_map != NULL) { 1315 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1316 txc->ste_map); 1317 txc->ste_map = NULL; 1318 } 1319 } 1320 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1321 sc->ste_cdata.ste_tx_tag = NULL; 1322 } 1323 /* Rx buffers. */ 1324 if (sc->ste_cdata.ste_rx_tag != NULL) { 1325 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1326 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1327 if (rxc->ste_map != NULL) { 1328 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1329 rxc->ste_map); 1330 rxc->ste_map = NULL; 1331 } 1332 } 1333 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1334 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1335 sc->ste_cdata.ste_rx_sparemap); 1336 sc->ste_cdata.ste_rx_sparemap = NULL; 1337 } 1338 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1339 sc->ste_cdata.ste_rx_tag = NULL; 1340 } 1341 /* Tx descriptor list. */ 1342 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1343 if (sc->ste_cdata.ste_tx_list_map != NULL) 1344 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1345 sc->ste_cdata.ste_tx_list_map); 1346 if (sc->ste_cdata.ste_tx_list_map != NULL && 1347 sc->ste_ldata.ste_tx_list != NULL) 1348 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1349 sc->ste_ldata.ste_tx_list, 1350 sc->ste_cdata.ste_tx_list_map); 1351 sc->ste_ldata.ste_tx_list = NULL; 1352 sc->ste_cdata.ste_tx_list_map = NULL; 1353 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1354 sc->ste_cdata.ste_tx_list_tag = NULL; 1355 } 1356 /* Rx descriptor list. */ 1357 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1358 if (sc->ste_cdata.ste_rx_list_map != NULL) 1359 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1360 sc->ste_cdata.ste_rx_list_map); 1361 if (sc->ste_cdata.ste_rx_list_map != NULL && 1362 sc->ste_ldata.ste_rx_list != NULL) 1363 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1364 sc->ste_ldata.ste_rx_list, 1365 sc->ste_cdata.ste_rx_list_map); 1366 sc->ste_ldata.ste_rx_list = NULL; 1367 sc->ste_cdata.ste_rx_list_map = NULL; 1368 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1369 sc->ste_cdata.ste_rx_list_tag = NULL; 1370 } 1371 if (sc->ste_cdata.ste_parent_tag != NULL) { 1372 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1373 sc->ste_cdata.ste_parent_tag = NULL; 1374 } 1375} 1376 1377static int 1378ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1379{ 1380 struct mbuf *m; 1381 bus_dma_segment_t segs[1]; 1382 bus_dmamap_t map; 1383 int error, nsegs; 1384 1385 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1386 if (m == NULL) 1387 return (ENOBUFS); 1388 m->m_len = m->m_pkthdr.len = MCLBYTES; 1389 m_adj(m, ETHER_ALIGN); 1390 1391 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1392 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1393 m_freem(m); 1394 return (error); 1395 } 1396 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1397 1398 if (rxc->ste_mbuf != NULL) { 1399 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1400 BUS_DMASYNC_POSTREAD); 1401 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1402 } 1403 map = rxc->ste_map; 1404 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1405 sc->ste_cdata.ste_rx_sparemap = map; 1406 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1407 BUS_DMASYNC_PREREAD); 1408 rxc->ste_mbuf = m; 1409 rxc->ste_ptr->ste_status = 0; 1410 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1411 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1412 STE_FRAG_LAST); 1413 return (0); 1414} 1415 1416static int 1417ste_init_rx_list(struct ste_softc *sc) 1418{ 1419 struct ste_chain_data *cd; 1420 struct ste_list_data *ld; 1421 int error, i; 1422 1423 cd = &sc->ste_cdata; 1424 ld = &sc->ste_ldata; 1425 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1426 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1427 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1428 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1429 if (error != 0) 1430 return (error); 1431 if (i == (STE_RX_LIST_CNT - 1)) { 1432 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1433 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1434 (sizeof(struct ste_desc_onefrag) * 0); 1435 } else { 1436 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1437 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1438 (sizeof(struct ste_desc_onefrag) * (i + 1)); 1439 } 1440 } 1441 1442 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1443 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1444 sc->ste_cdata.ste_rx_list_map, 1445 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1446 1447 return (0); 1448} 1449 1450static void 1451ste_init_tx_list(struct ste_softc *sc) 1452{ 1453 struct ste_chain_data *cd; 1454 struct ste_list_data *ld; 1455 int i; 1456 1457 cd = &sc->ste_cdata; 1458 ld = &sc->ste_ldata; 1459 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1460 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1461 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1462 cd->ste_tx_chain[i].ste_mbuf = NULL; 1463 if (i == (STE_TX_LIST_CNT - 1)) { 1464 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1465 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1466 ld->ste_tx_list_paddr + 1467 (sizeof(struct ste_desc) * 0))); 1468 } else { 1469 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1470 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1471 ld->ste_tx_list_paddr + 1472 (sizeof(struct ste_desc) * (i + 1)))); 1473 } 1474 } 1475 1476 cd->ste_last_tx = NULL; 1477 cd->ste_tx_prod = 0; 1478 cd->ste_tx_cons = 0; 1479 cd->ste_tx_cnt = 0; 1480 1481 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1482 sc->ste_cdata.ste_tx_list_map, 1483 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1484} 1485 1486static void 1487ste_init(void *xsc) 1488{ 1489 struct ste_softc *sc; 1490 1491 sc = xsc; 1492 STE_LOCK(sc); 1493 ste_init_locked(sc); 1494 STE_UNLOCK(sc); 1495} 1496 1497static void 1498ste_init_locked(struct ste_softc *sc) 1499{ 1500 struct ifnet *ifp; 1501 int i; 1502 1503 STE_LOCK_ASSERT(sc); 1504 ifp = sc->ste_ifp; 1505 1506 ste_stop(sc); 1507 1508 /* Init our MAC address */ 1509 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1510 CSR_WRITE_2(sc, STE_PAR0 + i, 1511 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1512 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1513 } 1514 1515 /* Init RX list */ 1516 if (ste_init_rx_list(sc) != 0) { 1517 device_printf(sc->ste_dev, 1518 "initialization failed: no memory for RX buffers\n"); 1519 ste_stop(sc); 1520 return; 1521 } 1522 1523 /* Set RX polling interval */ 1524 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1525 1526 /* Init TX descriptors */ 1527 ste_init_tx_list(sc); 1528 1529 /* Set the TX freethresh value */ 1530 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1531 1532 /* Set the TX start threshold for best performance. */ 1533 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1534 1535 /* Set the TX reclaim threshold. */ 1536 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1537 1538 /* Set up the RX filter. */ 1539 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1540 1541 /* If we want promiscuous mode, set the allframes bit. */ 1542 if (ifp->if_flags & IFF_PROMISC) { 1543 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1544 } else { 1545 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1546 } 1547 1548 /* Set capture broadcast bit to accept broadcast frames. */ 1549 if (ifp->if_flags & IFF_BROADCAST) { 1550 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1551 } else { 1552 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1553 } 1554 1555 ste_setmulti(sc); 1556 1557 /* Load the address of the RX list. */ 1558 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1559 ste_wait(sc); 1560 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1561 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1562 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1563 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1564 1565 /* Set TX polling interval(defer until we TX first packet). */ 1566 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1567 1568 /* Load address of the TX list */ 1569 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1570 ste_wait(sc); 1571 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1572 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1573 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1574 ste_wait(sc); 1575 1576 /* Enable receiver and transmitter */ 1577 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1578 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1579 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1580 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1581 1582 /* Enable stats counters. */ 1583 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1584 1585 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1586#ifdef DEVICE_POLLING 1587 /* Disable interrupts if we are polling. */ 1588 if (ifp->if_capenable & IFCAP_POLLING) 1589 CSR_WRITE_2(sc, STE_IMR, 0); 1590 else 1591#endif 1592 /* Enable interrupts. */ 1593 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1594 1595 /* Accept VLAN length packets */ 1596 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1597 1598 ste_ifmedia_upd_locked(ifp); 1599 1600 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1601 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1602 1603 callout_reset(&sc->ste_stat_callout, hz, ste_stats_update, sc); 1604} 1605 1606static void 1607ste_stop(struct ste_softc *sc) 1608{ 1609 struct ifnet *ifp; 1610 struct ste_chain_onefrag *cur_rx; 1611 struct ste_chain *cur_tx; 1612 int i; 1613 1614 STE_LOCK_ASSERT(sc); 1615 ifp = sc->ste_ifp; 1616 1617 callout_stop(&sc->ste_stat_callout); 1618 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1619 1620 CSR_WRITE_2(sc, STE_IMR, 0); 1621 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1622 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1623 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1624 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1625 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1626 ste_wait(sc); 1627 /* 1628 * Try really hard to stop the RX engine or under heavy RX 1629 * data chip will write into de-allocated memory. 1630 */ 1631 ste_reset(sc); 1632 1633 sc->ste_link = 0; 1634 1635 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1636 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1637 if (cur_rx->ste_mbuf != NULL) { 1638 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1639 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1640 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1641 cur_rx->ste_map); 1642 m_freem(cur_rx->ste_mbuf); 1643 cur_rx->ste_mbuf = NULL; 1644 } 1645 } 1646 1647 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1648 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1649 if (cur_tx->ste_mbuf != NULL) { 1650 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1651 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1652 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1653 cur_tx->ste_map); 1654 m_freem(cur_tx->ste_mbuf); 1655 cur_tx->ste_mbuf = NULL; 1656 } 1657 } 1658} 1659 1660static void 1661ste_reset(struct ste_softc *sc) 1662{ 1663 int i; 1664 1665 STE_SETBIT4(sc, STE_ASICCTL, 1666 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1667 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1668 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1669 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1670 STE_ASICCTL_EXTRESET_RESET); 1671 1672 DELAY(100000); 1673 1674 for (i = 0; i < STE_TIMEOUT; i++) { 1675 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1676 break; 1677 } 1678 1679 if (i == STE_TIMEOUT) 1680 device_printf(sc->ste_dev, "global reset never completed\n"); 1681} 1682 1683static int 1684ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1685{ 1686 struct ste_softc *sc; 1687 struct ifreq *ifr; 1688 struct mii_data *mii; 1689 int error = 0; 1690 1691 sc = ifp->if_softc; 1692 ifr = (struct ifreq *)data; 1693 1694 switch (command) { 1695 case SIOCSIFFLAGS: 1696 STE_LOCK(sc); 1697 if (ifp->if_flags & IFF_UP) { 1698 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1699 ifp->if_flags & IFF_PROMISC && 1700 !(sc->ste_if_flags & IFF_PROMISC)) { 1701 STE_SETBIT1(sc, STE_RX_MODE, 1702 STE_RXMODE_PROMISC); 1703 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1704 !(ifp->if_flags & IFF_PROMISC) && 1705 sc->ste_if_flags & IFF_PROMISC) { 1706 STE_CLRBIT1(sc, STE_RX_MODE, 1707 STE_RXMODE_PROMISC); 1708 } 1709 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1710 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1711 ste_setmulti(sc); 1712 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1713 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1714 ste_init_locked(sc); 1715 } 1716 } else { 1717 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1718 ste_stop(sc); 1719 } 1720 sc->ste_if_flags = ifp->if_flags; 1721 STE_UNLOCK(sc); 1722 error = 0; 1723 break; 1724 case SIOCADDMULTI: 1725 case SIOCDELMULTI: 1726 STE_LOCK(sc); 1727 ste_setmulti(sc); 1728 STE_UNLOCK(sc); 1729 error = 0; 1730 break; 1731 case SIOCGIFMEDIA: 1732 case SIOCSIFMEDIA: 1733 mii = device_get_softc(sc->ste_miibus); 1734 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1735 break; 1736 case SIOCSIFCAP: 1737#ifdef DEVICE_POLLING 1738 if (ifr->ifr_reqcap & IFCAP_POLLING && 1739 !(ifp->if_capenable & IFCAP_POLLING)) { 1740 error = ether_poll_register(ste_poll, ifp); 1741 if (error) 1742 return (error); 1743 STE_LOCK(sc); 1744 /* Disable interrupts */ 1745 CSR_WRITE_2(sc, STE_IMR, 0); 1746 ifp->if_capenable |= IFCAP_POLLING; 1747 STE_UNLOCK(sc); 1748 return (error); 1749 1750 } 1751 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1752 ifp->if_capenable & IFCAP_POLLING) { 1753 error = ether_poll_deregister(ifp); 1754 /* Enable interrupts. */ 1755 STE_LOCK(sc); 1756 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1757 ifp->if_capenable &= ~IFCAP_POLLING; 1758 STE_UNLOCK(sc); 1759 return (error); 1760 } 1761#endif /* DEVICE_POLLING */ 1762 break; 1763 default: 1764 error = ether_ioctl(ifp, command, data); 1765 break; 1766 } 1767 1768 return (error); 1769} 1770 1771static int 1772ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1773{ 1774 struct ste_frag *frag; 1775 struct mbuf *m; 1776 struct ste_desc *desc; 1777 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1778 int error, i, nsegs; 1779 1780 STE_LOCK_ASSERT(sc); 1781 M_ASSERTPKTHDR((*m_head)); 1782 1783 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1784 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1785 if (error == EFBIG) { 1786 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS); 1787 if (m == NULL) { 1788 m_freem(*m_head); 1789 *m_head = NULL; 1790 return (ENOMEM); 1791 } 1792 *m_head = m; 1793 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1794 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1795 if (error != 0) { 1796 m_freem(*m_head); 1797 *m_head = NULL; 1798 return (error); 1799 } 1800 } else if (error != 0) 1801 return (error); 1802 if (nsegs == 0) { 1803 m_freem(*m_head); 1804 *m_head = NULL; 1805 return (EIO); 1806 } 1807 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1808 BUS_DMASYNC_PREWRITE); 1809 1810 desc = txc->ste_ptr; 1811 for (i = 0; i < nsegs; i++) { 1812 frag = &desc->ste_frags[i]; 1813 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1814 frag->ste_len = htole32(txsegs[i].ds_len); 1815 } 1816 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1817 /* 1818 * Because we use Tx polling we can't chain multiple 1819 * Tx descriptors here. Otherwise we race with controller. 1820 */ 1821 desc->ste_next = 0; 1822 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | STE_TXCTL_DMAINTR); 1823 txc->ste_mbuf = *m_head; 1824 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1825 sc->ste_cdata.ste_tx_cnt++; 1826 1827 return (0); 1828} 1829 1830static void 1831ste_start(struct ifnet *ifp) 1832{ 1833 struct ste_softc *sc; 1834 1835 sc = ifp->if_softc; 1836 STE_LOCK(sc); 1837 ste_start_locked(ifp); 1838 STE_UNLOCK(sc); 1839} 1840 1841static void 1842ste_start_locked(struct ifnet *ifp) 1843{ 1844 struct ste_softc *sc; 1845 struct ste_chain *cur_tx; 1846 struct mbuf *m_head = NULL; 1847 int enq; 1848 1849 sc = ifp->if_softc; 1850 STE_LOCK_ASSERT(sc); 1851 1852 if (!sc->ste_link) 1853 return; 1854 1855 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1856 return; 1857 1858 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 1859 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1860 /* 1861 * Controller may have cached copy of the last used 1862 * next ptr so we have to reserve one TFD to avoid 1863 * TFD overruns. 1864 */ 1865 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1866 break; 1867 } 1868 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1869 if (m_head == NULL) 1870 break; 1871 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1872 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1873 if (m_head == NULL) 1874 break; 1875 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1876 break; 1877 } 1878 if (sc->ste_cdata.ste_last_tx == NULL) { 1879 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1880 sc->ste_cdata.ste_tx_list_map, 1881 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1882 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1883 ste_wait(sc); 1884 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1885 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1886 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1887 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1888 ste_wait(sc); 1889 } else { 1890 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1891 sc->ste_cdata.ste_last_tx->ste_phys; 1892 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1893 sc->ste_cdata.ste_tx_list_map, 1894 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1895 } 1896 sc->ste_cdata.ste_last_tx = cur_tx; 1897 1898 enq++; 1899 /* 1900 * If there's a BPF listener, bounce a copy of this frame 1901 * to him. 1902 */ 1903 BPF_MTAP(ifp, m_head); 1904 } 1905 1906 if (enq > 0) 1907 sc->ste_timer = STE_TX_TIMEOUT; 1908} 1909 1910static void 1911ste_watchdog(struct ste_softc *sc) 1912{ 1913 struct ifnet *ifp; 1914 1915 ifp = sc->ste_ifp; 1916 STE_LOCK_ASSERT(sc); 1917 1918 ifp->if_oerrors++; 1919 if_printf(ifp, "watchdog timeout\n"); 1920 1921 ste_txeoc(sc); 1922 ste_txeof(sc); 1923 ste_rxeof(sc, -1); 1924 ste_reset(sc); 1925 ste_init_locked(sc); 1926 1927 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1928 ste_start_locked(ifp); 1929} 1930 1931static int 1932ste_shutdown(device_t dev) 1933{ 1934 struct ste_softc *sc; 1935 1936 sc = device_get_softc(dev); 1937 1938 STE_LOCK(sc); 1939 ste_stop(sc); 1940 STE_UNLOCK(sc); 1941 1942 return (0); 1943} 1944